1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
5 // Author: Timur Tabi <timur@freescale.com>
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
11 // The i.MX SSI core has some nasty limitations in AC97 mode. While most
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
14 // which slots we want to receive. The WM9712 with which this driver
15 // was developed with always sends GPIO status data in slot 12 which
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
18 // from 48000Hz not every frame has valid receive data, so the ratio
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
20 // able to handle this, hence this driver only works with 48000Hz sampling
22 // Reading and writing AC97 registers is another challenge. The core
23 // provides us status bits when the read register is updated with *another*
24 // value. When we read the same register two times (and the register still
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
28 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/interrupt.h>
32 #include <linux/clk.h>
33 #include <linux/ctype.h>
34 #include <linux/device.h>
35 #include <linux/delay.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/of_platform.h>
44 #include <sound/core.h>
45 #include <sound/pcm.h>
46 #include <sound/pcm_params.h>
47 #include <sound/initval.h>
48 #include <sound/soc.h>
49 #include <sound/dmaengine_pcm.h>
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
61 * The SSI has a limitation in that the samples must be in the same byte
62 * order as the host CPU. This is because when multiple bytes are written
63 * to the STX register, the bytes and bits must be written in the same
64 * order. The STX is a shift register, so all the bits need to be aligned
65 * (bit-endianness must match byte-endianness). Processors typically write
66 * the bits within a byte in the same order that the bytes of a word are
67 * written in. So if the host CPU is big-endian, then only big-endian
68 * samples will be written to STX properly.
71 #define FSLSSI_I2S_FORMATS \
72 (SNDRV_PCM_FMTBIT_S8 | \
73 SNDRV_PCM_FMTBIT_S16_BE | \
74 SNDRV_PCM_FMTBIT_S18_3BE | \
75 SNDRV_PCM_FMTBIT_S20_3BE | \
76 SNDRV_PCM_FMTBIT_S24_3BE | \
77 SNDRV_PCM_FMTBIT_S24_BE)
79 #define FSLSSI_I2S_FORMATS \
80 (SNDRV_PCM_FMTBIT_S8 | \
81 SNDRV_PCM_FMTBIT_S16_LE | \
82 SNDRV_PCM_FMTBIT_S18_3LE | \
83 SNDRV_PCM_FMTBIT_S20_3LE | \
84 SNDRV_PCM_FMTBIT_S24_3LE | \
85 SNDRV_PCM_FMTBIT_S24_LE)
89 * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
90 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
91 * - Also have NB_NF to mark these two clocks will not be inverted
93 #define FSLSSI_AC97_DAIFMT \
94 (SND_SOC_DAIFMT_AC97 | \
95 SND_SOC_DAIFMT_CBM_CFS | \
98 #define FSLSSI_SIER_DBG_RX_FLAGS \
104 #define FSLSSI_SIER_DBG_TX_FLAGS \
105 (SSI_SIER_TFE0_EN | \
118 struct fsl_ssi_regvals {
125 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
129 case REG_SSI_SACCDIS:
136 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
157 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
172 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
184 static const struct regmap_config fsl_ssi_regconfig = {
185 .max_register = REG_SSI_SACCDIS,
189 .val_format_endian = REGMAP_ENDIAN_NATIVE,
190 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
191 .readable_reg = fsl_ssi_readable_reg,
192 .volatile_reg = fsl_ssi_volatile_reg,
193 .precious_reg = fsl_ssi_precious_reg,
194 .writeable_reg = fsl_ssi_writeable_reg,
195 .cache_type = REGCACHE_FLAT,
198 struct fsl_ssi_soc_data {
200 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
206 * fsl_ssi: per-SSI private data
208 * @regs: Pointer to the regmap registers
209 * @irq: IRQ of this SSI
210 * @cpu_dai_drv: CPU DAI driver for this device
212 * @dai_fmt: DAI configuration this device is currently used with
213 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
214 * @i2s_net: I2S and Network mode configurations of SCR register
215 * (this is the initial settings based on the DAI format)
216 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
217 * @use_dma: DMA is used or FIQ with stream filter
218 * @use_dual_fifo: DMA with support for dual FIFO mode
219 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
220 * @fifo_depth: Depth of the SSI FIFOs
221 * @slot_width: Width of each DAI slot
222 * @slots: Number of slots
223 * @regvals: Specific RX/TX register settings
225 * @clk: Clock source to access register
226 * @baudclk: Clock source to generate bit and frame-sync clocks
227 * @baudclk_streams: Active streams that are using baudclk
229 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
230 * @regcache_sacnt: Cache sacnt register value during suspend and resume
232 * @dma_params_tx: DMA transmit parameters
233 * @dma_params_rx: DMA receive parameters
234 * @ssi_phys: physical address of the SSI registers
236 * @fiq_params: FIQ stream filtering parameters
238 * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
239 * to register a CODEC platform device for AC97
240 * @card_name: Platform_device name to register a sound card for PowerPC or
241 * to register a CODEC platform device for AC97
242 * @card_idx: The index of SSI to register a sound card for PowerPC or
243 * to register a CODEC platform device for AC97
245 * @dbg_stats: Debugging statistics
247 * @soc: SoC specific data
248 * @dev: Pointer to &pdev->dev
250 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
251 * @fifo_watermark or fewer words in TX fifo or
252 * @fifo_watermark or more empty words in RX fifo.
253 * @dma_maxburst: Max number of words to transfer in one go. So far,
254 * this is always the same as fifo_watermark.
256 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
261 struct snd_soc_dai_driver cpu_dai_drv;
263 unsigned int dai_fmt;
269 bool has_ipg_clk_name;
270 unsigned int fifo_depth;
271 unsigned int slot_width;
273 struct fsl_ssi_regvals regvals[2];
277 unsigned int baudclk_streams;
282 struct snd_dmaengine_dai_dma_data dma_params_tx;
283 struct snd_dmaengine_dai_dma_data dma_params_rx;
286 struct imx_pcm_fiq_params fiq_params;
288 struct platform_device *card_pdev;
292 struct fsl_ssi_dbg dbg_stats;
294 const struct fsl_ssi_soc_data *soc;
300 struct mutex ac97_reg_lock;
307 * 1) SSI in earlier SoCS has critical bits in control registers that
308 * cannot be changed after SSI starts running -- a software reset
309 * (set SSIEN to 0) is required to change their values. So adding
310 * an offline_config flag for these SoCs.
311 * 2) SDMA is available since imx35. However, imx35 does not support
312 * DMA bits changing when SSI is running, so set offline_config.
313 * 3) imx51 and later versions support register configurations when
314 * SSI is running (SSIEN); For these versions, DMA needs to be
315 * configured before SSI sends DMA request to avoid an undefined
316 * DMA request on the SDMA side.
319 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
321 .offline_config = true,
322 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
323 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
324 SSI_SISR_TUE0 | SSI_SISR_TUE1,
327 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
330 .offline_config = true,
331 .sisr_write_mask = 0,
334 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
336 .offline_config = true,
337 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
338 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
339 SSI_SISR_TUE0 | SSI_SISR_TUE1,
342 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
344 .offline_config = false,
345 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
346 SSI_SISR_TUE0 | SSI_SISR_TUE1,
349 static const struct of_device_id fsl_ssi_ids[] = {
350 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
351 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
352 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
353 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
356 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
358 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
360 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
364 static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi)
366 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
367 SND_SOC_DAIFMT_CBS_CFS;
370 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi)
372 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
373 SND_SOC_DAIFMT_CBM_CFS;
377 * Interrupt handler to gather states
379 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
381 struct fsl_ssi *ssi = dev_id;
382 struct regmap *regs = ssi->regs;
385 regmap_read(regs, REG_SSI_SISR, &sisr);
387 sisr2 = sisr & ssi->soc->sisr_write_mask;
388 /* Clear the bits that we set */
390 regmap_write(regs, REG_SSI_SISR, sisr2);
392 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
398 * Set SCR, SIER, STCR and SRCR registers with cached values in regvals
401 * 1) For offline_config SoCs, enable all necessary bits of both streams
402 * when 1st stream starts, even if the opposite stream will not start
403 * 2) It also clears FIFO before setting regvals; SOR is safe to set online
405 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
407 struct fsl_ssi_regvals *vals = ssi->regvals;
408 int dir = tx ? TX : RX;
409 u32 sier, srcr, stcr;
411 /* Clear dirty data in the FIFO; It also prevents channel slipping */
412 regmap_update_bits(ssi->regs, REG_SSI_SOR,
413 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
416 * On offline_config SoCs, SxCR and SIER are already configured when
417 * the previous stream started. So skip all SxCR and SIER settings
418 * to prevent online reconfigurations, then jump to set SCR directly
420 if (ssi->soc->offline_config && ssi->streams)
423 if (ssi->soc->offline_config) {
425 * Online reconfiguration not supported, so enable all bits for
426 * both streams at once to avoid necessity of reconfigurations
428 srcr = vals[RX].srcr | vals[TX].srcr;
429 stcr = vals[RX].stcr | vals[TX].stcr;
430 sier = vals[RX].sier | vals[TX].sier;
432 /* Otherwise, only set bits for the current stream */
433 srcr = vals[dir].srcr;
434 stcr = vals[dir].stcr;
435 sier = vals[dir].sier;
438 /* Configure SRCR, STCR and SIER at once */
439 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
440 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
441 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
445 * Start DMA before setting TE to avoid FIFO underrun
446 * which may cause a channel slip or a channel swap
448 * TODO: FIQ cases might also need this upon testing
450 if (ssi->use_dma && tx) {
454 /* Enable SSI first to send TX DMA request */
455 regmap_update_bits(ssi->regs, REG_SSI_SCR,
456 SSI_SCR_SSIEN, SSI_SCR_SSIEN);
458 /* Busy wait until TX FIFO not empty -- DMA working */
460 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
461 if (SSI_SFCSR_TFCNT0(sfcsr))
465 /* FIFO still empty -- something might be wrong */
466 if (!SSI_SFCSR_TFCNT0(sfcsr))
467 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
469 /* Enable all remaining bits in SCR */
470 regmap_update_bits(ssi->regs, REG_SSI_SCR,
471 vals[dir].scr, vals[dir].scr);
473 /* Log the enabled stream to the mask */
474 ssi->streams |= BIT(dir);
478 * Exclude bits that are used by the opposite stream
480 * When both streams are active, disabling some bits for the current stream
481 * might break the other stream if these bits are used by it.
483 * @vals : regvals of the current stream
484 * @avals: regvals of the opposite stream
485 * @aactive: active state of the opposite stream
487 * 1) XOR vals and avals to get the differences if the other stream is active;
488 * Otherwise, return current vals if the other stream is not active
489 * 2) AND the result of 1) with the current vals
491 #define _ssi_xor_shared_bits(vals, avals, aactive) \
492 ((vals) ^ ((avals) * (aactive)))
494 #define ssi_excl_shared_bits(vals, avals, aactive) \
495 ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
498 * Unset SCR, SIER, STCR and SRCR registers with cached values in regvals
501 * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
502 * bits of both streams at once when the last stream is abort to end
503 * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
505 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
507 struct fsl_ssi_regvals *vals, *avals;
508 u32 sier, srcr, stcr, scr;
509 int adir = tx ? RX : TX;
510 int dir = tx ? TX : RX;
513 /* Check if the opposite stream is active */
514 aactive = ssi->streams & BIT(adir);
516 vals = &ssi->regvals[dir];
518 /* Get regvals of the opposite stream to keep opposite stream safe */
519 avals = &ssi->regvals[adir];
522 * To keep the other stream safe, exclude shared bits between
523 * both streams, and get safe bits to disable current stream
525 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
527 /* Disable safe bits of SCR register for the current stream */
528 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
530 /* Log the disabled stream to the mask */
531 ssi->streams &= ~BIT(dir);
534 * On offline_config SoCs, if the other stream is active, skip
535 * SxCR and SIER settings to prevent online reconfigurations
537 if (ssi->soc->offline_config && aactive)
540 if (ssi->soc->offline_config) {
541 /* Now there is only current stream active, disable all bits */
542 srcr = vals->srcr | avals->srcr;
543 stcr = vals->stcr | avals->stcr;
544 sier = vals->sier | avals->sier;
547 * To keep the other stream safe, exclude shared bits between
548 * both streams, and get safe bits to disable current stream
550 sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
551 srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
552 stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
555 /* Clear configurations of SRCR, STCR and SIER at once */
556 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
557 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
558 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
561 /* Clear remaining data in the FIFO */
562 regmap_update_bits(ssi->regs, REG_SSI_SOR,
563 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
566 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
568 struct regmap *regs = ssi->regs;
570 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
571 if (!ssi->soc->imx21regs) {
572 /* Disable all channel slots */
573 regmap_write(regs, REG_SSI_SACCDIS, 0xff);
574 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
575 regmap_write(regs, REG_SSI_SACCEN, 0x300);
580 * Cache critical bits of SIER, SRCR, STCR and SCR to later set them safely
582 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
584 struct fsl_ssi_regvals *vals = ssi->regvals;
586 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
587 vals[RX].srcr = SSI_SRCR_RFEN0;
588 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
589 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
590 vals[TX].stcr = SSI_STCR_TFEN0;
591 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
593 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
594 if (fsl_ssi_is_ac97(ssi))
595 vals[RX].scr = vals[TX].scr = 0;
597 if (ssi->use_dual_fifo) {
598 vals[RX].srcr |= SSI_SRCR_RFEN1;
599 vals[TX].stcr |= SSI_STCR_TFEN1;
603 vals[RX].sier |= SSI_SIER_RDMAE;
604 vals[TX].sier |= SSI_SIER_TDMAE;
606 vals[RX].sier |= SSI_SIER_RIE;
607 vals[TX].sier |= SSI_SIER_TIE;
611 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
613 struct regmap *regs = ssi->regs;
615 /* Setup the clock control register */
616 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
617 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
619 /* Enable AC97 mode and startup the SSI */
620 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
622 /* AC97 has to communicate with codec before starting a stream */
623 regmap_update_bits(regs, REG_SSI_SCR,
624 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
625 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
627 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
630 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
631 struct snd_soc_dai *dai)
633 struct snd_soc_pcm_runtime *rtd = substream->private_data;
634 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
637 ret = clk_prepare_enable(ssi->clk);
642 * When using dual fifo mode, it is safer to ensure an even period
643 * size. If appearing to an odd number while DMA always starts its
644 * task from fifo0, fifo1 would be neglected at the end of each
645 * period. But SSI would still access fifo1 with an invalid data.
647 if (ssi->use_dual_fifo)
648 snd_pcm_hw_constraint_step(substream->runtime, 0,
649 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
654 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
655 struct snd_soc_dai *dai)
657 struct snd_soc_pcm_runtime *rtd = substream->private_data;
658 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
660 clk_disable_unprepare(ssi->clk);
664 * Configure Digital Audio Interface bit clock
666 * Note: This function can be only called when using SSI as DAI master
668 * Quick instruction for parameters:
669 * freq: Output BCLK frequency = samplerate * slots * slot_width
670 * (In 2-channel I2S Master mode, slot_width is fixed 32)
672 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
673 struct snd_soc_dai *dai,
674 struct snd_pcm_hw_params *hw_params)
676 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
677 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
678 struct regmap *regs = ssi->regs;
679 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
680 unsigned long clkrate, baudrate, tmprate;
681 unsigned int channels = params_channels(hw_params);
682 unsigned int slot_width = params_width(hw_params);
683 unsigned int slots = 2;
684 u64 sub, savesub = 100000;
686 bool baudclk_is_used;
689 /* Override slots and slot_width if being specifically set... */
693 slot_width = ssi->slot_width;
695 /* ...but force 32 bits for stereo audio using I2S Master Mode */
697 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
700 /* Generate bit clock based on the slot number and slot width */
701 freq = slots * slot_width * params_rate(hw_params);
703 /* Don't apply it to any non-baudclk circumstance */
704 if (IS_ERR(ssi->baudclk))
708 * Hardware limitation: The bclk rate must be
709 * never greater than 1/5 IPG clock rate
711 if (freq * 5 > clk_get_rate(ssi->clk)) {
712 dev_err(dai->dev, "bitclk > ipgclk / 5\n");
716 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
718 /* It should be already enough to divide clock by setting pm alone */
722 factor = (div2 + 1) * (7 * psr + 1) * 2;
724 for (i = 0; i < 255; i++) {
725 tmprate = freq * factor * (i + 1);
728 clkrate = clk_get_rate(ssi->baudclk);
730 clkrate = clk_round_rate(ssi->baudclk, tmprate);
733 afreq = clkrate / (i + 1);
737 else if (freq / afreq == 1)
739 else if (afreq / freq == 1)
744 /* Calculate the fraction */
748 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
759 /* No proper pm found if it is still remaining the initial value */
761 dev_err(dai->dev, "failed to handle the required sysclk\n");
765 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
766 (psr ? SSI_SxCCR_PSR : 0);
767 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
769 /* STCCR is used for RX in synchronous mode */
770 tx2 = tx || ssi->synchronous;
771 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
773 if (!baudclk_is_used) {
774 ret = clk_set_rate(ssi->baudclk, baudrate);
776 dev_err(dai->dev, "failed to set baudclk rate\n");
785 * Configure SSI based on PCM hardware parameters
788 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
789 * disabled on offline_config SoCs. Even for online configurable SoCs
790 * running in synchronous mode (both TX and RX use STCCR), it is not
791 * safe to re-configure them when both two streams start running.
792 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
793 * fsl_ssi_set_bclk() if SSI is the DAI clock master.
795 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
796 struct snd_pcm_hw_params *hw_params,
797 struct snd_soc_dai *dai)
799 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
800 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
801 struct regmap *regs = ssi->regs;
802 unsigned int channels = params_channels(hw_params);
803 unsigned int sample_size = params_width(hw_params);
804 u32 wl = SSI_SxCCR_WL(sample_size);
807 if (fsl_ssi_is_i2s_master(ssi)) {
808 ret = fsl_ssi_set_bclk(substream, dai, hw_params);
812 /* Do not enable the clock if it is already enabled */
813 if (!(ssi->baudclk_streams & BIT(substream->stream))) {
814 ret = clk_prepare_enable(ssi->baudclk);
818 ssi->baudclk_streams |= BIT(substream->stream);
823 * SSI is properly configured if it is enabled and running in
824 * the synchronous mode; Note that AC97 mode is an exception
825 * that should set separate configurations for STCCR and SRCCR
826 * despite running in the synchronous mode.
828 if (ssi->streams && ssi->synchronous)
831 if (!fsl_ssi_is_ac97(ssi)) {
833 * Keep the ssi->i2s_net intact while having a local variable
834 * to override settings for special use cases. Otherwise, the
835 * ssi->i2s_net will lose the settings for regular use cases.
837 u8 i2s_net = ssi->i2s_net;
839 /* Normal + Network mode to send 16-bit data in 32-bit frames */
840 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
841 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
843 /* Use Normal mode to send mono data at 1st slot of 2 slots */
845 i2s_net = SSI_SCR_I2S_MODE_NORMAL;
847 regmap_update_bits(regs, REG_SSI_SCR,
848 SSI_SCR_I2S_NET_MASK, i2s_net);
851 /* In synchronous mode, the SSI uses STCCR for capture */
852 tx2 = tx || ssi->synchronous;
853 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
858 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
859 struct snd_soc_dai *dai)
861 struct snd_soc_pcm_runtime *rtd = substream->private_data;
862 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
864 if (fsl_ssi_is_i2s_master(ssi) &&
865 ssi->baudclk_streams & BIT(substream->stream)) {
866 clk_disable_unprepare(ssi->baudclk);
867 ssi->baudclk_streams &= ~BIT(substream->stream);
873 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
875 u32 strcr = 0, scr = 0, stcr, srcr, mask;
880 /* Synchronize frame sync clock for TE to avoid data slipping */
881 scr |= SSI_SCR_SYNC_TX_FS;
883 /* Set to default shifting settings: LSB_ALIGNED */
884 strcr |= SSI_STCR_TXBIT0;
886 /* Use Network mode as default */
887 ssi->i2s_net = SSI_SCR_NET;
888 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
889 case SND_SOC_DAIFMT_I2S:
890 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
891 case SND_SOC_DAIFMT_CBS_CFS:
892 if (IS_ERR(ssi->baudclk)) {
894 "missing baudclk for master mode\n");
898 case SND_SOC_DAIFMT_CBM_CFS:
899 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
901 case SND_SOC_DAIFMT_CBM_CFM:
902 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
908 slots = ssi->slots ? : 2;
909 regmap_update_bits(ssi->regs, REG_SSI_STCCR,
910 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
911 regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
912 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
914 /* Data on rising edge of bclk, frame low, 1clk before data */
915 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
917 case SND_SOC_DAIFMT_LEFT_J:
918 /* Data on rising edge of bclk, frame high */
919 strcr |= SSI_STCR_TSCKP;
921 case SND_SOC_DAIFMT_DSP_A:
922 /* Data on rising edge of bclk, frame high, 1clk before data */
923 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
925 case SND_SOC_DAIFMT_DSP_B:
926 /* Data on rising edge of bclk, frame high */
927 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
929 case SND_SOC_DAIFMT_AC97:
930 /* Data on falling edge of bclk, frame high, 1clk before data */
931 strcr |= SSI_STCR_TEFS;
939 /* DAI clock inversion */
940 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
941 case SND_SOC_DAIFMT_NB_NF:
942 /* Nothing to do for both normal cases */
944 case SND_SOC_DAIFMT_IB_NF:
945 /* Invert bit clock */
946 strcr ^= SSI_STCR_TSCKP;
948 case SND_SOC_DAIFMT_NB_IF:
949 /* Invert frame clock */
950 strcr ^= SSI_STCR_TFSI;
952 case SND_SOC_DAIFMT_IB_IF:
953 /* Invert both clocks */
954 strcr ^= SSI_STCR_TSCKP;
955 strcr ^= SSI_STCR_TFSI;
961 /* DAI clock master masks */
962 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
963 case SND_SOC_DAIFMT_CBS_CFS:
964 /* Output bit and frame sync clocks */
965 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
966 scr |= SSI_SCR_SYS_CLK_EN;
968 case SND_SOC_DAIFMT_CBM_CFM:
969 /* Input bit or frame sync clocks */
971 case SND_SOC_DAIFMT_CBM_CFS:
972 /* Input bit clock but output frame sync clock */
973 strcr |= SSI_STCR_TFDIR;
982 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
983 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
984 srcr &= ~SSI_SRCR_RXDIR;
988 mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
989 SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
991 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
992 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
994 mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
995 SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
996 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1002 * Configure Digital Audio Interface (DAI) Format
1004 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1006 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1008 /* AC97 configured DAIFMT earlier in the probe() */
1009 if (fsl_ssi_is_ac97(ssi))
1012 return _fsl_ssi_set_dai_fmt(ssi, fmt);
1016 * Set TDM slot number and slot width
1018 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
1019 u32 rx_mask, int slots, int slot_width)
1021 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1022 struct regmap *regs = ssi->regs;
1025 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
1026 if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
1027 dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
1031 /* The slot number should be >= 2 if using Network mode or I2S mode */
1032 if (ssi->i2s_net && slots < 2) {
1033 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
1037 regmap_update_bits(regs, REG_SSI_STCCR,
1038 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1039 regmap_update_bits(regs, REG_SSI_SRCCR,
1040 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1042 /* Save the SCR register value */
1043 regmap_read(regs, REG_SSI_SCR, &val);
1044 /* Temporarily enable SSI to allow SxMSKs to be configurable */
1045 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
1047 regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1048 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1050 /* Restore the value of SSIEN bit */
1051 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1053 ssi->slot_width = slot_width;
1060 * Start or stop SSI and corresponding DMA transaction.
1062 * The DMA channel is in external master start and pause mode, which
1063 * means the SSI completely controls the flow of data.
1065 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1066 struct snd_soc_dai *dai)
1068 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1069 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1070 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
1073 case SNDRV_PCM_TRIGGER_START:
1074 case SNDRV_PCM_TRIGGER_RESUME:
1075 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1077 * SACCST might be modified via AC Link by a CODEC if it sends
1078 * extra bits in their SLOTREQ requests, which'll accidentally
1079 * send valid data to slots other than normal playback slots.
1081 * To be safe, configure SACCST right before TX starts.
1083 if (tx && fsl_ssi_is_ac97(ssi))
1084 fsl_ssi_tx_ac97_saccst_setup(ssi);
1085 fsl_ssi_config_enable(ssi, tx);
1088 case SNDRV_PCM_TRIGGER_STOP:
1089 case SNDRV_PCM_TRIGGER_SUSPEND:
1090 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1091 fsl_ssi_config_disable(ssi, tx);
1101 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1103 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1105 if (ssi->soc->imx && ssi->use_dma)
1106 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1107 &ssi->dma_params_rx);
1112 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1113 .startup = fsl_ssi_startup,
1114 .shutdown = fsl_ssi_shutdown,
1115 .hw_params = fsl_ssi_hw_params,
1116 .hw_free = fsl_ssi_hw_free,
1117 .set_fmt = fsl_ssi_set_dai_fmt,
1118 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1119 .trigger = fsl_ssi_trigger,
1122 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1123 .probe = fsl_ssi_dai_probe,
1125 .stream_name = "CPU-Playback",
1128 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1129 .formats = FSLSSI_I2S_FORMATS,
1132 .stream_name = "CPU-Capture",
1135 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1136 .formats = FSLSSI_I2S_FORMATS,
1138 .ops = &fsl_ssi_dai_ops,
1141 static const struct snd_soc_component_driver fsl_ssi_component = {
1145 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1146 .bus_control = true,
1147 .symmetric_channels = 1,
1148 .probe = fsl_ssi_dai_probe,
1150 .stream_name = "AC97 Playback",
1153 .rates = SNDRV_PCM_RATE_8000_48000,
1154 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
1157 .stream_name = "AC97 Capture",
1160 .rates = SNDRV_PCM_RATE_48000,
1161 /* 16-bit capture is broken (errata ERR003778) */
1162 .formats = SNDRV_PCM_FMTBIT_S20,
1164 .ops = &fsl_ssi_dai_ops,
1167 static struct fsl_ssi *fsl_ac97_data;
1169 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1172 struct regmap *regs = fsl_ac97_data->regs;
1180 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1182 ret = clk_prepare_enable(fsl_ac97_data->clk);
1184 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1190 regmap_write(regs, REG_SSI_SACADD, lreg);
1193 regmap_write(regs, REG_SSI_SACDAT, lval);
1195 regmap_update_bits(regs, REG_SSI_SACNT,
1196 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
1199 clk_disable_unprepare(fsl_ac97_data->clk);
1202 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1205 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1208 struct regmap *regs = fsl_ac97_data->regs;
1209 unsigned short val = 0;
1214 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1216 ret = clk_prepare_enable(fsl_ac97_data->clk);
1218 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1222 lreg = (reg & 0x7f) << 12;
1223 regmap_write(regs, REG_SSI_SACADD, lreg);
1224 regmap_update_bits(regs, REG_SSI_SACNT,
1225 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
1229 regmap_read(regs, REG_SSI_SACDAT, ®_val);
1230 val = (reg_val >> 4) & 0xffff;
1232 clk_disable_unprepare(fsl_ac97_data->clk);
1235 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1239 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1240 .read = fsl_ssi_ac97_read,
1241 .write = fsl_ssi_ac97_write,
1245 * Initialize SSI registers
1247 static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1249 u32 wm = ssi->fifo_watermark;
1251 /* Initialize regvals */
1252 fsl_ssi_setup_regvals(ssi);
1254 /* Set watermarks */
1255 regmap_write(ssi->regs, REG_SSI_SFCSR,
1256 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1257 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1259 /* Enable Dual FIFO mode */
1260 if (ssi->use_dual_fifo)
1261 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1262 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
1264 /* AC97 should start earlier to communicate with CODECs */
1265 if (fsl_ssi_is_ac97(ssi)) {
1266 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1267 fsl_ssi_setup_ac97(ssi);
1274 * Clear SSI registers
1276 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1278 /* Disable registers for AC97 */
1279 if (fsl_ssi_is_ac97(ssi)) {
1280 /* Disable TE and RE bits first */
1281 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1282 SSI_SCR_TE | SSI_SCR_RE, 0);
1283 /* Disable AC97 mode */
1284 regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1285 /* Unset WAIT bits */
1286 regmap_write(ssi->regs, REG_SSI_SOR, 0);
1287 /* Disable SSI -- software reset */
1288 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1292 * Make every character in a string lower-case
1294 static void make_lowercase(char *s)
1302 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1303 struct fsl_ssi *ssi, void __iomem *iomem)
1305 struct device *dev = &pdev->dev;
1308 /* Backward compatible for a DT without ipg clock name assigned */
1309 if (ssi->has_ipg_clk_name)
1310 ssi->clk = devm_clk_get(dev, "ipg");
1312 ssi->clk = devm_clk_get(dev, NULL);
1313 if (IS_ERR(ssi->clk)) {
1314 ret = PTR_ERR(ssi->clk);
1315 dev_err(dev, "failed to get clock: %d\n", ret);
1319 /* Enable the clock since regmap will not handle it in this case */
1320 if (!ssi->has_ipg_clk_name) {
1321 ret = clk_prepare_enable(ssi->clk);
1323 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1328 /* Do not error out for slave cases that live without a baud clock */
1329 ssi->baudclk = devm_clk_get(dev, "baud");
1330 if (IS_ERR(ssi->baudclk))
1331 dev_dbg(dev, "failed to get baud clock: %ld\n",
1332 PTR_ERR(ssi->baudclk));
1334 ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1335 ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1336 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1337 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1339 /* Use even numbers to avoid channel swap due to SDMA script design */
1340 if (ssi->use_dual_fifo) {
1341 ssi->dma_params_tx.maxburst &= ~0x1;
1342 ssi->dma_params_rx.maxburst &= ~0x1;
1345 if (!ssi->use_dma) {
1347 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
1348 * to get it working, as DMA is not possible in this situation.
1350 ssi->fiq_params.irq = ssi->irq;
1351 ssi->fiq_params.base = iomem;
1352 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1353 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1355 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1359 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1367 if (!ssi->has_ipg_clk_name)
1368 clk_disable_unprepare(ssi->clk);
1373 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1376 imx_pcm_fiq_exit(pdev);
1377 if (!ssi->has_ipg_clk_name)
1378 clk_disable_unprepare(ssi->clk);
1381 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1383 struct device *dev = ssi->dev;
1384 struct device_node *np = dev->of_node;
1385 const struct of_device_id *of_id;
1386 const char *p, *sprop;
1387 const __be32 *iprop;
1391 of_id = of_match_device(fsl_ssi_ids, dev);
1392 if (!of_id || !of_id->data)
1395 ssi->soc = of_id->data;
1397 ret = of_property_match_string(np, "clock-names", "ipg");
1398 /* Get error code if not found */
1399 ssi->has_ipg_clk_name = ret >= 0;
1401 /* Check if being used in AC97 mode */
1402 sprop = of_get_property(np, "fsl,mode", NULL);
1403 if (sprop && !strcmp(sprop, "ac97-slave")) {
1404 ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1406 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1408 dev_err(dev, "failed to get SSI index property\n");
1411 strcpy(ssi->card_name, "ac97-codec");
1412 } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1414 * In synchronous mode, STCK and STFS ports are used by RX
1415 * as well. So the software should limit the sample rates,
1416 * sample bits and channels to be symmetric.
1418 * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
1419 * in the SSI synchronous mode however it does not have to
1420 * limit symmetric sample rates and sample bits.
1422 ssi->synchronous = true;
1425 /* Select DMA or FIQ */
1426 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1428 /* Fetch FIFO depth; Set to 8 for older DT without this property */
1429 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1431 ssi->fifo_depth = be32_to_cpup(iprop);
1433 ssi->fifo_depth = 8;
1435 /* Use dual FIFO mode depending on the support from SDMA script */
1436 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1437 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1438 ssi->use_dual_fifo = true;
1441 * Backward compatible for older bindings by manually triggering the
1442 * machine driver's probe(). Use /compatible property, including the
1443 * address of CPU DAI driver structure, as the name of machine driver
1445 * If card_name is set by AC97 earlier, bypass here since it uses a
1446 * different name to register the device.
1448 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1449 struct device_node *root = of_find_node_by_path("/");
1451 sprop = of_get_property(root, "compatible", NULL);
1453 /* Strip "fsl," in the compatible name if applicable */
1454 p = strrchr(sprop, ',');
1457 snprintf(ssi->card_name, sizeof(ssi->card_name),
1458 "snd-soc-%s", sprop);
1459 make_lowercase(ssi->card_name);
1466 static int fsl_ssi_probe(struct platform_device *pdev)
1468 struct regmap_config regconfig = fsl_ssi_regconfig;
1469 struct device *dev = &pdev->dev;
1470 struct fsl_ssi *ssi;
1471 struct resource *res;
1472 void __iomem *iomem;
1475 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1482 ret = fsl_ssi_probe_from_dt(ssi);
1486 if (fsl_ssi_is_ac97(ssi)) {
1487 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1488 sizeof(fsl_ssi_ac97_dai));
1489 fsl_ac97_data = ssi;
1491 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1492 sizeof(fsl_ssi_dai_template));
1494 ssi->cpu_dai_drv.name = dev_name(dev);
1496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1497 iomem = devm_ioremap_resource(dev, res);
1499 return PTR_ERR(iomem);
1500 ssi->ssi_phys = res->start;
1502 if (ssi->soc->imx21regs) {
1503 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
1504 regconfig.max_register = REG_SSI_SRMSK;
1505 regconfig.num_reg_defaults_raw =
1506 REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1509 if (ssi->has_ipg_clk_name)
1510 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1513 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
1514 if (IS_ERR(ssi->regs)) {
1515 dev_err(dev, "failed to init register map\n");
1516 return PTR_ERR(ssi->regs);
1519 ssi->irq = platform_get_irq(pdev, 0);
1521 dev_err(dev, "no irq for node %s\n", pdev->name);
1525 /* Set software limitations for synchronous mode except AC97 */
1526 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1527 ssi->cpu_dai_drv.symmetric_rates = 1;
1528 ssi->cpu_dai_drv.symmetric_channels = 1;
1529 ssi->cpu_dai_drv.symmetric_samplebits = 1;
1533 * Configure TX and RX DMA watermarks -- when to send a DMA request
1535 * Values should be tested to avoid FIFO under/over run. Set maxburst
1536 * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
1538 switch (ssi->fifo_depth) {
1541 * Set to 8 as a balanced configuration -- When TX FIFO has 8
1542 * empty slots, send a DMA request to fill these 8 slots. The
1543 * remaining 7 slots should be able to allow DMA to finish the
1544 * transaction before TX FIFO underruns; Same applies to RX.
1546 * Tested with cases running at 48kHz @ 16 bits x 16 channels
1548 ssi->fifo_watermark = 8;
1549 ssi->dma_maxburst = 8;
1553 /* Safely use old watermark configurations for older chips */
1554 ssi->fifo_watermark = ssi->fifo_depth - 2;
1555 ssi->dma_maxburst = ssi->fifo_depth - 2;
1559 dev_set_drvdata(dev, ssi);
1561 if (ssi->soc->imx) {
1562 ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1567 if (fsl_ssi_is_ac97(ssi)) {
1568 mutex_init(&ssi->ac97_reg_lock);
1569 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1571 dev_err(dev, "failed to set AC'97 ops\n");
1572 goto error_ac97_ops;
1576 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1577 &ssi->cpu_dai_drv, 1);
1579 dev_err(dev, "failed to register DAI: %d\n", ret);
1580 goto error_asoc_register;
1584 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1585 dev_name(dev), ssi);
1587 dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1588 goto error_asoc_register;
1592 ret = fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1594 goto error_asoc_register;
1596 /* Initially configures SSI registers */
1597 fsl_ssi_hw_init(ssi);
1599 /* Register a platform device for older bindings or AC97 */
1600 if (ssi->card_name[0]) {
1601 struct device *parent = dev;
1603 * Do not set SSI dev as the parent of AC97 CODEC device since
1604 * it does not have a DT node. Otherwise ASoC core will assume
1605 * CODEC has the same DT node as the SSI, so it may bypass the
1606 * dai_probe() of SSI and then cause NULL DMA data pointers.
1608 if (fsl_ssi_is_ac97(ssi))
1611 ssi->card_pdev = platform_device_register_data(parent,
1612 ssi->card_name, ssi->card_idx, NULL, 0);
1613 if (IS_ERR(ssi->card_pdev)) {
1614 ret = PTR_ERR(ssi->card_pdev);
1615 dev_err(dev, "failed to register %s: %d\n",
1616 ssi->card_name, ret);
1617 goto error_sound_card;
1624 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1625 error_asoc_register:
1626 if (fsl_ssi_is_ac97(ssi))
1627 snd_soc_set_ac97_ops(NULL);
1629 if (fsl_ssi_is_ac97(ssi))
1630 mutex_destroy(&ssi->ac97_reg_lock);
1633 fsl_ssi_imx_clean(pdev, ssi);
1638 static int fsl_ssi_remove(struct platform_device *pdev)
1640 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1642 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1645 platform_device_unregister(ssi->card_pdev);
1647 /* Clean up SSI registers */
1648 fsl_ssi_hw_clean(ssi);
1651 fsl_ssi_imx_clean(pdev, ssi);
1653 if (fsl_ssi_is_ac97(ssi)) {
1654 snd_soc_set_ac97_ops(NULL);
1655 mutex_destroy(&ssi->ac97_reg_lock);
1661 #ifdef CONFIG_PM_SLEEP
1662 static int fsl_ssi_suspend(struct device *dev)
1664 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1665 struct regmap *regs = ssi->regs;
1667 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1668 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1670 regcache_cache_only(regs, true);
1671 regcache_mark_dirty(regs);
1676 static int fsl_ssi_resume(struct device *dev)
1678 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1679 struct regmap *regs = ssi->regs;
1681 regcache_cache_only(regs, false);
1683 regmap_update_bits(regs, REG_SSI_SFCSR,
1684 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1685 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1686 ssi->regcache_sfcsr);
1687 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1689 return regcache_sync(regs);
1691 #endif /* CONFIG_PM_SLEEP */
1693 static const struct dev_pm_ops fsl_ssi_pm = {
1694 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1697 static struct platform_driver fsl_ssi_driver = {
1699 .name = "fsl-ssi-dai",
1700 .of_match_table = fsl_ssi_ids,
1703 .probe = fsl_ssi_probe,
1704 .remove = fsl_ssi_remove,
1707 module_platform_driver(fsl_ssi_driver);
1709 MODULE_ALIAS("platform:fsl-ssi-dai");
1710 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1711 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1712 MODULE_LICENSE("GPL v2");