2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val {
110 struct fsl_ssi_rxtx_reg_val {
111 struct fsl_ssi_reg_val rx;
112 struct fsl_ssi_reg_val tx;
115 static const struct reg_default fsl_ssi_reg_defaults[] = {
129 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
132 case CCSR_SSI_SACCEN:
133 case CCSR_SSI_SACCDIS:
140 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
150 case CCSR_SSI_SACADD:
151 case CCSR_SSI_SACDAT:
153 case CCSR_SSI_SACCST:
160 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
165 case CCSR_SSI_SACCST:
172 static const struct regmap_config fsl_ssi_regconfig = {
173 .max_register = CCSR_SSI_SACCDIS,
177 .val_format_endian = REGMAP_ENDIAN_NATIVE,
178 .reg_defaults = fsl_ssi_reg_defaults,
179 .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
180 .readable_reg = fsl_ssi_readable_reg,
181 .volatile_reg = fsl_ssi_volatile_reg,
182 .writeable_reg = fsl_ssi_writeable_reg,
183 .cache_type = REGCACHE_RBTREE,
186 struct fsl_ssi_soc_data {
193 * fsl_ssi_private: per-SSI private data
195 * @reg: Pointer to the regmap registers
196 * @irq: IRQ of this SSI
197 * @cpu_dai_drv: CPU DAI driver for this device
199 * @dai_fmt: DAI configuration this device is currently used with
200 * @i2s_mode: i2s and network mode configuration of the device. Is used to
201 * switch between normal and i2s/network mode
202 * mode depending on the number of channels
203 * @use_dma: DMA is used or FIQ with stream filter
204 * @use_dual_fifo: DMA with support for both FIFOs used
205 * @fifo_deph: Depth of the SSI FIFOs
206 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
209 * @baudclk: SSI baud clock for master mode
210 * @baudclk_streams: Active streams that are using baudclk
211 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
213 * @dma_params_tx: DMA transmit parameters
214 * @dma_params_rx: DMA receive parameters
215 * @ssi_phys: physical address of the SSI registers
217 * @fiq_params: FIQ stream filtering parameters
219 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
221 * @dbg_stats: Debugging statistics
223 * @soc: SoC specific data
225 struct fsl_ssi_private {
228 struct snd_soc_dai_driver cpu_dai_drv;
230 unsigned int dai_fmt;
234 bool has_ipg_clk_name;
235 unsigned int fifo_depth;
236 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
240 unsigned int baudclk_streams;
241 unsigned int bitclk_freq;
243 /* regcache for volatile regs */
248 struct snd_dmaengine_dai_dma_data dma_params_tx;
249 struct snd_dmaengine_dai_dma_data dma_params_rx;
252 /* params for non-dma FIQ stream filtered mode */
253 struct imx_pcm_fiq_params fiq_params;
255 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
256 * should be replaced with simple-sound-card. */
257 struct platform_device *pdev;
259 struct fsl_ssi_dbg dbg_stats;
261 const struct fsl_ssi_soc_data *soc;
265 * imx51 and later SoCs have a slightly different IP that allows the
266 * SSI configuration while the SSI unit is running.
268 * More important, it is necessary on those SoCs to configure the
269 * sperate TX/RX DMA bits just before starting the stream
270 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
271 * sends any DMA requests to the SDMA unit, otherwise it is not defined
272 * how the SDMA unit handles the DMA request.
274 * SDMA units are present on devices starting at imx35 but the imx35
275 * reference manual states that the DMA bits should not be changed
276 * while the SSI unit is running (SSIEN). So we support the necessary
277 * online configuration of fsl-ssi starting at imx51.
280 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
282 .offline_config = true,
283 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
284 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
285 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
288 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
290 .offline_config = true,
291 .sisr_write_mask = 0,
294 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
296 .offline_config = true,
297 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
298 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
299 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
302 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
304 .offline_config = false,
305 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
306 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
309 static const struct of_device_id fsl_ssi_ids[] = {
310 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
311 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
312 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
313 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
316 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
318 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
320 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
324 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
326 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
327 SND_SOC_DAIFMT_CBS_CFS;
330 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
332 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
333 SND_SOC_DAIFMT_CBM_CFS;
336 * fsl_ssi_isr: SSI interrupt handler
338 * Although it's possible to use the interrupt handler to send and receive
339 * data to/from the SSI, we use the DMA instead. Programming is more
340 * complicated, but the performance is much better.
342 * This interrupt handler is used only to gather statistics.
344 * @irq: IRQ of the SSI device
345 * @dev_id: pointer to the ssi_private structure for this SSI device
347 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
349 struct fsl_ssi_private *ssi_private = dev_id;
350 struct regmap *regs = ssi_private->regs;
354 /* We got an interrupt, so read the status register to see what we
355 were interrupted for. We mask it with the Interrupt Enable register
356 so that we only check for events that we're interested in.
358 regmap_read(regs, CCSR_SSI_SISR, &sisr);
360 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
361 /* Clear the bits that we set */
363 regmap_write(regs, CCSR_SSI_SISR, sisr2);
365 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
371 * Enable/Disable all rx/tx config flags at once.
373 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
376 struct regmap *regs = ssi_private->regs;
377 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
380 regmap_update_bits(regs, CCSR_SSI_SIER,
381 vals->rx.sier | vals->tx.sier,
382 vals->rx.sier | vals->tx.sier);
383 regmap_update_bits(regs, CCSR_SSI_SRCR,
384 vals->rx.srcr | vals->tx.srcr,
385 vals->rx.srcr | vals->tx.srcr);
386 regmap_update_bits(regs, CCSR_SSI_STCR,
387 vals->rx.stcr | vals->tx.stcr,
388 vals->rx.stcr | vals->tx.stcr);
390 regmap_update_bits(regs, CCSR_SSI_SRCR,
391 vals->rx.srcr | vals->tx.srcr, 0);
392 regmap_update_bits(regs, CCSR_SSI_STCR,
393 vals->rx.stcr | vals->tx.stcr, 0);
394 regmap_update_bits(regs, CCSR_SSI_SIER,
395 vals->rx.sier | vals->tx.sier, 0);
400 * Calculate the bits that have to be disabled for the current stream that is
401 * getting disabled. This keeps the bits enabled that are necessary for the
402 * second stream to work if 'stream_active' is true.
404 * Detailed calculation:
405 * These are the values that need to be active after disabling. For non-active
406 * second stream, this is 0:
407 * vals_stream * !!stream_active
409 * The following computes the overall differences between the setup for the
410 * to-disable stream and the active stream, a simple XOR:
411 * vals_disable ^ (vals_stream * !!(stream_active))
413 * The full expression adds a mask on all values we care about
415 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
417 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
420 * Enable/Disable a ssi configuration. You have to pass either
421 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
423 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
424 struct fsl_ssi_reg_val *vals)
426 struct regmap *regs = ssi_private->regs;
427 struct fsl_ssi_reg_val *avals;
428 int nr_active_streams;
432 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
434 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
435 !!(scr_val & CCSR_SSI_SCR_RE);
437 if (nr_active_streams - 1 > 0)
442 /* Find the other direction values rx or tx which we do not want to
444 if (&ssi_private->rxtx_reg_val.rx == vals)
445 avals = &ssi_private->rxtx_reg_val.tx;
447 avals = &ssi_private->rxtx_reg_val.rx;
449 /* If vals should be disabled, start with disabling the unit */
451 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
453 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
457 * We are running on a SoC which does not support online SSI
458 * reconfiguration, so we have to enable all necessary flags at once
459 * even if we do not use them later (capture and playback configuration)
461 if (ssi_private->soc->offline_config) {
462 if ((enable && !nr_active_streams) ||
463 (!enable && !keep_active))
464 fsl_ssi_rxtx_config(ssi_private, enable);
470 * Configure single direction units while the SSI unit is running
471 * (online configuration)
474 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
475 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
476 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
483 * Disabling the necessary flags for one of rx/tx while the
484 * other stream is active is a little bit more difficult. We
485 * have to disable only those flags that differ between both
486 * streams (rx XOR tx) and that are set in the stream that is
487 * disabled now. Otherwise we could alter flags of the other
491 /* These assignments are simply vals without bits set in avals*/
492 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
494 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
496 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
499 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
500 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
501 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
505 /* Enabling of subunits is done after configuration */
507 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
511 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
513 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
516 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
518 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
522 * Setup rx/tx register values used to enable/disable the streams. These will
523 * be used later in fsl_ssi_config to setup the streams without the need to
524 * check for all different SSI modes.
526 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
528 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
530 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
531 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
533 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
534 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
537 if (!fsl_ssi_is_ac97(ssi_private)) {
538 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
539 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
540 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
541 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
544 if (ssi_private->use_dma) {
545 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
546 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
548 reg->rx.sier |= CCSR_SSI_SIER_RIE;
549 reg->tx.sier |= CCSR_SSI_SIER_TIE;
552 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
553 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
556 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
558 struct regmap *regs = ssi_private->regs;
561 * Setup the clock control register
563 regmap_write(regs, CCSR_SSI_STCCR,
564 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
565 regmap_write(regs, CCSR_SSI_SRCCR,
566 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
569 * Enable AC97 mode and startup the SSI
571 regmap_write(regs, CCSR_SSI_SACNT,
572 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
573 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
574 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
577 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
578 * codec before a stream is started.
580 regmap_update_bits(regs, CCSR_SSI_SCR,
581 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
582 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
584 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
588 * fsl_ssi_startup: create a new substream
590 * This is the first function called when a stream is opened.
592 * If this is the first stream open, then grab the IRQ and program most of
595 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
596 struct snd_soc_dai *dai)
598 struct snd_soc_pcm_runtime *rtd = substream->private_data;
599 struct fsl_ssi_private *ssi_private =
600 snd_soc_dai_get_drvdata(rtd->cpu_dai);
603 ret = clk_prepare_enable(ssi_private->clk);
607 /* When using dual fifo mode, it is safer to ensure an even period
608 * size. If appearing to an odd number while DMA always starts its
609 * task from fifo0, fifo1 would be neglected at the end of each
610 * period. But SSI would still access fifo1 with an invalid data.
612 if (ssi_private->use_dual_fifo)
613 snd_pcm_hw_constraint_step(substream->runtime, 0,
614 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
620 * fsl_ssi_shutdown: shutdown the SSI
623 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
624 struct snd_soc_dai *dai)
626 struct snd_soc_pcm_runtime *rtd = substream->private_data;
627 struct fsl_ssi_private *ssi_private =
628 snd_soc_dai_get_drvdata(rtd->cpu_dai);
630 clk_disable_unprepare(ssi_private->clk);
635 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
637 * Note: This function can be only called when using SSI as DAI master
639 * Quick instruction for parameters:
640 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
641 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
643 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
644 struct snd_soc_dai *cpu_dai,
645 struct snd_pcm_hw_params *hw_params)
647 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
648 struct regmap *regs = ssi_private->regs;
649 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
650 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
651 unsigned long clkrate, baudrate, tmprate;
652 u64 sub, savesub = 100000;
654 bool baudclk_is_used;
656 /* Prefer the explicitly set bitclock frequency */
657 if (ssi_private->bitclk_freq)
658 freq = ssi_private->bitclk_freq;
660 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
662 /* Don't apply it to any non-baudclk circumstance */
663 if (IS_ERR(ssi_private->baudclk))
666 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
668 /* It should be already enough to divide clock by setting pm alone */
672 factor = (div2 + 1) * (7 * psr + 1) * 2;
674 for (i = 0; i < 255; i++) {
675 tmprate = freq * factor * (i + 1);
678 clkrate = clk_get_rate(ssi_private->baudclk);
680 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
683 * Hardware limitation: The bclk rate must be
684 * never greater than 1/5 IPG clock rate
686 if (clkrate * 5 > clk_get_rate(ssi_private->clk))
690 afreq = clkrate / (i + 1);
694 else if (freq / afreq == 1)
696 else if (afreq / freq == 1)
701 /* Calculate the fraction */
705 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
716 /* No proper pm found if it is still remaining the initial value */
718 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
722 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
723 (psr ? CCSR_SSI_SxCCR_PSR : 0);
724 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
728 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
730 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
732 if (!baudclk_is_used) {
733 ret = clk_set_rate(ssi_private->baudclk, baudrate);
735 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
743 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
744 int clk_id, unsigned int freq, int dir)
746 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
748 ssi_private->bitclk_freq = freq;
754 * fsl_ssi_hw_params - program the sample size
756 * Most of the SSI registers have been programmed in the startup function,
757 * but the word length must be programmed here. Unfortunately, programming
758 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
759 * cause a problem with supporting simultaneous playback and capture. If
760 * the SSI is already playing a stream, then that stream may be temporarily
761 * stopped when you start capture.
763 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
766 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
767 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
769 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
770 struct regmap *regs = ssi_private->regs;
771 unsigned int channels = params_channels(hw_params);
772 unsigned int sample_size =
773 snd_pcm_format_width(params_format(hw_params));
774 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
779 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
780 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
783 * If we're in synchronous mode, and the SSI is already enabled,
784 * then STCCR is already set properly.
786 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
789 if (fsl_ssi_is_i2s_master(ssi_private)) {
790 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
794 /* Do not enable the clock if it is already enabled */
795 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
796 ret = clk_prepare_enable(ssi_private->baudclk);
800 ssi_private->baudclk_streams |= BIT(substream->stream);
804 if (!fsl_ssi_is_ac97(ssi_private)) {
807 * Switch to normal net mode in order to have a frame sync
808 * signal every 32 bits instead of 16 bits
810 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
811 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
814 i2smode = ssi_private->i2s_mode;
816 regmap_update_bits(regs, CCSR_SSI_SCR,
817 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
818 channels == 1 ? 0 : i2smode);
822 * FIXME: The documentation says that SxCCR[WL] should not be
823 * modified while the SSI is enabled. The only time this can
824 * happen is if we're trying to do simultaneous playback and
825 * capture in asynchronous mode. Unfortunately, I have been enable
826 * to get that to work at all on the P1022DS. Therefore, we don't
827 * bother to disable/enable the SSI when setting SxCCR[WL], because
828 * the SSI will stop anyway. Maybe one day, this will get fixed.
831 /* In synchronous mode, the SSI uses STCCR for capture */
832 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
833 ssi_private->cpu_dai_drv.symmetric_rates)
834 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
837 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
843 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
844 struct snd_soc_dai *cpu_dai)
846 struct snd_soc_pcm_runtime *rtd = substream->private_data;
847 struct fsl_ssi_private *ssi_private =
848 snd_soc_dai_get_drvdata(rtd->cpu_dai);
850 if (fsl_ssi_is_i2s_master(ssi_private) &&
851 ssi_private->baudclk_streams & BIT(substream->stream)) {
852 clk_disable_unprepare(ssi_private->baudclk);
853 ssi_private->baudclk_streams &= ~BIT(substream->stream);
859 static int _fsl_ssi_set_dai_fmt(struct device *dev,
860 struct fsl_ssi_private *ssi_private,
863 struct regmap *regs = ssi_private->regs;
864 u32 strcr = 0, stcr, srcr, scr, mask;
867 ssi_private->dai_fmt = fmt;
869 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
870 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
874 fsl_ssi_setup_reg_vals(ssi_private);
876 regmap_read(regs, CCSR_SSI_SCR, &scr);
877 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
878 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
880 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
881 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
883 regmap_read(regs, CCSR_SSI_STCR, &stcr);
884 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
888 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
889 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
890 case SND_SOC_DAIFMT_I2S:
891 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
892 case SND_SOC_DAIFMT_CBM_CFS:
893 case SND_SOC_DAIFMT_CBS_CFS:
894 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
895 regmap_update_bits(regs, CCSR_SSI_STCCR,
896 CCSR_SSI_SxCCR_DC_MASK,
897 CCSR_SSI_SxCCR_DC(2));
898 regmap_update_bits(regs, CCSR_SSI_SRCCR,
899 CCSR_SSI_SxCCR_DC_MASK,
900 CCSR_SSI_SxCCR_DC(2));
902 case SND_SOC_DAIFMT_CBM_CFM:
903 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
909 /* Data on rising edge of bclk, frame low, 1clk before data */
910 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
911 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
913 case SND_SOC_DAIFMT_LEFT_J:
914 /* Data on rising edge of bclk, frame high */
915 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
917 case SND_SOC_DAIFMT_DSP_A:
918 /* Data on rising edge of bclk, frame high, 1clk before data */
919 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
920 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
922 case SND_SOC_DAIFMT_DSP_B:
923 /* Data on rising edge of bclk, frame high */
924 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
925 CCSR_SSI_STCR_TXBIT0;
927 case SND_SOC_DAIFMT_AC97:
928 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
933 scr |= ssi_private->i2s_mode;
935 /* DAI clock inversion */
936 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
937 case SND_SOC_DAIFMT_NB_NF:
938 /* Nothing to do for both normal cases */
940 case SND_SOC_DAIFMT_IB_NF:
941 /* Invert bit clock */
942 strcr ^= CCSR_SSI_STCR_TSCKP;
944 case SND_SOC_DAIFMT_NB_IF:
945 /* Invert frame clock */
946 strcr ^= CCSR_SSI_STCR_TFSI;
948 case SND_SOC_DAIFMT_IB_IF:
949 /* Invert both clocks */
950 strcr ^= CCSR_SSI_STCR_TSCKP;
951 strcr ^= CCSR_SSI_STCR_TFSI;
957 /* DAI clock master masks */
958 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
959 case SND_SOC_DAIFMT_CBS_CFS:
960 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
961 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
963 case SND_SOC_DAIFMT_CBM_CFM:
964 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
966 case SND_SOC_DAIFMT_CBM_CFS:
967 strcr &= ~CCSR_SSI_STCR_TXDIR;
968 strcr |= CCSR_SSI_STCR_TFDIR;
969 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
972 if (!fsl_ssi_is_ac97(ssi_private))
979 if (ssi_private->cpu_dai_drv.symmetric_rates
980 || fsl_ssi_is_ac97(ssi_private)) {
981 /* Need to clear RXDIR when using SYNC or AC97 mode */
982 srcr &= ~CCSR_SSI_SRCR_RXDIR;
983 scr |= CCSR_SSI_SCR_SYN;
986 regmap_write(regs, CCSR_SSI_STCR, stcr);
987 regmap_write(regs, CCSR_SSI_SRCR, srcr);
988 regmap_write(regs, CCSR_SSI_SCR, scr);
991 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
992 * use FIFO 1. We program the transmit water to signal a DMA transfer
993 * if there are only two (or fewer) elements left in the FIFO. Two
994 * elements equals one frame (left channel, right channel). This value,
995 * however, depends on the depth of the transmit buffer.
997 * We set the watermark on the same level as the DMA burstsize. For
998 * fiq it is probably better to use the biggest possible watermark
1001 if (ssi_private->use_dma)
1002 wm = ssi_private->fifo_depth - 2;
1004 wm = ssi_private->fifo_depth;
1006 regmap_write(regs, CCSR_SSI_SFCSR,
1007 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1008 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1010 if (ssi_private->use_dual_fifo) {
1011 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1012 CCSR_SSI_SRCR_RFEN1);
1013 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1014 CCSR_SSI_STCR_TFEN1);
1015 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1016 CCSR_SSI_SCR_TCH_EN);
1019 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1020 fsl_ssi_setup_ac97(ssi_private);
1027 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1029 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1031 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1033 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1037 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1039 * Note: This function can be only called when using SSI as DAI master
1041 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1042 u32 rx_mask, int slots, int slot_width)
1044 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1045 struct regmap *regs = ssi_private->regs;
1048 /* The slot number should be >= 2 if using Network mode or I2S mode */
1049 regmap_read(regs, CCSR_SSI_SCR, &val);
1050 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1051 if (val && slots < 2) {
1052 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1056 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1057 CCSR_SSI_SxCCR_DC(slots));
1058 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1059 CCSR_SSI_SxCCR_DC(slots));
1061 /* The register SxMSKs needs SSI to provide essential clock due to
1062 * hardware design. So we here temporarily enable SSI to set them.
1064 regmap_read(regs, CCSR_SSI_SCR, &val);
1065 val &= CCSR_SSI_SCR_SSIEN;
1066 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1067 CCSR_SSI_SCR_SSIEN);
1069 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1070 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1072 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1078 * fsl_ssi_trigger: start and stop the DMA transfer.
1080 * This function is called by ALSA to start, stop, pause, and resume the DMA
1083 * The DMA channel is in external master start and pause mode, which
1084 * means the SSI completely controls the flow of data.
1086 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1087 struct snd_soc_dai *dai)
1089 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1090 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1091 struct regmap *regs = ssi_private->regs;
1094 case SNDRV_PCM_TRIGGER_START:
1095 case SNDRV_PCM_TRIGGER_RESUME:
1096 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1098 fsl_ssi_tx_config(ssi_private, true);
1100 fsl_ssi_rx_config(ssi_private, true);
1103 case SNDRV_PCM_TRIGGER_STOP:
1104 case SNDRV_PCM_TRIGGER_SUSPEND:
1105 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1107 fsl_ssi_tx_config(ssi_private, false);
1109 fsl_ssi_rx_config(ssi_private, false);
1116 if (fsl_ssi_is_ac97(ssi_private)) {
1117 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1118 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1120 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1126 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1128 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1130 if (ssi_private->soc->imx && ssi_private->use_dma) {
1131 dai->playback_dma_data = &ssi_private->dma_params_tx;
1132 dai->capture_dma_data = &ssi_private->dma_params_rx;
1138 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1139 .startup = fsl_ssi_startup,
1140 .shutdown = fsl_ssi_shutdown,
1141 .hw_params = fsl_ssi_hw_params,
1142 .hw_free = fsl_ssi_hw_free,
1143 .set_fmt = fsl_ssi_set_dai_fmt,
1144 .set_sysclk = fsl_ssi_set_dai_sysclk,
1145 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1146 .trigger = fsl_ssi_trigger,
1149 /* Template for the CPU dai driver structure */
1150 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1151 .probe = fsl_ssi_dai_probe,
1153 .stream_name = "CPU-Playback",
1156 .rates = FSLSSI_I2S_RATES,
1157 .formats = FSLSSI_I2S_FORMATS,
1160 .stream_name = "CPU-Capture",
1163 .rates = FSLSSI_I2S_RATES,
1164 .formats = FSLSSI_I2S_FORMATS,
1166 .ops = &fsl_ssi_dai_ops,
1169 static const struct snd_soc_component_driver fsl_ssi_component = {
1173 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1174 .bus_control = true,
1175 .probe = fsl_ssi_dai_probe,
1177 .stream_name = "AC97 Playback",
1180 .rates = SNDRV_PCM_RATE_8000_48000,
1181 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1184 .stream_name = "AC97 Capture",
1187 .rates = SNDRV_PCM_RATE_48000,
1188 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1190 .ops = &fsl_ssi_dai_ops,
1194 static struct fsl_ssi_private *fsl_ac97_data;
1196 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1199 struct regmap *regs = fsl_ac97_data->regs;
1207 ret = clk_prepare_enable(fsl_ac97_data->clk);
1209 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1215 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1218 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1220 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1224 clk_disable_unprepare(fsl_ac97_data->clk);
1227 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1230 struct regmap *regs = fsl_ac97_data->regs;
1232 unsigned short val = -1;
1237 ret = clk_prepare_enable(fsl_ac97_data->clk);
1239 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1244 lreg = (reg & 0x7f) << 12;
1245 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1246 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1251 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1252 val = (reg_val >> 4) & 0xffff;
1254 clk_disable_unprepare(fsl_ac97_data->clk);
1259 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1260 .read = fsl_ssi_ac97_read,
1261 .write = fsl_ssi_ac97_write,
1265 * Make every character in a string lower-case
1267 static void make_lowercase(char *s)
1273 if ((c >= 'A') && (c <= 'Z'))
1274 *p = c + ('a' - 'A');
1279 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1280 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1282 struct device_node *np = pdev->dev.of_node;
1286 if (ssi_private->has_ipg_clk_name)
1287 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1289 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1290 if (IS_ERR(ssi_private->clk)) {
1291 ret = PTR_ERR(ssi_private->clk);
1292 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1296 if (!ssi_private->has_ipg_clk_name) {
1297 ret = clk_prepare_enable(ssi_private->clk);
1299 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1304 /* For those SLAVE implementations, we ignore non-baudclk cases
1305 * and, instead, abandon MASTER mode that needs baud clock.
1307 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1308 if (IS_ERR(ssi_private->baudclk))
1309 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1310 PTR_ERR(ssi_private->baudclk));
1313 * We have burstsize be "fifo_depth - 2" to match the SSI
1314 * watermark setting in fsl_ssi_startup().
1316 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1317 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1318 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1319 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1321 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1322 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1323 ssi_private->use_dual_fifo = true;
1324 /* When using dual fifo mode, we need to keep watermark
1325 * as even numbers due to dma script limitation.
1327 ssi_private->dma_params_tx.maxburst &= ~0x1;
1328 ssi_private->dma_params_rx.maxburst &= ~0x1;
1331 if (!ssi_private->use_dma) {
1334 * Some boards use an incompatible codec. To get it
1335 * working, we are using imx-fiq-pcm-audio, that
1336 * can handle those codecs. DMA is not possible in this
1340 ssi_private->fiq_params.irq = ssi_private->irq;
1341 ssi_private->fiq_params.base = iomem;
1342 ssi_private->fiq_params.dma_params_rx =
1343 &ssi_private->dma_params_rx;
1344 ssi_private->fiq_params.dma_params_tx =
1345 &ssi_private->dma_params_tx;
1347 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1351 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1360 if (!ssi_private->has_ipg_clk_name)
1361 clk_disable_unprepare(ssi_private->clk);
1365 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1366 struct fsl_ssi_private *ssi_private)
1368 if (!ssi_private->use_dma)
1369 imx_pcm_fiq_exit(pdev);
1370 if (!ssi_private->has_ipg_clk_name)
1371 clk_disable_unprepare(ssi_private->clk);
1374 static int fsl_ssi_probe(struct platform_device *pdev)
1376 struct fsl_ssi_private *ssi_private;
1378 struct device_node *np = pdev->dev.of_node;
1379 struct device_node *root;
1380 const struct of_device_id *of_id;
1381 const char *p, *sprop;
1382 const uint32_t *iprop;
1383 struct resource *res;
1384 void __iomem *iomem;
1387 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1388 if (!of_id || !of_id->data)
1391 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1394 dev_err(&pdev->dev, "could not allocate DAI object\n");
1398 ssi_private->soc = of_id->data;
1400 sprop = of_get_property(np, "fsl,mode", NULL);
1402 if (!strcmp(sprop, "ac97-slave"))
1403 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1406 ssi_private->use_dma = !of_property_read_bool(np,
1407 "fsl,fiq-stream-filter");
1409 if (fsl_ssi_is_ac97(ssi_private)) {
1410 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1411 sizeof(fsl_ssi_ac97_dai));
1413 fsl_ac97_data = ssi_private;
1415 /* Initialize this copy of the CPU DAI driver structure */
1416 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1417 sizeof(fsl_ssi_dai_template));
1419 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1421 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1422 iomem = devm_ioremap_resource(&pdev->dev, res);
1424 return PTR_ERR(iomem);
1425 ssi_private->ssi_phys = res->start;
1427 ret = of_property_match_string(np, "clock-names", "ipg");
1429 ssi_private->has_ipg_clk_name = false;
1430 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1431 &fsl_ssi_regconfig);
1433 ssi_private->has_ipg_clk_name = true;
1434 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1435 "ipg", iomem, &fsl_ssi_regconfig);
1437 if (IS_ERR(ssi_private->regs)) {
1438 dev_err(&pdev->dev, "Failed to init register map\n");
1439 return PTR_ERR(ssi_private->regs);
1442 ssi_private->irq = platform_get_irq(pdev, 0);
1443 if (ssi_private->irq < 0) {
1444 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1445 return ssi_private->irq;
1448 /* Are the RX and the TX clocks locked? */
1449 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1450 if (!fsl_ssi_is_ac97(ssi_private))
1451 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1453 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1454 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1457 /* Determine the FIFO depth. */
1458 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1460 ssi_private->fifo_depth = be32_to_cpup(iprop);
1462 /* Older 8610 DTs didn't have the fifo-depth property */
1463 ssi_private->fifo_depth = 8;
1465 dev_set_drvdata(&pdev->dev, ssi_private);
1467 if (ssi_private->soc->imx) {
1468 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1473 if (fsl_ssi_is_ac97(ssi_private)) {
1474 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1476 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1477 goto error_ac97_ops;
1481 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1482 &ssi_private->cpu_dai_drv, 1);
1484 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1485 goto error_asoc_register;
1488 if (ssi_private->use_dma) {
1489 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1490 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1493 dev_err(&pdev->dev, "could not claim irq %u\n",
1495 goto error_asoc_register;
1499 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1501 goto error_asoc_register;
1504 * If codec-handle property is missing from SSI node, we assume
1505 * that the machine driver uses new binding which does not require
1506 * SSI driver to trigger machine driver's probe.
1508 if (!of_get_property(np, "codec-handle", NULL))
1511 /* Trigger the machine driver's probe function. The platform driver
1512 * name of the machine driver is taken from /compatible property of the
1513 * device tree. We also pass the address of the CPU DAI driver
1516 root = of_find_node_by_path("/");
1517 sprop = of_get_property(root, "compatible", NULL);
1519 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1520 p = strrchr(sprop, ',');
1523 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1524 make_lowercase(name);
1527 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1528 if (IS_ERR(ssi_private->pdev)) {
1529 ret = PTR_ERR(ssi_private->pdev);
1530 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1531 goto error_sound_card;
1535 if (ssi_private->dai_fmt)
1536 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1537 ssi_private->dai_fmt);
1539 if (fsl_ssi_is_ac97(ssi_private)) {
1542 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1544 dev_err(&pdev->dev, "cannot get SSI index property\n");
1545 goto error_sound_card;
1549 platform_device_register_data(NULL,
1550 "ac97-codec", ssi_idx, NULL, 0);
1551 if (IS_ERR(ssi_private->pdev)) {
1552 ret = PTR_ERR(ssi_private->pdev);
1554 "failed to register AC97 codec platform: %d\n",
1556 goto error_sound_card;
1563 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1565 error_asoc_register:
1566 if (fsl_ssi_is_ac97(ssi_private))
1567 snd_soc_set_ac97_ops(NULL);
1570 if (ssi_private->soc->imx)
1571 fsl_ssi_imx_clean(pdev, ssi_private);
1576 static int fsl_ssi_remove(struct platform_device *pdev)
1578 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1580 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1582 if (ssi_private->pdev)
1583 platform_device_unregister(ssi_private->pdev);
1585 if (ssi_private->soc->imx)
1586 fsl_ssi_imx_clean(pdev, ssi_private);
1588 if (fsl_ssi_is_ac97(ssi_private))
1589 snd_soc_set_ac97_ops(NULL);
1594 #ifdef CONFIG_PM_SLEEP
1595 static int fsl_ssi_suspend(struct device *dev)
1597 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1598 struct regmap *regs = ssi_private->regs;
1600 regmap_read(regs, CCSR_SSI_SFCSR,
1601 &ssi_private->regcache_sfcsr);
1602 regmap_read(regs, CCSR_SSI_SACNT,
1603 &ssi_private->regcache_sacnt);
1605 regcache_cache_only(regs, true);
1606 regcache_mark_dirty(regs);
1611 static int fsl_ssi_resume(struct device *dev)
1613 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1614 struct regmap *regs = ssi_private->regs;
1616 regcache_cache_only(regs, false);
1618 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1619 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1620 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1621 ssi_private->regcache_sfcsr);
1622 regmap_write(regs, CCSR_SSI_SACNT,
1623 ssi_private->regcache_sacnt);
1625 return regcache_sync(regs);
1627 #endif /* CONFIG_PM_SLEEP */
1629 static const struct dev_pm_ops fsl_ssi_pm = {
1630 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1633 static struct platform_driver fsl_ssi_driver = {
1635 .name = "fsl-ssi-dai",
1636 .of_match_table = fsl_ssi_ids,
1639 .probe = fsl_ssi_probe,
1640 .remove = fsl_ssi_remove,
1643 module_platform_driver(fsl_ssi_driver);
1645 MODULE_ALIAS("platform:fsl-ssi-dai");
1646 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1647 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1648 MODULE_LICENSE("GPL v2");