1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
20 #include <sound/asoundef.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/soc.h>
24 #include "fsl_spdif.h"
27 #define FSL_SPDIF_TXFIFO_WML 0x8
28 #define FSL_SPDIF_RXFIFO_WML 0x8
30 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
31 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
32 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
33 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
34 INT_LOSS_LOCK | INT_DPLL_LOCKED)
36 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
38 /* Index list for the values that has if (DPLL Locked) condition */
39 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
40 #define SRPC_NODPLL_START1 0x5
41 #define SRPC_NODPLL_START2 0xc
43 #define DEFAULT_RXCLK_SRC 1
46 * SPDIF control structure
47 * Defines channel status, subcode and Q sub
49 struct spdif_mixer_control {
50 /* spinlock to access control data */
53 /* IEC958 channel tx status bit */
54 unsigned char ch_status[4];
57 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
59 /* Q subcode part of user bits */
60 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
62 /* Buffer offset for U/Q */
66 /* Ready buffer index of the two buffers */
71 * fsl_spdif_priv: Freescale SPDIF private data
73 * @fsl_spdif_control: SPDIF control data
74 * @cpu_dai_drv: cpu dai driver
75 * @pdev: platform device pointer
76 * @regmap: regmap handler
77 * @dpll_locked: dpll lock flag
78 * @txrate: the best rates for playback
79 * @txclk_df: STC_TXCLK_DF dividers value for playback
80 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
81 * @txclk_src: STC_TXCLK_SRC values for playback
82 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
83 * @txclk: tx clock sources for playback
84 * @rxclk: rx clock sources for capture
85 * @coreclk: core clock for register access via DMA
86 * @sysclk: system clock for rx clock rate measurement
87 * @spbaclk: SPBA clock (optional, depending on SoC design)
88 * @dma_params_tx: DMA parameters for transmit channel
89 * @dma_params_rx: DMA parameters for receive channel
91 struct fsl_spdif_priv {
92 struct spdif_mixer_control fsl_spdif_control;
93 struct snd_soc_dai_driver cpu_dai_drv;
94 struct platform_device *pdev;
95 struct regmap *regmap;
97 u32 txrate[SPDIF_TXRATE_MAX];
98 u8 txclk_df[SPDIF_TXRATE_MAX];
99 u8 sysclk_df[SPDIF_TXRATE_MAX];
100 u8 txclk_src[SPDIF_TXRATE_MAX];
102 struct clk *txclk[SPDIF_TXRATE_MAX];
107 struct snd_dmaengine_dai_dma_data dma_params_tx;
108 struct snd_dmaengine_dai_dma_data dma_params_rx;
109 /* regcache for SRPC */
113 /* DPLL locked and lock loss interrupt handler */
114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
116 struct regmap *regmap = spdif_priv->regmap;
117 struct platform_device *pdev = spdif_priv->pdev;
120 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
121 locked &= SRPC_DPLL_LOCKED;
123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
124 locked ? "locked" : "loss lock");
126 spdif_priv->dpll_locked = locked ? true : false;
129 /* Receiver found illegal symbol interrupt handler */
130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
132 struct regmap *regmap = spdif_priv->regmap;
133 struct platform_device *pdev = spdif_priv->pdev;
135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
137 /* Clear illegal symbol if DPLL unlocked since no audio stream */
138 if (!spdif_priv->dpll_locked)
139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
142 /* U/Q Channel receive register full */
143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
146 struct regmap *regmap = spdif_priv->regmap;
147 struct platform_device *pdev = spdif_priv->pdev;
148 u32 *pos, size, val, reg;
153 size = SPDIF_UBITS_SIZE;
158 size = SPDIF_QSUB_SIZE;
162 dev_err(&pdev->dev, "unsupported channel name\n");
166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
168 if (*pos >= size * 2) {
170 } else if (unlikely((*pos % size) + 3 > size)) {
171 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
175 regmap_read(regmap, reg, &val);
176 ctrl->subcode[*pos++] = val >> 16;
177 ctrl->subcode[*pos++] = val >> 8;
178 ctrl->subcode[*pos++] = val;
181 /* U/Q Channel sync found */
182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
185 struct platform_device *pdev = spdif_priv->pdev;
187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
189 /* U/Q buffer reset */
193 /* Set ready to this buffer */
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
197 /* U/Q Channel framing error */
198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
201 struct regmap *regmap = spdif_priv->regmap;
202 struct platform_device *pdev = spdif_priv->pdev;
205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
207 /* Read U/Q data to clear the irq and do buffer reset */
208 regmap_read(regmap, REG_SPDIF_SRU, &val);
209 regmap_read(regmap, REG_SPDIF_SRQ, &val);
211 /* Drop this U/Q buffer */
217 /* Get spdif interrupt status and clear the interrupt */
218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
220 struct regmap *regmap = spdif_priv->regmap;
223 regmap_read(regmap, REG_SPDIF_SIS, &val);
224 regmap_read(regmap, REG_SPDIF_SIE, &val2);
226 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
231 static irqreturn_t spdif_isr(int irq, void *devid)
233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
234 struct platform_device *pdev = spdif_priv->pdev;
237 sis = spdif_intr_status_clear(spdif_priv);
239 if (sis & INT_DPLL_LOCKED)
240 spdif_irq_dpll_lock(spdif_priv);
242 if (sis & INT_TXFIFO_UNOV)
243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
245 if (sis & INT_TXFIFO_RESYNC)
246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
249 dev_dbg(&pdev->dev, "isr: cstatus new\n");
251 if (sis & INT_VAL_NOGOOD)
252 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
254 if (sis & INT_SYM_ERR)
255 spdif_irq_sym_error(spdif_priv);
257 if (sis & INT_BIT_ERR)
258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
260 if (sis & INT_URX_FUL)
261 spdif_irq_uqrx_full(spdif_priv, 'U');
263 if (sis & INT_URX_OV)
264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
266 if (sis & INT_QRX_FUL)
267 spdif_irq_uqrx_full(spdif_priv, 'Q');
269 if (sis & INT_QRX_OV)
270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
272 if (sis & INT_UQ_SYNC)
273 spdif_irq_uq_sync(spdif_priv);
275 if (sis & INT_UQ_ERR)
276 spdif_irq_uq_err(spdif_priv);
278 if (sis & INT_RXFIFO_UNOV)
279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
281 if (sis & INT_RXFIFO_RESYNC)
282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
284 if (sis & INT_LOSS_LOCK)
285 spdif_irq_dpll_lock(spdif_priv);
287 /* FIXME: Write Tx FIFO to clear TxEm */
289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
292 if (sis & INT_RXFIFO_FUL)
293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
300 struct regmap *regmap = spdif_priv->regmap;
301 u32 val, cycle = 1000;
303 regcache_cache_bypass(regmap, true);
305 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
308 * RESET bit would be cleared after finishing its reset procedure,
309 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
312 regmap_read(regmap, REG_SPDIF_SCR, &val);
313 } while ((val & SCR_SOFT_RESET) && cycle--);
315 regcache_cache_bypass(regmap, false);
316 regcache_mark_dirty(regmap);
317 regcache_sync(regmap);
325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
328 ctrl->ch_status[3] &= ~mask;
329 ctrl->ch_status[3] |= cstatus & mask;
332 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
335 struct regmap *regmap = spdif_priv->regmap;
336 struct platform_device *pdev = spdif_priv->pdev;
339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
340 (bitrev8(ctrl->ch_status[1]) << 8) |
341 bitrev8(ctrl->ch_status[2]);
342 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
346 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
347 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
352 /* Set SPDIF PhaseConfig register for rx clock */
353 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
354 enum spdif_gainsel gainsel, int dpll_locked)
356 struct regmap *regmap = spdif_priv->regmap;
357 u8 clksrc = spdif_priv->rxclk_src;
359 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
362 regmap_update_bits(regmap, REG_SPDIF_SRPC,
363 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
364 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
369 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
372 struct snd_soc_pcm_runtime *rtd = substream->private_data;
373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
375 struct regmap *regmap = spdif_priv->regmap;
376 struct platform_device *pdev = spdif_priv->pdev;
377 unsigned long csfs = 0;
379 u8 clk, txclk_df, sysclk_df;
382 switch (sample_rate) {
384 rate = SPDIF_TXRATE_32000;
385 csfs = IEC958_AES3_CON_FS_32000;
388 rate = SPDIF_TXRATE_44100;
389 csfs = IEC958_AES3_CON_FS_44100;
392 rate = SPDIF_TXRATE_48000;
393 csfs = IEC958_AES3_CON_FS_48000;
396 rate = SPDIF_TXRATE_96000;
397 csfs = IEC958_AES3_CON_FS_96000;
400 rate = SPDIF_TXRATE_192000;
401 csfs = IEC958_AES3_CON_FS_192000;
404 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
408 clk = spdif_priv->txclk_src[rate];
409 if (clk >= STC_TXCLK_SRC_MAX) {
410 dev_err(&pdev->dev, "tx clock source is out of range\n");
414 txclk_df = spdif_priv->txclk_df[rate];
416 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
420 sysclk_df = spdif_priv->sysclk_df[rate];
422 /* Don't mess up the clocks from other modules */
423 if (clk != STC_TXCLK_SPDIF_ROOT)
426 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
427 ret = clk_set_rate(spdif_priv->txclk[rate],
428 64 * sample_rate * txclk_df);
430 dev_err(&pdev->dev, "failed to set tx clock rate\n");
435 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
436 (64 * sample_rate * txclk_df * sysclk_df));
437 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
438 clk_get_rate(spdif_priv->txclk[rate]));
440 /* set fs field in consumer channel status */
441 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
443 /* select clock source and divisor */
444 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
445 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
446 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
447 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
448 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
450 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
451 spdif_priv->txrate[rate], sample_rate);
456 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
457 struct snd_soc_dai *cpu_dai)
459 struct snd_soc_pcm_runtime *rtd = substream->private_data;
460 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
461 struct platform_device *pdev = spdif_priv->pdev;
462 struct regmap *regmap = spdif_priv->regmap;
467 /* Reset module and interrupts only for first initialization */
468 if (!cpu_dai->active) {
469 ret = clk_prepare_enable(spdif_priv->coreclk);
471 dev_err(&pdev->dev, "failed to enable core clock\n");
475 if (!IS_ERR(spdif_priv->spbaclk)) {
476 ret = clk_prepare_enable(spdif_priv->spbaclk);
478 dev_err(&pdev->dev, "failed to enable spba clock\n");
483 ret = spdif_softreset(spdif_priv);
485 dev_err(&pdev->dev, "failed to soft reset\n");
489 /* Disable all the interrupts */
490 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
494 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
495 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
497 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
498 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
499 SCR_TXFIFO_FSEL_MASK;
500 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
501 ret = clk_prepare_enable(spdif_priv->txclk[i]);
506 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
507 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
508 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
509 ret = clk_prepare_enable(spdif_priv->rxclk);
513 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
515 /* Power up SPDIF module */
516 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
521 for (i--; i >= 0; i--)
522 clk_disable_unprepare(spdif_priv->txclk[i]);
524 if (!IS_ERR(spdif_priv->spbaclk))
525 clk_disable_unprepare(spdif_priv->spbaclk);
527 clk_disable_unprepare(spdif_priv->coreclk);
532 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
533 struct snd_soc_dai *cpu_dai)
535 struct snd_soc_pcm_runtime *rtd = substream->private_data;
536 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
537 struct regmap *regmap = spdif_priv->regmap;
540 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
542 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
543 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
544 SCR_TXFIFO_FSEL_MASK;
545 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
546 clk_disable_unprepare(spdif_priv->txclk[i]);
548 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
549 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
550 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
551 clk_disable_unprepare(spdif_priv->rxclk);
553 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
555 /* Power down SPDIF module only if tx&rx are both inactive */
556 if (!cpu_dai->active) {
557 spdif_intr_status_clear(spdif_priv);
558 regmap_update_bits(regmap, REG_SPDIF_SCR,
559 SCR_LOW_POWER, SCR_LOW_POWER);
560 if (!IS_ERR(spdif_priv->spbaclk))
561 clk_disable_unprepare(spdif_priv->spbaclk);
562 clk_disable_unprepare(spdif_priv->coreclk);
566 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
567 struct snd_pcm_hw_params *params,
568 struct snd_soc_dai *dai)
570 struct snd_soc_pcm_runtime *rtd = substream->private_data;
571 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
572 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
573 struct platform_device *pdev = spdif_priv->pdev;
574 u32 sample_rate = params_rate(params);
577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
578 ret = spdif_set_sample_rate(substream, sample_rate);
580 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
581 __func__, sample_rate);
584 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
585 IEC958_AES3_CON_CLOCK_1000PPM);
586 spdif_write_channel_status(spdif_priv);
588 /* Setup rx clock source */
589 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
595 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
596 int cmd, struct snd_soc_dai *dai)
598 struct snd_soc_pcm_runtime *rtd = substream->private_data;
599 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
600 struct regmap *regmap = spdif_priv->regmap;
601 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
602 u32 intr = SIE_INTR_FOR(tx);
603 u32 dmaen = SCR_DMA_xX_EN(tx);
606 case SNDRV_PCM_TRIGGER_START:
607 case SNDRV_PCM_TRIGGER_RESUME:
608 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
609 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
610 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
612 case SNDRV_PCM_TRIGGER_STOP:
613 case SNDRV_PCM_TRIGGER_SUSPEND:
614 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
615 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
616 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
617 regmap_write(regmap, REG_SPDIF_STL, 0x0);
618 regmap_write(regmap, REG_SPDIF_STR, 0x0);
627 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
628 .startup = fsl_spdif_startup,
629 .hw_params = fsl_spdif_hw_params,
630 .trigger = fsl_spdif_trigger,
631 .shutdown = fsl_spdif_shutdown,
636 * FSL SPDIF IEC958 controller(mixer) functions
638 * Channel status get/put control
639 * User bit value get/put control
640 * Valid bit value get control
641 * DPLL lock status get control
642 * User bit sync mode selection control
645 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
646 struct snd_ctl_elem_info *uinfo)
648 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
654 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
655 struct snd_ctl_elem_value *uvalue)
657 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
658 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
659 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
661 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
662 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
663 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
664 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
669 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
670 struct snd_ctl_elem_value *uvalue)
672 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
673 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
674 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
676 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
677 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
678 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
679 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
681 spdif_write_channel_status(spdif_priv);
686 /* Get channel status from SPDIF_RX_CCHAN register */
687 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
688 struct snd_ctl_elem_value *ucontrol)
690 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
691 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
692 struct regmap *regmap = spdif_priv->regmap;
695 regmap_read(regmap, REG_SPDIF_SIS, &val);
696 if (!(val & INT_CNEW))
699 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
700 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
701 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
702 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
704 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
705 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
706 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
707 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
710 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
716 * Get User bits (subcode) from chip value which readed out
717 * in UChannel register.
719 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
720 struct snd_ctl_elem_value *ucontrol)
722 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
723 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
724 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
728 spin_lock_irqsave(&ctrl->ctl_lock, flags);
729 if (ctrl->ready_buf) {
730 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
731 memcpy(&ucontrol->value.iec958.subcode[0],
732 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
735 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
740 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
741 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
742 struct snd_ctl_elem_info *uinfo)
744 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
745 uinfo->count = SPDIF_QSUB_SIZE;
750 /* Get Q subcode from chip value which readed out in QChannel register */
751 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_value *ucontrol)
754 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
755 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
756 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
760 spin_lock_irqsave(&ctrl->ctl_lock, flags);
761 if (ctrl->ready_buf) {
762 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
763 memcpy(&ucontrol->value.bytes.data[0],
764 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
767 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
772 /* Valid bit information */
773 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
774 struct snd_ctl_elem_info *uinfo)
776 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
778 uinfo->value.integer.min = 0;
779 uinfo->value.integer.max = 1;
784 /* Get valid good bit from interrupt status register */
785 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
786 struct snd_ctl_elem_value *ucontrol)
788 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
789 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
790 struct regmap *regmap = spdif_priv->regmap;
793 regmap_read(regmap, REG_SPDIF_SIS, &val);
794 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
795 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
800 /* DPLL lock information */
801 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_info *uinfo)
804 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
806 uinfo->value.integer.min = 16000;
807 uinfo->value.integer.max = 96000;
812 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
813 24, 16, 12, 8, 6, 4, 3,
816 /* Get RX data clock rate given the SPDIF bus_clk */
817 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
818 enum spdif_gainsel gainsel)
820 struct regmap *regmap = spdif_priv->regmap;
821 struct platform_device *pdev = spdif_priv->pdev;
822 u64 tmpval64, busclk_freq = 0;
823 u32 freqmeas, phaseconf;
826 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
827 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
829 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
831 /* Get bus clock from system */
832 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
833 busclk_freq = clk_get_rate(spdif_priv->sysclk);
835 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
836 tmpval64 = (u64) busclk_freq * freqmeas;
837 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
838 do_div(tmpval64, 128 * 1024);
840 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
841 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
842 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
844 return (int)tmpval64;
848 * Get DPLL lock or not info from stable interrupt status register.
849 * User application must use this control to get locked,
850 * then can do next PCM operation
852 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
853 struct snd_ctl_elem_value *ucontrol)
855 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
856 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
859 if (spdif_priv->dpll_locked)
860 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
862 ucontrol->value.integer.value[0] = rate;
867 /* User bit sync mode info */
868 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
869 struct snd_ctl_elem_info *uinfo)
871 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
873 uinfo->value.integer.min = 0;
874 uinfo->value.integer.max = 1;
880 * User bit sync mode:
881 * 1 CD User channel subcode
884 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
885 struct snd_ctl_elem_value *ucontrol)
887 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
888 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
889 struct regmap *regmap = spdif_priv->regmap;
892 regmap_read(regmap, REG_SPDIF_SRCD, &val);
893 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
899 * User bit sync mode:
900 * 1 CD User channel subcode
903 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
904 struct snd_ctl_elem_value *ucontrol)
906 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
907 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
908 struct regmap *regmap = spdif_priv->regmap;
909 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
911 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
916 /* FSL SPDIF IEC958 controller defines */
917 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
918 /* Status cchanel controller */
920 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
921 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
922 .access = SNDRV_CTL_ELEM_ACCESS_READ |
923 SNDRV_CTL_ELEM_ACCESS_WRITE |
924 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
925 .info = fsl_spdif_info,
926 .get = fsl_spdif_pb_get,
927 .put = fsl_spdif_pb_put,
930 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
931 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
932 .access = SNDRV_CTL_ELEM_ACCESS_READ |
933 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
934 .info = fsl_spdif_info,
935 .get = fsl_spdif_capture_get,
937 /* User bits controller */
939 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
940 .name = "IEC958 Subcode Capture Default",
941 .access = SNDRV_CTL_ELEM_ACCESS_READ |
942 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
943 .info = fsl_spdif_info,
944 .get = fsl_spdif_subcode_get,
947 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
948 .name = "IEC958 Q-subcode Capture Default",
949 .access = SNDRV_CTL_ELEM_ACCESS_READ |
950 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
951 .info = fsl_spdif_qinfo,
952 .get = fsl_spdif_qget,
954 /* Valid bit error controller */
956 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
957 .name = "IEC958 V-Bit Errors",
958 .access = SNDRV_CTL_ELEM_ACCESS_READ |
959 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
960 .info = fsl_spdif_vbit_info,
961 .get = fsl_spdif_vbit_get,
963 /* DPLL lock info get controller */
965 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
966 .name = "RX Sample Rate",
967 .access = SNDRV_CTL_ELEM_ACCESS_READ |
968 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
969 .info = fsl_spdif_rxrate_info,
970 .get = fsl_spdif_rxrate_get,
972 /* User bit sync mode set/get controller */
974 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
975 .name = "IEC958 USyncMode CDText",
976 .access = SNDRV_CTL_ELEM_ACCESS_READ |
977 SNDRV_CTL_ELEM_ACCESS_WRITE |
978 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
979 .info = fsl_spdif_usync_info,
980 .get = fsl_spdif_usync_get,
981 .put = fsl_spdif_usync_put,
985 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
987 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
989 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
990 &spdif_private->dma_params_rx);
992 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
997 static struct snd_soc_dai_driver fsl_spdif_dai = {
998 .probe = &fsl_spdif_dai_probe,
1000 .stream_name = "CPU-Playback",
1003 .rates = FSL_SPDIF_RATES_PLAYBACK,
1004 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1007 .stream_name = "CPU-Capture",
1010 .rates = FSL_SPDIF_RATES_CAPTURE,
1011 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1013 .ops = &fsl_spdif_dai_ops,
1016 static const struct snd_soc_component_driver fsl_spdif_component = {
1017 .name = "fsl-spdif",
1020 /* FSL SPDIF REGMAP */
1021 static const struct reg_default fsl_spdif_reg_defaults[] = {
1022 {REG_SPDIF_SCR, 0x00000400},
1023 {REG_SPDIF_SRCD, 0x00000000},
1024 {REG_SPDIF_SIE, 0x00000000},
1025 {REG_SPDIF_STL, 0x00000000},
1026 {REG_SPDIF_STR, 0x00000000},
1027 {REG_SPDIF_STCSCH, 0x00000000},
1028 {REG_SPDIF_STCSCL, 0x00000000},
1029 {REG_SPDIF_STC, 0x00020f00},
1032 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1036 case REG_SPDIF_SRCD:
1037 case REG_SPDIF_SRPC:
1042 case REG_SPDIF_SRCSH:
1043 case REG_SPDIF_SRCSL:
1046 case REG_SPDIF_STCSCH:
1047 case REG_SPDIF_STCSCL:
1048 case REG_SPDIF_SRFM:
1056 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1059 case REG_SPDIF_SRPC:
1063 case REG_SPDIF_SRCSH:
1064 case REG_SPDIF_SRCSL:
1067 case REG_SPDIF_SRFM:
1074 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1078 case REG_SPDIF_SRCD:
1079 case REG_SPDIF_SRPC:
1084 case REG_SPDIF_STCSCH:
1085 case REG_SPDIF_STCSCL:
1093 static const struct regmap_config fsl_spdif_regmap_config = {
1098 .max_register = REG_SPDIF_STC,
1099 .reg_defaults = fsl_spdif_reg_defaults,
1100 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1101 .readable_reg = fsl_spdif_readable_reg,
1102 .volatile_reg = fsl_spdif_volatile_reg,
1103 .writeable_reg = fsl_spdif_writeable_reg,
1104 .cache_type = REGCACHE_FLAT,
1107 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1108 struct clk *clk, u64 savesub,
1109 enum spdif_txrate index, bool round)
1111 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1112 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1113 u64 rate_ideal, rate_actual, sub;
1114 u32 sysclk_dfmin, sysclk_dfmax;
1115 u32 txclk_df, sysclk_df, arate;
1117 /* The sysclk has an extra divisor [2, 512] */
1118 sysclk_dfmin = is_sysclk ? 2 : 1;
1119 sysclk_dfmax = is_sysclk ? 512 : 1;
1121 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1122 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1123 rate_ideal = rate[index] * txclk_df * 64ULL;
1125 rate_actual = clk_round_rate(clk, rate_ideal);
1127 rate_actual = clk_get_rate(clk);
1129 arate = rate_actual / 64;
1130 arate /= txclk_df * sysclk_df;
1132 if (arate == rate[index]) {
1135 spdif_priv->txclk_df[index] = txclk_df;
1136 spdif_priv->sysclk_df[index] = sysclk_df;
1137 spdif_priv->txrate[index] = arate;
1139 } else if (arate / rate[index] == 1) {
1140 /* A little bigger than expect */
1141 sub = (u64)(arate - rate[index]) * 100000;
1142 do_div(sub, rate[index]);
1146 spdif_priv->txclk_df[index] = txclk_df;
1147 spdif_priv->sysclk_df[index] = sysclk_df;
1148 spdif_priv->txrate[index] = arate;
1149 } else if (rate[index] / arate == 1) {
1150 /* A little smaller than expect */
1151 sub = (u64)(rate[index] - arate) * 100000;
1152 do_div(sub, rate[index]);
1156 spdif_priv->txclk_df[index] = txclk_df;
1157 spdif_priv->sysclk_df[index] = sysclk_df;
1158 spdif_priv->txrate[index] = arate;
1167 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1168 enum spdif_txrate index)
1170 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 };
1171 struct platform_device *pdev = spdif_priv->pdev;
1172 struct device *dev = &pdev->dev;
1173 u64 savesub = 100000, ret;
1178 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1179 sprintf(tmp, "rxtx%d", i);
1180 clk = devm_clk_get(&pdev->dev, tmp);
1182 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1183 return PTR_ERR(clk);
1185 if (!clk_get_rate(clk))
1188 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1189 i == STC_TXCLK_SPDIF_ROOT);
1194 spdif_priv->txclk[index] = clk;
1195 spdif_priv->txclk_src[index] = i;
1197 /* To quick catch a divisor, we allow a 0.1% deviation */
1202 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1203 spdif_priv->txclk_src[index], rate[index]);
1204 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
1205 spdif_priv->txclk_df[index], rate[index]);
1206 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1207 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
1208 spdif_priv->sysclk_df[index], rate[index]);
1209 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
1210 rate[index], spdif_priv->txrate[index]);
1215 static int fsl_spdif_probe(struct platform_device *pdev)
1217 struct device_node *np = pdev->dev.of_node;
1218 struct fsl_spdif_priv *spdif_priv;
1219 struct spdif_mixer_control *ctrl;
1220 struct resource *res;
1227 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1231 spdif_priv->pdev = pdev;
1233 /* Initialize this copy of the CPU DAI driver structure */
1234 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1235 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1237 /* Get the addresses and IRQ */
1238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1239 regs = devm_ioremap_resource(&pdev->dev, res);
1241 return PTR_ERR(regs);
1243 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1244 "core", regs, &fsl_spdif_regmap_config);
1245 if (IS_ERR(spdif_priv->regmap)) {
1246 dev_err(&pdev->dev, "regmap init failed\n");
1247 return PTR_ERR(spdif_priv->regmap);
1250 irq = platform_get_irq(pdev, 0);
1252 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1256 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1257 dev_name(&pdev->dev), spdif_priv);
1259 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1263 /* Get system clock for rx clock rate calculation */
1264 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1265 if (IS_ERR(spdif_priv->sysclk)) {
1266 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1267 return PTR_ERR(spdif_priv->sysclk);
1270 /* Get core clock for data register access via DMA */
1271 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1272 if (IS_ERR(spdif_priv->coreclk)) {
1273 dev_err(&pdev->dev, "no core clock in devicetree\n");
1274 return PTR_ERR(spdif_priv->coreclk);
1277 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1278 if (IS_ERR(spdif_priv->spbaclk))
1279 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1281 /* Select clock source for rx/tx clock */
1282 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1283 if (IS_ERR(spdif_priv->rxclk)) {
1284 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1285 return PTR_ERR(spdif_priv->rxclk);
1287 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1289 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1290 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1295 /* Initial spinlock for control data */
1296 ctrl = &spdif_priv->fsl_spdif_control;
1297 spin_lock_init(&ctrl->ctl_lock);
1299 /* Init tx channel status default value */
1300 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1301 IEC958_AES0_CON_EMPHASIS_5015;
1302 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1303 ctrl->ch_status[2] = 0x00;
1304 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1305 IEC958_AES3_CON_CLOCK_1000PPM;
1307 spdif_priv->dpll_locked = false;
1309 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
1310 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
1311 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1312 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1314 /* Register with ASoC */
1315 dev_set_drvdata(&pdev->dev, spdif_priv);
1317 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1318 &spdif_priv->cpu_dai_drv, 1);
1320 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1324 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1326 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
1331 #ifdef CONFIG_PM_SLEEP
1332 static int fsl_spdif_suspend(struct device *dev)
1334 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1336 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1337 &spdif_priv->regcache_srpc);
1339 regcache_cache_only(spdif_priv->regmap, true);
1340 regcache_mark_dirty(spdif_priv->regmap);
1345 static int fsl_spdif_resume(struct device *dev)
1347 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1349 regcache_cache_only(spdif_priv->regmap, false);
1351 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1352 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1353 spdif_priv->regcache_srpc);
1355 return regcache_sync(spdif_priv->regmap);
1357 #endif /* CONFIG_PM_SLEEP */
1359 static const struct dev_pm_ops fsl_spdif_pm = {
1360 SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
1363 static const struct of_device_id fsl_spdif_dt_ids[] = {
1364 { .compatible = "fsl,imx35-spdif", },
1365 { .compatible = "fsl,vf610-spdif", },
1368 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1370 static struct platform_driver fsl_spdif_driver = {
1372 .name = "fsl-spdif-dai",
1373 .of_match_table = fsl_spdif_dt_ids,
1374 .pm = &fsl_spdif_pm,
1376 .probe = fsl_spdif_probe,
1379 module_platform_driver(fsl_spdif_driver);
1381 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1382 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1383 MODULE_LICENSE("GPL v2");
1384 MODULE_ALIAS("platform:fsl-spdif-dai");