1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/pm_qos.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/time.h>
18 #include <sound/core.h>
19 #include <sound/dmaengine_pcm.h>
20 #include <sound/pcm_params.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
25 #include "fsl_utils.h"
28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
31 static const unsigned int fsl_sai_rates[] = {
32 8000, 11025, 12000, 16000, 22050,
33 24000, 32000, 44100, 48000, 64000,
34 88200, 96000, 176400, 192000, 352800,
35 384000, 705600, 768000, 1411200, 2822400,
38 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
39 .count = ARRAY_SIZE(fsl_sai_rates),
40 .list = fsl_sai_rates,
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
47 * or Receiver's for both streams. This function is used to check if clocks of
48 * the stream's are synced by the opposite stream.
51 * @dir: stream direction
53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir)
55 int adir = (dir == TX) ? RX : TX;
57 /* current dir in async mode while opposite dir in sync mode */
58 return !sai->synchronous[dir] && sai->synchronous[adir];
61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk)
63 struct pinctrl_state *state = NULL;
65 if (sai->is_pdm_mode) {
66 /* DSD512@44.1kHz, DSD512@48kHz */
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512");
70 /* Get default DSD state */
71 if (IS_ERR_OR_NULL(state))
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd");
74 /* 706k32b2c, 768k32b2c, etc */
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m");
79 /* Get default state */
80 if (IS_ERR_OR_NULL(state))
81 state = pinctrl_lookup_state(sai->pinctrl, "default");
86 static irqreturn_t fsl_sai_isr(int irq, void *devid)
88 struct fsl_sai *sai = (struct fsl_sai *)devid;
89 unsigned int ofs = sai->soc_data->reg_offset;
90 struct device *dev = &sai->pdev->dev;
91 u32 flags, xcsr, mask;
92 irqreturn_t iret = IRQ_NONE;
95 * Both IRQ status bits and IRQ mask bits are in the xCSR but
96 * different shifts. And we here create a mask only for those
97 * IRQs that we activated.
99 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
110 if (flags & FSL_SAI_CSR_WSF)
111 dev_dbg(dev, "isr: Start of Tx word detected\n");
113 if (flags & FSL_SAI_CSR_SEF)
114 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
116 if (flags & FSL_SAI_CSR_FEF)
117 dev_dbg(dev, "isr: Transmit underrun detected\n");
119 if (flags & FSL_SAI_CSR_FWF)
120 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
122 if (flags & FSL_SAI_CSR_FRF)
123 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
125 flags &= FSL_SAI_CSR_xF_W_MASK;
126 xcsr &= ~FSL_SAI_CSR_xF_MASK;
129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
141 if (flags & FSL_SAI_CSR_WSF)
142 dev_dbg(dev, "isr: Start of Rx word detected\n");
144 if (flags & FSL_SAI_CSR_SEF)
145 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
147 if (flags & FSL_SAI_CSR_FEF)
148 dev_dbg(dev, "isr: Receive overflow detected\n");
150 if (flags & FSL_SAI_CSR_FWF)
151 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
153 if (flags & FSL_SAI_CSR_FRF)
154 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
156 flags &= FSL_SAI_CSR_xF_W_MASK;
157 xcsr &= ~FSL_SAI_CSR_xF_MASK;
160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
166 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
167 u32 rx_mask, int slots, int slot_width)
169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
172 sai->slot_width = slot_width;
177 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
180 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
182 sai->bclk_ratio = ratio;
187 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
188 int clk_id, unsigned int freq, bool tx)
190 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
191 unsigned int ofs = sai->soc_data->reg_offset;
195 case FSL_SAI_CLK_BUS:
196 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
198 case FSL_SAI_CLK_MAST1:
199 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
201 case FSL_SAI_CLK_MAST2:
202 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
204 case FSL_SAI_CLK_MAST3:
205 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
211 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
212 FSL_SAI_CR2_MSEL_MASK, val_cr2);
217 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq)
219 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
222 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id],
223 sai->pll8k_clk, sai->pll11k_clk, freq);
225 ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
227 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret);
232 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
233 int clk_id, unsigned int freq, int dir)
235 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
238 if (dir == SND_SOC_CLOCK_IN)
241 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
242 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
243 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
247 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) {
248 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id);
252 if (sai->mclk_streams == 0) {
253 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
259 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true);
261 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
265 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false);
267 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
272 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
273 unsigned int fmt, bool tx)
275 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
276 unsigned int ofs = sai->soc_data->reg_offset;
277 u32 val_cr2 = 0, val_cr4 = 0;
279 if (!sai->is_lsb_first)
280 val_cr4 |= FSL_SAI_CR4_MF;
282 sai->is_pdm_mode = false;
283 sai->is_dsp_mode = false;
285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
286 case SND_SOC_DAIFMT_I2S:
288 * Frame low, 1clk before data, one word length for frame sync,
289 * frame sync starts one serial clock cycle earlier,
290 * that is, together with the last bit of the previous
293 val_cr2 |= FSL_SAI_CR2_BCP;
294 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
296 case SND_SOC_DAIFMT_LEFT_J:
298 * Frame high, one word length for frame sync,
299 * frame sync asserts with the first bit of the frame.
301 val_cr2 |= FSL_SAI_CR2_BCP;
303 case SND_SOC_DAIFMT_DSP_A:
305 * Frame high, 1clk before data, one bit for frame sync,
306 * frame sync starts one serial clock cycle earlier,
307 * that is, together with the last bit of the previous
310 val_cr2 |= FSL_SAI_CR2_BCP;
311 val_cr4 |= FSL_SAI_CR4_FSE;
312 sai->is_dsp_mode = true;
314 case SND_SOC_DAIFMT_DSP_B:
316 * Frame high, one bit for frame sync,
317 * frame sync asserts with the first bit of the frame.
319 val_cr2 |= FSL_SAI_CR2_BCP;
320 sai->is_dsp_mode = true;
322 case SND_SOC_DAIFMT_PDM:
323 val_cr2 |= FSL_SAI_CR2_BCP;
324 val_cr4 &= ~FSL_SAI_CR4_MF;
325 sai->is_pdm_mode = true;
327 case SND_SOC_DAIFMT_RIGHT_J:
333 /* DAI clock inversion */
334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
335 case SND_SOC_DAIFMT_IB_IF:
336 /* Invert both clocks */
337 val_cr2 ^= FSL_SAI_CR2_BCP;
338 val_cr4 ^= FSL_SAI_CR4_FSP;
340 case SND_SOC_DAIFMT_IB_NF:
341 /* Invert bit clock */
342 val_cr2 ^= FSL_SAI_CR2_BCP;
344 case SND_SOC_DAIFMT_NB_IF:
345 /* Invert frame clock */
346 val_cr4 ^= FSL_SAI_CR4_FSP;
348 case SND_SOC_DAIFMT_NB_NF:
349 /* Nothing to do for both normal cases */
355 /* DAI clock provider masks */
356 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
357 case SND_SOC_DAIFMT_BP_FP:
358 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
359 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
360 sai->is_consumer_mode = false;
362 case SND_SOC_DAIFMT_BC_FC:
363 sai->is_consumer_mode = true;
365 case SND_SOC_DAIFMT_BP_FC:
366 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
367 sai->is_consumer_mode = false;
369 case SND_SOC_DAIFMT_BC_FP:
370 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
371 sai->is_consumer_mode = true;
377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
378 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
380 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
381 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
386 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
390 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true);
392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false);
398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
403 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
406 unsigned int reg, ofs = sai->soc_data->reg_offset;
407 unsigned long clk_rate;
408 u32 savediv = 0, ratio, bestdiff = freq;
409 int adir = tx ? RX : TX;
410 int dir = tx ? TX : RX;
412 bool support_1_1_ratio = sai->verid.version >= 0x0301;
414 /* Don't apply to consumer mode */
415 if (sai->is_consumer_mode)
419 * There is no point in polling MCLK0 if it is identical to MCLK1.
420 * And given that MQS use case has to use MCLK1 though two clocks
421 * are the same, we simply skip MCLK0 and start to find from MCLK1.
423 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
425 for (; id < FSL_SAI_MCLK_MAX; id++) {
428 clk_rate = clk_get_rate(sai->mclk_clk[id]);
432 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
433 if (!ratio || ratio > 512)
435 if (ratio == 1 && !support_1_1_ratio)
437 if ((ratio & 1) && ratio > 1)
440 diff = abs((long)clk_rate - ratio * freq);
443 * Drop the source that can not be
444 * divided into the required rate.
446 if (diff != 0 && clk_rate / diff < 1000)
450 "ratio %d for freq %dHz based on clock %ldHz\n",
451 ratio, freq, clk_rate);
454 if (diff < bestdiff) {
456 sai->mclk_id[tx] = id;
465 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
466 tx ? 'T' : 'R', freq);
470 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
471 sai->mclk_id[tx], savediv, bestdiff);
474 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
475 * set TCR2 register for playback.
476 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
478 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
480 * 4) For Tx and Rx are both Synchronous with another SAI, we just
483 if (fsl_sai_dir_is_synced(sai, adir))
484 reg = FSL_SAI_xCR2(!tx, ofs);
485 else if (!sai->synchronous[dir])
486 reg = FSL_SAI_xCR2(tx, ofs);
490 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
491 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
494 regmap_update_bits(sai->regmap, reg,
495 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
497 if (fsl_sai_dir_is_synced(sai, adir))
498 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
499 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI);
501 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
504 regmap_update_bits(sai->regmap, reg,
505 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
512 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
513 struct snd_pcm_hw_params *params,
514 struct snd_soc_dai *cpu_dai)
516 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
517 unsigned int ofs = sai->soc_data->reg_offset;
518 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
519 unsigned int channels = params_channels(params);
520 struct snd_dmaengine_dai_dma_data *dma_params;
521 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg;
522 u32 word_width = params_width(params);
523 int trce_mask = 0, dl_cfg_idx = 0;
524 int dl_cfg_cnt = sai->dl_cfg_cnt;
525 u32 dl_type = FSL_SAI_DL_I2S;
526 u32 val_cr4 = 0, val_cr5 = 0;
527 u32 slots = (channels == 1) ? 2 : channels;
528 u32 slot_width = word_width;
529 int adir = tx ? RX : TX;
535 slot_width = sai->slot_width;
539 else if (sai->bclk_ratio)
540 slots = sai->bclk_ratio / slot_width;
542 pins = DIV_ROUND_UP(channels, slots);
545 * PDM mode, channels are independent
546 * each channels are on one dataline/FIFO.
548 if (sai->is_pdm_mode) {
550 dl_type = FSL_SAI_DL_PDM;
553 for (i = 0; i < dl_cfg_cnt; i++) {
554 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) {
560 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) {
561 dev_err(cpu_dai->dev, "channel not supported\n");
565 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width);
567 if (!IS_ERR_OR_NULL(sai->pinctrl)) {
568 sai->pins_state = fsl_sai_get_pins_state(sai, bclk);
569 if (!IS_ERR_OR_NULL(sai->pins_state)) {
570 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
572 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret);
578 if (!sai->is_consumer_mode) {
579 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk);
583 /* Do not enable the clock if it is already enabled */
584 if (!(sai->mclk_streams & BIT(substream->stream))) {
585 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
589 sai->mclk_streams |= BIT(substream->stream);
593 if (!sai->is_dsp_mode && !sai->is_pdm_mode)
594 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
596 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
597 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
599 if (sai->is_lsb_first || sai->is_pdm_mode)
600 val_cr5 |= FSL_SAI_CR5_FBT(0);
602 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
604 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
606 /* Set to output mode to avoid tri-stated data pins */
608 val_cr4 |= FSL_SAI_CR4_CHMOD;
611 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
612 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
613 * RCR5(TCR5) for playback(capture), or there will be sync error.
616 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) {
617 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
618 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
619 FSL_SAI_CR4_CHMOD_MASK,
621 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
622 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
623 FSL_SAI_CR5_FBT_MASK, val_cr5);
627 * Combine mode has limation:
628 * - Can't used for singel dataline/FIFO case except the FIFO0
629 * - Can't used for multi dataline/FIFO case except the enabled FIFOs
630 * are successive and start from FIFO0
632 * So for common usage, all multi fifo case disable the combine mode.
634 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma)
635 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
636 FSL_SAI_CR4_FCOMB_MASK, 0);
638 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
639 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT);
641 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx;
642 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) +
643 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4;
645 if (sai->is_multi_fifo_dma) {
646 sai->audio_config[tx].words_per_fifo = min(slots, channels);
648 sai->audio_config[tx].n_fifos_dst = pins;
649 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx];
651 sai->audio_config[tx].n_fifos_src = pins;
652 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx];
654 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins;
655 dma_params->peripheral_config = &sai->audio_config[tx];
656 dma_params->peripheral_size = sizeof(sai->audio_config[tx]);
658 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) :
659 (dma_params->maxburst - 1);
660 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs),
661 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
665 /* Find a proper tcre setting */
666 for (i = 0; i < sai->soc_data->pins; i++) {
667 trce_mask = (1 << (i + 1)) - 1;
668 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins)
672 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
673 FSL_SAI_CR3_TRCE_MASK,
674 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask)));
677 * When the TERE and FSD_MSTR enabled before configuring the word width
678 * There will be no frame sync clock issue, because word width impact
679 * the generation of frame sync clock.
681 * TERE enabled earlier only for i.MX8MP case for the hardware limitation,
682 * We need to disable FSD_MSTR before configuring word width, then enable
683 * FSD_MSTR bit for this specific case.
685 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
686 !sai->is_consumer_mode)
687 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
688 FSL_SAI_CR4_FSD_MSTR, 0);
690 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
691 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
692 FSL_SAI_CR4_CHMOD_MASK,
694 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
695 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
696 FSL_SAI_CR5_FBT_MASK, val_cr5);
698 /* Enable FSD_MSTR after configuring word width */
699 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
700 !sai->is_consumer_mode)
701 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
702 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR);
704 regmap_write(sai->regmap, FSL_SAI_xMR(tx),
705 ~0UL - ((1 << min(channels, slots)) - 1));
710 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
711 struct snd_soc_dai *cpu_dai)
713 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
714 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
715 unsigned int ofs = sai->soc_data->reg_offset;
717 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */
718 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0);
720 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
721 FSL_SAI_CR3_TRCE_MASK, 0);
723 if (!sai->is_consumer_mode &&
724 sai->mclk_streams & BIT(substream->stream)) {
725 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
726 sai->mclk_streams &= ~BIT(substream->stream);
732 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir)
734 unsigned int ofs = sai->soc_data->reg_offset;
736 u32 xcsr, count = 100, mask;
738 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
739 mask = FSL_SAI_CSR_TERE;
741 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
743 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
746 /* TERE will remain set till the end of current frame */
749 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr);
750 } while (--count && xcsr & FSL_SAI_CSR_TERE);
752 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
753 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
756 * For sai master mode, after several open/close sai,
757 * there will be no frame clock, and can't recover
758 * anymore. Add software reset to fix this issue.
759 * This is a hardware bug, and will be fix in the
762 if (!sai->is_consumer_mode) {
764 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR);
765 /* Clear SR bit to finish the reset */
766 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0);
770 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
771 struct snd_soc_dai *cpu_dai)
773 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
774 unsigned int ofs = sai->soc_data->reg_offset;
776 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
777 int adir = tx ? RX : TX;
778 int dir = tx ? TX : RX;
782 * Asynchronous mode: Clear SYNC for both Tx and Rx.
783 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
784 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
786 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
787 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
788 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
789 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
792 * It is recommended that the transmitter is the last enabled
793 * and the first disabled.
796 case SNDRV_PCM_TRIGGER_START:
797 case SNDRV_PCM_TRIGGER_RESUME:
798 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
799 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
800 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
802 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
803 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
805 * Enable the opposite direction for synchronous mode
806 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
807 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
809 * RM recommends to enable RE after TE for case 1 and to enable
810 * TE after RE for case 2, but we here may not always guarantee
811 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
812 * TE after RE, which is against what RM recommends but should
813 * be safe to do, judging by years of testing results.
815 if (fsl_sai_dir_is_synced(sai, adir))
816 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs),
817 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
819 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
820 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
822 case SNDRV_PCM_TRIGGER_STOP:
823 case SNDRV_PCM_TRIGGER_SUSPEND:
824 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
825 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
826 FSL_SAI_CSR_FRDE, 0);
827 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
828 FSL_SAI_CSR_xIE_MASK, 0);
830 /* Check if the opposite FRDE is also disabled */
831 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
834 * If opposite stream provides clocks for synchronous mode and
835 * it is inactive, disable it before disabling the current one
837 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE))
838 fsl_sai_config_disable(sai, adir);
841 * Disable current stream if either of:
842 * 1. current stream doesn't provide clocks for synchronous mode
843 * 2. current stream provides clocks for synchronous mode but no
844 * more stream is active.
846 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE))
847 fsl_sai_config_disable(sai, dir);
857 static int fsl_sai_startup(struct snd_pcm_substream *substream,
858 struct snd_soc_dai *cpu_dai)
860 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
861 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
865 * EDMA controller needs period size to be a multiple of
868 if (sai->soc_data->use_edma)
869 snd_pcm_hw_constraint_step(substream->runtime, 0,
870 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
871 tx ? sai->dma_params_tx.maxburst :
872 sai->dma_params_rx.maxburst);
874 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
875 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
880 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
882 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
883 unsigned int ofs = sai->soc_data->reg_offset;
885 /* Software Reset for both Tx and Rx */
886 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
887 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
888 /* Clear SR bit to finish the reset */
889 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
890 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
892 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
893 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
894 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst);
895 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
896 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth),
897 sai->dma_params_rx.maxburst - 1);
899 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
900 &sai->dma_params_rx);
905 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
906 .probe = fsl_sai_dai_probe,
907 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
908 .set_sysclk = fsl_sai_set_dai_sysclk,
909 .set_fmt = fsl_sai_set_dai_fmt,
910 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
911 .hw_params = fsl_sai_hw_params,
912 .hw_free = fsl_sai_hw_free,
913 .trigger = fsl_sai_trigger,
914 .startup = fsl_sai_startup,
917 static int fsl_sai_dai_resume(struct snd_soc_component *component)
919 struct fsl_sai *sai = snd_soc_component_get_drvdata(component);
920 struct device *dev = &sai->pdev->dev;
923 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) {
924 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state);
926 dev_err(dev, "failed to set proper pins state: %d\n", ret);
934 static struct snd_soc_dai_driver fsl_sai_dai_template = {
936 .stream_name = "CPU-Playback",
941 .rates = SNDRV_PCM_RATE_KNOT,
942 .formats = FSL_SAI_FORMATS,
945 .stream_name = "CPU-Capture",
950 .rates = SNDRV_PCM_RATE_KNOT,
951 .formats = FSL_SAI_FORMATS,
953 .ops = &fsl_sai_pcm_dai_ops,
956 static const struct snd_soc_component_driver fsl_component = {
958 .resume = fsl_sai_dai_resume,
959 .legacy_dai_naming = 1,
962 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
963 {FSL_SAI_TCR1(0), 0},
964 {FSL_SAI_TCR2(0), 0},
965 {FSL_SAI_TCR3(0), 0},
966 {FSL_SAI_TCR4(0), 0},
967 {FSL_SAI_TCR5(0), 0},
977 {FSL_SAI_RCR1(0), 0},
978 {FSL_SAI_RCR2(0), 0},
979 {FSL_SAI_RCR3(0), 0},
980 {FSL_SAI_RCR4(0), 0},
981 {FSL_SAI_RCR5(0), 0},
985 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
986 {FSL_SAI_TCR1(8), 0},
987 {FSL_SAI_TCR2(8), 0},
988 {FSL_SAI_TCR3(8), 0},
989 {FSL_SAI_TCR4(8), 0},
990 {FSL_SAI_TCR5(8), 0},
1000 {FSL_SAI_RCR1(8), 0},
1001 {FSL_SAI_RCR2(8), 0},
1002 {FSL_SAI_RCR3(8), 0},
1003 {FSL_SAI_RCR4(8), 0},
1004 {FSL_SAI_RCR5(8), 0},
1010 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
1012 struct fsl_sai *sai = dev_get_drvdata(dev);
1013 unsigned int ofs = sai->soc_data->reg_offset;
1015 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1018 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1066 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
1068 struct fsl_sai *sai = dev_get_drvdata(dev);
1069 unsigned int ofs = sai->soc_data->reg_offset;
1071 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
1074 /* Set VERID and PARAM be volatile for reading value in probe */
1075 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM))
1109 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
1111 struct fsl_sai *sai = dev_get_drvdata(dev);
1112 unsigned int ofs = sai->soc_data->reg_offset;
1114 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
1117 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
1141 static struct regmap_config fsl_sai_regmap_config = {
1147 .max_register = FSL_SAI_RMR,
1148 .reg_defaults = fsl_sai_reg_defaults_ofs0,
1149 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
1150 .readable_reg = fsl_sai_readable_reg,
1151 .volatile_reg = fsl_sai_volatile_reg,
1152 .writeable_reg = fsl_sai_writeable_reg,
1153 .cache_type = REGCACHE_FLAT,
1156 static int fsl_sai_check_version(struct device *dev)
1158 struct fsl_sai *sai = dev_get_drvdata(dev);
1159 unsigned char ofs = sai->soc_data->reg_offset;
1163 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID)
1166 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val);
1170 dev_dbg(dev, "VERID: 0x%016X\n", val);
1172 sai->verid.version = val &
1173 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK);
1174 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT;
1175 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK;
1177 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
1181 dev_dbg(dev, "PARAM: 0x%016X\n", val);
1183 /* Max slots per frame, power of 2 */
1184 sai->param.slot_num = 1 <<
1185 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT);
1187 /* Words per fifo, power of 2 */
1188 sai->param.fifo_depth = 1 <<
1189 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT);
1191 /* Number of datalines implemented */
1192 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK;
1198 * Calculate the offset between first two datalines, don't
1199 * different offset in one case.
1201 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask)
1203 int fbidx, nbidx, offset;
1205 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1206 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1);
1207 offset = nbidx - fbidx - 1;
1209 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset);
1213 * read the fsl,dataline property from dts file.
1214 * It has 3 value for each configuration, first one means the type:
1215 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is
1216 * dataline mask for 'tx'. for example
1218 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>,
1220 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
1221 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
1224 static int fsl_sai_read_dlcfg(struct fsl_sai *sai)
1226 struct platform_device *pdev = sai->pdev;
1227 struct device_node *np = pdev->dev.of_node;
1228 struct device *dev = &pdev->dev;
1229 int ret, elems, i, index, num_cfg;
1230 char *propname = "fsl,dataline";
1231 struct fsl_sai_dl_cfg *cfg;
1232 unsigned long dl_mask;
1233 unsigned int soc_dl;
1236 elems = of_property_count_u32_elems(np, propname);
1240 } else if (elems % 3) {
1241 dev_err(dev, "Number of elements must be divisible to 3.\n");
1245 num_cfg = elems / 3;
1246 /* Add one more for default value */
1247 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL);
1251 /* Consider default value "0 0xFF 0xFF" if property is missing */
1252 soc_dl = BIT(sai->soc_data->pins) - 1;
1253 cfg[0].type = FSL_SAI_DL_DEFAULT;
1254 cfg[0].pins[0] = sai->soc_data->pins;
1255 cfg[0].mask[0] = soc_dl;
1256 cfg[0].start_off[0] = 0;
1257 cfg[0].next_off[0] = 0;
1259 cfg[0].pins[1] = sai->soc_data->pins;
1260 cfg[0].mask[1] = soc_dl;
1261 cfg[0].start_off[1] = 0;
1262 cfg[0].next_off[1] = 0;
1263 for (i = 1, index = 0; i < num_cfg + 1; i++) {
1266 * 0 means default mode
1270 ret = of_property_read_u32_index(np, propname, index++, &type);
1274 ret = of_property_read_u32_index(np, propname, index++, &rx);
1278 ret = of_property_read_u32_index(np, propname, index++, &tx);
1282 if ((rx & ~soc_dl) || (tx & ~soc_dl)) {
1283 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl);
1291 cfg[i].pins[0] = hweight8(rx);
1292 cfg[i].mask[0] = rx;
1294 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1295 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx);
1297 cfg[i].pins[1] = hweight8(tx);
1298 cfg[i].mask[1] = tx;
1300 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM);
1301 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx);
1305 sai->dl_cfg_cnt = num_cfg + 1;
1309 static int fsl_sai_runtime_suspend(struct device *dev);
1310 static int fsl_sai_runtime_resume(struct device *dev);
1312 static int fsl_sai_probe(struct platform_device *pdev)
1314 struct device_node *np = pdev->dev.of_node;
1315 struct device *dev = &pdev->dev;
1316 struct fsl_sai *sai;
1324 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL);
1329 sai->soc_data = of_device_get_match_data(dev);
1331 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
1333 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res);
1335 return PTR_ERR(base);
1337 if (sai->soc_data->reg_offset == 8) {
1338 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
1339 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV;
1340 fsl_sai_regmap_config.num_reg_defaults =
1341 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
1344 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config);
1345 if (IS_ERR(sai->regmap)) {
1346 dev_err(dev, "regmap init failed\n");
1347 return PTR_ERR(sai->regmap);
1350 sai->bus_clk = devm_clk_get(dev, "bus");
1351 /* Compatible with old DTB cases */
1352 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER)
1353 sai->bus_clk = devm_clk_get(dev, "sai");
1354 if (IS_ERR(sai->bus_clk)) {
1355 dev_err(dev, "failed to get bus clock: %ld\n",
1356 PTR_ERR(sai->bus_clk));
1358 return PTR_ERR(sai->bus_clk);
1361 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
1362 sprintf(tmp, "mclk%d", i);
1363 sai->mclk_clk[i] = devm_clk_get(dev, tmp);
1364 if (IS_ERR(sai->mclk_clk[i])) {
1365 dev_err(dev, "failed to get mclk%d clock: %ld\n",
1366 i, PTR_ERR(sai->mclk_clk[i]));
1367 sai->mclk_clk[i] = NULL;
1371 if (sai->soc_data->mclk0_is_mclk1)
1372 sai->mclk_clk[0] = sai->mclk_clk[1];
1374 sai->mclk_clk[0] = sai->bus_clk;
1376 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk,
1379 /* Use Multi FIFO mode depending on the support from SDMA script */
1380 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1381 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1382 sai->is_multi_fifo_dma = true;
1384 /* read dataline mask for rx and tx*/
1385 ret = fsl_sai_read_dlcfg(sai);
1387 dev_err(dev, "failed to read dlcfg %d\n", ret);
1391 irq = platform_get_irq(pdev, 0);
1395 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED,
1398 dev_err(dev, "failed to claim irq %u\n", irq);
1402 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template,
1403 sizeof(fsl_sai_dai_template));
1405 /* Sync Tx with Rx as default by following old DT binding */
1406 sai->synchronous[RX] = true;
1407 sai->synchronous[TX] = false;
1408 sai->cpu_dai_drv.symmetric_rate = 1;
1409 sai->cpu_dai_drv.symmetric_channels = 1;
1410 sai->cpu_dai_drv.symmetric_sample_bits = 1;
1412 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") &&
1413 of_property_read_bool(np, "fsl,sai-asynchronous")) {
1414 /* error out if both synchronous and asynchronous are present */
1415 dev_err(dev, "invalid binding for synchronous mode\n");
1419 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) {
1420 /* Sync Rx with Tx */
1421 sai->synchronous[RX] = false;
1422 sai->synchronous[TX] = true;
1423 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) {
1424 /* Discard all settings for asynchronous mode */
1425 sai->synchronous[RX] = false;
1426 sai->synchronous[TX] = false;
1427 sai->cpu_dai_drv.symmetric_rate = 0;
1428 sai->cpu_dai_drv.symmetric_channels = 0;
1429 sai->cpu_dai_drv.symmetric_sample_bits = 0;
1432 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output");
1434 if (sai->mclk_direction_output &&
1435 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
1436 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
1438 dev_err(dev, "cannot find iomuxc registers\n");
1439 return PTR_ERR(gpr);
1442 index = of_alias_get_id(np, "sai");
1446 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1450 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0;
1451 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0;
1452 sai->dma_params_rx.maxburst =
1453 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX;
1454 sai->dma_params_tx.maxburst =
1455 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX;
1457 sai->pinctrl = devm_pinctrl_get(&pdev->dev);
1459 platform_set_drvdata(pdev, sai);
1460 pm_runtime_enable(dev);
1461 if (!pm_runtime_enabled(dev)) {
1462 ret = fsl_sai_runtime_resume(dev);
1464 goto err_pm_disable;
1467 ret = pm_runtime_resume_and_get(dev);
1469 goto err_pm_get_sync;
1471 /* Get sai version */
1472 ret = fsl_sai_check_version(dev);
1474 dev_warn(dev, "Error reading SAI version: %d\n", ret);
1476 /* Select MCLK direction */
1477 if (sai->mclk_direction_output &&
1478 sai->soc_data->max_register >= FSL_SAI_MCTL) {
1479 regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
1480 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
1483 ret = pm_runtime_put_sync(dev);
1484 if (ret < 0 && ret != -ENOSYS)
1485 goto err_pm_get_sync;
1488 * Register platform component before registering cpu dai for there
1489 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1491 if (sai->soc_data->use_imx_pcm) {
1492 ret = imx_pcm_dma_init(pdev);
1494 dev_err_probe(dev, ret, "PCM DMA init failed\n");
1495 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA))
1496 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n");
1497 goto err_pm_get_sync;
1500 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1502 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n");
1503 goto err_pm_get_sync;
1507 ret = devm_snd_soc_register_component(dev, &fsl_component,
1508 &sai->cpu_dai_drv, 1);
1510 goto err_pm_get_sync;
1515 if (!pm_runtime_status_suspended(dev))
1516 fsl_sai_runtime_suspend(dev);
1518 pm_runtime_disable(dev);
1523 static void fsl_sai_remove(struct platform_device *pdev)
1525 pm_runtime_disable(&pdev->dev);
1526 if (!pm_runtime_status_suspended(&pdev->dev))
1527 fsl_sai_runtime_suspend(&pdev->dev);
1530 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1531 .use_imx_pcm = false,
1536 .mclk0_is_mclk1 = false,
1538 .max_register = FSL_SAI_RMR,
1541 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1542 .use_imx_pcm = true,
1547 .mclk0_is_mclk1 = true,
1549 .max_register = FSL_SAI_RMR,
1552 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1553 .use_imx_pcm = true,
1558 .mclk0_is_mclk1 = false,
1559 .flags = PMQOS_CPU_LATENCY,
1560 .max_register = FSL_SAI_RMR,
1563 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1564 .use_imx_pcm = true,
1569 .mclk0_is_mclk1 = false,
1571 .max_register = FSL_SAI_RMR,
1574 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1575 .use_imx_pcm = true,
1580 .mclk0_is_mclk1 = false,
1582 .max_register = FSL_SAI_RMR,
1585 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
1586 .use_imx_pcm = true,
1590 .mclk0_is_mclk1 = false,
1593 .max_register = FSL_SAI_MCTL,
1596 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
1597 .use_imx_pcm = true,
1601 .mclk0_is_mclk1 = false,
1604 .max_register = FSL_SAI_MDIV,
1607 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
1608 .use_imx_pcm = true,
1612 .mclk0_is_mclk1 = false,
1615 .max_register = FSL_SAI_MDIV,
1616 .mclk_with_tere = true,
1619 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
1620 .use_imx_pcm = true,
1624 .mclk0_is_mclk1 = false,
1626 .flags = PMQOS_CPU_LATENCY,
1627 .max_register = FSL_SAI_RTCAP,
1630 static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
1631 .use_imx_pcm = true,
1635 .mclk0_is_mclk1 = false,
1638 .max_register = FSL_SAI_MCTL,
1639 .max_burst = {8, 8},
1642 static const struct of_device_id fsl_sai_ids[] = {
1643 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1644 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1645 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1646 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1647 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1648 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1649 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1650 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1651 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1652 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1653 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1656 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1658 static int fsl_sai_runtime_suspend(struct device *dev)
1660 struct fsl_sai *sai = dev_get_drvdata(dev);
1662 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1663 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1665 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1666 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1668 clk_disable_unprepare(sai->bus_clk);
1670 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1671 cpu_latency_qos_remove_request(&sai->pm_qos_req);
1673 regcache_cache_only(sai->regmap, true);
1678 static int fsl_sai_runtime_resume(struct device *dev)
1680 struct fsl_sai *sai = dev_get_drvdata(dev);
1681 unsigned int ofs = sai->soc_data->reg_offset;
1684 ret = clk_prepare_enable(sai->bus_clk);
1686 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1690 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1691 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1693 goto disable_bus_clk;
1696 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1697 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1699 goto disable_tx_clk;
1702 if (sai->soc_data->flags & PMQOS_CPU_LATENCY)
1703 cpu_latency_qos_add_request(&sai->pm_qos_req, 0);
1705 regcache_cache_only(sai->regmap, false);
1706 regcache_mark_dirty(sai->regmap);
1707 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1708 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1709 usleep_range(1000, 2000);
1710 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1711 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1713 ret = regcache_sync(sai->regmap);
1715 goto disable_rx_clk;
1717 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
1718 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
1719 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
1724 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1725 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1727 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1728 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1730 clk_disable_unprepare(sai->bus_clk);
1735 static const struct dev_pm_ops fsl_sai_pm_ops = {
1736 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1737 fsl_sai_runtime_resume, NULL)
1738 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1739 pm_runtime_force_resume)
1742 static struct platform_driver fsl_sai_driver = {
1743 .probe = fsl_sai_probe,
1744 .remove_new = fsl_sai_remove,
1747 .pm = &fsl_sai_pm_ops,
1748 .of_match_table = fsl_sai_ids,
1751 module_platform_driver(fsl_sai_driver);
1753 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1754 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1755 MODULE_ALIAS("platform:fsl-sai");
1756 MODULE_LICENSE("GPL");