2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
22 #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
23 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
24 SNDRV_PCM_FMTBIT_S16_LE | \
25 SNDRV_PCM_FMTBIT_S20_3LE | \
26 SNDRV_PCM_FMTBIT_S24_LE)
29 * fsl_esai: ESAI private data
31 * @dma_params_rx: DMA parameters for receive channel
32 * @dma_params_tx: DMA parameters for transmit channel
33 * @pdev: platform device pointer
34 * @regmap: regmap handler
35 * @coreclk: clock source to access register
36 * @extalclk: esai clock source to derive HCK, SCK and FS
37 * @fsysclk: system clock source to derive HCK, SCK and FS
38 * @spbaclk: SPBA clock (optional, depending on SoC design)
39 * @fifo_depth: depth of tx/rx FIFO
40 * @slot_width: width of each DAI slot
41 * @slots: number of slots
42 * @hck_rate: clock rate of desired HCKx clock
43 * @sck_rate: clock rate of desired SCKx clock
44 * @hck_dir: the direction of HCKx pads
45 * @sck_div: if using PSR/PM dividers for SCKx clock
46 * @slave_mode: if fully using DAI slave mode
47 * @synchronous: if using tx/rx synchronous mode
51 struct snd_dmaengine_dai_dma_data dma_params_rx;
52 struct snd_dmaengine_dai_dma_data dma_params_tx;
53 struct platform_device *pdev;
54 struct regmap *regmap;
73 static irqreturn_t esai_isr(int irq, void *devid)
75 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
76 struct platform_device *pdev = esai_priv->pdev;
79 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
81 if (esr & ESAI_ESR_TINIT_MASK)
82 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
84 if (esr & ESAI_ESR_RFF_MASK)
85 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
87 if (esr & ESAI_ESR_TFE_MASK)
88 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
90 if (esr & ESAI_ESR_TLS_MASK)
91 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
93 if (esr & ESAI_ESR_TDE_MASK)
94 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
96 if (esr & ESAI_ESR_TED_MASK)
97 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
99 if (esr & ESAI_ESR_TD_MASK)
100 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
102 if (esr & ESAI_ESR_RLS_MASK)
103 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
105 if (esr & ESAI_ESR_RDE_MASK)
106 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
108 if (esr & ESAI_ESR_RED_MASK)
109 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
111 if (esr & ESAI_ESR_RD_MASK)
112 dev_dbg(&pdev->dev, "isr: Receiving data\n");
118 * This function is used to calculate the divisors of psr, pm, fp and it is
119 * supposed to be called in set_dai_sysclk() and set_bclk().
121 * @ratio: desired overall ratio for the paticipating dividers
122 * @usefp: for HCK setting, there is no need to set fp divider
123 * @fp: bypass other dividers by setting fp directly if fp != 0
124 * @tx: current setting is for playback or capture
126 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
129 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
130 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
132 maxfp = usefp ? 16 : 1;
137 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
138 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
139 2 * 8 * 256 * maxfp);
141 } else if (ratio % 2) {
142 dev_err(dai->dev, "the raio must be even if using upper divider\n");
148 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
150 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
157 /* Set the max fluctuation -- 0.1% of the max devisor */
158 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
160 /* Find the best value for PM */
161 for (i = 1; i <= 256; i++) {
162 for (j = 1; j <= maxfp; j++) {
163 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
164 prod = (psr ? 1 : 8) * i * j;
168 else if (prod / ratio == 1)
170 else if (ratio / prod == 1)
175 /* Calculate the fraction */
176 sub = sub * 1000 / ratio;
190 dev_err(dai->dev, "failed to calculate proper divisors\n");
195 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
196 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
197 psr | ESAI_xCCR_xPM(pm));
200 /* Bypass fp if not being required */
204 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
205 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
211 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
214 * clk_id: The clock source of HCKT/HCKR
215 * (Input from outside; output from inside, FSYS or EXTAL)
216 * freq: The required clock rate of HCKT/HCKR
217 * dir: The clock direction of HCKT/HCKR
219 * Note: If the direction is input, we do not care about clk_id.
221 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
222 unsigned int freq, int dir)
224 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
225 struct clk *clksrc = esai_priv->extalclk;
226 bool tx = clk_id <= ESAI_HCKT_EXTAL;
227 bool in = dir == SND_SOC_CLOCK_IN;
229 unsigned long clk_rate;
232 /* Bypass divider settings if the requirement doesn't change */
233 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
236 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
237 esai_priv->sck_div[tx] = true;
239 /* Set the direction of HCKT/HCKR pins */
240 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
241 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
249 clksrc = esai_priv->fsysclk;
251 case ESAI_HCKT_EXTAL:
253 case ESAI_HCKR_EXTAL:
260 if (IS_ERR(clksrc)) {
261 dev_err(dai->dev, "no assigned %s clock\n",
262 clk_id % 2 ? "extal" : "fsys");
263 return PTR_ERR(clksrc);
265 clk_rate = clk_get_rate(clksrc);
267 ratio = clk_rate / freq;
268 if (ratio * freq > clk_rate)
269 ret = ratio * freq - clk_rate;
270 else if (ratio * freq < clk_rate)
271 ret = clk_rate - ratio * freq;
275 /* Block if clock source can not be divided into the required rate */
276 if (ret != 0 && clk_rate / ret < 1000) {
277 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
282 /* Only EXTAL source can be output directly without using PSR and PM */
283 if (ratio == 1 && clksrc == esai_priv->extalclk) {
284 /* Bypass all the dividers if not being needed */
285 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
287 } else if (ratio < 2) {
288 /* The ratio should be no less than 2 if using other sources */
289 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
294 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
298 esai_priv->sck_div[tx] = false;
301 esai_priv->hck_dir[tx] = dir;
302 esai_priv->hck_rate[tx] = freq;
304 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
305 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
306 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
312 * This function configures the related dividers according to the bclk rate
314 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
316 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
317 u32 hck_rate = esai_priv->hck_rate[tx];
318 u32 sub, ratio = hck_rate / freq;
321 /* Don't apply for fully slave mode or unchanged bclk */
322 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
325 if (ratio * freq > hck_rate)
326 sub = ratio * freq - hck_rate;
327 else if (ratio * freq < hck_rate)
328 sub = hck_rate - ratio * freq;
332 /* Block if clock source can not be divided into the required rate */
333 if (sub != 0 && hck_rate / sub < 1000) {
334 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
339 /* The ratio should be contented by FP alone if bypassing PM and PSR */
340 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
341 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
345 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
346 esai_priv->sck_div[tx] ? 0 : ratio);
350 /* Save current bclk rate */
351 esai_priv->sck_rate[tx] = freq;
356 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
357 u32 rx_mask, int slots, int slot_width)
359 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
361 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
362 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
364 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
365 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
367 esai_priv->slot_width = slot_width;
368 esai_priv->slots = slots;
369 esai_priv->tx_mask = tx_mask;
370 esai_priv->rx_mask = rx_mask;
375 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
377 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
378 u32 xcr = 0, xccr = 0, mask;
381 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
382 case SND_SOC_DAIFMT_I2S:
383 /* Data on rising edge of bclk, frame low, 1clk before data */
384 xcr |= ESAI_xCR_xFSR;
385 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
387 case SND_SOC_DAIFMT_LEFT_J:
388 /* Data on rising edge of bclk, frame high */
389 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
391 case SND_SOC_DAIFMT_RIGHT_J:
392 /* Data on rising edge of bclk, frame high, right aligned */
393 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
396 case SND_SOC_DAIFMT_DSP_A:
397 /* Data on rising edge of bclk, frame high, 1clk before data */
398 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
399 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
401 case SND_SOC_DAIFMT_DSP_B:
402 /* Data on rising edge of bclk, frame high */
403 xcr |= ESAI_xCR_xFSL;
404 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
410 /* DAI clock inversion */
411 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
412 case SND_SOC_DAIFMT_NB_NF:
413 /* Nothing to do for both normal cases */
415 case SND_SOC_DAIFMT_IB_NF:
416 /* Invert bit clock */
417 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
419 case SND_SOC_DAIFMT_NB_IF:
420 /* Invert frame clock */
421 xccr ^= ESAI_xCCR_xFSP;
423 case SND_SOC_DAIFMT_IB_IF:
424 /* Invert both clocks */
425 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
431 esai_priv->slave_mode = false;
433 /* DAI clock master masks */
434 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
435 case SND_SOC_DAIFMT_CBM_CFM:
436 esai_priv->slave_mode = true;
438 case SND_SOC_DAIFMT_CBS_CFM:
439 xccr |= ESAI_xCCR_xCKD;
441 case SND_SOC_DAIFMT_CBM_CFS:
442 xccr |= ESAI_xCCR_xFSD;
444 case SND_SOC_DAIFMT_CBS_CFS:
445 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
451 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
452 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
453 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
455 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
456 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
457 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
458 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
463 static int fsl_esai_startup(struct snd_pcm_substream *substream,
464 struct snd_soc_dai *dai)
466 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
470 * Some platforms might use the same bit to gate all three or two of
471 * clocks, so keep all clocks open/close at the same time for safety
473 ret = clk_prepare_enable(esai_priv->coreclk);
476 if (!IS_ERR(esai_priv->spbaclk)) {
477 ret = clk_prepare_enable(esai_priv->spbaclk);
481 if (!IS_ERR(esai_priv->extalclk)) {
482 ret = clk_prepare_enable(esai_priv->extalclk);
486 if (!IS_ERR(esai_priv->fsysclk)) {
487 ret = clk_prepare_enable(esai_priv->fsysclk);
493 /* Set synchronous mode */
494 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
495 ESAI_SAICR_SYNC, esai_priv->synchronous ?
496 ESAI_SAICR_SYNC : 0);
498 /* Set slots count */
499 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
501 ESAI_xCCR_xDC(esai_priv->slots));
502 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
504 ESAI_xCCR_xDC(esai_priv->slots));
510 if (!IS_ERR(esai_priv->extalclk))
511 clk_disable_unprepare(esai_priv->extalclk);
513 if (!IS_ERR(esai_priv->spbaclk))
514 clk_disable_unprepare(esai_priv->spbaclk);
516 clk_disable_unprepare(esai_priv->coreclk);
521 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
522 struct snd_pcm_hw_params *params,
523 struct snd_soc_dai *dai)
525 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
526 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
527 u32 width = params_width(params);
528 u32 channels = params_channels(params);
529 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
530 u32 slot_width = width;
534 /* Override slot_width if being specifically set */
535 if (esai_priv->slot_width)
536 slot_width = esai_priv->slot_width;
538 bclk = params_rate(params) * slot_width * esai_priv->slots;
540 ret = fsl_esai_set_bclk(dai, tx, bclk);
544 /* Use Normal mode to support monaural audio */
545 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
546 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
547 ESAI_xCR_xMOD_NETWORK : 0);
549 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
550 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
552 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
553 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
554 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
555 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
557 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
559 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
560 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
562 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
564 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
565 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
566 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
567 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
568 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
572 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
573 struct snd_soc_dai *dai)
575 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
577 if (!IS_ERR(esai_priv->fsysclk))
578 clk_disable_unprepare(esai_priv->fsysclk);
579 if (!IS_ERR(esai_priv->extalclk))
580 clk_disable_unprepare(esai_priv->extalclk);
581 if (!IS_ERR(esai_priv->spbaclk))
582 clk_disable_unprepare(esai_priv->spbaclk);
583 clk_disable_unprepare(esai_priv->coreclk);
586 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
587 struct snd_soc_dai *dai)
589 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
590 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
591 u8 i, channels = substream->runtime->channels;
592 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
596 case SNDRV_PCM_TRIGGER_START:
597 case SNDRV_PCM_TRIGGER_RESUME:
598 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
599 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
600 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
602 /* Write initial words reqiured by ESAI as normal procedure */
603 for (i = 0; tx && i < channels; i++)
604 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
607 * When set the TE/RE in the end of enablement flow, there
608 * will be channel swap issue for multi data line case.
609 * In order to workaround this issue, we switch the bit
610 * enablement sequence to below sequence
611 * 1) clear the xSMB & xSMA: which is done in probe and
615 * 4) set xSMA: xSMA is the last one in this flow, which
616 * will trigger esai to start.
618 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
619 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
620 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
621 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
623 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
624 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
625 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
626 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
629 case SNDRV_PCM_TRIGGER_SUSPEND:
630 case SNDRV_PCM_TRIGGER_STOP:
631 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
632 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
633 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
634 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
635 ESAI_xSMA_xS_MASK, 0);
636 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
637 ESAI_xSMB_xS_MASK, 0);
639 /* Disable and reset FIFO */
640 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
641 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
642 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
652 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
653 .startup = fsl_esai_startup,
654 .shutdown = fsl_esai_shutdown,
655 .trigger = fsl_esai_trigger,
656 .hw_params = fsl_esai_hw_params,
657 .set_sysclk = fsl_esai_set_dai_sysclk,
658 .set_fmt = fsl_esai_set_dai_fmt,
659 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
662 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
664 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
666 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
667 &esai_priv->dma_params_rx);
672 static struct snd_soc_dai_driver fsl_esai_dai = {
673 .probe = fsl_esai_dai_probe,
675 .stream_name = "CPU-Playback",
678 .rates = FSL_ESAI_RATES,
679 .formats = FSL_ESAI_FORMATS,
682 .stream_name = "CPU-Capture",
685 .rates = FSL_ESAI_RATES,
686 .formats = FSL_ESAI_FORMATS,
688 .ops = &fsl_esai_dai_ops,
691 static const struct snd_soc_component_driver fsl_esai_component = {
695 static const struct reg_default fsl_esai_reg_defaults[] = {
696 {REG_ESAI_ETDR, 0x00000000},
697 {REG_ESAI_ECR, 0x00000000},
698 {REG_ESAI_TFCR, 0x00000000},
699 {REG_ESAI_RFCR, 0x00000000},
700 {REG_ESAI_TX0, 0x00000000},
701 {REG_ESAI_TX1, 0x00000000},
702 {REG_ESAI_TX2, 0x00000000},
703 {REG_ESAI_TX3, 0x00000000},
704 {REG_ESAI_TX4, 0x00000000},
705 {REG_ESAI_TX5, 0x00000000},
706 {REG_ESAI_TSR, 0x00000000},
707 {REG_ESAI_SAICR, 0x00000000},
708 {REG_ESAI_TCR, 0x00000000},
709 {REG_ESAI_TCCR, 0x00000000},
710 {REG_ESAI_RCR, 0x00000000},
711 {REG_ESAI_RCCR, 0x00000000},
712 {REG_ESAI_TSMA, 0x0000ffff},
713 {REG_ESAI_TSMB, 0x0000ffff},
714 {REG_ESAI_RSMA, 0x0000ffff},
715 {REG_ESAI_RSMB, 0x0000ffff},
716 {REG_ESAI_PRRC, 0x00000000},
717 {REG_ESAI_PCRC, 0x00000000},
720 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
752 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
770 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
801 static const struct regmap_config fsl_esai_regmap_config = {
806 .max_register = REG_ESAI_PCRC,
807 .reg_defaults = fsl_esai_reg_defaults,
808 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
809 .readable_reg = fsl_esai_readable_reg,
810 .volatile_reg = fsl_esai_volatile_reg,
811 .writeable_reg = fsl_esai_writeable_reg,
812 .cache_type = REGCACHE_FLAT,
815 static int fsl_esai_probe(struct platform_device *pdev)
817 struct device_node *np = pdev->dev.of_node;
818 struct fsl_esai *esai_priv;
819 struct resource *res;
820 const uint32_t *iprop;
824 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
828 esai_priv->pdev = pdev;
829 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
831 /* Get the addresses and IRQ */
832 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833 regs = devm_ioremap_resource(&pdev->dev, res);
835 return PTR_ERR(regs);
837 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
838 "core", regs, &fsl_esai_regmap_config);
839 if (IS_ERR(esai_priv->regmap)) {
840 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
841 PTR_ERR(esai_priv->regmap));
842 return PTR_ERR(esai_priv->regmap);
845 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
846 if (IS_ERR(esai_priv->coreclk)) {
847 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
848 PTR_ERR(esai_priv->coreclk));
849 return PTR_ERR(esai_priv->coreclk);
852 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
853 if (IS_ERR(esai_priv->extalclk))
854 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
855 PTR_ERR(esai_priv->extalclk));
857 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
858 if (IS_ERR(esai_priv->fsysclk))
859 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
860 PTR_ERR(esai_priv->fsysclk));
862 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
863 if (IS_ERR(esai_priv->spbaclk))
864 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
865 PTR_ERR(esai_priv->spbaclk));
867 irq = platform_get_irq(pdev, 0);
869 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
873 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
874 esai_priv->name, esai_priv);
876 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
880 /* Set a default slot number */
881 esai_priv->slots = 2;
883 /* Set a default master/slave state */
884 esai_priv->slave_mode = true;
886 /* Determine the FIFO depth */
887 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
889 esai_priv->fifo_depth = be32_to_cpup(iprop);
891 esai_priv->fifo_depth = 64;
893 esai_priv->dma_params_tx.maxburst = 16;
894 esai_priv->dma_params_rx.maxburst = 16;
895 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
896 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
898 esai_priv->synchronous =
899 of_property_read_bool(np, "fsl,esai-synchronous");
901 /* Implement full symmetry for synchronous mode */
902 if (esai_priv->synchronous) {
903 fsl_esai_dai.symmetric_rates = 1;
904 fsl_esai_dai.symmetric_channels = 1;
905 fsl_esai_dai.symmetric_samplebits = 1;
908 dev_set_drvdata(&pdev->dev, esai_priv);
910 /* Reset ESAI unit */
911 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
913 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
918 * We need to enable ESAI so as to access some of its registers.
919 * Otherwise, we would fail to dump regmap from user space.
921 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
923 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
927 esai_priv->tx_mask = 0xFFFFFFFF;
928 esai_priv->rx_mask = 0xFFFFFFFF;
930 /* Clear the TSMA, TSMB, RSMA, RSMB */
931 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
932 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
933 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
934 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
936 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
939 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
943 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
945 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
950 static const struct of_device_id fsl_esai_dt_ids[] = {
951 { .compatible = "fsl,imx35-esai", },
952 { .compatible = "fsl,vf610-esai", },
955 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
957 #ifdef CONFIG_PM_SLEEP
958 static int fsl_esai_suspend(struct device *dev)
960 struct fsl_esai *esai = dev_get_drvdata(dev);
962 regcache_cache_only(esai->regmap, true);
963 regcache_mark_dirty(esai->regmap);
968 static int fsl_esai_resume(struct device *dev)
970 struct fsl_esai *esai = dev_get_drvdata(dev);
973 regcache_cache_only(esai->regmap, false);
975 /* FIFO reset for safety */
976 regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
977 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
978 regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
979 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
981 ret = regcache_sync(esai->regmap);
985 /* FIFO reset done */
986 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
987 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
991 #endif /* CONFIG_PM_SLEEP */
993 static const struct dev_pm_ops fsl_esai_pm_ops = {
994 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
997 static struct platform_driver fsl_esai_driver = {
998 .probe = fsl_esai_probe,
1000 .name = "fsl-esai-dai",
1001 .pm = &fsl_esai_pm_ops,
1002 .of_match_table = fsl_esai_dt_ids,
1006 module_platform_driver(fsl_esai_driver);
1008 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1009 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1010 MODULE_LICENSE("GPL v2");
1011 MODULE_ALIAS("platform:fsl-esai-dai");