1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
5 // Copyright (C) 2014 Freescale Semiconductor, Inc.
8 #include <linux/dmaengine.h>
9 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_platform.h>
12 #include <linux/pm_runtime.h>
13 #include <sound/dmaengine_pcm.h>
14 #include <sound/pcm_params.h>
19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
20 SNDRV_PCM_FMTBIT_S16_LE | \
21 SNDRV_PCM_FMTBIT_S20_3LE | \
22 SNDRV_PCM_FMTBIT_S24_LE)
25 * fsl_esai: ESAI private data
27 * @dma_params_rx: DMA parameters for receive channel
28 * @dma_params_tx: DMA parameters for transmit channel
29 * @pdev: platform device pointer
30 * @regmap: regmap handler
31 * @coreclk: clock source to access register
32 * @extalclk: esai clock source to derive HCK, SCK and FS
33 * @fsysclk: system clock source to derive HCK, SCK and FS
34 * @spbaclk: SPBA clock (optional, depending on SoC design)
35 * @task: tasklet to handle the reset operation
36 * @lock: spin lock between hw_reset() and trigger()
37 * @fifo_depth: depth of tx/rx FIFO
38 * @slot_width: width of each DAI slot
39 * @slots: number of slots
40 * @channels: channel num for tx or rx
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
47 * @reset_at_xrun: flags for enable reset operaton
51 struct snd_dmaengine_dai_dma_data dma_params_rx;
52 struct snd_dmaengine_dai_dma_data dma_params_tx;
53 struct platform_device *pdev;
54 struct regmap *regmap;
59 struct tasklet_struct task;
60 spinlock_t lock; /* Protect hw_reset and trigger */
77 static irqreturn_t esai_isr(int irq, void *devid)
79 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
80 struct platform_device *pdev = esai_priv->pdev;
84 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
85 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
87 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) &&
88 esai_priv->reset_at_xrun) {
89 dev_dbg(&pdev->dev, "reset module for xrun\n");
90 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
91 ESAI_xCR_xEIE_MASK, 0);
92 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
93 ESAI_xCR_xEIE_MASK, 0);
94 tasklet_schedule(&esai_priv->task);
97 if (esr & ESAI_ESR_TINIT_MASK)
98 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n");
100 if (esr & ESAI_ESR_RFF_MASK)
101 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
103 if (esr & ESAI_ESR_TFE_MASK)
104 dev_warn(&pdev->dev, "isr: Transmission underrun\n");
106 if (esr & ESAI_ESR_TLS_MASK)
107 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
109 if (esr & ESAI_ESR_TDE_MASK)
110 dev_dbg(&pdev->dev, "isr: Transmission data exception\n");
112 if (esr & ESAI_ESR_TED_MASK)
113 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
115 if (esr & ESAI_ESR_TD_MASK)
116 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
118 if (esr & ESAI_ESR_RLS_MASK)
119 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
121 if (esr & ESAI_ESR_RDE_MASK)
122 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
124 if (esr & ESAI_ESR_RED_MASK)
125 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
127 if (esr & ESAI_ESR_RD_MASK)
128 dev_dbg(&pdev->dev, "isr: Receiving data\n");
134 * This function is used to calculate the divisors of psr, pm, fp and it is
135 * supposed to be called in set_dai_sysclk() and set_bclk().
137 * @ratio: desired overall ratio for the paticipating dividers
138 * @usefp: for HCK setting, there is no need to set fp divider
139 * @fp: bypass other dividers by setting fp directly if fp != 0
140 * @tx: current setting is for playback or capture
142 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
145 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
146 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
148 maxfp = usefp ? 16 : 1;
153 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
154 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
155 2 * 8 * 256 * maxfp);
157 } else if (ratio % 2) {
158 dev_err(dai->dev, "the raio must be even if using upper divider\n");
164 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
166 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */
173 /* Set the max fluctuation -- 0.1% of the max devisor */
174 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
176 /* Find the best value for PM */
177 for (i = 1; i <= 256; i++) {
178 for (j = 1; j <= maxfp; j++) {
179 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
180 prod = (psr ? 1 : 8) * i * j;
184 else if (prod / ratio == 1)
186 else if (ratio / prod == 1)
191 /* Calculate the fraction */
192 sub = sub * 1000 / ratio;
206 dev_err(dai->dev, "failed to calculate proper divisors\n");
211 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
212 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
213 psr | ESAI_xCCR_xPM(pm));
216 /* Bypass fp if not being required */
220 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
221 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
227 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
230 * clk_id: The clock source of HCKT/HCKR
231 * (Input from outside; output from inside, FSYS or EXTAL)
232 * freq: The required clock rate of HCKT/HCKR
233 * dir: The clock direction of HCKT/HCKR
235 * Note: If the direction is input, we do not care about clk_id.
237 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
238 unsigned int freq, int dir)
240 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
241 struct clk *clksrc = esai_priv->extalclk;
242 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous);
243 bool in = dir == SND_SOC_CLOCK_IN;
245 unsigned long clk_rate;
249 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n",
250 in ? "in" : "out", tx ? 'T' : 'R');
254 /* Bypass divider settings if the requirement doesn't change */
255 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
258 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
259 esai_priv->sck_div[tx] = true;
261 /* Set the direction of HCKT/HCKR pins */
262 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
263 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
271 clksrc = esai_priv->fsysclk;
273 case ESAI_HCKT_EXTAL:
276 case ESAI_HCKR_EXTAL:
277 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
283 if (IS_ERR(clksrc)) {
284 dev_err(dai->dev, "no assigned %s clock\n",
285 clk_id % 2 ? "extal" : "fsys");
286 return PTR_ERR(clksrc);
288 clk_rate = clk_get_rate(clksrc);
290 ratio = clk_rate / freq;
291 if (ratio * freq > clk_rate)
292 ret = ratio * freq - clk_rate;
293 else if (ratio * freq < clk_rate)
294 ret = clk_rate - ratio * freq;
298 /* Block if clock source can not be divided into the required rate */
299 if (ret != 0 && clk_rate / ret < 1000) {
300 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
305 /* Only EXTAL source can be output directly without using PSR and PM */
306 if (ratio == 1 && clksrc == esai_priv->extalclk) {
307 /* Bypass all the dividers if not being needed */
308 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
310 } else if (ratio < 2) {
311 /* The ratio should be no less than 2 if using other sources */
312 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
317 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
321 esai_priv->sck_div[tx] = false;
324 esai_priv->hck_dir[tx] = dir;
325 esai_priv->hck_rate[tx] = freq;
327 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
328 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
329 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
335 * This function configures the related dividers according to the bclk rate
337 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
339 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
340 u32 hck_rate = esai_priv->hck_rate[tx];
341 u32 sub, ratio = hck_rate / freq;
344 /* Don't apply for fully slave mode or unchanged bclk */
345 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
348 if (ratio * freq > hck_rate)
349 sub = ratio * freq - hck_rate;
350 else if (ratio * freq < hck_rate)
351 sub = hck_rate - ratio * freq;
355 /* Block if clock source can not be divided into the required rate */
356 if (sub != 0 && hck_rate / sub < 1000) {
357 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
362 /* The ratio should be contented by FP alone if bypassing PM and PSR */
363 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
364 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
368 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
369 esai_priv->sck_div[tx] ? 0 : ratio);
373 /* Save current bclk rate */
374 esai_priv->sck_rate[tx] = freq;
379 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
380 u32 rx_mask, int slots, int slot_width)
382 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
384 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
385 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
387 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
388 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
390 esai_priv->slot_width = slot_width;
391 esai_priv->slots = slots;
392 esai_priv->tx_mask = tx_mask;
393 esai_priv->rx_mask = rx_mask;
398 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
400 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
401 u32 xcr = 0, xccr = 0, mask;
404 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
405 case SND_SOC_DAIFMT_I2S:
406 /* Data on rising edge of bclk, frame low, 1clk before data */
407 xcr |= ESAI_xCR_xFSR;
408 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
410 case SND_SOC_DAIFMT_LEFT_J:
411 /* Data on rising edge of bclk, frame high */
412 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
414 case SND_SOC_DAIFMT_RIGHT_J:
415 /* Data on rising edge of bclk, frame high, right aligned */
416 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
419 case SND_SOC_DAIFMT_DSP_A:
420 /* Data on rising edge of bclk, frame high, 1clk before data */
421 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
422 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
424 case SND_SOC_DAIFMT_DSP_B:
425 /* Data on rising edge of bclk, frame high */
426 xcr |= ESAI_xCR_xFSL;
427 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
433 /* DAI clock inversion */
434 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
435 case SND_SOC_DAIFMT_NB_NF:
436 /* Nothing to do for both normal cases */
438 case SND_SOC_DAIFMT_IB_NF:
439 /* Invert bit clock */
440 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
442 case SND_SOC_DAIFMT_NB_IF:
443 /* Invert frame clock */
444 xccr ^= ESAI_xCCR_xFSP;
446 case SND_SOC_DAIFMT_IB_IF:
447 /* Invert both clocks */
448 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
454 esai_priv->slave_mode = false;
456 /* DAI clock master masks */
457 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
458 case SND_SOC_DAIFMT_CBM_CFM:
459 esai_priv->slave_mode = true;
461 case SND_SOC_DAIFMT_CBS_CFM:
462 xccr |= ESAI_xCCR_xCKD;
464 case SND_SOC_DAIFMT_CBM_CFS:
465 xccr |= ESAI_xCCR_xFSD;
467 case SND_SOC_DAIFMT_CBS_CFS:
468 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
474 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA;
475 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
476 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
478 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
479 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
480 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
481 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
486 static int fsl_esai_startup(struct snd_pcm_substream *substream,
487 struct snd_soc_dai *dai)
489 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
492 /* Set synchronous mode */
493 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
494 ESAI_SAICR_SYNC, esai_priv->synchronous ?
495 ESAI_SAICR_SYNC : 0);
497 /* Set slots count */
498 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
500 ESAI_xCCR_xDC(esai_priv->slots));
501 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
503 ESAI_xCCR_xDC(esai_priv->slots));
510 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
511 struct snd_pcm_hw_params *params,
512 struct snd_soc_dai *dai)
514 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
515 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
516 u32 width = params_width(params);
517 u32 channels = params_channels(params);
518 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
519 u32 slot_width = width;
523 /* Override slot_width if being specifically set */
524 if (esai_priv->slot_width)
525 slot_width = esai_priv->slot_width;
527 bclk = params_rate(params) * slot_width * esai_priv->slots;
529 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk);
533 mask = ESAI_xCR_xSWS_MASK;
534 val = ESAI_xCR_xSWS(slot_width, width);
536 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
537 /* Recording in synchronous mode needs to set TCR also */
538 if (!tx && esai_priv->synchronous)
539 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
541 /* Use Normal mode to support monaural audio */
542 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
543 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
544 ESAI_xCR_xMOD_NETWORK : 0);
546 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
547 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
549 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
550 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
551 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
552 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
554 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
557 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
558 ESAI_xCR_PADC, ESAI_xCR_PADC);
560 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
561 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
562 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
563 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
564 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
568 static int fsl_esai_hw_init(struct fsl_esai *esai_priv)
570 struct platform_device *pdev = esai_priv->pdev;
573 /* Reset ESAI unit */
574 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
575 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
576 ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
578 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
583 * We need to enable ESAI so as to access some of its registers.
584 * Otherwise, we would fail to dump regmap from user space.
586 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
587 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
590 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
594 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
595 ESAI_PRRC_PDC_MASK, 0);
596 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
597 ESAI_PCRC_PC_MASK, 0);
602 static int fsl_esai_register_restore(struct fsl_esai *esai_priv)
606 /* FIFO reset for safety */
607 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR,
608 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
609 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR,
610 ESAI_xFCR_xFR, ESAI_xFCR_xFR);
612 regcache_mark_dirty(esai_priv->regmap);
613 ret = regcache_sync(esai_priv->regmap);
617 /* FIFO reset done */
618 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
619 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
624 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx)
626 u8 i, channels = esai_priv->channels[tx];
627 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
630 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
631 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
633 /* Write initial words reqiured by ESAI as normal procedure */
634 for (i = 0; tx && i < channels; i++)
635 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
638 * When set the TE/RE in the end of enablement flow, there
639 * will be channel swap issue for multi data line case.
640 * In order to workaround this issue, we switch the bit
641 * enablement sequence to below sequence
642 * 1) clear the xSMB & xSMA: which is done in probe and
646 * 4) set xSMA: xSMA is the last one in this flow, which
647 * will trigger esai to start.
649 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
650 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
651 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
652 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
654 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
655 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
656 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
657 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
659 /* Enable Exception interrupt */
660 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
661 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE);
664 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx)
666 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
667 ESAI_xCR_xEIE_MASK, 0);
669 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
670 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
671 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
672 ESAI_xSMA_xS_MASK, 0);
673 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
674 ESAI_xSMB_xS_MASK, 0);
676 /* Disable and reset FIFO */
677 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
678 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
679 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
683 static void fsl_esai_hw_reset(unsigned long arg)
685 struct fsl_esai *esai_priv = (struct fsl_esai *)arg;
686 bool tx = true, rx = false, enabled[2];
687 unsigned long lock_flags;
690 spin_lock_irqsave(&esai_priv->lock, lock_flags);
691 /* Save the registers */
692 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr);
693 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr);
694 enabled[tx] = tfcr & ESAI_xFCR_xFEN;
695 enabled[rx] = rfcr & ESAI_xFCR_xFEN;
697 /* Stop the tx & rx */
698 fsl_esai_trigger_stop(esai_priv, tx);
699 fsl_esai_trigger_stop(esai_priv, rx);
701 /* Reset the esai, and ignore return value */
702 fsl_esai_hw_init(esai_priv);
704 /* Enforce ESAI personal resets for both TX and RX */
705 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
706 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
707 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
708 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
710 /* Restore registers by regcache_sync, and ignore return value */
711 fsl_esai_register_restore(esai_priv);
713 /* Remove ESAI personal resets by configuring PCRC and PRRC also */
714 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
715 ESAI_xCR_xPR_MASK, 0);
716 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
717 ESAI_xCR_xPR_MASK, 0);
718 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
719 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
720 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
721 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
723 /* Restart tx / rx, if they already enabled */
725 fsl_esai_trigger_start(esai_priv, tx);
727 fsl_esai_trigger_start(esai_priv, rx);
729 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
732 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
733 struct snd_soc_dai *dai)
735 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
736 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
737 unsigned long lock_flags;
739 esai_priv->channels[tx] = substream->runtime->channels;
742 case SNDRV_PCM_TRIGGER_START:
743 case SNDRV_PCM_TRIGGER_RESUME:
744 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
745 spin_lock_irqsave(&esai_priv->lock, lock_flags);
746 fsl_esai_trigger_start(esai_priv, tx);
747 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
749 case SNDRV_PCM_TRIGGER_SUSPEND:
750 case SNDRV_PCM_TRIGGER_STOP:
751 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
752 spin_lock_irqsave(&esai_priv->lock, lock_flags);
753 fsl_esai_trigger_stop(esai_priv, tx);
754 spin_unlock_irqrestore(&esai_priv->lock, lock_flags);
763 static const struct snd_soc_dai_ops fsl_esai_dai_ops = {
764 .startup = fsl_esai_startup,
765 .trigger = fsl_esai_trigger,
766 .hw_params = fsl_esai_hw_params,
767 .set_sysclk = fsl_esai_set_dai_sysclk,
768 .set_fmt = fsl_esai_set_dai_fmt,
769 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
772 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
774 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
776 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
777 &esai_priv->dma_params_rx);
782 static struct snd_soc_dai_driver fsl_esai_dai = {
783 .probe = fsl_esai_dai_probe,
785 .stream_name = "CPU-Playback",
788 .rates = SNDRV_PCM_RATE_8000_192000,
789 .formats = FSL_ESAI_FORMATS,
792 .stream_name = "CPU-Capture",
795 .rates = SNDRV_PCM_RATE_8000_192000,
796 .formats = FSL_ESAI_FORMATS,
798 .ops = &fsl_esai_dai_ops,
801 static const struct snd_soc_component_driver fsl_esai_component = {
805 static const struct reg_default fsl_esai_reg_defaults[] = {
806 {REG_ESAI_ETDR, 0x00000000},
807 {REG_ESAI_ECR, 0x00000000},
808 {REG_ESAI_TFCR, 0x00000000},
809 {REG_ESAI_RFCR, 0x00000000},
810 {REG_ESAI_TX0, 0x00000000},
811 {REG_ESAI_TX1, 0x00000000},
812 {REG_ESAI_TX2, 0x00000000},
813 {REG_ESAI_TX3, 0x00000000},
814 {REG_ESAI_TX4, 0x00000000},
815 {REG_ESAI_TX5, 0x00000000},
816 {REG_ESAI_TSR, 0x00000000},
817 {REG_ESAI_SAICR, 0x00000000},
818 {REG_ESAI_TCR, 0x00000000},
819 {REG_ESAI_TCCR, 0x00000000},
820 {REG_ESAI_RCR, 0x00000000},
821 {REG_ESAI_RCCR, 0x00000000},
822 {REG_ESAI_TSMA, 0x0000ffff},
823 {REG_ESAI_TSMB, 0x0000ffff},
824 {REG_ESAI_RSMA, 0x0000ffff},
825 {REG_ESAI_RSMB, 0x0000ffff},
826 {REG_ESAI_PRRC, 0x00000000},
827 {REG_ESAI_PCRC, 0x00000000},
830 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
862 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
880 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
911 static const struct regmap_config fsl_esai_regmap_config = {
916 .max_register = REG_ESAI_PCRC,
917 .reg_defaults = fsl_esai_reg_defaults,
918 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults),
919 .readable_reg = fsl_esai_readable_reg,
920 .volatile_reg = fsl_esai_volatile_reg,
921 .writeable_reg = fsl_esai_writeable_reg,
922 .cache_type = REGCACHE_FLAT,
925 static int fsl_esai_probe(struct platform_device *pdev)
927 struct device_node *np = pdev->dev.of_node;
928 struct fsl_esai *esai_priv;
929 struct resource *res;
934 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
938 esai_priv->pdev = pdev;
939 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np);
941 if (of_device_is_compatible(np, "fsl,vf610-esai") ||
942 of_device_is_compatible(np, "fsl,imx35-esai"))
943 esai_priv->reset_at_xrun = true;
945 /* Get the addresses and IRQ */
946 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
947 regs = devm_ioremap_resource(&pdev->dev, res);
949 return PTR_ERR(regs);
951 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
952 "core", regs, &fsl_esai_regmap_config);
953 if (IS_ERR(esai_priv->regmap)) {
954 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
955 PTR_ERR(esai_priv->regmap));
956 return PTR_ERR(esai_priv->regmap);
959 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
960 if (IS_ERR(esai_priv->coreclk)) {
961 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
962 PTR_ERR(esai_priv->coreclk));
963 return PTR_ERR(esai_priv->coreclk);
966 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
967 if (IS_ERR(esai_priv->extalclk))
968 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
969 PTR_ERR(esai_priv->extalclk));
971 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
972 if (IS_ERR(esai_priv->fsysclk))
973 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
974 PTR_ERR(esai_priv->fsysclk));
976 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
977 if (IS_ERR(esai_priv->spbaclk))
978 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
979 PTR_ERR(esai_priv->spbaclk));
981 irq = platform_get_irq(pdev, 0);
985 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
986 esai_priv->name, esai_priv);
988 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
992 /* Set a default slot number */
993 esai_priv->slots = 2;
995 /* Set a default master/slave state */
996 esai_priv->slave_mode = true;
998 /* Determine the FIFO depth */
999 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1001 esai_priv->fifo_depth = be32_to_cpup(iprop);
1003 esai_priv->fifo_depth = 64;
1005 esai_priv->dma_params_tx.maxburst = 16;
1006 esai_priv->dma_params_rx.maxburst = 16;
1007 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
1008 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
1010 esai_priv->synchronous =
1011 of_property_read_bool(np, "fsl,esai-synchronous");
1013 /* Implement full symmetry for synchronous mode */
1014 if (esai_priv->synchronous) {
1015 fsl_esai_dai.symmetric_rates = 1;
1016 fsl_esai_dai.symmetric_channels = 1;
1017 fsl_esai_dai.symmetric_samplebits = 1;
1020 dev_set_drvdata(&pdev->dev, esai_priv);
1022 spin_lock_init(&esai_priv->lock);
1023 ret = fsl_esai_hw_init(esai_priv);
1027 esai_priv->tx_mask = 0xFFFFFFFF;
1028 esai_priv->rx_mask = 0xFFFFFFFF;
1030 /* Clear the TSMA, TSMB, RSMA, RSMB */
1031 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0);
1032 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0);
1033 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0);
1034 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0);
1036 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
1039 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1043 tasklet_init(&esai_priv->task, fsl_esai_hw_reset,
1044 (unsigned long)esai_priv);
1046 pm_runtime_enable(&pdev->dev);
1048 regcache_cache_only(esai_priv->regmap, true);
1050 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
1052 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
1057 static int fsl_esai_remove(struct platform_device *pdev)
1059 struct fsl_esai *esai_priv = platform_get_drvdata(pdev);
1061 pm_runtime_disable(&pdev->dev);
1062 tasklet_kill(&esai_priv->task);
1067 static const struct of_device_id fsl_esai_dt_ids[] = {
1068 { .compatible = "fsl,imx35-esai", },
1069 { .compatible = "fsl,vf610-esai", },
1070 { .compatible = "fsl,imx6ull-esai", },
1073 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
1076 static int fsl_esai_runtime_resume(struct device *dev)
1078 struct fsl_esai *esai = dev_get_drvdata(dev);
1082 * Some platforms might use the same bit to gate all three or two of
1083 * clocks, so keep all clocks open/close at the same time for safety
1085 ret = clk_prepare_enable(esai->coreclk);
1088 if (!IS_ERR(esai->spbaclk)) {
1089 ret = clk_prepare_enable(esai->spbaclk);
1093 if (!IS_ERR(esai->extalclk)) {
1094 ret = clk_prepare_enable(esai->extalclk);
1098 if (!IS_ERR(esai->fsysclk)) {
1099 ret = clk_prepare_enable(esai->fsysclk);
1104 regcache_cache_only(esai->regmap, false);
1106 ret = fsl_esai_register_restore(esai);
1108 goto err_regcache_sync;
1113 if (!IS_ERR(esai->fsysclk))
1114 clk_disable_unprepare(esai->fsysclk);
1116 if (!IS_ERR(esai->extalclk))
1117 clk_disable_unprepare(esai->extalclk);
1119 if (!IS_ERR(esai->spbaclk))
1120 clk_disable_unprepare(esai->spbaclk);
1122 clk_disable_unprepare(esai->coreclk);
1127 static int fsl_esai_runtime_suspend(struct device *dev)
1129 struct fsl_esai *esai = dev_get_drvdata(dev);
1131 regcache_cache_only(esai->regmap, true);
1133 if (!IS_ERR(esai->fsysclk))
1134 clk_disable_unprepare(esai->fsysclk);
1135 if (!IS_ERR(esai->extalclk))
1136 clk_disable_unprepare(esai->extalclk);
1137 if (!IS_ERR(esai->spbaclk))
1138 clk_disable_unprepare(esai->spbaclk);
1139 clk_disable_unprepare(esai->coreclk);
1143 #endif /* CONFIG_PM */
1145 static const struct dev_pm_ops fsl_esai_pm_ops = {
1146 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend,
1147 fsl_esai_runtime_resume,
1149 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1150 pm_runtime_force_resume)
1153 static struct platform_driver fsl_esai_driver = {
1154 .probe = fsl_esai_probe,
1155 .remove = fsl_esai_remove,
1157 .name = "fsl-esai-dai",
1158 .pm = &fsl_esai_pm_ops,
1159 .of_match_table = fsl_esai_dt_ids,
1163 module_platform_driver(fsl_esai_driver);
1165 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1166 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
1167 MODULE_LICENSE("GPL v2");
1168 MODULE_ALIAS("platform:fsl-esai-dai");