2 * ALSA SoC Synopsys I2S Audio Layer
4 * sound/soc/dwc/designware_i2s.c
6 * Copyright (C) 2010 ST Microelectronics
7 * Rajeev Kumar <rajeevkumar.linux@gmail.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/pm_runtime.h>
22 #include <sound/designware_i2s.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/dmaengine_pcm.h>
29 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
31 writel(val, io_base + reg);
34 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
36 return readl(io_base + reg);
39 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
43 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
44 for (i = 0; i < 4; i++)
45 i2s_write_reg(dev->i2s_base, TER(i), 0);
47 for (i = 0; i < 4; i++)
48 i2s_write_reg(dev->i2s_base, RER(i), 0);
52 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
56 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
57 for (i = 0; i < 4; i++)
58 i2s_read_reg(dev->i2s_base, TOR(i));
60 for (i = 0; i < 4; i++)
61 i2s_read_reg(dev->i2s_base, ROR(i));
65 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
70 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
71 for (i = 0; i < (chan_nr / 2); i++) {
72 irq = i2s_read_reg(dev->i2s_base, IMR(i));
73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
76 for (i = 0; i < (chan_nr / 2); i++) {
77 irq = i2s_read_reg(dev->i2s_base, IMR(i));
78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
83 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
88 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
89 for (i = 0; i < (chan_nr / 2); i++) {
90 irq = i2s_read_reg(dev->i2s_base, IMR(i));
91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
94 for (i = 0; i < (chan_nr / 2); i++) {
95 irq = i2s_read_reg(dev->i2s_base, IMR(i));
96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
101 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
103 struct dw_i2s_dev *dev = dev_id;
104 bool irq_valid = false;
108 for (i = 0; i < 4; i++)
109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
114 for (i = 0; i < 4; i++) {
116 * Check if TX fifo is empty. If empty fill FIFO with samples
117 * NOTE: Only two channels supported
119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
125 * Data available. Retrieve samples from FIFO
126 * NOTE: Only two channels supported
128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
133 /* Error Handling: TX */
134 if (isr[i] & ISR_TXFO) {
135 dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
139 /* Error Handling: TX */
140 if (isr[i] & ISR_RXFO) {
141 dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
152 static void i2s_start(struct dw_i2s_dev *dev,
153 struct snd_pcm_substream *substream)
155 struct i2s_clk_config_data *config = &dev->config;
157 i2s_write_reg(dev->i2s_base, IER, 1);
158 i2s_enable_irqs(dev, substream->stream, config->chan_nr);
160 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
161 i2s_write_reg(dev->i2s_base, ITER, 1);
163 i2s_write_reg(dev->i2s_base, IRER, 1);
165 i2s_write_reg(dev->i2s_base, CER, 1);
168 static void i2s_stop(struct dw_i2s_dev *dev,
169 struct snd_pcm_substream *substream)
172 i2s_clear_irqs(dev, substream->stream);
173 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
174 i2s_write_reg(dev->i2s_base, ITER, 0);
176 i2s_write_reg(dev->i2s_base, IRER, 0);
178 i2s_disable_irqs(dev, substream->stream, 8);
181 i2s_write_reg(dev->i2s_base, CER, 0);
182 i2s_write_reg(dev->i2s_base, IER, 0);
186 static int dw_i2s_startup(struct snd_pcm_substream *substream,
187 struct snd_soc_dai *cpu_dai)
189 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
190 union dw_i2s_snd_dma_data *dma_data = NULL;
192 if (!(dev->capability & DWC_I2S_RECORD) &&
193 (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
196 if (!(dev->capability & DWC_I2S_PLAY) &&
197 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 dma_data = &dev->play_dma_data;
202 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
203 dma_data = &dev->capture_dma_data;
205 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
210 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
213 struct i2s_clk_config_data *config = &dev->config;
216 i2s_disable_channels(dev, stream);
218 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
220 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
221 dev->xfer_resolution);
222 i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
224 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
226 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
227 dev->xfer_resolution);
228 i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
230 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
236 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
237 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
239 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
240 struct i2s_clk_config_data *config = &dev->config;
243 switch (params_format(params)) {
244 case SNDRV_PCM_FORMAT_S16_LE:
245 config->data_width = 16;
247 dev->xfer_resolution = 0x02;
250 case SNDRV_PCM_FORMAT_S24_LE:
251 config->data_width = 24;
253 dev->xfer_resolution = 0x04;
256 case SNDRV_PCM_FORMAT_S32_LE:
257 config->data_width = 32;
259 dev->xfer_resolution = 0x05;
263 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
267 config->chan_nr = params_channels(params);
269 switch (config->chan_nr) {
270 case EIGHT_CHANNEL_SUPPORT:
271 case SIX_CHANNEL_SUPPORT:
272 case FOUR_CHANNEL_SUPPORT:
273 case TWO_CHANNEL_SUPPORT:
276 dev_err(dev->dev, "channel not supported\n");
280 dw_i2s_config(dev, substream->stream);
282 i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
284 config->sample_rate = params_rate(params);
286 if (dev->capability & DW_I2S_MASTER) {
287 if (dev->i2s_clk_cfg) {
288 ret = dev->i2s_clk_cfg(config);
290 dev_err(dev->dev, "runtime audio clk config fail\n");
294 u32 bitclk = config->sample_rate *
295 config->data_width * 2;
297 ret = clk_set_rate(dev->clk, bitclk);
299 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
308 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
309 struct snd_soc_dai *dai)
311 snd_soc_dai_set_dma_data(dai, substream, NULL);
314 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
315 struct snd_soc_dai *dai)
317 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
319 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
320 i2s_write_reg(dev->i2s_base, TXFFR, 1);
322 i2s_write_reg(dev->i2s_base, RXFFR, 1);
327 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
328 int cmd, struct snd_soc_dai *dai)
330 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
334 case SNDRV_PCM_TRIGGER_START:
335 case SNDRV_PCM_TRIGGER_RESUME:
336 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
338 i2s_start(dev, substream);
341 case SNDRV_PCM_TRIGGER_STOP:
342 case SNDRV_PCM_TRIGGER_SUSPEND:
343 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
345 i2s_stop(dev, substream);
354 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
356 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
359 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
360 case SND_SOC_DAIFMT_CBP_CFP:
361 if (dev->capability & DW_I2S_SLAVE)
366 case SND_SOC_DAIFMT_CBC_CFC:
367 if (dev->capability & DW_I2S_MASTER)
372 case SND_SOC_DAIFMT_CBP_CFC:
373 case SND_SOC_DAIFMT_CBC_CFP:
377 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
384 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
385 .startup = dw_i2s_startup,
386 .shutdown = dw_i2s_shutdown,
387 .hw_params = dw_i2s_hw_params,
388 .prepare = dw_i2s_prepare,
389 .trigger = dw_i2s_trigger,
390 .set_fmt = dw_i2s_set_fmt,
394 static int dw_i2s_runtime_suspend(struct device *dev)
396 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
398 if (dw_dev->capability & DW_I2S_MASTER)
399 clk_disable(dw_dev->clk);
403 static int dw_i2s_runtime_resume(struct device *dev)
405 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
408 if (dw_dev->capability & DW_I2S_MASTER) {
409 ret = clk_enable(dw_dev->clk);
416 static int dw_i2s_suspend(struct snd_soc_component *component)
418 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
420 if (dev->capability & DW_I2S_MASTER)
421 clk_disable(dev->clk);
425 static int dw_i2s_resume(struct snd_soc_component *component)
427 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
428 struct snd_soc_dai *dai;
431 if (dev->capability & DW_I2S_MASTER) {
432 ret = clk_enable(dev->clk);
437 for_each_component_dais(component, dai) {
438 for_each_pcm_streams(stream)
439 if (snd_soc_dai_stream_active(dai, stream))
440 dw_i2s_config(dev, stream);
447 #define dw_i2s_suspend NULL
448 #define dw_i2s_resume NULL
451 static const struct snd_soc_component_driver dw_i2s_component = {
453 .suspend = dw_i2s_suspend,
454 .resume = dw_i2s_resume,
458 * The following tables allow a direct lookup of various parameters
459 * defined in the I2S block's configuration in terms of sound system
460 * parameters. Each table is sized to the number of entries possible
461 * according to the number of configuration bits describing an I2S
465 /* Maximum bit resolution of a channel - not uniformly spaced */
466 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
467 12, 16, 20, 24, 32, 0, 0, 0
470 /* Width of (DMA) bus */
471 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
472 DMA_SLAVE_BUSWIDTH_1_BYTE,
473 DMA_SLAVE_BUSWIDTH_2_BYTES,
474 DMA_SLAVE_BUSWIDTH_4_BYTES,
475 DMA_SLAVE_BUSWIDTH_UNDEFINED
478 /* PCM format to support channel resolution */
479 static const u32 formats[COMP_MAX_WORDSIZE] = {
480 SNDRV_PCM_FMTBIT_S16_LE,
481 SNDRV_PCM_FMTBIT_S16_LE,
482 SNDRV_PCM_FMTBIT_S24_LE,
483 SNDRV_PCM_FMTBIT_S24_LE,
484 SNDRV_PCM_FMTBIT_S32_LE,
490 static int dw_configure_dai(struct dw_i2s_dev *dev,
491 struct snd_soc_dai_driver *dw_i2s_dai,
495 * Read component parameter registers to extract
496 * the I2S block's configuration.
498 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
499 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
500 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
503 if (dev->capability & DWC_I2S_RECORD &&
504 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
505 comp1 = comp1 & ~BIT(5);
507 if (dev->capability & DWC_I2S_PLAY &&
508 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
509 comp1 = comp1 & ~BIT(6);
511 if (COMP1_TX_ENABLED(comp1)) {
512 dev_dbg(dev->dev, " designware: play supported\n");
513 idx = COMP1_TX_WORDSIZE_0(comp1);
514 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
516 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
518 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
519 dw_i2s_dai->playback.channels_max =
520 1 << (COMP1_TX_CHANNELS(comp1) + 1);
521 dw_i2s_dai->playback.formats = formats[idx];
522 dw_i2s_dai->playback.rates = rates;
525 if (COMP1_RX_ENABLED(comp1)) {
526 dev_dbg(dev->dev, "designware: record supported\n");
527 idx = COMP2_RX_WORDSIZE_0(comp2);
528 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
530 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
532 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
533 dw_i2s_dai->capture.channels_max =
534 1 << (COMP1_RX_CHANNELS(comp1) + 1);
535 dw_i2s_dai->capture.formats = formats[idx];
536 dw_i2s_dai->capture.rates = rates;
539 if (COMP1_MODE_EN(comp1)) {
540 dev_dbg(dev->dev, "designware: i2s master mode supported\n");
541 dev->capability |= DW_I2S_MASTER;
543 dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
544 dev->capability |= DW_I2S_SLAVE;
547 dev->fifo_th = fifo_depth / 2;
551 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
552 struct snd_soc_dai_driver *dw_i2s_dai,
553 struct resource *res,
554 const struct i2s_platform_data *pdata)
556 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
557 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
560 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
563 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
567 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
569 /* Set DMA slaves info */
570 dev->play_dma_data.pd.data = pdata->play_dma_data;
571 dev->capture_dma_data.pd.data = pdata->capture_dma_data;
572 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
573 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
574 dev->play_dma_data.pd.max_burst = 16;
575 dev->capture_dma_data.pd.max_burst = 16;
576 dev->play_dma_data.pd.addr_width = bus_widths[idx];
577 dev->capture_dma_data.pd.addr_width = bus_widths[idx];
578 dev->play_dma_data.pd.filter = pdata->filter;
579 dev->capture_dma_data.pd.filter = pdata->filter;
584 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
585 struct snd_soc_dai_driver *dw_i2s_dai,
586 struct resource *res)
588 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
589 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
590 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
591 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
595 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
598 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
602 if (COMP1_TX_ENABLED(comp1)) {
603 idx2 = COMP1_TX_WORDSIZE_0(comp1);
605 dev->capability |= DWC_I2S_PLAY;
606 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
607 dev->play_dma_data.dt.addr_width = bus_widths[idx];
608 dev->play_dma_data.dt.fifo_size = fifo_depth *
609 (fifo_width[idx2]) >> 8;
610 dev->play_dma_data.dt.maxburst = 16;
612 if (COMP1_RX_ENABLED(comp1)) {
613 idx2 = COMP2_RX_WORDSIZE_0(comp2);
615 dev->capability |= DWC_I2S_RECORD;
616 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
617 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
618 dev->capture_dma_data.dt.fifo_size = fifo_depth *
619 (fifo_width[idx2] >> 8);
620 dev->capture_dma_data.dt.maxburst = 16;
627 static int dw_i2s_probe(struct platform_device *pdev)
629 const struct i2s_platform_data *pdata = pdev->dev.platform_data;
630 struct dw_i2s_dev *dev;
631 struct resource *res;
633 struct snd_soc_dai_driver *dw_i2s_dai;
636 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
640 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
644 dw_i2s_dai->ops = &dw_i2s_dai_ops;
646 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
647 if (IS_ERR(dev->i2s_base))
648 return PTR_ERR(dev->i2s_base);
650 dev->dev = &pdev->dev;
652 irq = platform_get_irq_optional(pdev, 0);
654 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
657 dev_err(&pdev->dev, "failed to request irq\n");
662 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
663 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
665 dev->capability = pdata->cap;
667 dev->quirks = pdata->quirks;
668 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
669 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
670 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
672 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
675 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
680 if (dev->capability & DW_I2S_MASTER) {
682 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
683 if (!dev->i2s_clk_cfg) {
684 dev_err(&pdev->dev, "no clock configure method\n");
688 dev->clk = devm_clk_get(&pdev->dev, clk_id);
690 if (IS_ERR(dev->clk))
691 return PTR_ERR(dev->clk);
693 ret = clk_prepare_enable(dev->clk);
698 dev_set_drvdata(&pdev->dev, dev);
699 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
702 dev_err(&pdev->dev, "not able to register dai\n");
703 goto err_clk_disable;
708 ret = dw_pcm_register(pdev);
711 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
713 dev->use_pio = false;
717 dev_err(&pdev->dev, "could not register pcm: %d\n",
719 goto err_clk_disable;
723 pm_runtime_enable(&pdev->dev);
727 if (dev->capability & DW_I2S_MASTER)
728 clk_disable_unprepare(dev->clk);
732 static int dw_i2s_remove(struct platform_device *pdev)
734 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
736 if (dev->capability & DW_I2S_MASTER)
737 clk_disable_unprepare(dev->clk);
739 pm_runtime_disable(&pdev->dev);
744 static const struct of_device_id dw_i2s_of_match[] = {
745 { .compatible = "snps,designware-i2s", },
749 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
752 static const struct dev_pm_ops dwc_pm_ops = {
753 SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
756 static struct platform_driver dw_i2s_driver = {
757 .probe = dw_i2s_probe,
758 .remove = dw_i2s_remove,
760 .name = "designware-i2s",
761 .of_match_table = of_match_ptr(dw_i2s_of_match),
766 module_platform_driver(dw_i2s_driver);
768 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
769 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
770 MODULE_LICENSE("GPL");
771 MODULE_ALIAS("platform:designware_i2s");