2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
42 #include "davinci-mcasp.h"
44 #define MCASP_MAX_AFIFO_DEPTH 64
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
81 struct snd_pcm_substream *substreams[2];
83 /* McASP specific data */
99 /* McASP FIFO related */
105 /* Used for comstraint setting on the second stream */
108 #ifdef CONFIG_PM_SLEEP
109 struct davinci_mcasp_context context;
112 struct davinci_mcasp_ruledata ruledata[2];
113 struct snd_pcm_hw_constraint_list chconstr[2];
116 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
119 void __iomem *reg = mcasp->base + offset;
120 __raw_writel(__raw_readl(reg) | val, reg);
123 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
126 void __iomem *reg = mcasp->base + offset;
127 __raw_writel((__raw_readl(reg) & ~(val)), reg);
130 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
133 void __iomem *reg = mcasp->base + offset;
134 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
137 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
140 __raw_writel(val, mcasp->base + offset);
143 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
145 return (u32)__raw_readl(mcasp->base + offset);
148 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
152 mcasp_set_bits(mcasp, ctl_reg, val);
154 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
155 /* loop count is to avoid the lock-up */
156 for (i = 0; i < 1000; i++) {
157 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
161 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
162 printk(KERN_ERR "GBLCTL write error\n");
165 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
167 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
168 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
170 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
173 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
175 if (mcasp->rxnumevt) { /* enable FIFO */
176 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
178 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
179 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
183 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
186 * When ASYNC == 0 the transmit and receive sections operate
187 * synchronously from the transmit clock and frame sync. We need to make
188 * sure that the TX signlas are enabled when starting reception.
190 if (mcasp_is_synchronous(mcasp)) {
191 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
195 /* Activate serializer(s) */
196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
197 /* Release RX state machine */
198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
199 /* Release Frame Sync generator */
200 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
201 if (mcasp_is_synchronous(mcasp))
202 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
204 /* enable receive IRQs */
205 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
206 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
209 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
213 if (mcasp->txnumevt) { /* enable FIFO */
214 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
216 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
217 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
221 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
223 /* Activate serializer(s) */
224 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
226 /* wait for XDATA to be cleared */
228 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
232 /* Release TX state machine */
233 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
234 /* Release Frame Sync generator */
235 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
237 /* enable transmit IRQs */
238 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
239 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
242 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
246 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
247 mcasp_start_tx(mcasp);
249 mcasp_start_rx(mcasp);
252 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
254 /* disable IRQ sources */
255 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
256 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
259 * In synchronous mode stop the TX clocks if no other stream is
262 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
263 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
265 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
268 if (mcasp->rxnumevt) { /* disable FIFO */
269 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
271 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
275 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
279 /* disable IRQ sources */
280 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
281 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
284 * In synchronous mode keep TX clocks running if the capture stream is
287 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
288 val = TXHCLKRST | TXCLKRST | TXFSRST;
290 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
293 if (mcasp->txnumevt) { /* disable FIFO */
294 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
296 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
300 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
304 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
305 mcasp_stop_tx(mcasp);
307 mcasp_stop_rx(mcasp);
310 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
312 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
313 struct snd_pcm_substream *substream;
314 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
315 u32 handled_mask = 0;
318 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
319 if (stat & XUNDRN & irq_mask) {
320 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
321 handled_mask |= XUNDRN;
323 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
325 snd_pcm_stream_lock_irq(substream);
326 if (snd_pcm_running(substream))
327 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
328 snd_pcm_stream_unlock_irq(substream);
333 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
337 handled_mask |= XRERR;
339 /* Ack the handled event only */
340 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
342 return IRQ_RETVAL(handled_mask);
345 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
347 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
348 struct snd_pcm_substream *substream;
349 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
350 u32 handled_mask = 0;
353 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
354 if (stat & ROVRN & irq_mask) {
355 dev_warn(mcasp->dev, "Receive buffer overflow\n");
356 handled_mask |= ROVRN;
358 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
360 snd_pcm_stream_lock_irq(substream);
361 if (snd_pcm_running(substream))
362 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
363 snd_pcm_stream_unlock_irq(substream);
368 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
372 handled_mask |= XRERR;
374 /* Ack the handled event only */
375 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
377 return IRQ_RETVAL(handled_mask);
380 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
382 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
383 irqreturn_t ret = IRQ_NONE;
385 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
386 ret = davinci_mcasp_tx_irq_handler(irq, data);
388 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
389 ret |= davinci_mcasp_rx_irq_handler(irq, data);
394 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
397 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
403 pm_runtime_get_sync(mcasp->dev);
404 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
405 case SND_SOC_DAIFMT_DSP_A:
406 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
407 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
408 /* 1st data bit occur one ACLK cycle after the frame sync */
411 case SND_SOC_DAIFMT_DSP_B:
412 case SND_SOC_DAIFMT_AC97:
413 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
414 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
415 /* No delay after FS */
418 case SND_SOC_DAIFMT_I2S:
419 /* configure a full-word SYNC pulse (LRCLK) */
420 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
421 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
422 /* 1st data bit occur one ACLK cycle after the frame sync */
424 /* FS need to be inverted */
427 case SND_SOC_DAIFMT_LEFT_J:
428 /* configure a full-word SYNC pulse (LRCLK) */
429 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
430 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
431 /* No delay after FS */
439 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
441 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
444 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
445 case SND_SOC_DAIFMT_CBS_CFS:
446 /* codec is clock and frame slave */
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
448 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
453 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
454 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
455 mcasp->bclk_master = 1;
457 case SND_SOC_DAIFMT_CBS_CFM:
458 /* codec is clock slave and frame master */
459 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
460 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
462 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
463 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
466 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
467 mcasp->bclk_master = 1;
469 case SND_SOC_DAIFMT_CBM_CFS:
470 /* codec is clock master and frame slave */
471 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
472 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
474 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
477 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
478 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
479 mcasp->bclk_master = 0;
481 case SND_SOC_DAIFMT_CBM_CFM:
482 /* codec is clock and frame master */
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
484 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
486 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
489 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
490 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
491 mcasp->bclk_master = 0;
498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
499 case SND_SOC_DAIFMT_IB_NF:
500 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
501 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
502 fs_pol_rising = true;
504 case SND_SOC_DAIFMT_NB_IF:
505 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
506 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
507 fs_pol_rising = false;
509 case SND_SOC_DAIFMT_IB_IF:
510 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
512 fs_pol_rising = false;
514 case SND_SOC_DAIFMT_NB_NF:
515 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
517 fs_pol_rising = true;
525 fs_pol_rising = !fs_pol_rising;
528 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
529 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
532 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
535 pm_runtime_put(mcasp->dev);
539 static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
540 int div, bool explicit)
542 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
544 pm_runtime_get_sync(mcasp->dev);
546 case 0: /* MCLK divider */
547 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
548 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
550 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
553 case 1: /* BCLK divider */
554 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
555 ACLKXDIV(div - 1), ACLKXDIV_MASK);
556 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
557 ACLKRDIV(div - 1), ACLKRDIV_MASK);
559 mcasp->bclk_div = div;
563 * BCLK/LRCLK ratio descries how many bit-clock cycles
564 * fit into one frame. The clock ratio is given for a
565 * full period of data (for I2S format both left and
566 * right channels), so it has to be divided by number
567 * of tdm-slots (for I2S - divided by 2).
568 * Instead of storing this ratio, we calculate a new
569 * tdm_slot width by dividing the the ratio by the
570 * number of configured tdm slots.
572 mcasp->slot_width = div / mcasp->tdm_slots;
573 if (div % mcasp->tdm_slots)
575 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
576 __func__, div, mcasp->tdm_slots);
583 pm_runtime_put(mcasp->dev);
587 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
590 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
593 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
594 unsigned int freq, int dir)
596 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
598 pm_runtime_get_sync(mcasp->dev);
599 if (dir == SND_SOC_CLOCK_OUT) {
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
602 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
605 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
606 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
609 mcasp->sysclk_freq = freq;
611 pm_runtime_put(mcasp->dev);
615 /* All serializers must have equal number of channels */
616 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
619 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
620 unsigned int *list = (unsigned int *) cl->list;
621 int slots = mcasp->tdm_slots;
624 if (mcasp->tdm_mask[stream])
625 slots = hweight32(mcasp->tdm_mask[stream]);
627 for (i = 2; i <= slots; i++)
630 for (i = 2; i <= serializers; i++)
631 list[count++] = i*slots;
638 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
640 int rx_serializers = 0, tx_serializers = 0, ret, i;
642 for (i = 0; i < mcasp->num_serializer; i++)
643 if (mcasp->serial_dir[i] == TX_MODE)
645 else if (mcasp->serial_dir[i] == RX_MODE)
648 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
653 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
660 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
661 unsigned int tx_mask,
662 unsigned int rx_mask,
663 int slots, int slot_width)
665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
668 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
669 __func__, tx_mask, rx_mask, slots, slot_width);
671 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
673 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
674 tx_mask, rx_mask, slots);
679 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
680 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
681 __func__, slot_width);
685 mcasp->tdm_slots = slots;
686 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
687 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
688 mcasp->slot_width = slot_width;
690 return davinci_mcasp_set_ch_constraints(mcasp);
693 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
697 u32 tx_rotate = (sample_width / 4) & 0x7;
698 u32 mask = (1ULL << sample_width) - 1;
699 u32 slot_width = sample_width;
702 * For captured data we should not rotate, inversion and masking is
703 * enoguh to get the data to the right position:
704 * Format data from bus after reverse (XRBUF)
705 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
706 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
707 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
708 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
713 * Setting the tdm slot width either with set_clkdiv() or
714 * set_tdm_slot() allows us to for example send 32 bits per
715 * channel to the codec, while only 16 of them carry audio
718 if (mcasp->slot_width) {
720 * When we have more bclk then it is needed for the
721 * data, we need to use the rotation to move the
722 * received samples to have correct alignment.
724 slot_width = mcasp->slot_width;
725 rx_rotate = (slot_width - sample_width) / 4;
728 /* mapping of the XSSZ bit-field as described in the datasheet */
729 fmt = (slot_width >> 1) - 1;
731 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
732 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
734 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
736 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
738 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
740 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
743 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
748 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
749 int period_words, int channels)
751 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
755 u8 slots = mcasp->tdm_slots;
756 u8 max_active_serializers = (channels + slots - 1) / slots;
757 int active_serializers, numevt;
759 /* Default configuration */
760 if (mcasp->version < MCASP_VERSION_3)
761 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
763 /* All PINS as McASP */
764 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
766 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
767 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
768 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
770 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
771 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
774 for (i = 0; i < mcasp->num_serializer; i++) {
775 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
776 mcasp->serial_dir[i]);
777 if (mcasp->serial_dir[i] == TX_MODE &&
778 tx_ser < max_active_serializers) {
779 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
780 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
781 DISMOD_LOW, DISMOD_MASK);
783 } else if (mcasp->serial_dir[i] == RX_MODE &&
784 rx_ser < max_active_serializers) {
785 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
788 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
789 SRMOD_INACTIVE, SRMOD_MASK);
793 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
794 active_serializers = tx_ser;
795 numevt = mcasp->txnumevt;
796 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
798 active_serializers = rx_ser;
799 numevt = mcasp->rxnumevt;
800 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
803 if (active_serializers < max_active_serializers) {
804 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
805 "enabled in mcasp (%d)\n", channels,
806 active_serializers * slots);
810 /* AFIFO is not in use */
812 /* Configure the burst size for platform drivers */
813 if (active_serializers > 1) {
815 * If more than one serializers are in use we have one
816 * DMA request to provide data for all serializers.
817 * For example if three serializers are enabled the DMA
818 * need to transfer three words per DMA request.
820 dma_data->maxburst = active_serializers;
822 dma_data->maxburst = 0;
827 if (period_words % active_serializers) {
828 dev_err(mcasp->dev, "Invalid combination of period words and "
829 "active serializers: %d, %d\n", period_words,
835 * Calculate the optimal AFIFO depth for platform side:
836 * The number of words for numevt need to be in steps of active
839 numevt = (numevt / active_serializers) * active_serializers;
841 while (period_words % numevt && numevt > 0)
842 numevt -= active_serializers;
844 numevt = active_serializers;
846 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
847 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
849 /* Configure the burst size for platform drivers */
852 dma_data->maxburst = numevt;
857 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
862 int active_serializers;
866 total_slots = mcasp->tdm_slots;
869 * If more than one serializer is needed, then use them with
870 * all the specified tdm_slots. Otherwise, one serializer can
871 * cope with the transaction using just as many slots as there
872 * are channels in the stream.
874 if (mcasp->tdm_mask[stream]) {
875 active_slots = hweight32(mcasp->tdm_mask[stream]);
876 active_serializers = (channels + active_slots - 1) /
878 if (active_serializers == 1)
879 active_slots = channels;
880 for (i = 0; i < total_slots; i++) {
881 if ((1 << i) & mcasp->tdm_mask[stream]) {
883 if (--active_slots <= 0)
888 active_serializers = (channels + total_slots - 1) / total_slots;
889 if (active_serializers == 1)
890 active_slots = channels;
892 active_slots = total_slots;
894 for (i = 0; i < active_slots; i++)
897 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
899 if (!mcasp->dat_port)
902 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
903 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
904 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
906 FSXMOD(total_slots), FSXMOD(0x1FF));
907 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
908 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
909 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
910 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
911 FSRMOD(total_slots), FSRMOD(0x1FF));
913 * If McASP is set to be TX/RX synchronous and the playback is
914 * not running already we need to configure the TX slots in
915 * order to have correct FSX on the bus
917 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
918 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
919 FSXMOD(total_slots), FSXMOD(0x1FF));
926 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
930 u8 *cs_bytes = (u8*) &cs_value;
932 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
934 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
936 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
937 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
939 /* Set the TX tdm : for all the slots */
940 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
942 /* Set the TX clock controls : div = 1 and internal */
943 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
945 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
947 /* Only 44100 and 48000 are valid, both have the same setting */
948 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
951 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
953 /* Set S/PDIF channel status bits */
954 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
955 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
959 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
962 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
965 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
968 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
971 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
974 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
977 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
980 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
983 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
986 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
991 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
996 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
997 unsigned int bclk_freq,
1000 int div = mcasp->sysclk_freq / bclk_freq;
1001 int rem = mcasp->sysclk_freq % bclk_freq;
1005 ((mcasp->sysclk_freq / div) - bclk_freq) >
1006 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
1008 rem = rem - bclk_freq;
1013 (div*1000000 + (int)div64_long(1000000LL*rem,
1020 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1021 struct snd_pcm_hw_params *params,
1022 struct snd_soc_dai *cpu_dai)
1024 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1026 int channels = params_channels(params);
1027 int period_size = params_period_size(params);
1031 * If mcasp is BCLK master, and a BCLK divider was not provided by
1032 * the machine driver, we need to calculate the ratio.
1034 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1035 int slots = mcasp->tdm_slots;
1036 int rate = params_rate(params);
1037 int sbits = params_width(params);
1040 if (mcasp->slot_width)
1041 sbits = mcasp->slot_width;
1043 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
1046 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1049 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
1052 ret = mcasp_common_hw_param(mcasp, substream->stream,
1053 period_size * channels, channels);
1057 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1058 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1060 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1066 switch (params_format(params)) {
1067 case SNDRV_PCM_FORMAT_U8:
1068 case SNDRV_PCM_FORMAT_S8:
1072 case SNDRV_PCM_FORMAT_U16_LE:
1073 case SNDRV_PCM_FORMAT_S16_LE:
1077 case SNDRV_PCM_FORMAT_U24_3LE:
1078 case SNDRV_PCM_FORMAT_S24_3LE:
1082 case SNDRV_PCM_FORMAT_U24_LE:
1083 case SNDRV_PCM_FORMAT_S24_LE:
1087 case SNDRV_PCM_FORMAT_U32_LE:
1088 case SNDRV_PCM_FORMAT_S32_LE:
1093 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1097 davinci_config_channel_size(mcasp, word_length);
1099 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1100 mcasp->channels = channels;
1105 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1106 int cmd, struct snd_soc_dai *cpu_dai)
1108 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1112 case SNDRV_PCM_TRIGGER_RESUME:
1113 case SNDRV_PCM_TRIGGER_START:
1114 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1115 davinci_mcasp_start(mcasp, substream->stream);
1117 case SNDRV_PCM_TRIGGER_SUSPEND:
1118 case SNDRV_PCM_TRIGGER_STOP:
1119 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1120 davinci_mcasp_stop(mcasp, substream->stream);
1130 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1131 struct snd_pcm_hw_rule *rule)
1133 struct davinci_mcasp_ruledata *rd = rule->private;
1134 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1135 struct snd_mask nfmt;
1138 snd_mask_none(&nfmt);
1139 slot_width = rd->mcasp->slot_width;
1141 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1142 if (snd_mask_test(fmt, i)) {
1143 if (snd_pcm_format_width(i) <= slot_width) {
1144 snd_mask_set(&nfmt, i);
1149 return snd_mask_refine(fmt, &nfmt);
1152 static const unsigned int davinci_mcasp_dai_rates[] = {
1153 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1154 88200, 96000, 176400, 192000,
1157 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1159 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1160 struct snd_pcm_hw_rule *rule)
1162 struct davinci_mcasp_ruledata *rd = rule->private;
1163 struct snd_interval *ri =
1164 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1165 int sbits = params_width(params);
1166 int slots = rd->mcasp->tdm_slots;
1167 struct snd_interval range;
1170 if (rd->mcasp->slot_width)
1171 sbits = rd->mcasp->slot_width;
1173 snd_interval_any(&range);
1176 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1177 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1178 uint bclk_freq = sbits*slots*
1179 davinci_mcasp_dai_rates[i];
1182 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1183 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1185 range.min = davinci_mcasp_dai_rates[i];
1188 range.max = davinci_mcasp_dai_rates[i];
1193 dev_dbg(rd->mcasp->dev,
1194 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1195 ri->min, ri->max, range.min, range.max, sbits, slots);
1197 return snd_interval_refine(hw_param_interval(params, rule->var),
1201 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1202 struct snd_pcm_hw_rule *rule)
1204 struct davinci_mcasp_ruledata *rd = rule->private;
1205 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1206 struct snd_mask nfmt;
1207 int rate = params_rate(params);
1208 int slots = rd->mcasp->tdm_slots;
1211 snd_mask_none(&nfmt);
1213 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1214 if (snd_mask_test(fmt, i)) {
1215 uint sbits = snd_pcm_format_width(i);
1218 if (rd->mcasp->slot_width)
1219 sbits = rd->mcasp->slot_width;
1221 davinci_mcasp_calc_clk_div(rd->mcasp, sbits*slots*rate,
1223 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1224 snd_mask_set(&nfmt, i);
1229 dev_dbg(rd->mcasp->dev,
1230 "%d possible sample format for %d Hz and %d tdm slots\n",
1231 count, rate, slots);
1233 return snd_mask_refine(fmt, &nfmt);
1236 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1237 struct snd_soc_dai *cpu_dai)
1239 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1240 struct davinci_mcasp_ruledata *ruledata =
1241 &mcasp->ruledata[substream->stream];
1242 u32 max_channels = 0;
1244 int tdm_slots = mcasp->tdm_slots;
1246 if (mcasp->tdm_mask[substream->stream])
1247 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1249 mcasp->substreams[substream->stream] = substream;
1251 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1255 * Limit the maximum allowed channels for the first stream:
1256 * number of serializers for the direction * tdm slots per serializer
1258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1263 for (i = 0; i < mcasp->num_serializer; i++) {
1264 if (mcasp->serial_dir[i] == dir)
1267 ruledata->serializers = max_channels;
1268 ruledata->mcasp = mcasp;
1269 max_channels *= tdm_slots;
1271 * If the already active stream has less channels than the calculated
1272 * limnit based on the seirializers * tdm_slots, we need to use that as
1273 * a constraint for the second stream.
1274 * Otherwise (first stream or less allowed channels) we use the
1275 * calculated constraint.
1277 if (mcasp->channels && mcasp->channels < max_channels)
1278 max_channels = mcasp->channels;
1280 * But we can always allow channels upto the amount of
1281 * the available tdm_slots.
1283 if (max_channels < tdm_slots)
1284 max_channels = tdm_slots;
1286 snd_pcm_hw_constraint_minmax(substream->runtime,
1287 SNDRV_PCM_HW_PARAM_CHANNELS,
1290 snd_pcm_hw_constraint_list(substream->runtime,
1291 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1292 &mcasp->chconstr[substream->stream]);
1294 if (mcasp->slot_width) {
1295 /* Only allow formats require <= slot_width bits on the bus */
1296 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1297 SNDRV_PCM_HW_PARAM_FORMAT,
1298 davinci_mcasp_hw_rule_slot_width,
1300 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1306 * If we rely on implicit BCLK divider setting we should
1307 * set constraints based on what we can provide.
1309 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1310 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1311 SNDRV_PCM_HW_PARAM_RATE,
1312 davinci_mcasp_hw_rule_rate,
1314 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1317 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1318 SNDRV_PCM_HW_PARAM_FORMAT,
1319 davinci_mcasp_hw_rule_format,
1321 SNDRV_PCM_HW_PARAM_RATE, -1);
1329 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1330 struct snd_soc_dai *cpu_dai)
1332 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1334 mcasp->substreams[substream->stream] = NULL;
1336 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1339 if (!cpu_dai->active)
1340 mcasp->channels = 0;
1343 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1344 .startup = davinci_mcasp_startup,
1345 .shutdown = davinci_mcasp_shutdown,
1346 .trigger = davinci_mcasp_trigger,
1347 .hw_params = davinci_mcasp_hw_params,
1348 .set_fmt = davinci_mcasp_set_dai_fmt,
1349 .set_clkdiv = davinci_mcasp_set_clkdiv,
1350 .set_sysclk = davinci_mcasp_set_sysclk,
1351 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1354 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1356 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1358 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1359 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1364 #ifdef CONFIG_PM_SLEEP
1365 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1367 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1368 struct davinci_mcasp_context *context = &mcasp->context;
1372 context->pm_state = pm_runtime_active(mcasp->dev);
1373 if (!context->pm_state)
1374 pm_runtime_get_sync(mcasp->dev);
1376 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1377 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1379 if (mcasp->txnumevt) {
1380 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1381 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1383 if (mcasp->rxnumevt) {
1384 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1385 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1388 for (i = 0; i < mcasp->num_serializer; i++)
1389 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1390 DAVINCI_MCASP_XRSRCTL_REG(i));
1392 pm_runtime_put_sync(mcasp->dev);
1397 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1399 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1400 struct davinci_mcasp_context *context = &mcasp->context;
1404 pm_runtime_get_sync(mcasp->dev);
1406 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1407 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1409 if (mcasp->txnumevt) {
1410 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1411 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1413 if (mcasp->rxnumevt) {
1414 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1415 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1418 for (i = 0; i < mcasp->num_serializer; i++)
1419 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1420 context->xrsr_regs[i]);
1422 if (!context->pm_state)
1423 pm_runtime_put_sync(mcasp->dev);
1428 #define davinci_mcasp_suspend NULL
1429 #define davinci_mcasp_resume NULL
1432 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1434 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1435 SNDRV_PCM_FMTBIT_U8 | \
1436 SNDRV_PCM_FMTBIT_S16_LE | \
1437 SNDRV_PCM_FMTBIT_U16_LE | \
1438 SNDRV_PCM_FMTBIT_S24_LE | \
1439 SNDRV_PCM_FMTBIT_U24_LE | \
1440 SNDRV_PCM_FMTBIT_S24_3LE | \
1441 SNDRV_PCM_FMTBIT_U24_3LE | \
1442 SNDRV_PCM_FMTBIT_S32_LE | \
1443 SNDRV_PCM_FMTBIT_U32_LE)
1445 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1447 .name = "davinci-mcasp.0",
1448 .probe = davinci_mcasp_dai_probe,
1449 .suspend = davinci_mcasp_suspend,
1450 .resume = davinci_mcasp_resume,
1453 .channels_max = 32 * 16,
1454 .rates = DAVINCI_MCASP_RATES,
1455 .formats = DAVINCI_MCASP_PCM_FMTS,
1459 .channels_max = 32 * 16,
1460 .rates = DAVINCI_MCASP_RATES,
1461 .formats = DAVINCI_MCASP_PCM_FMTS,
1463 .ops = &davinci_mcasp_dai_ops,
1465 .symmetric_samplebits = 1,
1466 .symmetric_rates = 1,
1469 .name = "davinci-mcasp.1",
1470 .probe = davinci_mcasp_dai_probe,
1473 .channels_max = 384,
1474 .rates = DAVINCI_MCASP_RATES,
1475 .formats = DAVINCI_MCASP_PCM_FMTS,
1477 .ops = &davinci_mcasp_dai_ops,
1482 static const struct snd_soc_component_driver davinci_mcasp_component = {
1483 .name = "davinci-mcasp",
1486 /* Some HW specific values and defaults. The rest is filled in from DT. */
1487 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1488 .tx_dma_offset = 0x400,
1489 .rx_dma_offset = 0x400,
1490 .version = MCASP_VERSION_1,
1493 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1494 .tx_dma_offset = 0x2000,
1495 .rx_dma_offset = 0x2000,
1496 .version = MCASP_VERSION_2,
1499 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1502 .version = MCASP_VERSION_3,
1505 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1506 .tx_dma_offset = 0x200,
1507 .rx_dma_offset = 0x284,
1508 .version = MCASP_VERSION_4,
1511 static const struct of_device_id mcasp_dt_ids[] = {
1513 .compatible = "ti,dm646x-mcasp-audio",
1514 .data = &dm646x_mcasp_pdata,
1517 .compatible = "ti,da830-mcasp-audio",
1518 .data = &da830_mcasp_pdata,
1521 .compatible = "ti,am33xx-mcasp-audio",
1522 .data = &am33xx_mcasp_pdata,
1525 .compatible = "ti,dra7-mcasp-audio",
1526 .data = &dra7_mcasp_pdata,
1530 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1532 static int mcasp_reparent_fck(struct platform_device *pdev)
1534 struct device_node *node = pdev->dev.of_node;
1535 struct clk *gfclk, *parent_clk;
1536 const char *parent_name;
1542 parent_name = of_get_property(node, "fck_parent", NULL);
1546 gfclk = clk_get(&pdev->dev, "fck");
1547 if (IS_ERR(gfclk)) {
1548 dev_err(&pdev->dev, "failed to get fck\n");
1549 return PTR_ERR(gfclk);
1552 parent_clk = clk_get(NULL, parent_name);
1553 if (IS_ERR(parent_clk)) {
1554 dev_err(&pdev->dev, "failed to get parent clock\n");
1555 ret = PTR_ERR(parent_clk);
1559 ret = clk_set_parent(gfclk, parent_clk);
1561 dev_err(&pdev->dev, "failed to reparent fck\n");
1566 clk_put(parent_clk);
1572 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1573 struct platform_device *pdev)
1575 struct device_node *np = pdev->dev.of_node;
1576 struct davinci_mcasp_pdata *pdata = NULL;
1577 const struct of_device_id *match =
1578 of_match_device(mcasp_dt_ids, &pdev->dev);
1579 struct of_phandle_args dma_spec;
1581 const u32 *of_serial_dir32;
1585 if (pdev->dev.platform_data) {
1586 pdata = pdev->dev.platform_data;
1589 pdata = (struct davinci_mcasp_pdata*) match->data;
1591 /* control shouldn't reach here. something is wrong */
1596 ret = of_property_read_u32(np, "op-mode", &val);
1598 pdata->op_mode = val;
1600 ret = of_property_read_u32(np, "tdm-slots", &val);
1602 if (val < 2 || val > 32) {
1604 "tdm-slots must be in rage [2-32]\n");
1609 pdata->tdm_slots = val;
1612 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1614 if (of_serial_dir32) {
1615 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1616 (sizeof(*of_serial_dir) * val),
1618 if (!of_serial_dir) {
1623 for (i = 0; i < val; i++)
1624 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1626 pdata->num_serializer = val;
1627 pdata->serial_dir = of_serial_dir;
1630 ret = of_property_match_string(np, "dma-names", "tx");
1634 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1639 pdata->tx_dma_channel = dma_spec.args[0];
1641 /* RX is not valid in DIT mode */
1642 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1643 ret = of_property_match_string(np, "dma-names", "rx");
1647 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1652 pdata->rx_dma_channel = dma_spec.args[0];
1655 ret = of_property_read_u32(np, "tx-num-evt", &val);
1657 pdata->txnumevt = val;
1659 ret = of_property_read_u32(np, "rx-num-evt", &val);
1661 pdata->rxnumevt = val;
1663 ret = of_property_read_u32(np, "sram-size-playback", &val);
1665 pdata->sram_size_playback = val;
1667 ret = of_property_read_u32(np, "sram-size-capture", &val);
1669 pdata->sram_size_capture = val;
1675 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1686 static const char *sdma_prefix = "ti,omap";
1688 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1690 struct dma_chan *chan;
1694 if (!mcasp->dev->of_node)
1697 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1698 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1700 if (PTR_ERR(chan) != -EPROBE_DEFER)
1702 "Can't verify DMA configuration (%ld)\n",
1704 return PTR_ERR(chan);
1706 BUG_ON(!chan->device || !chan->device->dev);
1708 if (chan->device->dev->of_node)
1709 ret = of_property_read_string(chan->device->dev->of_node,
1710 "compatible", &tmp);
1712 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1714 dma_release_channel(chan);
1718 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1719 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1725 static int davinci_mcasp_probe(struct platform_device *pdev)
1727 struct snd_dmaengine_dai_dma_data *dma_data;
1728 struct resource *mem, *res, *dat;
1729 struct davinci_mcasp_pdata *pdata;
1730 struct davinci_mcasp *mcasp;
1736 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1737 dev_err(&pdev->dev, "No platform data supplied\n");
1741 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1746 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1748 dev_err(&pdev->dev, "no platform data\n");
1752 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1754 dev_warn(mcasp->dev,
1755 "\"mpu\" mem resource not found, using index 0\n");
1756 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758 dev_err(&pdev->dev, "no mem resource?\n");
1763 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1764 if (IS_ERR(mcasp->base))
1765 return PTR_ERR(mcasp->base);
1767 pm_runtime_enable(&pdev->dev);
1769 mcasp->op_mode = pdata->op_mode;
1770 /* sanity check for tdm slots parameter */
1771 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1772 if (pdata->tdm_slots < 2) {
1773 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1775 mcasp->tdm_slots = 2;
1776 } else if (pdata->tdm_slots > 32) {
1777 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1779 mcasp->tdm_slots = 32;
1781 mcasp->tdm_slots = pdata->tdm_slots;
1785 mcasp->num_serializer = pdata->num_serializer;
1786 #ifdef CONFIG_PM_SLEEP
1787 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1788 sizeof(u32) * mcasp->num_serializer,
1791 mcasp->serial_dir = pdata->serial_dir;
1792 mcasp->version = pdata->version;
1793 mcasp->txnumevt = pdata->txnumevt;
1794 mcasp->rxnumevt = pdata->rxnumevt;
1796 mcasp->dev = &pdev->dev;
1798 irq = platform_get_irq_byname(pdev, "common");
1800 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1801 dev_name(&pdev->dev));
1802 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1803 davinci_mcasp_common_irq_handler,
1804 IRQF_ONESHOT | IRQF_SHARED,
1807 dev_err(&pdev->dev, "common IRQ request failed\n");
1811 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1812 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1815 irq = platform_get_irq_byname(pdev, "rx");
1817 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1818 dev_name(&pdev->dev));
1819 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1820 davinci_mcasp_rx_irq_handler,
1821 IRQF_ONESHOT, irq_name, mcasp);
1823 dev_err(&pdev->dev, "RX IRQ request failed\n");
1827 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1830 irq = platform_get_irq_byname(pdev, "tx");
1832 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1833 dev_name(&pdev->dev));
1834 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1835 davinci_mcasp_tx_irq_handler,
1836 IRQF_ONESHOT, irq_name, mcasp);
1838 dev_err(&pdev->dev, "TX IRQ request failed\n");
1842 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1845 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1847 mcasp->dat_port = true;
1849 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1851 dma_data->addr = dat->start;
1853 dma_data->addr = mem->start + pdata->tx_dma_offset;
1855 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1856 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1860 *dma = pdata->tx_dma_channel;
1862 /* dmaengine filter data for DT and non-DT boot */
1863 if (pdev->dev.of_node)
1864 dma_data->filter_data = "tx";
1866 dma_data->filter_data = dma;
1868 /* RX is not valid in DIT mode */
1869 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1870 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1872 dma_data->addr = dat->start;
1874 dma_data->addr = mem->start + pdata->rx_dma_offset;
1876 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1877 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1881 *dma = pdata->rx_dma_channel;
1883 /* dmaengine filter data for DT and non-DT boot */
1884 if (pdev->dev.of_node)
1885 dma_data->filter_data = "rx";
1887 dma_data->filter_data = dma;
1890 if (mcasp->version < MCASP_VERSION_3) {
1891 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1892 /* dma_params->dma_addr is pointing to the data port address */
1893 mcasp->dat_port = true;
1895 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1898 /* Allocate memory for long enough list for all possible
1899 * scenarios. Maximum number tdm slots is 32 and there cannot
1900 * be more serializers than given in the configuration. The
1901 * serializer directions could be taken into account, but it
1902 * would make code much more complex and save only couple of
1905 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1906 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1907 (32 + mcasp->num_serializer - 2),
1910 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
1911 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
1912 (32 + mcasp->num_serializer - 2),
1915 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
1916 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
1919 ret = davinci_mcasp_set_ch_constraints(mcasp);
1923 dev_set_drvdata(&pdev->dev, mcasp);
1925 mcasp_reparent_fck(pdev);
1927 ret = devm_snd_soc_register_component(&pdev->dev,
1928 &davinci_mcasp_component,
1929 &davinci_mcasp_dai[pdata->op_mode], 1);
1934 ret = davinci_mcasp_get_dma_type(mcasp);
1937 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1938 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1939 IS_MODULE(CONFIG_SND_EDMA_SOC))
1940 ret = edma_pcm_platform_register(&pdev->dev);
1942 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
1948 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1949 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1950 IS_MODULE(CONFIG_SND_OMAP_SOC))
1951 ret = omap_pcm_platform_register(&pdev->dev);
1953 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
1959 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
1966 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1973 pm_runtime_disable(&pdev->dev);
1977 static int davinci_mcasp_remove(struct platform_device *pdev)
1979 pm_runtime_disable(&pdev->dev);
1984 static struct platform_driver davinci_mcasp_driver = {
1985 .probe = davinci_mcasp_probe,
1986 .remove = davinci_mcasp_remove,
1988 .name = "davinci-mcasp",
1989 .of_match_table = mcasp_dt_ids,
1993 module_platform_driver(davinci_mcasp_driver);
1995 MODULE_AUTHOR("Steve Chen");
1996 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1997 MODULE_LICENSE("GPL");