2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
39 #include <sound/omap-pcm.h>
42 #include "davinci-mcasp.h"
44 #define MCASP_MAX_AFIFO_DEPTH 64
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
81 struct snd_pcm_substream *substreams[2];
84 /* McASP specific data */
100 /* McASP FIFO related */
106 /* Used for comstraint setting on the second stream */
109 #ifdef CONFIG_PM_SLEEP
110 struct davinci_mcasp_context context;
113 struct davinci_mcasp_ruledata ruledata[2];
114 struct snd_pcm_hw_constraint_list chconstr[2];
117 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel(__raw_readl(reg) | val, reg);
124 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel((__raw_readl(reg) & ~(val)), reg);
131 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
138 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
141 __raw_writel(val, mcasp->base + offset);
144 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
146 return (u32)__raw_readl(mcasp->base + offset);
149 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
153 mcasp_set_bits(mcasp, ctl_reg, val);
155 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
156 /* loop count is to avoid the lock-up */
157 for (i = 0; i < 1000; i++) {
158 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
162 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
163 printk(KERN_ERR "GBLCTL write error\n");
166 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
168 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
169 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
171 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
174 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
176 if (mcasp->rxnumevt) { /* enable FIFO */
177 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
179 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
180 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
187 * When ASYNC == 0 the transmit and receive sections operate
188 * synchronously from the transmit clock and frame sync. We need to make
189 * sure that the TX signlas are enabled when starting reception.
191 if (mcasp_is_synchronous(mcasp)) {
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
196 /* Activate serializer(s) */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
198 /* Release RX state machine */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
200 /* Release Frame Sync generator */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
202 if (mcasp_is_synchronous(mcasp))
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
205 /* enable receive IRQs */
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
207 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
210 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
214 if (mcasp->txnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
224 /* Activate serializer(s) */
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
227 /* wait for XDATA to be cleared */
229 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
233 /* Release TX state machine */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
235 /* Release Frame Sync generator */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
238 /* enable transmit IRQs */
239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
240 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
243 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
248 mcasp_start_tx(mcasp);
250 mcasp_start_rx(mcasp);
253 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
255 /* disable IRQ sources */
256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
257 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
260 * In synchronous mode stop the TX clocks if no other stream is
263 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
269 if (mcasp->rxnumevt) { /* disable FIFO */
270 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
272 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
276 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
280 /* disable IRQ sources */
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
285 * In synchronous mode keep TX clocks running if the capture stream is
288 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
289 val = TXHCLKRST | TXCLKRST | TXFSRST;
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
294 if (mcasp->txnumevt) { /* disable FIFO */
295 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
297 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
301 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
305 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
306 mcasp_stop_tx(mcasp);
308 mcasp_stop_rx(mcasp);
311 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
313 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
314 struct snd_pcm_substream *substream;
315 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
316 u32 handled_mask = 0;
319 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
320 if (stat & XUNDRN & irq_mask) {
321 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
322 handled_mask |= XUNDRN;
324 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
326 snd_pcm_stream_lock_irq(substream);
327 if (snd_pcm_running(substream))
328 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
329 snd_pcm_stream_unlock_irq(substream);
334 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
338 handled_mask |= XRERR;
340 /* Ack the handled event only */
341 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
343 return IRQ_RETVAL(handled_mask);
346 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
348 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
349 struct snd_pcm_substream *substream;
350 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
351 u32 handled_mask = 0;
354 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
355 if (stat & ROVRN & irq_mask) {
356 dev_warn(mcasp->dev, "Receive buffer overflow\n");
357 handled_mask |= ROVRN;
359 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
361 snd_pcm_stream_lock_irq(substream);
362 if (snd_pcm_running(substream))
363 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
364 snd_pcm_stream_unlock_irq(substream);
369 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
373 handled_mask |= XRERR;
375 /* Ack the handled event only */
376 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
378 return IRQ_RETVAL(handled_mask);
381 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
383 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
384 irqreturn_t ret = IRQ_NONE;
386 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
387 ret = davinci_mcasp_tx_irq_handler(irq, data);
389 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
390 ret |= davinci_mcasp_rx_irq_handler(irq, data);
395 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
398 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
407 pm_runtime_get_sync(mcasp->dev);
408 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
409 case SND_SOC_DAIFMT_DSP_A:
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
411 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
412 /* 1st data bit occur one ACLK cycle after the frame sync */
415 case SND_SOC_DAIFMT_DSP_B:
416 case SND_SOC_DAIFMT_AC97:
417 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
418 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
419 /* No delay after FS */
422 case SND_SOC_DAIFMT_I2S:
423 /* configure a full-word SYNC pulse (LRCLK) */
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
426 /* 1st data bit occur one ACLK cycle after the frame sync */
428 /* FS need to be inverted */
431 case SND_SOC_DAIFMT_LEFT_J:
432 /* configure a full-word SYNC pulse (LRCLK) */
433 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
434 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
435 /* No delay after FS */
443 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
445 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
448 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
449 case SND_SOC_DAIFMT_CBS_CFS:
450 /* codec is clock and frame slave */
451 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
452 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
454 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
457 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
459 mcasp->bclk_master = 1;
461 case SND_SOC_DAIFMT_CBS_CFM:
462 /* codec is clock slave and frame master */
463 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
464 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
469 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
471 mcasp->bclk_master = 1;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 /* codec is clock master and frame slave */
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
481 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
482 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
483 mcasp->bclk_master = 0;
485 case SND_SOC_DAIFMT_CBM_CFM:
486 /* codec is clock and frame master */
487 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
488 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
491 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
493 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
494 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
495 mcasp->bclk_master = 0;
502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
503 case SND_SOC_DAIFMT_IB_NF:
504 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
506 fs_pol_rising = true;
508 case SND_SOC_DAIFMT_NB_IF:
509 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
511 fs_pol_rising = false;
513 case SND_SOC_DAIFMT_IB_IF:
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
515 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
516 fs_pol_rising = false;
518 case SND_SOC_DAIFMT_NB_NF:
519 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
520 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
521 fs_pol_rising = true;
529 fs_pol_rising = !fs_pol_rising;
532 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
535 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
536 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
539 mcasp->dai_fmt = fmt;
541 pm_runtime_put(mcasp->dev);
545 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
546 int div, bool explicit)
548 pm_runtime_get_sync(mcasp->dev);
550 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
551 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
552 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
553 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
554 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
557 case MCASP_CLKDIV_BCLK: /* BCLK divider */
558 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
559 ACLKXDIV(div - 1), ACLKXDIV_MASK);
560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
561 ACLKRDIV(div - 1), ACLKRDIV_MASK);
563 mcasp->bclk_div = div;
566 case MCASP_CLKDIV_BCLK_FS_RATIO:
568 * BCLK/LRCLK ratio descries how many bit-clock cycles
569 * fit into one frame. The clock ratio is given for a
570 * full period of data (for I2S format both left and
571 * right channels), so it has to be divided by number
572 * of tdm-slots (for I2S - divided by 2).
573 * Instead of storing this ratio, we calculate a new
574 * tdm_slot width by dividing the the ratio by the
575 * number of configured tdm slots.
577 mcasp->slot_width = div / mcasp->tdm_slots;
578 if (div % mcasp->tdm_slots)
580 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
581 __func__, div, mcasp->tdm_slots);
588 pm_runtime_put(mcasp->dev);
592 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
595 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
597 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
600 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
601 unsigned int freq, int dir)
603 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
605 pm_runtime_get_sync(mcasp->dev);
606 if (dir == SND_SOC_CLOCK_OUT) {
607 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
608 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
609 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
611 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
612 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
613 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
616 mcasp->sysclk_freq = freq;
618 pm_runtime_put(mcasp->dev);
622 /* All serializers must have equal number of channels */
623 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
626 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
627 unsigned int *list = (unsigned int *) cl->list;
628 int slots = mcasp->tdm_slots;
631 if (mcasp->tdm_mask[stream])
632 slots = hweight32(mcasp->tdm_mask[stream]);
634 for (i = 2; i <= slots; i++)
637 for (i = 2; i <= serializers; i++)
638 list[count++] = i*slots;
645 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
647 int rx_serializers = 0, tx_serializers = 0, ret, i;
649 for (i = 0; i < mcasp->num_serializer; i++)
650 if (mcasp->serial_dir[i] == TX_MODE)
652 else if (mcasp->serial_dir[i] == RX_MODE)
655 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
660 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
667 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
668 unsigned int tx_mask,
669 unsigned int rx_mask,
670 int slots, int slot_width)
672 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
675 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
676 __func__, tx_mask, rx_mask, slots, slot_width);
678 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
680 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
681 tx_mask, rx_mask, slots);
686 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
687 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
688 __func__, slot_width);
692 mcasp->tdm_slots = slots;
693 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
694 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
695 mcasp->slot_width = slot_width;
697 return davinci_mcasp_set_ch_constraints(mcasp);
700 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
704 u32 tx_rotate = (sample_width / 4) & 0x7;
705 u32 mask = (1ULL << sample_width) - 1;
706 u32 slot_width = sample_width;
709 * For captured data we should not rotate, inversion and masking is
710 * enoguh to get the data to the right position:
711 * Format data from bus after reverse (XRBUF)
712 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
713 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
714 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
715 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
720 * Setting the tdm slot width either with set_clkdiv() or
721 * set_tdm_slot() allows us to for example send 32 bits per
722 * channel to the codec, while only 16 of them carry audio
725 if (mcasp->slot_width) {
727 * When we have more bclk then it is needed for the
728 * data, we need to use the rotation to move the
729 * received samples to have correct alignment.
731 slot_width = mcasp->slot_width;
732 rx_rotate = (slot_width - sample_width) / 4;
735 /* mapping of the XSSZ bit-field as described in the datasheet */
736 fmt = (slot_width >> 1) - 1;
738 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
739 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
741 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
743 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
745 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
747 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
750 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
755 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
756 int period_words, int channels)
758 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
762 u8 slots = mcasp->tdm_slots;
763 u8 max_active_serializers = (channels + slots - 1) / slots;
764 int active_serializers, numevt;
766 /* Default configuration */
767 if (mcasp->version < MCASP_VERSION_3)
768 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
770 /* All PINS as McASP */
771 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
773 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
774 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
775 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
777 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
778 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
781 for (i = 0; i < mcasp->num_serializer; i++) {
782 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
783 mcasp->serial_dir[i]);
784 if (mcasp->serial_dir[i] == TX_MODE &&
785 tx_ser < max_active_serializers) {
786 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
787 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
788 DISMOD_LOW, DISMOD_MASK);
790 } else if (mcasp->serial_dir[i] == RX_MODE &&
791 rx_ser < max_active_serializers) {
792 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
795 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
796 SRMOD_INACTIVE, SRMOD_MASK);
800 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
801 active_serializers = tx_ser;
802 numevt = mcasp->txnumevt;
803 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
805 active_serializers = rx_ser;
806 numevt = mcasp->rxnumevt;
807 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
810 if (active_serializers < max_active_serializers) {
811 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
812 "enabled in mcasp (%d)\n", channels,
813 active_serializers * slots);
817 /* AFIFO is not in use */
819 /* Configure the burst size for platform drivers */
820 if (active_serializers > 1) {
822 * If more than one serializers are in use we have one
823 * DMA request to provide data for all serializers.
824 * For example if three serializers are enabled the DMA
825 * need to transfer three words per DMA request.
827 dma_data->maxburst = active_serializers;
829 dma_data->maxburst = 0;
834 if (period_words % active_serializers) {
835 dev_err(mcasp->dev, "Invalid combination of period words and "
836 "active serializers: %d, %d\n", period_words,
842 * Calculate the optimal AFIFO depth for platform side:
843 * The number of words for numevt need to be in steps of active
846 numevt = (numevt / active_serializers) * active_serializers;
848 while (period_words % numevt && numevt > 0)
849 numevt -= active_serializers;
851 numevt = active_serializers;
853 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
854 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
856 /* Configure the burst size for platform drivers */
859 dma_data->maxburst = numevt;
864 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
869 int active_serializers;
873 total_slots = mcasp->tdm_slots;
876 * If more than one serializer is needed, then use them with
877 * all the specified tdm_slots. Otherwise, one serializer can
878 * cope with the transaction using just as many slots as there
879 * are channels in the stream.
881 if (mcasp->tdm_mask[stream]) {
882 active_slots = hweight32(mcasp->tdm_mask[stream]);
883 active_serializers = (channels + active_slots - 1) /
885 if (active_serializers == 1)
886 active_slots = channels;
887 for (i = 0; i < total_slots; i++) {
888 if ((1 << i) & mcasp->tdm_mask[stream]) {
890 if (--active_slots <= 0)
895 active_serializers = (channels + total_slots - 1) / total_slots;
896 if (active_serializers == 1)
897 active_slots = channels;
899 active_slots = total_slots;
901 for (i = 0; i < active_slots; i++)
904 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
906 if (!mcasp->dat_port)
909 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
910 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
911 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
912 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
913 FSXMOD(total_slots), FSXMOD(0x1FF));
914 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
915 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
916 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
918 FSRMOD(total_slots), FSRMOD(0x1FF));
920 * If McASP is set to be TX/RX synchronous and the playback is
921 * not running already we need to configure the TX slots in
922 * order to have correct FSX on the bus
924 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
925 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
926 FSXMOD(total_slots), FSXMOD(0x1FF));
933 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
937 u8 *cs_bytes = (u8*) &cs_value;
939 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
941 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
943 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
944 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
946 /* Set the TX tdm : for all the slots */
947 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
949 /* Set the TX clock controls : div = 1 and internal */
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
952 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
954 /* Only 44100 and 48000 are valid, both have the same setting */
955 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
958 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
960 /* Set S/PDIF channel status bits */
961 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
962 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
966 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
969 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
972 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
975 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
978 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
981 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
984 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
987 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
990 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
993 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
997 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
998 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1003 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1004 unsigned int bclk_freq, bool set)
1007 unsigned int sysclk_freq = mcasp->sysclk_freq;
1008 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1009 int div = sysclk_freq / bclk_freq;
1010 int rem = sysclk_freq % bclk_freq;
1013 if (div > (ACLKXDIV_MASK + 1)) {
1014 if (reg & AHCLKXE) {
1015 aux_div = div / (ACLKXDIV_MASK + 1);
1016 if (div % (ACLKXDIV_MASK + 1))
1019 sysclk_freq /= aux_div;
1020 div = sysclk_freq / bclk_freq;
1021 rem = sysclk_freq % bclk_freq;
1023 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1030 ((sysclk_freq / div) - bclk_freq) >
1031 (bclk_freq - (sysclk_freq / (div+1)))) {
1033 rem = rem - bclk_freq;
1036 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1037 (int)bclk_freq)) / div - 1000000;
1041 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1044 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1046 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1053 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1054 struct snd_pcm_hw_params *params,
1055 struct snd_soc_dai *cpu_dai)
1057 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1059 int channels = params_channels(params);
1060 int period_size = params_period_size(params);
1063 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1068 * If mcasp is BCLK master, and a BCLK divider was not provided by
1069 * the machine driver, we need to calculate the ratio.
1071 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1072 int slots = mcasp->tdm_slots;
1073 int rate = params_rate(params);
1074 int sbits = params_width(params);
1076 if (mcasp->slot_width)
1077 sbits = mcasp->slot_width;
1079 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1082 ret = mcasp_common_hw_param(mcasp, substream->stream,
1083 period_size * channels, channels);
1087 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1088 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1090 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1096 switch (params_format(params)) {
1097 case SNDRV_PCM_FORMAT_U8:
1098 case SNDRV_PCM_FORMAT_S8:
1102 case SNDRV_PCM_FORMAT_U16_LE:
1103 case SNDRV_PCM_FORMAT_S16_LE:
1107 case SNDRV_PCM_FORMAT_U24_3LE:
1108 case SNDRV_PCM_FORMAT_S24_3LE:
1112 case SNDRV_PCM_FORMAT_U24_LE:
1113 case SNDRV_PCM_FORMAT_S24_LE:
1117 case SNDRV_PCM_FORMAT_U32_LE:
1118 case SNDRV_PCM_FORMAT_S32_LE:
1123 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1127 davinci_config_channel_size(mcasp, word_length);
1129 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1130 mcasp->channels = channels;
1135 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1136 int cmd, struct snd_soc_dai *cpu_dai)
1138 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1142 case SNDRV_PCM_TRIGGER_RESUME:
1143 case SNDRV_PCM_TRIGGER_START:
1144 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1145 davinci_mcasp_start(mcasp, substream->stream);
1147 case SNDRV_PCM_TRIGGER_SUSPEND:
1148 case SNDRV_PCM_TRIGGER_STOP:
1149 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1150 davinci_mcasp_stop(mcasp, substream->stream);
1160 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1161 struct snd_pcm_hw_rule *rule)
1163 struct davinci_mcasp_ruledata *rd = rule->private;
1164 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1165 struct snd_mask nfmt;
1168 snd_mask_none(&nfmt);
1169 slot_width = rd->mcasp->slot_width;
1171 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1172 if (snd_mask_test(fmt, i)) {
1173 if (snd_pcm_format_width(i) <= slot_width) {
1174 snd_mask_set(&nfmt, i);
1179 return snd_mask_refine(fmt, &nfmt);
1182 static const unsigned int davinci_mcasp_dai_rates[] = {
1183 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1184 88200, 96000, 176400, 192000,
1187 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1189 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1190 struct snd_pcm_hw_rule *rule)
1192 struct davinci_mcasp_ruledata *rd = rule->private;
1193 struct snd_interval *ri =
1194 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1195 int sbits = params_width(params);
1196 int slots = rd->mcasp->tdm_slots;
1197 struct snd_interval range;
1200 if (rd->mcasp->slot_width)
1201 sbits = rd->mcasp->slot_width;
1203 snd_interval_any(&range);
1206 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1207 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1208 uint bclk_freq = sbits*slots*
1209 davinci_mcasp_dai_rates[i];
1212 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1214 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1216 range.min = davinci_mcasp_dai_rates[i];
1219 range.max = davinci_mcasp_dai_rates[i];
1224 dev_dbg(rd->mcasp->dev,
1225 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1226 ri->min, ri->max, range.min, range.max, sbits, slots);
1228 return snd_interval_refine(hw_param_interval(params, rule->var),
1232 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1233 struct snd_pcm_hw_rule *rule)
1235 struct davinci_mcasp_ruledata *rd = rule->private;
1236 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1237 struct snd_mask nfmt;
1238 int rate = params_rate(params);
1239 int slots = rd->mcasp->tdm_slots;
1242 snd_mask_none(&nfmt);
1244 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1245 if (snd_mask_test(fmt, i)) {
1246 uint sbits = snd_pcm_format_width(i);
1249 if (rd->mcasp->slot_width)
1250 sbits = rd->mcasp->slot_width;
1252 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1253 sbits * slots * rate,
1255 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1256 snd_mask_set(&nfmt, i);
1261 dev_dbg(rd->mcasp->dev,
1262 "%d possible sample format for %d Hz and %d tdm slots\n",
1263 count, rate, slots);
1265 return snd_mask_refine(fmt, &nfmt);
1268 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1269 struct snd_soc_dai *cpu_dai)
1271 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1272 struct davinci_mcasp_ruledata *ruledata =
1273 &mcasp->ruledata[substream->stream];
1274 u32 max_channels = 0;
1276 int tdm_slots = mcasp->tdm_slots;
1278 /* Do not allow more then one stream per direction */
1279 if (mcasp->substreams[substream->stream])
1282 mcasp->substreams[substream->stream] = substream;
1284 if (mcasp->tdm_mask[substream->stream])
1285 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1287 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1291 * Limit the maximum allowed channels for the first stream:
1292 * number of serializers for the direction * tdm slots per serializer
1294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1299 for (i = 0; i < mcasp->num_serializer; i++) {
1300 if (mcasp->serial_dir[i] == dir)
1303 ruledata->serializers = max_channels;
1304 ruledata->mcasp = mcasp;
1305 max_channels *= tdm_slots;
1307 * If the already active stream has less channels than the calculated
1308 * limnit based on the seirializers * tdm_slots, we need to use that as
1309 * a constraint for the second stream.
1310 * Otherwise (first stream or less allowed channels) we use the
1311 * calculated constraint.
1313 if (mcasp->channels && mcasp->channels < max_channels)
1314 max_channels = mcasp->channels;
1316 * But we can always allow channels upto the amount of
1317 * the available tdm_slots.
1319 if (max_channels < tdm_slots)
1320 max_channels = tdm_slots;
1322 snd_pcm_hw_constraint_minmax(substream->runtime,
1323 SNDRV_PCM_HW_PARAM_CHANNELS,
1326 snd_pcm_hw_constraint_list(substream->runtime,
1327 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1328 &mcasp->chconstr[substream->stream]);
1330 if (mcasp->slot_width) {
1331 /* Only allow formats require <= slot_width bits on the bus */
1332 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1333 SNDRV_PCM_HW_PARAM_FORMAT,
1334 davinci_mcasp_hw_rule_slot_width,
1336 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1342 * If we rely on implicit BCLK divider setting we should
1343 * set constraints based on what we can provide.
1345 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1346 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1347 SNDRV_PCM_HW_PARAM_RATE,
1348 davinci_mcasp_hw_rule_rate,
1350 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1353 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1354 SNDRV_PCM_HW_PARAM_FORMAT,
1355 davinci_mcasp_hw_rule_format,
1357 SNDRV_PCM_HW_PARAM_RATE, -1);
1365 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1366 struct snd_soc_dai *cpu_dai)
1368 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1370 mcasp->substreams[substream->stream] = NULL;
1372 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1375 if (!cpu_dai->active)
1376 mcasp->channels = 0;
1379 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1380 .startup = davinci_mcasp_startup,
1381 .shutdown = davinci_mcasp_shutdown,
1382 .trigger = davinci_mcasp_trigger,
1383 .hw_params = davinci_mcasp_hw_params,
1384 .set_fmt = davinci_mcasp_set_dai_fmt,
1385 .set_clkdiv = davinci_mcasp_set_clkdiv,
1386 .set_sysclk = davinci_mcasp_set_sysclk,
1387 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1390 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1392 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1394 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1395 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1400 #ifdef CONFIG_PM_SLEEP
1401 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1403 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1404 struct davinci_mcasp_context *context = &mcasp->context;
1408 context->pm_state = pm_runtime_active(mcasp->dev);
1409 if (!context->pm_state)
1410 pm_runtime_get_sync(mcasp->dev);
1412 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1413 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1415 if (mcasp->txnumevt) {
1416 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1417 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1419 if (mcasp->rxnumevt) {
1420 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1421 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1424 for (i = 0; i < mcasp->num_serializer; i++)
1425 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1426 DAVINCI_MCASP_XRSRCTL_REG(i));
1428 pm_runtime_put_sync(mcasp->dev);
1433 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1435 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1436 struct davinci_mcasp_context *context = &mcasp->context;
1440 pm_runtime_get_sync(mcasp->dev);
1442 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1443 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1445 if (mcasp->txnumevt) {
1446 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1447 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1449 if (mcasp->rxnumevt) {
1450 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1451 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1454 for (i = 0; i < mcasp->num_serializer; i++)
1455 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1456 context->xrsr_regs[i]);
1458 if (!context->pm_state)
1459 pm_runtime_put_sync(mcasp->dev);
1464 #define davinci_mcasp_suspend NULL
1465 #define davinci_mcasp_resume NULL
1468 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1470 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1471 SNDRV_PCM_FMTBIT_U8 | \
1472 SNDRV_PCM_FMTBIT_S16_LE | \
1473 SNDRV_PCM_FMTBIT_U16_LE | \
1474 SNDRV_PCM_FMTBIT_S24_LE | \
1475 SNDRV_PCM_FMTBIT_U24_LE | \
1476 SNDRV_PCM_FMTBIT_S24_3LE | \
1477 SNDRV_PCM_FMTBIT_U24_3LE | \
1478 SNDRV_PCM_FMTBIT_S32_LE | \
1479 SNDRV_PCM_FMTBIT_U32_LE)
1481 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1483 .name = "davinci-mcasp.0",
1484 .probe = davinci_mcasp_dai_probe,
1485 .suspend = davinci_mcasp_suspend,
1486 .resume = davinci_mcasp_resume,
1489 .channels_max = 32 * 16,
1490 .rates = DAVINCI_MCASP_RATES,
1491 .formats = DAVINCI_MCASP_PCM_FMTS,
1495 .channels_max = 32 * 16,
1496 .rates = DAVINCI_MCASP_RATES,
1497 .formats = DAVINCI_MCASP_PCM_FMTS,
1499 .ops = &davinci_mcasp_dai_ops,
1501 .symmetric_samplebits = 1,
1502 .symmetric_rates = 1,
1505 .name = "davinci-mcasp.1",
1506 .probe = davinci_mcasp_dai_probe,
1509 .channels_max = 384,
1510 .rates = DAVINCI_MCASP_RATES,
1511 .formats = DAVINCI_MCASP_PCM_FMTS,
1513 .ops = &davinci_mcasp_dai_ops,
1518 static const struct snd_soc_component_driver davinci_mcasp_component = {
1519 .name = "davinci-mcasp",
1522 /* Some HW specific values and defaults. The rest is filled in from DT. */
1523 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1524 .tx_dma_offset = 0x400,
1525 .rx_dma_offset = 0x400,
1526 .version = MCASP_VERSION_1,
1529 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1530 .tx_dma_offset = 0x2000,
1531 .rx_dma_offset = 0x2000,
1532 .version = MCASP_VERSION_2,
1535 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1538 .version = MCASP_VERSION_3,
1541 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1542 /* The CFG port offset will be calculated if it is needed */
1545 .version = MCASP_VERSION_4,
1548 static const struct of_device_id mcasp_dt_ids[] = {
1550 .compatible = "ti,dm646x-mcasp-audio",
1551 .data = &dm646x_mcasp_pdata,
1554 .compatible = "ti,da830-mcasp-audio",
1555 .data = &da830_mcasp_pdata,
1558 .compatible = "ti,am33xx-mcasp-audio",
1559 .data = &am33xx_mcasp_pdata,
1562 .compatible = "ti,dra7-mcasp-audio",
1563 .data = &dra7_mcasp_pdata,
1567 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1569 static int mcasp_reparent_fck(struct platform_device *pdev)
1571 struct device_node *node = pdev->dev.of_node;
1572 struct clk *gfclk, *parent_clk;
1573 const char *parent_name;
1579 parent_name = of_get_property(node, "fck_parent", NULL);
1583 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1585 gfclk = clk_get(&pdev->dev, "fck");
1586 if (IS_ERR(gfclk)) {
1587 dev_err(&pdev->dev, "failed to get fck\n");
1588 return PTR_ERR(gfclk);
1591 parent_clk = clk_get(NULL, parent_name);
1592 if (IS_ERR(parent_clk)) {
1593 dev_err(&pdev->dev, "failed to get parent clock\n");
1594 ret = PTR_ERR(parent_clk);
1598 ret = clk_set_parent(gfclk, parent_clk);
1600 dev_err(&pdev->dev, "failed to reparent fck\n");
1605 clk_put(parent_clk);
1611 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1612 struct platform_device *pdev)
1614 struct device_node *np = pdev->dev.of_node;
1615 struct davinci_mcasp_pdata *pdata = NULL;
1616 const struct of_device_id *match =
1617 of_match_device(mcasp_dt_ids, &pdev->dev);
1618 struct of_phandle_args dma_spec;
1620 const u32 *of_serial_dir32;
1624 if (pdev->dev.platform_data) {
1625 pdata = pdev->dev.platform_data;
1628 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1632 "Failed to allocate memory for pdata\n");
1637 /* control shouldn't reach here. something is wrong */
1642 ret = of_property_read_u32(np, "op-mode", &val);
1644 pdata->op_mode = val;
1646 ret = of_property_read_u32(np, "tdm-slots", &val);
1648 if (val < 2 || val > 32) {
1650 "tdm-slots must be in rage [2-32]\n");
1655 pdata->tdm_slots = val;
1658 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1660 if (of_serial_dir32) {
1661 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1662 (sizeof(*of_serial_dir) * val),
1664 if (!of_serial_dir) {
1669 for (i = 0; i < val; i++)
1670 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1672 pdata->num_serializer = val;
1673 pdata->serial_dir = of_serial_dir;
1676 ret = of_property_match_string(np, "dma-names", "tx");
1680 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1685 pdata->tx_dma_channel = dma_spec.args[0];
1687 /* RX is not valid in DIT mode */
1688 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1689 ret = of_property_match_string(np, "dma-names", "rx");
1693 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1698 pdata->rx_dma_channel = dma_spec.args[0];
1701 ret = of_property_read_u32(np, "tx-num-evt", &val);
1703 pdata->txnumevt = val;
1705 ret = of_property_read_u32(np, "rx-num-evt", &val);
1707 pdata->rxnumevt = val;
1709 ret = of_property_read_u32(np, "sram-size-playback", &val);
1711 pdata->sram_size_playback = val;
1713 ret = of_property_read_u32(np, "sram-size-capture", &val);
1715 pdata->sram_size_capture = val;
1721 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1732 static const char *sdma_prefix = "ti,omap";
1734 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1736 struct dma_chan *chan;
1740 if (!mcasp->dev->of_node)
1743 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1744 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1746 if (PTR_ERR(chan) != -EPROBE_DEFER)
1748 "Can't verify DMA configuration (%ld)\n",
1750 return PTR_ERR(chan);
1752 BUG_ON(!chan->device || !chan->device->dev);
1754 if (chan->device->dev->of_node)
1755 ret = of_property_read_string(chan->device->dev->of_node,
1756 "compatible", &tmp);
1758 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1760 dma_release_channel(chan);
1764 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1765 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1771 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1776 if (pdata->version != MCASP_VERSION_4)
1777 return pdata->tx_dma_offset;
1779 for (i = 0; i < pdata->num_serializer; i++) {
1780 if (pdata->serial_dir[i] == TX_MODE) {
1782 offset = DAVINCI_MCASP_TXBUF_REG(i);
1784 pr_err("%s: Only one serializer allowed!\n",
1794 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1799 if (pdata->version != MCASP_VERSION_4)
1800 return pdata->rx_dma_offset;
1802 for (i = 0; i < pdata->num_serializer; i++) {
1803 if (pdata->serial_dir[i] == RX_MODE) {
1805 offset = DAVINCI_MCASP_RXBUF_REG(i);
1807 pr_err("%s: Only one serializer allowed!\n",
1817 static int davinci_mcasp_probe(struct platform_device *pdev)
1819 struct snd_dmaengine_dai_dma_data *dma_data;
1820 struct resource *mem, *res, *dat;
1821 struct davinci_mcasp_pdata *pdata;
1822 struct davinci_mcasp *mcasp;
1828 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1829 dev_err(&pdev->dev, "No platform data supplied\n");
1833 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1838 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1840 dev_err(&pdev->dev, "no platform data\n");
1844 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1846 dev_warn(mcasp->dev,
1847 "\"mpu\" mem resource not found, using index 0\n");
1848 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1850 dev_err(&pdev->dev, "no mem resource?\n");
1855 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1856 if (IS_ERR(mcasp->base))
1857 return PTR_ERR(mcasp->base);
1859 pm_runtime_enable(&pdev->dev);
1861 mcasp->op_mode = pdata->op_mode;
1862 /* sanity check for tdm slots parameter */
1863 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1864 if (pdata->tdm_slots < 2) {
1865 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1867 mcasp->tdm_slots = 2;
1868 } else if (pdata->tdm_slots > 32) {
1869 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1871 mcasp->tdm_slots = 32;
1873 mcasp->tdm_slots = pdata->tdm_slots;
1877 mcasp->num_serializer = pdata->num_serializer;
1878 #ifdef CONFIG_PM_SLEEP
1879 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1880 sizeof(u32) * mcasp->num_serializer,
1883 mcasp->serial_dir = pdata->serial_dir;
1884 mcasp->version = pdata->version;
1885 mcasp->txnumevt = pdata->txnumevt;
1886 mcasp->rxnumevt = pdata->rxnumevt;
1888 mcasp->dev = &pdev->dev;
1890 irq = platform_get_irq_byname(pdev, "common");
1892 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1893 dev_name(&pdev->dev));
1894 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1895 davinci_mcasp_common_irq_handler,
1896 IRQF_ONESHOT | IRQF_SHARED,
1899 dev_err(&pdev->dev, "common IRQ request failed\n");
1903 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1904 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1907 irq = platform_get_irq_byname(pdev, "rx");
1909 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1910 dev_name(&pdev->dev));
1911 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1912 davinci_mcasp_rx_irq_handler,
1913 IRQF_ONESHOT, irq_name, mcasp);
1915 dev_err(&pdev->dev, "RX IRQ request failed\n");
1919 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1922 irq = platform_get_irq_byname(pdev, "tx");
1924 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1925 dev_name(&pdev->dev));
1926 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1927 davinci_mcasp_tx_irq_handler,
1928 IRQF_ONESHOT, irq_name, mcasp);
1930 dev_err(&pdev->dev, "TX IRQ request failed\n");
1934 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1937 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1939 mcasp->dat_port = true;
1941 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1943 dma_data->addr = dat->start;
1945 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1947 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1948 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1952 *dma = pdata->tx_dma_channel;
1954 /* dmaengine filter data for DT and non-DT boot */
1955 if (pdev->dev.of_node)
1956 dma_data->filter_data = "tx";
1958 dma_data->filter_data = dma;
1960 /* RX is not valid in DIT mode */
1961 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1962 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1964 dma_data->addr = dat->start;
1967 mem->start + davinci_mcasp_rxdma_offset(pdata);
1969 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1970 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1974 *dma = pdata->rx_dma_channel;
1976 /* dmaengine filter data for DT and non-DT boot */
1977 if (pdev->dev.of_node)
1978 dma_data->filter_data = "rx";
1980 dma_data->filter_data = dma;
1983 if (mcasp->version < MCASP_VERSION_3) {
1984 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1985 /* dma_params->dma_addr is pointing to the data port address */
1986 mcasp->dat_port = true;
1988 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1991 /* Allocate memory for long enough list for all possible
1992 * scenarios. Maximum number tdm slots is 32 and there cannot
1993 * be more serializers than given in the configuration. The
1994 * serializer directions could be taken into account, but it
1995 * would make code much more complex and save only couple of
1998 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
1999 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2000 (32 + mcasp->num_serializer - 2),
2003 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2004 devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
2005 (32 + mcasp->num_serializer - 2),
2008 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2009 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list)
2012 ret = davinci_mcasp_set_ch_constraints(mcasp);
2016 dev_set_drvdata(&pdev->dev, mcasp);
2018 mcasp_reparent_fck(pdev);
2020 ret = devm_snd_soc_register_component(&pdev->dev,
2021 &davinci_mcasp_component,
2022 &davinci_mcasp_dai[pdata->op_mode], 1);
2027 ret = davinci_mcasp_get_dma_type(mcasp);
2030 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2031 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2032 IS_MODULE(CONFIG_SND_EDMA_SOC))
2033 ret = edma_pcm_platform_register(&pdev->dev);
2035 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2041 #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
2042 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2043 IS_MODULE(CONFIG_SND_OMAP_SOC))
2044 ret = omap_pcm_platform_register(&pdev->dev);
2046 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2052 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2059 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2066 pm_runtime_disable(&pdev->dev);
2070 static int davinci_mcasp_remove(struct platform_device *pdev)
2072 pm_runtime_disable(&pdev->dev);
2077 static struct platform_driver davinci_mcasp_driver = {
2078 .probe = davinci_mcasp_probe,
2079 .remove = davinci_mcasp_remove,
2081 .name = "davinci-mcasp",
2082 .of_match_table = mcasp_dt_ids,
2086 module_platform_driver(davinci_mcasp_driver);
2088 MODULE_AUTHOR("Steve Chen");
2089 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2090 MODULE_LICENSE("GPL");