2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_platform.h>
28 #include <linux/of_device.h>
29 #include <linux/platform_data/davinci_asp.h>
30 #include <linux/math64.h>
32 #include <sound/asoundef.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/initval.h>
37 #include <sound/soc.h>
38 #include <sound/dmaengine_pcm.h>
41 #include "../omap/sdma-pcm.h"
42 #include "davinci-mcasp.h"
44 #define MCASP_MAX_AFIFO_DEPTH 64
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_RXMASK_REG,
58 DAVINCI_MCASP_TXMASK_REG,
59 DAVINCI_MCASP_RXTDM_REG,
60 DAVINCI_MCASP_TXTDM_REG,
63 struct davinci_mcasp_context {
64 u32 config_regs[ARRAY_SIZE(context_regs)];
65 u32 afifo_regs[2]; /* for read/write fifo control registers */
66 u32 *xrsr_regs; /* for serializer configuration */
71 struct davinci_mcasp_ruledata {
72 struct davinci_mcasp *mcasp;
76 struct davinci_mcasp {
77 struct snd_dmaengine_dai_dma_data dma_data[2];
81 struct snd_pcm_substream *substreams[2];
84 /* McASP specific data */
100 /* McASP FIFO related */
106 /* Used for comstraint setting on the second stream */
109 #ifdef CONFIG_PM_SLEEP
110 struct davinci_mcasp_context context;
113 struct davinci_mcasp_ruledata ruledata[2];
114 struct snd_pcm_hw_constraint_list chconstr[2];
117 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
120 void __iomem *reg = mcasp->base + offset;
121 __raw_writel(__raw_readl(reg) | val, reg);
124 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
127 void __iomem *reg = mcasp->base + offset;
128 __raw_writel((__raw_readl(reg) & ~(val)), reg);
131 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
134 void __iomem *reg = mcasp->base + offset;
135 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
138 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
141 __raw_writel(val, mcasp->base + offset);
144 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
146 return (u32)__raw_readl(mcasp->base + offset);
149 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
153 mcasp_set_bits(mcasp, ctl_reg, val);
155 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
156 /* loop count is to avoid the lock-up */
157 for (i = 0; i < 1000; i++) {
158 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
162 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
163 printk(KERN_ERR "GBLCTL write error\n");
166 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
168 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
169 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
171 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
174 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
176 if (mcasp->rxnumevt) { /* enable FIFO */
177 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
179 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
180 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
184 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
185 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
187 * When ASYNC == 0 the transmit and receive sections operate
188 * synchronously from the transmit clock and frame sync. We need to make
189 * sure that the TX signlas are enabled when starting reception.
191 if (mcasp_is_synchronous(mcasp)) {
192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
193 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
196 /* Activate serializer(s) */
197 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
198 /* Release RX state machine */
199 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
200 /* Release Frame Sync generator */
201 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
202 if (mcasp_is_synchronous(mcasp))
203 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
205 /* enable receive IRQs */
206 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
207 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
210 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
214 if (mcasp->txnumevt) { /* enable FIFO */
215 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
224 /* Activate serializer(s) */
225 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
227 /* wait for XDATA to be cleared */
229 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
233 /* Release TX state machine */
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
235 /* Release Frame Sync generator */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
238 /* enable transmit IRQs */
239 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
240 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
243 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
247 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
248 mcasp_start_tx(mcasp);
250 mcasp_start_rx(mcasp);
253 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
255 /* disable IRQ sources */
256 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
257 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
260 * In synchronous mode stop the TX clocks if no other stream is
263 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
266 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
267 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
269 if (mcasp->rxnumevt) { /* disable FIFO */
270 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
272 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
276 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
280 /* disable IRQ sources */
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
285 * In synchronous mode keep TX clocks running if the capture stream is
288 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
289 val = TXHCLKRST | TXCLKRST | TXFSRST;
291 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
292 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
294 if (mcasp->txnumevt) { /* disable FIFO */
295 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
297 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
301 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
305 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
306 mcasp_stop_tx(mcasp);
308 mcasp_stop_rx(mcasp);
311 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
313 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
314 struct snd_pcm_substream *substream;
315 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
316 u32 handled_mask = 0;
319 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
320 if (stat & XUNDRN & irq_mask) {
321 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
322 handled_mask |= XUNDRN;
324 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
326 snd_pcm_stop_xrun(substream);
330 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
334 handled_mask |= XRERR;
336 /* Ack the handled event only */
337 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
339 return IRQ_RETVAL(handled_mask);
342 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
344 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
345 struct snd_pcm_substream *substream;
346 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
347 u32 handled_mask = 0;
350 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
351 if (stat & ROVRN & irq_mask) {
352 dev_warn(mcasp->dev, "Receive buffer overflow\n");
353 handled_mask |= ROVRN;
355 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
357 snd_pcm_stop_xrun(substream);
361 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
365 handled_mask |= XRERR;
367 /* Ack the handled event only */
368 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
370 return IRQ_RETVAL(handled_mask);
373 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
375 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
376 irqreturn_t ret = IRQ_NONE;
378 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
379 ret = davinci_mcasp_tx_irq_handler(irq, data);
381 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
382 ret |= davinci_mcasp_rx_irq_handler(irq, data);
387 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
390 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
399 pm_runtime_get_sync(mcasp->dev);
400 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
401 case SND_SOC_DAIFMT_DSP_A:
402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
404 /* 1st data bit occur one ACLK cycle after the frame sync */
407 case SND_SOC_DAIFMT_DSP_B:
408 case SND_SOC_DAIFMT_AC97:
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
411 /* No delay after FS */
414 case SND_SOC_DAIFMT_I2S:
415 /* configure a full-word SYNC pulse (LRCLK) */
416 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
417 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
418 /* 1st data bit occur one ACLK cycle after the frame sync */
420 /* FS need to be inverted */
423 case SND_SOC_DAIFMT_LEFT_J:
424 /* configure a full-word SYNC pulse (LRCLK) */
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
427 /* No delay after FS */
435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
441 case SND_SOC_DAIFMT_CBS_CFS:
442 /* codec is clock and frame slave */
443 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
446 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
449 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
451 mcasp->bclk_master = 1;
453 case SND_SOC_DAIFMT_CBS_CFM:
454 /* codec is clock slave and frame master */
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
463 mcasp->bclk_master = 1;
465 case SND_SOC_DAIFMT_CBM_CFS:
466 /* codec is clock master and frame slave */
467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
475 mcasp->bclk_master = 0;
477 case SND_SOC_DAIFMT_CBM_CFM:
478 /* codec is clock and frame master */
479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AFSX | ACLKR | AHCLKR | AFSR);
487 mcasp->bclk_master = 0;
494 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
495 case SND_SOC_DAIFMT_IB_NF:
496 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
498 fs_pol_rising = true;
500 case SND_SOC_DAIFMT_NB_IF:
501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
503 fs_pol_rising = false;
505 case SND_SOC_DAIFMT_IB_IF:
506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
508 fs_pol_rising = false;
510 case SND_SOC_DAIFMT_NB_NF:
511 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
513 fs_pol_rising = true;
521 fs_pol_rising = !fs_pol_rising;
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
531 mcasp->dai_fmt = fmt;
533 pm_runtime_put(mcasp->dev);
537 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
538 int div, bool explicit)
540 pm_runtime_get_sync(mcasp->dev);
542 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
544 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
546 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
549 case MCASP_CLKDIV_BCLK: /* BCLK divider */
550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
551 ACLKXDIV(div - 1), ACLKXDIV_MASK);
552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
553 ACLKRDIV(div - 1), ACLKRDIV_MASK);
555 mcasp->bclk_div = div;
558 case MCASP_CLKDIV_BCLK_FS_RATIO:
560 * BCLK/LRCLK ratio descries how many bit-clock cycles
561 * fit into one frame. The clock ratio is given for a
562 * full period of data (for I2S format both left and
563 * right channels), so it has to be divided by number
564 * of tdm-slots (for I2S - divided by 2).
565 * Instead of storing this ratio, we calculate a new
566 * tdm_slot width by dividing the the ratio by the
567 * number of configured tdm slots.
569 mcasp->slot_width = div / mcasp->tdm_slots;
570 if (div % mcasp->tdm_slots)
572 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
573 __func__, div, mcasp->tdm_slots);
580 pm_runtime_put(mcasp->dev);
584 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
587 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
589 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
592 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
593 unsigned int freq, int dir)
595 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
597 pm_runtime_get_sync(mcasp->dev);
598 if (dir == SND_SOC_CLOCK_OUT) {
599 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
600 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
601 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
603 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
605 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
608 mcasp->sysclk_freq = freq;
610 pm_runtime_put(mcasp->dev);
614 /* All serializers must have equal number of channels */
615 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
618 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
619 unsigned int *list = (unsigned int *) cl->list;
620 int slots = mcasp->tdm_slots;
623 if (mcasp->tdm_mask[stream])
624 slots = hweight32(mcasp->tdm_mask[stream]);
626 for (i = 1; i <= slots; i++)
629 for (i = 2; i <= serializers; i++)
630 list[count++] = i*slots;
637 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
639 int rx_serializers = 0, tx_serializers = 0, ret, i;
641 for (i = 0; i < mcasp->num_serializer; i++)
642 if (mcasp->serial_dir[i] == TX_MODE)
644 else if (mcasp->serial_dir[i] == RX_MODE)
647 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
652 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
659 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
660 unsigned int tx_mask,
661 unsigned int rx_mask,
662 int slots, int slot_width)
664 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
667 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
668 __func__, tx_mask, rx_mask, slots, slot_width);
670 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
672 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
673 tx_mask, rx_mask, slots);
678 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
679 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
680 __func__, slot_width);
684 mcasp->tdm_slots = slots;
685 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
686 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
687 mcasp->slot_width = slot_width;
689 return davinci_mcasp_set_ch_constraints(mcasp);
692 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
696 u32 tx_rotate = (sample_width / 4) & 0x7;
697 u32 mask = (1ULL << sample_width) - 1;
698 u32 slot_width = sample_width;
701 * For captured data we should not rotate, inversion and masking is
702 * enoguh to get the data to the right position:
703 * Format data from bus after reverse (XRBUF)
704 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
705 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
706 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
707 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
712 * Setting the tdm slot width either with set_clkdiv() or
713 * set_tdm_slot() allows us to for example send 32 bits per
714 * channel to the codec, while only 16 of them carry audio
717 if (mcasp->slot_width) {
719 * When we have more bclk then it is needed for the
720 * data, we need to use the rotation to move the
721 * received samples to have correct alignment.
723 slot_width = mcasp->slot_width;
724 rx_rotate = (slot_width - sample_width) / 4;
727 /* mapping of the XSSZ bit-field as described in the datasheet */
728 fmt = (slot_width >> 1) - 1;
730 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
731 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
733 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
735 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
737 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
739 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
742 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
747 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
748 int period_words, int channels)
750 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
754 u8 slots = mcasp->tdm_slots;
755 u8 max_active_serializers = (channels + slots - 1) / slots;
756 int active_serializers, numevt;
758 /* Default configuration */
759 if (mcasp->version < MCASP_VERSION_3)
760 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
762 /* All PINS as McASP */
763 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
765 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
766 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
767 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
769 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
770 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
773 for (i = 0; i < mcasp->num_serializer; i++) {
774 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
775 mcasp->serial_dir[i]);
776 if (mcasp->serial_dir[i] == TX_MODE &&
777 tx_ser < max_active_serializers) {
778 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
779 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
780 DISMOD_LOW, DISMOD_MASK);
782 } else if (mcasp->serial_dir[i] == RX_MODE &&
783 rx_ser < max_active_serializers) {
784 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
786 } else if (mcasp->serial_dir[i] == INACTIVE_MODE) {
787 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
788 SRMOD_INACTIVE, SRMOD_MASK);
792 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
793 active_serializers = tx_ser;
794 numevt = mcasp->txnumevt;
795 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
797 active_serializers = rx_ser;
798 numevt = mcasp->rxnumevt;
799 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
802 if (active_serializers < max_active_serializers) {
803 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
804 "enabled in mcasp (%d)\n", channels,
805 active_serializers * slots);
809 /* AFIFO is not in use */
811 /* Configure the burst size for platform drivers */
812 if (active_serializers > 1) {
814 * If more than one serializers are in use we have one
815 * DMA request to provide data for all serializers.
816 * For example if three serializers are enabled the DMA
817 * need to transfer three words per DMA request.
819 dma_data->maxburst = active_serializers;
821 dma_data->maxburst = 0;
826 if (period_words % active_serializers) {
827 dev_err(mcasp->dev, "Invalid combination of period words and "
828 "active serializers: %d, %d\n", period_words,
834 * Calculate the optimal AFIFO depth for platform side:
835 * The number of words for numevt need to be in steps of active
838 numevt = (numevt / active_serializers) * active_serializers;
840 while (period_words % numevt && numevt > 0)
841 numevt -= active_serializers;
843 numevt = active_serializers;
845 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
846 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
848 /* Configure the burst size for platform drivers */
851 dma_data->maxburst = numevt;
856 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
861 int active_serializers;
865 total_slots = mcasp->tdm_slots;
868 * If more than one serializer is needed, then use them with
869 * all the specified tdm_slots. Otherwise, one serializer can
870 * cope with the transaction using just as many slots as there
871 * are channels in the stream.
873 if (mcasp->tdm_mask[stream]) {
874 active_slots = hweight32(mcasp->tdm_mask[stream]);
875 active_serializers = (channels + active_slots - 1) /
877 if (active_serializers == 1)
878 active_slots = channels;
879 for (i = 0; i < total_slots; i++) {
880 if ((1 << i) & mcasp->tdm_mask[stream]) {
882 if (--active_slots <= 0)
887 active_serializers = (channels + total_slots - 1) / total_slots;
888 if (active_serializers == 1)
889 active_slots = channels;
891 active_slots = total_slots;
893 for (i = 0; i < active_slots; i++)
896 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
898 if (!mcasp->dat_port)
901 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
902 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
903 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
904 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
905 FSXMOD(total_slots), FSXMOD(0x1FF));
906 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
907 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
908 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
909 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
910 FSRMOD(total_slots), FSRMOD(0x1FF));
912 * If McASP is set to be TX/RX synchronous and the playback is
913 * not running already we need to configure the TX slots in
914 * order to have correct FSX on the bus
916 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
917 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
918 FSXMOD(total_slots), FSXMOD(0x1FF));
925 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
929 u8 *cs_bytes = (u8*) &cs_value;
931 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
933 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
935 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
936 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
938 /* Set the TX tdm : for all the slots */
939 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
941 /* Set the TX clock controls : div = 1 and internal */
942 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
944 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
946 /* Only 44100 and 48000 are valid, both have the same setting */
947 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
950 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
952 /* Set S/PDIF channel status bits */
953 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
954 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
958 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
961 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
964 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
967 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
970 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
973 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
976 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
979 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
982 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
985 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
989 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
990 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
995 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
996 unsigned int bclk_freq, bool set)
999 unsigned int sysclk_freq = mcasp->sysclk_freq;
1000 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1001 int div = sysclk_freq / bclk_freq;
1002 int rem = sysclk_freq % bclk_freq;
1005 if (div > (ACLKXDIV_MASK + 1)) {
1006 if (reg & AHCLKXE) {
1007 aux_div = div / (ACLKXDIV_MASK + 1);
1008 if (div % (ACLKXDIV_MASK + 1))
1011 sysclk_freq /= aux_div;
1012 div = sysclk_freq / bclk_freq;
1013 rem = sysclk_freq % bclk_freq;
1015 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1022 ((sysclk_freq / div) - bclk_freq) >
1023 (bclk_freq - (sysclk_freq / (div+1)))) {
1025 rem = rem - bclk_freq;
1028 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1029 (int)bclk_freq)) / div - 1000000;
1033 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1036 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1038 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1045 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1046 struct snd_pcm_hw_params *params,
1047 struct snd_soc_dai *cpu_dai)
1049 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1051 int channels = params_channels(params);
1052 int period_size = params_period_size(params);
1055 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1060 * If mcasp is BCLK master, and a BCLK divider was not provided by
1061 * the machine driver, we need to calculate the ratio.
1063 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1064 int slots = mcasp->tdm_slots;
1065 int rate = params_rate(params);
1066 int sbits = params_width(params);
1068 if (mcasp->slot_width)
1069 sbits = mcasp->slot_width;
1071 davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true);
1074 ret = mcasp_common_hw_param(mcasp, substream->stream,
1075 period_size * channels, channels);
1079 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1080 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1082 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1088 switch (params_format(params)) {
1089 case SNDRV_PCM_FORMAT_U8:
1090 case SNDRV_PCM_FORMAT_S8:
1094 case SNDRV_PCM_FORMAT_U16_LE:
1095 case SNDRV_PCM_FORMAT_S16_LE:
1099 case SNDRV_PCM_FORMAT_U24_3LE:
1100 case SNDRV_PCM_FORMAT_S24_3LE:
1104 case SNDRV_PCM_FORMAT_U24_LE:
1105 case SNDRV_PCM_FORMAT_S24_LE:
1109 case SNDRV_PCM_FORMAT_U32_LE:
1110 case SNDRV_PCM_FORMAT_S32_LE:
1115 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1119 davinci_config_channel_size(mcasp, word_length);
1121 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
1122 mcasp->channels = channels;
1127 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1128 int cmd, struct snd_soc_dai *cpu_dai)
1130 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1134 case SNDRV_PCM_TRIGGER_RESUME:
1135 case SNDRV_PCM_TRIGGER_START:
1136 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1137 davinci_mcasp_start(mcasp, substream->stream);
1139 case SNDRV_PCM_TRIGGER_SUSPEND:
1140 case SNDRV_PCM_TRIGGER_STOP:
1141 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1142 davinci_mcasp_stop(mcasp, substream->stream);
1152 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1153 struct snd_pcm_hw_rule *rule)
1155 struct davinci_mcasp_ruledata *rd = rule->private;
1156 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1157 struct snd_mask nfmt;
1160 snd_mask_none(&nfmt);
1161 slot_width = rd->mcasp->slot_width;
1163 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1164 if (snd_mask_test(fmt, i)) {
1165 if (snd_pcm_format_width(i) <= slot_width) {
1166 snd_mask_set(&nfmt, i);
1171 return snd_mask_refine(fmt, &nfmt);
1174 static const unsigned int davinci_mcasp_dai_rates[] = {
1175 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1176 88200, 96000, 176400, 192000,
1179 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1181 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1182 struct snd_pcm_hw_rule *rule)
1184 struct davinci_mcasp_ruledata *rd = rule->private;
1185 struct snd_interval *ri =
1186 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1187 int sbits = params_width(params);
1188 int slots = rd->mcasp->tdm_slots;
1189 struct snd_interval range;
1192 if (rd->mcasp->slot_width)
1193 sbits = rd->mcasp->slot_width;
1195 snd_interval_any(&range);
1198 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1199 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1200 uint bclk_freq = sbits*slots*
1201 davinci_mcasp_dai_rates[i];
1204 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq,
1206 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1208 range.min = davinci_mcasp_dai_rates[i];
1211 range.max = davinci_mcasp_dai_rates[i];
1216 dev_dbg(rd->mcasp->dev,
1217 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1218 ri->min, ri->max, range.min, range.max, sbits, slots);
1220 return snd_interval_refine(hw_param_interval(params, rule->var),
1224 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1225 struct snd_pcm_hw_rule *rule)
1227 struct davinci_mcasp_ruledata *rd = rule->private;
1228 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1229 struct snd_mask nfmt;
1230 int rate = params_rate(params);
1231 int slots = rd->mcasp->tdm_slots;
1234 snd_mask_none(&nfmt);
1236 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1237 if (snd_mask_test(fmt, i)) {
1238 uint sbits = snd_pcm_format_width(i);
1241 if (rd->mcasp->slot_width)
1242 sbits = rd->mcasp->slot_width;
1244 ppm = davinci_mcasp_calc_clk_div(rd->mcasp,
1245 sbits * slots * rate,
1247 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1248 snd_mask_set(&nfmt, i);
1253 dev_dbg(rd->mcasp->dev,
1254 "%d possible sample format for %d Hz and %d tdm slots\n",
1255 count, rate, slots);
1257 return snd_mask_refine(fmt, &nfmt);
1260 static int davinci_mcasp_hw_rule_min_periodsize(
1261 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1263 struct snd_interval *period_size = hw_param_interval(params,
1264 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1265 struct snd_interval frames;
1267 snd_interval_any(&frames);
1271 return snd_interval_refine(period_size, &frames);
1274 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1275 struct snd_soc_dai *cpu_dai)
1277 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1278 struct davinci_mcasp_ruledata *ruledata =
1279 &mcasp->ruledata[substream->stream];
1280 u32 max_channels = 0;
1282 int tdm_slots = mcasp->tdm_slots;
1284 /* Do not allow more then one stream per direction */
1285 if (mcasp->substreams[substream->stream])
1288 mcasp->substreams[substream->stream] = substream;
1290 if (mcasp->tdm_mask[substream->stream])
1291 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1293 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1297 * Limit the maximum allowed channels for the first stream:
1298 * number of serializers for the direction * tdm slots per serializer
1300 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1305 for (i = 0; i < mcasp->num_serializer; i++) {
1306 if (mcasp->serial_dir[i] == dir)
1309 ruledata->serializers = max_channels;
1310 ruledata->mcasp = mcasp;
1311 max_channels *= tdm_slots;
1313 * If the already active stream has less channels than the calculated
1314 * limnit based on the seirializers * tdm_slots, we need to use that as
1315 * a constraint for the second stream.
1316 * Otherwise (first stream or less allowed channels) we use the
1317 * calculated constraint.
1319 if (mcasp->channels && mcasp->channels < max_channels)
1320 max_channels = mcasp->channels;
1322 * But we can always allow channels upto the amount of
1323 * the available tdm_slots.
1325 if (max_channels < tdm_slots)
1326 max_channels = tdm_slots;
1328 snd_pcm_hw_constraint_minmax(substream->runtime,
1329 SNDRV_PCM_HW_PARAM_CHANNELS,
1332 snd_pcm_hw_constraint_list(substream->runtime,
1333 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1334 &mcasp->chconstr[substream->stream]);
1336 if (mcasp->slot_width) {
1337 /* Only allow formats require <= slot_width bits on the bus */
1338 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1339 SNDRV_PCM_HW_PARAM_FORMAT,
1340 davinci_mcasp_hw_rule_slot_width,
1342 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1348 * If we rely on implicit BCLK divider setting we should
1349 * set constraints based on what we can provide.
1351 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1352 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1353 SNDRV_PCM_HW_PARAM_RATE,
1354 davinci_mcasp_hw_rule_rate,
1356 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1359 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1360 SNDRV_PCM_HW_PARAM_FORMAT,
1361 davinci_mcasp_hw_rule_format,
1363 SNDRV_PCM_HW_PARAM_RATE, -1);
1368 snd_pcm_hw_rule_add(substream->runtime, 0,
1369 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1370 davinci_mcasp_hw_rule_min_periodsize, NULL,
1371 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1376 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1377 struct snd_soc_dai *cpu_dai)
1379 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1381 mcasp->substreams[substream->stream] = NULL;
1383 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1386 if (!cpu_dai->active)
1387 mcasp->channels = 0;
1390 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1391 .startup = davinci_mcasp_startup,
1392 .shutdown = davinci_mcasp_shutdown,
1393 .trigger = davinci_mcasp_trigger,
1394 .hw_params = davinci_mcasp_hw_params,
1395 .set_fmt = davinci_mcasp_set_dai_fmt,
1396 .set_clkdiv = davinci_mcasp_set_clkdiv,
1397 .set_sysclk = davinci_mcasp_set_sysclk,
1398 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1401 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1403 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1405 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1406 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1411 #ifdef CONFIG_PM_SLEEP
1412 static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1414 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1415 struct davinci_mcasp_context *context = &mcasp->context;
1419 context->pm_state = pm_runtime_active(mcasp->dev);
1420 if (!context->pm_state)
1421 pm_runtime_get_sync(mcasp->dev);
1423 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1424 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
1426 if (mcasp->txnumevt) {
1427 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1428 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1430 if (mcasp->rxnumevt) {
1431 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1432 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1435 for (i = 0; i < mcasp->num_serializer; i++)
1436 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1437 DAVINCI_MCASP_XRSRCTL_REG(i));
1439 pm_runtime_put_sync(mcasp->dev);
1444 static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1446 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1447 struct davinci_mcasp_context *context = &mcasp->context;
1451 pm_runtime_get_sync(mcasp->dev);
1453 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1454 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
1456 if (mcasp->txnumevt) {
1457 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1458 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1460 if (mcasp->rxnumevt) {
1461 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1462 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1465 for (i = 0; i < mcasp->num_serializer; i++)
1466 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1467 context->xrsr_regs[i]);
1469 if (!context->pm_state)
1470 pm_runtime_put_sync(mcasp->dev);
1475 #define davinci_mcasp_suspend NULL
1476 #define davinci_mcasp_resume NULL
1479 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1481 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1482 SNDRV_PCM_FMTBIT_U8 | \
1483 SNDRV_PCM_FMTBIT_S16_LE | \
1484 SNDRV_PCM_FMTBIT_U16_LE | \
1485 SNDRV_PCM_FMTBIT_S24_LE | \
1486 SNDRV_PCM_FMTBIT_U24_LE | \
1487 SNDRV_PCM_FMTBIT_S24_3LE | \
1488 SNDRV_PCM_FMTBIT_U24_3LE | \
1489 SNDRV_PCM_FMTBIT_S32_LE | \
1490 SNDRV_PCM_FMTBIT_U32_LE)
1492 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1494 .name = "davinci-mcasp.0",
1495 .probe = davinci_mcasp_dai_probe,
1496 .suspend = davinci_mcasp_suspend,
1497 .resume = davinci_mcasp_resume,
1500 .channels_max = 32 * 16,
1501 .rates = DAVINCI_MCASP_RATES,
1502 .formats = DAVINCI_MCASP_PCM_FMTS,
1506 .channels_max = 32 * 16,
1507 .rates = DAVINCI_MCASP_RATES,
1508 .formats = DAVINCI_MCASP_PCM_FMTS,
1510 .ops = &davinci_mcasp_dai_ops,
1512 .symmetric_samplebits = 1,
1513 .symmetric_rates = 1,
1516 .name = "davinci-mcasp.1",
1517 .probe = davinci_mcasp_dai_probe,
1520 .channels_max = 384,
1521 .rates = DAVINCI_MCASP_RATES,
1522 .formats = DAVINCI_MCASP_PCM_FMTS,
1524 .ops = &davinci_mcasp_dai_ops,
1529 static const struct snd_soc_component_driver davinci_mcasp_component = {
1530 .name = "davinci-mcasp",
1533 /* Some HW specific values and defaults. The rest is filled in from DT. */
1534 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1535 .tx_dma_offset = 0x400,
1536 .rx_dma_offset = 0x400,
1537 .version = MCASP_VERSION_1,
1540 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1541 .tx_dma_offset = 0x2000,
1542 .rx_dma_offset = 0x2000,
1543 .version = MCASP_VERSION_2,
1546 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1549 .version = MCASP_VERSION_3,
1552 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1553 /* The CFG port offset will be calculated if it is needed */
1556 .version = MCASP_VERSION_4,
1559 static const struct of_device_id mcasp_dt_ids[] = {
1561 .compatible = "ti,dm646x-mcasp-audio",
1562 .data = &dm646x_mcasp_pdata,
1565 .compatible = "ti,da830-mcasp-audio",
1566 .data = &da830_mcasp_pdata,
1569 .compatible = "ti,am33xx-mcasp-audio",
1570 .data = &am33xx_mcasp_pdata,
1573 .compatible = "ti,dra7-mcasp-audio",
1574 .data = &dra7_mcasp_pdata,
1578 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1580 static int mcasp_reparent_fck(struct platform_device *pdev)
1582 struct device_node *node = pdev->dev.of_node;
1583 struct clk *gfclk, *parent_clk;
1584 const char *parent_name;
1590 parent_name = of_get_property(node, "fck_parent", NULL);
1594 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1596 gfclk = clk_get(&pdev->dev, "fck");
1597 if (IS_ERR(gfclk)) {
1598 dev_err(&pdev->dev, "failed to get fck\n");
1599 return PTR_ERR(gfclk);
1602 parent_clk = clk_get(NULL, parent_name);
1603 if (IS_ERR(parent_clk)) {
1604 dev_err(&pdev->dev, "failed to get parent clock\n");
1605 ret = PTR_ERR(parent_clk);
1609 ret = clk_set_parent(gfclk, parent_clk);
1611 dev_err(&pdev->dev, "failed to reparent fck\n");
1616 clk_put(parent_clk);
1622 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1623 struct platform_device *pdev)
1625 struct device_node *np = pdev->dev.of_node;
1626 struct davinci_mcasp_pdata *pdata = NULL;
1627 const struct of_device_id *match =
1628 of_match_device(mcasp_dt_ids, &pdev->dev);
1629 struct of_phandle_args dma_spec;
1631 const u32 *of_serial_dir32;
1635 if (pdev->dev.platform_data) {
1636 pdata = pdev->dev.platform_data;
1639 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1646 /* control shouldn't reach here. something is wrong */
1651 ret = of_property_read_u32(np, "op-mode", &val);
1653 pdata->op_mode = val;
1655 ret = of_property_read_u32(np, "tdm-slots", &val);
1657 if (val < 2 || val > 32) {
1659 "tdm-slots must be in rage [2-32]\n");
1664 pdata->tdm_slots = val;
1667 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1669 if (of_serial_dir32) {
1670 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1671 (sizeof(*of_serial_dir) * val),
1673 if (!of_serial_dir) {
1678 for (i = 0; i < val; i++)
1679 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1681 pdata->num_serializer = val;
1682 pdata->serial_dir = of_serial_dir;
1685 ret = of_property_match_string(np, "dma-names", "tx");
1689 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1694 pdata->tx_dma_channel = dma_spec.args[0];
1696 /* RX is not valid in DIT mode */
1697 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1698 ret = of_property_match_string(np, "dma-names", "rx");
1702 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1707 pdata->rx_dma_channel = dma_spec.args[0];
1710 ret = of_property_read_u32(np, "tx-num-evt", &val);
1712 pdata->txnumevt = val;
1714 ret = of_property_read_u32(np, "rx-num-evt", &val);
1716 pdata->rxnumevt = val;
1718 ret = of_property_read_u32(np, "sram-size-playback", &val);
1720 pdata->sram_size_playback = val;
1722 ret = of_property_read_u32(np, "sram-size-capture", &val);
1724 pdata->sram_size_capture = val;
1730 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1741 static const char *sdma_prefix = "ti,omap";
1743 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1745 struct dma_chan *chan;
1749 if (!mcasp->dev->of_node)
1752 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1753 chan = dma_request_slave_channel_reason(mcasp->dev, tmp);
1755 if (PTR_ERR(chan) != -EPROBE_DEFER)
1757 "Can't verify DMA configuration (%ld)\n",
1759 return PTR_ERR(chan);
1761 if (WARN_ON(!chan->device || !chan->device->dev)) {
1762 dma_release_channel(chan);
1766 if (chan->device->dev->of_node)
1767 ret = of_property_read_string(chan->device->dev->of_node,
1768 "compatible", &tmp);
1770 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1772 dma_release_channel(chan);
1776 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1777 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1783 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1788 if (pdata->version != MCASP_VERSION_4)
1789 return pdata->tx_dma_offset;
1791 for (i = 0; i < pdata->num_serializer; i++) {
1792 if (pdata->serial_dir[i] == TX_MODE) {
1794 offset = DAVINCI_MCASP_TXBUF_REG(i);
1796 pr_err("%s: Only one serializer allowed!\n",
1806 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1811 if (pdata->version != MCASP_VERSION_4)
1812 return pdata->rx_dma_offset;
1814 for (i = 0; i < pdata->num_serializer; i++) {
1815 if (pdata->serial_dir[i] == RX_MODE) {
1817 offset = DAVINCI_MCASP_RXBUF_REG(i);
1819 pr_err("%s: Only one serializer allowed!\n",
1829 static int davinci_mcasp_probe(struct platform_device *pdev)
1831 struct snd_dmaengine_dai_dma_data *dma_data;
1832 struct resource *mem, *res, *dat;
1833 struct davinci_mcasp_pdata *pdata;
1834 struct davinci_mcasp *mcasp;
1840 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1841 dev_err(&pdev->dev, "No platform data supplied\n");
1845 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
1850 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1852 dev_err(&pdev->dev, "no platform data\n");
1856 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1858 dev_warn(mcasp->dev,
1859 "\"mpu\" mem resource not found, using index 0\n");
1860 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862 dev_err(&pdev->dev, "no mem resource?\n");
1867 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
1868 if (IS_ERR(mcasp->base))
1869 return PTR_ERR(mcasp->base);
1871 pm_runtime_enable(&pdev->dev);
1873 mcasp->op_mode = pdata->op_mode;
1874 /* sanity check for tdm slots parameter */
1875 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1876 if (pdata->tdm_slots < 2) {
1877 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1879 mcasp->tdm_slots = 2;
1880 } else if (pdata->tdm_slots > 32) {
1881 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1883 mcasp->tdm_slots = 32;
1885 mcasp->tdm_slots = pdata->tdm_slots;
1889 mcasp->num_serializer = pdata->num_serializer;
1890 #ifdef CONFIG_PM_SLEEP
1891 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
1892 mcasp->num_serializer, sizeof(u32),
1894 if (!mcasp->context.xrsr_regs) {
1899 mcasp->serial_dir = pdata->serial_dir;
1900 mcasp->version = pdata->version;
1901 mcasp->txnumevt = pdata->txnumevt;
1902 mcasp->rxnumevt = pdata->rxnumevt;
1904 mcasp->dev = &pdev->dev;
1906 irq = platform_get_irq_byname(pdev, "common");
1908 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
1909 dev_name(&pdev->dev));
1914 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1915 davinci_mcasp_common_irq_handler,
1916 IRQF_ONESHOT | IRQF_SHARED,
1919 dev_err(&pdev->dev, "common IRQ request failed\n");
1923 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1924 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1927 irq = platform_get_irq_byname(pdev, "rx");
1929 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
1930 dev_name(&pdev->dev));
1935 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1936 davinci_mcasp_rx_irq_handler,
1937 IRQF_ONESHOT, irq_name, mcasp);
1939 dev_err(&pdev->dev, "RX IRQ request failed\n");
1943 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1946 irq = platform_get_irq_byname(pdev, "tx");
1948 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
1949 dev_name(&pdev->dev));
1954 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1955 davinci_mcasp_tx_irq_handler,
1956 IRQF_ONESHOT, irq_name, mcasp);
1958 dev_err(&pdev->dev, "TX IRQ request failed\n");
1962 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1965 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
1967 mcasp->dat_port = true;
1969 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1971 dma_data->addr = dat->start;
1973 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
1975 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
1976 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1980 *dma = pdata->tx_dma_channel;
1982 /* dmaengine filter data for DT and non-DT boot */
1983 if (pdev->dev.of_node)
1984 dma_data->filter_data = "tx";
1986 dma_data->filter_data = dma;
1988 /* RX is not valid in DIT mode */
1989 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
1990 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1992 dma_data->addr = dat->start;
1995 mem->start + davinci_mcasp_rxdma_offset(pdata);
1997 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
1998 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2002 *dma = pdata->rx_dma_channel;
2004 /* dmaengine filter data for DT and non-DT boot */
2005 if (pdev->dev.of_node)
2006 dma_data->filter_data = "rx";
2008 dma_data->filter_data = dma;
2011 if (mcasp->version < MCASP_VERSION_3) {
2012 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2013 /* dma_params->dma_addr is pointing to the data port address */
2014 mcasp->dat_port = true;
2016 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2019 /* Allocate memory for long enough list for all possible
2020 * scenarios. Maximum number tdm slots is 32 and there cannot
2021 * be more serializers than given in the configuration. The
2022 * serializer directions could be taken into account, but it
2023 * would make code much more complex and save only couple of
2026 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2027 devm_kcalloc(mcasp->dev,
2028 32 + mcasp->num_serializer - 1,
2029 sizeof(unsigned int),
2032 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2033 devm_kcalloc(mcasp->dev,
2034 32 + mcasp->num_serializer - 1,
2035 sizeof(unsigned int),
2038 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2039 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2044 ret = davinci_mcasp_set_ch_constraints(mcasp);
2048 dev_set_drvdata(&pdev->dev, mcasp);
2050 mcasp_reparent_fck(pdev);
2052 ret = devm_snd_soc_register_component(&pdev->dev,
2053 &davinci_mcasp_component,
2054 &davinci_mcasp_dai[pdata->op_mode], 1);
2059 ret = davinci_mcasp_get_dma_type(mcasp);
2062 #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
2063 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2064 IS_MODULE(CONFIG_SND_EDMA_SOC))
2065 ret = edma_pcm_platform_register(&pdev->dev);
2067 dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n");
2073 #if IS_BUILTIN(CONFIG_SND_SDMA_SOC) || \
2074 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
2075 IS_MODULE(CONFIG_SND_SDMA_SOC))
2076 ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL);
2078 dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n");
2084 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2091 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2098 pm_runtime_disable(&pdev->dev);
2102 static int davinci_mcasp_remove(struct platform_device *pdev)
2104 pm_runtime_disable(&pdev->dev);
2109 static struct platform_driver davinci_mcasp_driver = {
2110 .probe = davinci_mcasp_probe,
2111 .remove = davinci_mcasp_remove,
2113 .name = "davinci-mcasp",
2114 .of_match_table = mcasp_dt_ids,
2118 module_platform_driver(davinci_mcasp_driver);
2120 MODULE_AUTHOR("Steve Chen");
2121 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2122 MODULE_LICENSE("GPL");