1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm9081.c -- WM9081 ALSA SoC Audio driver
7 * Copyright 2009-12 Wolfson Microelectronics plc
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
16 #include <linux/i2c.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
26 #include <sound/wm9081.h>
29 static const struct reg_default wm9081_reg[] = {
30 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
31 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
32 { 4, 0x0001 }, /* R4 - VMID Control */
33 { 5, 0x0068 }, /* R5 - Bias Control 1 */
34 { 7, 0x0000 }, /* R7 - Analogue Mixer */
35 { 8, 0x0000 }, /* R8 - Anti Pop Control */
36 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
37 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
38 { 11, 0x0180 }, /* R11 - Power Management */
39 { 12, 0x0000 }, /* R12 - Clock Control 1 */
40 { 13, 0x0038 }, /* R13 - Clock Control 2 */
41 { 14, 0x4000 }, /* R14 - Clock Control 3 */
42 { 16, 0x0000 }, /* R16 - FLL Control 1 */
43 { 17, 0x0200 }, /* R17 - FLL Control 2 */
44 { 18, 0x0000 }, /* R18 - FLL Control 3 */
45 { 19, 0x0204 }, /* R19 - FLL Control 4 */
46 { 20, 0x0000 }, /* R20 - FLL Control 5 */
47 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
48 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
49 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
50 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
51 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
52 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
53 { 29, 0x0000 }, /* R29 - Interrupt Control */
54 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
55 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
56 { 32, 0x09AF }, /* R32 - DRC 1 */
57 { 33, 0x4201 }, /* R33 - DRC 2 */
58 { 34, 0x0000 }, /* R34 - DRC 3 */
59 { 35, 0x0000 }, /* R35 - DRC 4 */
60 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
61 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
62 { 40, 0x0002 }, /* R40 - MW Slave 1 */
63 { 42, 0x0000 }, /* R42 - EQ 1 */
64 { 43, 0x0000 }, /* R43 - EQ 2 */
65 { 44, 0x0FCA }, /* R44 - EQ 3 */
66 { 45, 0x0400 }, /* R45 - EQ 4 */
67 { 46, 0x00B8 }, /* R46 - EQ 5 */
68 { 47, 0x1EB5 }, /* R47 - EQ 6 */
69 { 48, 0xF145 }, /* R48 - EQ 7 */
70 { 49, 0x0B75 }, /* R49 - EQ 8 */
71 { 50, 0x01C5 }, /* R50 - EQ 9 */
72 { 51, 0x169E }, /* R51 - EQ 10 */
73 { 52, 0xF829 }, /* R52 - EQ 11 */
74 { 53, 0x07AD }, /* R53 - EQ 12 */
75 { 54, 0x1103 }, /* R54 - EQ 13 */
76 { 55, 0x1C58 }, /* R55 - EQ 14 */
77 { 56, 0xF373 }, /* R56 - EQ 15 */
78 { 57, 0x0A54 }, /* R57 - EQ 16 */
79 { 58, 0x0558 }, /* R58 - EQ 17 */
80 { 59, 0x0564 }, /* R59 - EQ 18 */
81 { 60, 0x0559 }, /* R60 - EQ 19 */
82 { 61, 0x4000 }, /* R61 - EQ 20 */
119 int div; /* *10 due to .5s */
146 struct regmap *regmap;
156 struct wm9081_pdata pdata;
159 static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
162 case WM9081_SOFTWARE_RESET:
163 case WM9081_INTERRUPT_STATUS:
170 static bool wm9081_readable_register(struct device *dev, unsigned int reg)
173 case WM9081_SOFTWARE_RESET:
174 case WM9081_ANALOGUE_LINEOUT:
175 case WM9081_ANALOGUE_SPEAKER_PGA:
176 case WM9081_VMID_CONTROL:
177 case WM9081_BIAS_CONTROL_1:
178 case WM9081_ANALOGUE_MIXER:
179 case WM9081_ANTI_POP_CONTROL:
180 case WM9081_ANALOGUE_SPEAKER_1:
181 case WM9081_ANALOGUE_SPEAKER_2:
182 case WM9081_POWER_MANAGEMENT:
183 case WM9081_CLOCK_CONTROL_1:
184 case WM9081_CLOCK_CONTROL_2:
185 case WM9081_CLOCK_CONTROL_3:
186 case WM9081_FLL_CONTROL_1:
187 case WM9081_FLL_CONTROL_2:
188 case WM9081_FLL_CONTROL_3:
189 case WM9081_FLL_CONTROL_4:
190 case WM9081_FLL_CONTROL_5:
191 case WM9081_AUDIO_INTERFACE_1:
192 case WM9081_AUDIO_INTERFACE_2:
193 case WM9081_AUDIO_INTERFACE_3:
194 case WM9081_AUDIO_INTERFACE_4:
195 case WM9081_INTERRUPT_STATUS:
196 case WM9081_INTERRUPT_STATUS_MASK:
197 case WM9081_INTERRUPT_POLARITY:
198 case WM9081_INTERRUPT_CONTROL:
199 case WM9081_DAC_DIGITAL_1:
200 case WM9081_DAC_DIGITAL_2:
205 case WM9081_WRITE_SEQUENCER_1:
206 case WM9081_WRITE_SEQUENCER_2:
207 case WM9081_MW_SLAVE_1:
234 static int wm9081_reset(struct regmap *map)
236 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
239 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
240 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
241 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
242 static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
243 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
244 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
245 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
246 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
248 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
249 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
251 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
253 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
254 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
255 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
257 static const char *drc_high_text[] = {
266 static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text);
268 static const char *drc_low_text[] = {
276 static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text);
278 static const char *drc_atk_text[] = {
293 static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text);
295 static const char *drc_dcy_text[] = {
307 static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text);
309 static const char *drc_qr_dcy_text[] = {
315 static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text);
317 static const char *dac_deemph_text[] = {
324 static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1,
327 static const char *speaker_mode_text[] = {
332 static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
335 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_value *ucontrol)
338 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
341 reg = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
342 if (reg & WM9081_SPK_MODE)
343 ucontrol->value.enumerated.item[0] = 1;
345 ucontrol->value.enumerated.item[0] = 0;
351 * Stop any attempts to change speaker mode while the speaker is enabled.
353 * We also have some special anti-pop controls dependent on speaker
354 * mode which must be changed along with the mode.
356 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
359 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
360 unsigned int reg_pwr = snd_soc_component_read(component, WM9081_POWER_MANAGEMENT);
361 unsigned int reg2 = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
363 /* Are we changing anything? */
364 if (ucontrol->value.enumerated.item[0] ==
365 ((reg2 & WM9081_SPK_MODE) != 0))
368 /* Don't try to change modes while enabled */
369 if (reg_pwr & WM9081_SPK_ENA)
372 if (ucontrol->value.enumerated.item[0]) {
374 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
375 reg2 |= WM9081_SPK_MODE;
378 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
379 reg2 &= ~WM9081_SPK_MODE;
382 snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2);
387 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
388 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
389 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
391 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
393 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
394 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
395 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
397 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
398 SOC_ENUM("DRC High Slope", drc_high),
399 SOC_ENUM("DRC Low Slope", drc_low),
400 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
401 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
402 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
403 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
404 SOC_ENUM("DRC Attack", drc_atk),
405 SOC_ENUM("DRC Decay", drc_dcy),
406 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
407 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
408 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
409 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
411 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
413 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
414 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
415 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
416 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
417 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
419 SOC_ENUM("DAC Deemphasis", dac_deemph),
420 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
423 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
424 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
425 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
426 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
427 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
428 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
431 static const struct snd_kcontrol_new mixer[] = {
432 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
433 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
434 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
445 /* The size in bits of the FLL divide multiplied by 10
446 * to allow rounding later */
447 #define FIXED_FLL_SIZE ((1 << 16) * 10)
456 { 64000, 128000, 3, 8 },
457 { 128000, 256000, 2, 4 },
458 { 256000, 1000000, 1, 2 },
459 { 1000000, 13500000, 0, 1 },
462 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
466 unsigned int K, Ndiv, Nmod, target;
470 /* Fref must be <=13.5MHz */
472 while ((Fref / div) > 13500000) {
476 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
481 fll_div->fll_clk_ref_div = div / 2;
483 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
485 /* Apply the division for our remaining calculations */
488 /* Fvco should be 90-100MHz; don't check the upper bound */
491 while (target < 90000000) {
495 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
500 fll_div->fll_outdiv = div;
502 pr_debug("Fvco=%dHz\n", target);
504 /* Find an appropriate FLL_FRATIO and factor it out of the target */
505 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
506 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
507 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
508 target /= fll_fratios[i].ratio;
512 if (i == ARRAY_SIZE(fll_fratios)) {
513 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
517 /* Now, calculate N.K */
518 Ndiv = target / Fref;
521 Nmod = target % Fref;
522 pr_debug("Nmod=%d\n", Nmod);
524 /* Calculate fractional part - scale up so we can round. */
525 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
529 K = Kpart & 0xFFFFFFFF;
534 /* Move down to proper range now rounding is done */
537 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
538 fll_div->n, fll_div->k,
539 fll_div->fll_fratio, fll_div->fll_outdiv,
540 fll_div->fll_clk_ref_div);
545 static int wm9081_set_fll(struct snd_soc_component *component, int fll_id,
546 unsigned int Fref, unsigned int Fout)
548 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
549 u16 reg1, reg4, reg5;
550 struct _fll_div fll_div;
555 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
558 /* Disable the FLL */
560 dev_dbg(component->dev, "FLL disabled\n");
561 wm9081->fll_fref = 0;
562 wm9081->fll_fout = 0;
567 ret = fll_factors(&fll_div, Fref, Fout);
571 reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5);
572 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
575 case WM9081_SYSCLK_FLL_MCLK:
580 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
584 /* Disable CLK_SYS while we reconfigure */
585 clk_sys_reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
586 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
587 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3,
588 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
590 /* Any FLL configuration change requires that the FLL be
592 reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1);
593 reg1 &= ~WM9081_FLL_ENA;
594 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
596 /* Apply the configuration */
598 reg1 |= WM9081_FLL_FRAC_MASK;
600 reg1 &= ~WM9081_FLL_FRAC_MASK;
601 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
603 snd_soc_component_write(component, WM9081_FLL_CONTROL_2,
604 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
605 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
606 snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
608 reg4 = snd_soc_component_read(component, WM9081_FLL_CONTROL_4);
609 reg4 &= ~WM9081_FLL_N_MASK;
610 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
611 snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4);
613 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
614 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
615 snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);
617 /* Set gain to the recommended value */
618 snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4,
619 WM9081_FLL_GAIN_MASK, 0);
622 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
624 /* Then bring CLK_SYS up again if it was disabled */
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
628 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
630 wm9081->fll_fref = Fref;
631 wm9081->fll_fout = Fout;
636 static int configure_clock(struct snd_soc_component *component)
638 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
639 int new_sysclk, i, target;
645 switch (wm9081->sysclk_source) {
646 case WM9081_SYSCLK_MCLK:
647 if (wm9081->mclk_rate > 12225000) {
649 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
651 wm9081->sysclk_rate = wm9081->mclk_rate;
653 wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0);
656 case WM9081_SYSCLK_FLL_MCLK:
657 /* If we have a sample rate calculate a CLK_SYS that
658 * gives us a suitable DAC configuration, plus BCLK.
659 * Ideally we would check to see if we can clock
660 * directly from MCLK and only use the FLL if this is
661 * not the case, though care must be taken with free
664 if (wm9081->master && wm9081->bclk) {
665 /* Make sure we can generate CLK_SYS and BCLK
666 * and that we've got 3MHz for optimal
668 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
669 target = wm9081->fs * clk_sys_rates[i].ratio;
671 if (target >= wm9081->bclk &&
676 if (i == ARRAY_SIZE(clk_sys_rates))
679 } else if (wm9081->fs) {
680 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
681 new_sysclk = clk_sys_rates[i].ratio
683 if (new_sysclk > 3000000)
687 if (i == ARRAY_SIZE(clk_sys_rates))
691 new_sysclk = 12288000;
694 ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK,
695 wm9081->mclk_rate, new_sysclk);
697 wm9081->sysclk_rate = new_sysclk;
699 /* Switch SYSCLK over to FLL */
702 wm9081->sysclk_rate = wm9081->mclk_rate;
710 reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_1);
712 reg |= WM9081_MCLKDIV2;
714 reg &= ~WM9081_MCLKDIV2;
715 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg);
717 reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
719 reg |= WM9081_CLK_SRC_SEL;
721 reg &= ~WM9081_CLK_SRC_SEL;
722 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg);
724 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
729 static int clk_sys_event(struct snd_soc_dapm_widget *w,
730 struct snd_kcontrol *kcontrol, int event)
732 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
733 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
735 /* This should be done on init() for bypass paths */
736 switch (wm9081->sysclk_source) {
737 case WM9081_SYSCLK_MCLK:
738 dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
740 case WM9081_SYSCLK_FLL_MCLK:
741 dev_dbg(component->dev, "Using %dHz MCLK with FLL\n",
745 dev_err(component->dev, "System clock not configured\n");
750 case SND_SOC_DAPM_PRE_PMU:
751 configure_clock(component);
754 case SND_SOC_DAPM_POST_PMD:
755 /* Disable the FLL if it's running */
756 wm9081_set_fll(component, 0, 0, 0);
763 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
764 SND_SOC_DAPM_INPUT("IN1"),
765 SND_SOC_DAPM_INPUT("IN2"),
767 SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
769 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
770 mixer, ARRAY_SIZE(mixer)),
772 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
774 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
775 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
777 SND_SOC_DAPM_OUTPUT("LINEOUT"),
778 SND_SOC_DAPM_OUTPUT("SPKN"),
779 SND_SOC_DAPM_OUTPUT("SPKP"),
781 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
783 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
784 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
785 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
789 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
790 { "DAC", NULL, "CLK_SYS" },
791 { "DAC", NULL, "CLK_DSP" },
792 { "DAC", NULL, "AIF" },
794 { "Mixer", "IN1 Switch", "IN1" },
795 { "Mixer", "IN2 Switch", "IN2" },
796 { "Mixer", "Playback Switch", "DAC" },
798 { "LINEOUT PGA", NULL, "Mixer" },
799 { "LINEOUT PGA", NULL, "TOCLK" },
800 { "LINEOUT PGA", NULL, "CLK_SYS" },
802 { "LINEOUT", NULL, "LINEOUT PGA" },
804 { "Speaker PGA", NULL, "Mixer" },
805 { "Speaker PGA", NULL, "TOCLK" },
806 { "Speaker PGA", NULL, "CLK_SYS" },
808 { "Speaker", NULL, "Speaker PGA" },
809 { "Speaker", NULL, "TSENSE" },
811 { "SPKN", NULL, "Speaker" },
812 { "SPKP", NULL, "Speaker" },
815 static int wm9081_set_bias_level(struct snd_soc_component *component,
816 enum snd_soc_bias_level level)
818 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
821 case SND_SOC_BIAS_ON:
824 case SND_SOC_BIAS_PREPARE:
826 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
827 WM9081_VMID_SEL_MASK, 0x2);
829 /* Normal bias current */
830 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
831 WM9081_STBY_BIAS_ENA, 0);
834 case SND_SOC_BIAS_STANDBY:
835 /* Initial cold start */
836 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
837 regcache_cache_only(wm9081->regmap, false);
838 regcache_sync(wm9081->regmap);
840 /* Disable LINEOUT discharge */
841 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
842 WM9081_LINEOUT_DISCH, 0);
844 /* Select startup bias source */
845 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
846 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
847 WM9081_BIAS_SRC | WM9081_BIAS_ENA);
849 /* VMID 2*4k; Soft VMID ramp enable */
850 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
852 WM9081_VMID_SEL_MASK,
853 WM9081_VMID_RAMP | 0x6);
857 /* Normal bias enable & soft start off */
858 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
859 WM9081_VMID_RAMP, 0);
861 /* Standard bias source */
862 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
867 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
868 WM9081_VMID_SEL_MASK, 0x04);
870 /* Standby bias current on */
871 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
872 WM9081_STBY_BIAS_ENA,
873 WM9081_STBY_BIAS_ENA);
876 case SND_SOC_BIAS_OFF:
877 /* Startup bias source and disable bias */
878 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
879 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
882 /* Disable VMID with soft ramping */
883 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
884 WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
887 /* Actively discharge LINEOUT */
888 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
889 WM9081_LINEOUT_DISCH,
890 WM9081_LINEOUT_DISCH);
892 regcache_cache_only(wm9081->regmap, true);
899 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
902 struct snd_soc_component *component = dai->component;
903 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
904 unsigned int aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
906 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
907 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
909 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
910 case SND_SOC_DAIFMT_CBS_CFS:
913 case SND_SOC_DAIFMT_CBS_CFM:
914 aif2 |= WM9081_LRCLK_DIR;
917 case SND_SOC_DAIFMT_CBM_CFS:
918 aif2 |= WM9081_BCLK_DIR;
921 case SND_SOC_DAIFMT_CBM_CFM:
922 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
930 case SND_SOC_DAIFMT_DSP_B:
931 aif2 |= WM9081_AIF_LRCLK_INV;
933 case SND_SOC_DAIFMT_DSP_A:
936 case SND_SOC_DAIFMT_I2S:
939 case SND_SOC_DAIFMT_RIGHT_J:
941 case SND_SOC_DAIFMT_LEFT_J:
948 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
949 case SND_SOC_DAIFMT_DSP_A:
950 case SND_SOC_DAIFMT_DSP_B:
951 /* frame inversion not valid for DSP modes */
952 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
953 case SND_SOC_DAIFMT_NB_NF:
955 case SND_SOC_DAIFMT_IB_NF:
956 aif2 |= WM9081_AIF_BCLK_INV;
963 case SND_SOC_DAIFMT_I2S:
964 case SND_SOC_DAIFMT_RIGHT_J:
965 case SND_SOC_DAIFMT_LEFT_J:
966 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
967 case SND_SOC_DAIFMT_NB_NF:
969 case SND_SOC_DAIFMT_IB_IF:
970 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
972 case SND_SOC_DAIFMT_IB_NF:
973 aif2 |= WM9081_AIF_BCLK_INV;
975 case SND_SOC_DAIFMT_NB_IF:
976 aif2 |= WM9081_AIF_LRCLK_INV;
986 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
991 static int wm9081_hw_params(struct snd_pcm_substream *substream,
992 struct snd_pcm_hw_params *params,
993 struct snd_soc_dai *dai)
995 struct snd_soc_component *component = dai->component;
996 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
997 int ret, i, best, best_val, cur_val;
998 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1000 clk_ctrl2 = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_2);
1001 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1003 aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1005 aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
1006 aif2 &= ~WM9081_AIF_WL_MASK;
1008 aif3 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_3);
1009 aif3 &= ~WM9081_BCLK_DIV_MASK;
1011 aif4 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_4);
1012 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1014 wm9081->fs = params_rate(params);
1016 if (wm9081->tdm_width) {
1017 /* If TDM is set up then that fixes our BCLK. */
1018 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1019 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1021 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1023 /* Otherwise work out a BCLK from the sample size */
1024 wm9081->bclk = 2 * wm9081->fs;
1026 switch (params_width(params)) {
1047 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1049 ret = configure_clock(component);
1053 /* Select nearest CLK_SYS_RATE */
1055 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1057 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1058 cur_val = abs((wm9081->sysclk_rate /
1059 clk_sys_rates[i].ratio) - wm9081->fs);
1060 if (cur_val < best_val) {
1065 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1066 clk_sys_rates[best].ratio);
1067 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1068 << WM9081_CLK_SYS_RATE_SHIFT);
1072 best_val = abs(wm9081->fs - sample_rates[0].rate);
1073 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1075 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1076 if (cur_val < best_val) {
1081 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1082 sample_rates[best].rate);
1083 clk_ctrl2 |= (sample_rates[best].sample_rate
1084 << WM9081_SAMPLE_RATE_SHIFT);
1089 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1090 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1092 if (cur_val < 0) /* Table is sorted */
1094 if (cur_val < best_val) {
1099 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1100 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1101 bclk_divs[best].div, wm9081->bclk);
1102 aif3 |= bclk_divs[best].bclk_div;
1104 /* LRCLK is a simple fraction of BCLK */
1105 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1106 aif4 |= wm9081->bclk / wm9081->fs;
1108 /* Apply a ReTune Mobile configuration if it's in use */
1109 if (wm9081->pdata.num_retune_configs) {
1110 struct wm9081_pdata *pdata = &wm9081->pdata;
1111 struct wm9081_retune_mobile_setting *s;
1115 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1116 for (i = 0; i < pdata->num_retune_configs; i++) {
1117 cur_val = abs(pdata->retune_configs[i].rate -
1119 if (cur_val < best_val) {
1124 s = &pdata->retune_configs[best];
1126 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1129 /* If the EQ is enabled then disable it while we write out */
1130 eq1 = snd_soc_component_read(component, WM9081_EQ_1) & WM9081_EQ_ENA;
1131 if (eq1 & WM9081_EQ_ENA)
1132 snd_soc_component_write(component, WM9081_EQ_1, 0);
1134 /* Write out the other values */
1135 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1136 snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]);
1138 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1139 snd_soc_component_write(component, WM9081_EQ_1, eq1);
1142 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1143 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
1144 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3);
1145 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4);
1150 static int wm9081_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1152 struct snd_soc_component *component = codec_dai->component;
1155 reg = snd_soc_component_read(component, WM9081_DAC_DIGITAL_2);
1158 reg |= WM9081_DAC_MUTE;
1160 reg &= ~WM9081_DAC_MUTE;
1162 snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg);
1167 static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id,
1168 int source, unsigned int freq, int dir)
1170 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1173 case WM9081_SYSCLK_MCLK:
1174 case WM9081_SYSCLK_FLL_MCLK:
1175 wm9081->sysclk_source = clk_id;
1176 wm9081->mclk_rate = freq;
1186 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1187 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1189 struct snd_soc_component *component = dai->component;
1190 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1191 unsigned int aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1193 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1195 if (slots < 0 || slots > 4)
1198 wm9081->tdm_width = slot_width;
1203 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1221 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1);
1226 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1228 #define WM9081_FORMATS \
1229 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1230 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1232 static const struct snd_soc_dai_ops wm9081_dai_ops = {
1233 .hw_params = wm9081_hw_params,
1234 .set_fmt = wm9081_set_dai_fmt,
1235 .mute_stream = wm9081_mute,
1236 .set_tdm_slot = wm9081_set_tdm_slot,
1237 .no_capture_mute = 1,
1240 /* We report two channels because the CODEC processes a stereo signal, even
1241 * though it is only capable of handling a mono output.
1243 static struct snd_soc_dai_driver wm9081_dai = {
1244 .name = "wm9081-hifi",
1246 .stream_name = "AIF",
1249 .rates = WM9081_RATES,
1250 .formats = WM9081_FORMATS,
1252 .ops = &wm9081_dai_ops,
1255 static int wm9081_probe(struct snd_soc_component *component)
1257 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1259 /* Enable zero cross by default */
1260 snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT,
1261 WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1262 snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA,
1263 WM9081_SPKPGAZC, WM9081_SPKPGAZC);
1265 if (!wm9081->pdata.num_retune_configs) {
1266 dev_dbg(component->dev,
1267 "No ReTune Mobile data, using normal EQ\n");
1268 snd_soc_add_component_controls(component, wm9081_eq_controls,
1269 ARRAY_SIZE(wm9081_eq_controls));
1275 static const struct snd_soc_component_driver soc_component_dev_wm9081 = {
1276 .probe = wm9081_probe,
1277 .set_sysclk = wm9081_set_sysclk,
1278 .set_bias_level = wm9081_set_bias_level,
1279 .controls = wm9081_snd_controls,
1280 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
1281 .dapm_widgets = wm9081_dapm_widgets,
1282 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1283 .dapm_routes = wm9081_audio_paths,
1284 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
1285 .use_pmdown_time = 1,
1287 .non_legacy_dai_naming = 1,
1290 static const struct regmap_config wm9081_regmap = {
1294 .max_register = WM9081_MAX_REGISTER,
1295 .reg_defaults = wm9081_reg,
1296 .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1297 .volatile_reg = wm9081_volatile_register,
1298 .readable_reg = wm9081_readable_register,
1299 .cache_type = REGCACHE_RBTREE,
1302 static int wm9081_i2c_probe(struct i2c_client *i2c)
1304 struct wm9081_priv *wm9081;
1308 wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
1313 i2c_set_clientdata(i2c, wm9081);
1315 wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap);
1316 if (IS_ERR(wm9081->regmap)) {
1317 ret = PTR_ERR(wm9081->regmap);
1318 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1322 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, ®);
1324 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1327 if (reg != 0x9081) {
1328 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1332 ret = wm9081_reset(wm9081->regmap);
1334 dev_err(&i2c->dev, "Failed to issue reset\n");
1338 if (dev_get_platdata(&i2c->dev))
1339 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1340 sizeof(wm9081->pdata));
1343 if (wm9081->pdata.irq_high)
1344 reg |= WM9081_IRQ_POL;
1345 if (!wm9081->pdata.irq_cmos)
1346 reg |= WM9081_IRQ_OP_CTRL;
1347 regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
1348 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1350 regcache_cache_only(wm9081->regmap, true);
1352 ret = devm_snd_soc_register_component(&i2c->dev,
1353 &soc_component_dev_wm9081, &wm9081_dai, 1);
1360 static int wm9081_i2c_remove(struct i2c_client *client)
1365 static const struct i2c_device_id wm9081_i2c_id[] = {
1369 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1371 static struct i2c_driver wm9081_i2c_driver = {
1375 .probe_new = wm9081_i2c_probe,
1376 .remove = wm9081_i2c_remove,
1377 .id_table = wm9081_i2c_id,
1380 module_i2c_driver(wm9081_i2c_driver);
1382 MODULE_DESCRIPTION("ASoC WM9081 driver");
1383 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1384 MODULE_LICENSE("GPL");