2 * wm8995.c -- WM8995 ALSA SoC Audio driver
4 * Copyright 2010 Wolfson Microelectronics plc
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/spi/spi.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #define WM8995_NUM_SUPPLIES 8
36 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = {
47 static const struct reg_default wm8995_reg_defaults[] = {
381 struct regmap *regmap;
385 struct fll_config fll[2], fll_suspend[2];
386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES];
387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES];
388 struct snd_soc_component *component;
392 * We can't use the same notifier block for more than one supply and
393 * there's no way I can see to get from a callback to the caller
394 * except container_of().
396 #define WM8995_REGULATOR_EVENT(n) \
397 static int wm8995_regulator_event_##n(struct notifier_block *nb, \
398 unsigned long event, void *data) \
400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \
402 if (event & REGULATOR_EVENT_DISABLE) { \
403 regcache_mark_dirty(wm8995->regmap); \
408 WM8995_REGULATOR_EVENT(0)
409 WM8995_REGULATOR_EVENT(1)
410 WM8995_REGULATOR_EVENT(2)
411 WM8995_REGULATOR_EVENT(3)
412 WM8995_REGULATOR_EVENT(4)
413 WM8995_REGULATOR_EVENT(5)
414 WM8995_REGULATOR_EVENT(6)
415 WM8995_REGULATOR_EVENT(7)
417 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
418 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
419 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
420 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
422 static const char *in1l_text[] = {
423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
426 static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
429 static const char *in1r_text[] = {
430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
433 static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
436 static const char *dmic_src_text[] = {
437 "DMICDAT1", "DMICDAT2", "DMICDAT3"
440 static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
442 static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
445 static const struct snd_kcontrol_new wm8995_snd_controls[] = {
446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
467 4, 3, 0, in1l_boost_tlv),
469 SOC_ENUM("IN1L Mode", in1l_enum),
470 SOC_ENUM("IN1R Mode", in1r_enum),
472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
476 24, 0, sidetone_tlv),
477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
478 24, 0, sidetone_tlv),
480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
488 static void wm8995_update_class_w(struct snd_soc_component *component)
491 int source = 0; /* GCC flow analysis can't track enable */
494 /* We also need the same setting for L/R and only one path */
495 reg = snd_soc_component_read32(component, WM8995_DAC1_LEFT_MIXER_ROUTING);
497 case WM8995_AIF2DACL_TO_DAC1L:
498 dev_dbg(component->dev, "Class W source AIF2DAC\n");
499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
501 case WM8995_AIF1DAC2L_TO_DAC1L:
502 dev_dbg(component->dev, "Class W source AIF1DAC2\n");
503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
505 case WM8995_AIF1DAC1L_TO_DAC1L:
506 dev_dbg(component->dev, "Class W source AIF1DAC1\n");
507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
510 dev_dbg(component->dev, "DAC mixer setting: %x\n", reg);
515 reg_r = snd_soc_component_read32(component, WM8995_DAC1_RIGHT_MIXER_ROUTING);
517 dev_dbg(component->dev, "Left and right DAC mixers different\n");
522 dev_dbg(component->dev, "Class W enabled\n");
523 snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
524 WM8995_CP_DYN_PWR_MASK |
525 WM8995_CP_DYN_SRC_SEL_MASK,
526 source | WM8995_CP_DYN_PWR);
528 dev_dbg(component->dev, "Class W disabled\n");
529 snd_soc_component_update_bits(component, WM8995_CLASS_W_1,
530 WM8995_CP_DYN_PWR_MASK, 0);
534 static int check_clk_sys(struct snd_soc_dapm_widget *source,
535 struct snd_soc_dapm_widget *sink)
537 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
541 reg = snd_soc_component_read32(component, WM8995_CLOCKING_1);
542 /* Check what we're currently using for CLK_SYS */
543 if (reg & WM8995_SYSCLK_SRC)
547 return !strcmp(source->name, clk);
550 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
551 struct snd_ctl_elem_value *ucontrol)
553 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
556 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
557 wm8995_update_class_w(component);
561 static int hp_supply_event(struct snd_soc_dapm_widget *w,
562 struct snd_kcontrol *kcontrol, int event)
564 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
567 case SND_SOC_DAPM_PRE_PMU:
568 /* Enable the headphone amp */
569 snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
570 WM8995_HPOUT1L_ENA_MASK |
571 WM8995_HPOUT1R_ENA_MASK,
575 /* Enable the second stage */
576 snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
577 WM8995_HPOUT1L_DLY_MASK |
578 WM8995_HPOUT1R_DLY_MASK,
582 case SND_SOC_DAPM_PRE_PMD:
583 snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
584 WM8995_CP_ENA_MASK, 0);
591 static void dc_servo_cmd(struct snd_soc_component *component,
592 unsigned int reg, unsigned int val, unsigned int mask)
596 dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
597 __func__, reg, val, mask);
599 snd_soc_component_write(component, reg, val);
602 val = snd_soc_component_read32(component, WM8995_DC_SERVO_READBACK_0);
603 if ((val & mask) == mask)
607 dev_err(component->dev, "Timed out waiting for DC Servo\n");
610 static int hp_event(struct snd_soc_dapm_widget *w,
611 struct snd_kcontrol *kcontrol, int event)
613 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
616 reg = snd_soc_component_read32(component, WM8995_ANALOGUE_HP_1);
619 case SND_SOC_DAPM_POST_PMU:
620 snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1,
621 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
625 snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
626 WM8995_HPOUT1L_ENA_MASK |
627 WM8995_HPOUT1R_ENA_MASK,
628 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
632 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
633 snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
635 snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
636 WM8995_DCS_ENA_CHAN_1);
638 dc_servo_cmd(component, WM8995_DC_SERVO_2,
639 WM8995_DCS_TRIG_STARTUP_0 |
640 WM8995_DCS_TRIG_STARTUP_1,
641 WM8995_DCS_TRIG_DAC_WR_0 |
642 WM8995_DCS_TRIG_DAC_WR_1);
644 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
645 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
646 snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg);
649 case SND_SOC_DAPM_PRE_PMD:
650 snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
651 WM8995_HPOUT1L_OUTP_MASK |
652 WM8995_HPOUT1R_OUTP_MASK |
653 WM8995_HPOUT1L_RMV_SHORT_MASK |
654 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
656 snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1,
657 WM8995_HPOUT1L_DLY_MASK |
658 WM8995_HPOUT1R_DLY_MASK, 0);
660 snd_soc_component_write(component, WM8995_DC_SERVO_1, 0);
662 snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
663 WM8995_HPOUT1L_ENA_MASK |
664 WM8995_HPOUT1R_ENA_MASK,
672 static int configure_aif_clock(struct snd_soc_component *component, int aif)
674 struct wm8995_priv *wm8995;
679 wm8995 = snd_soc_component_get_drvdata(component);
686 switch (wm8995->sysclk[aif]) {
687 case WM8995_SYSCLK_MCLK1:
688 rate = wm8995->mclk[0];
690 case WM8995_SYSCLK_MCLK2:
692 rate = wm8995->mclk[1];
694 case WM8995_SYSCLK_FLL1:
696 rate = wm8995->fll[0].out;
698 case WM8995_SYSCLK_FLL2:
700 rate = wm8995->fll[1].out;
706 if (rate >= 13500000) {
708 reg1 |= WM8995_AIF1CLK_DIV;
710 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
714 wm8995->aifclk[aif] = rate;
716 snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset,
717 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
722 static int configure_clock(struct snd_soc_component *component)
724 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
725 struct wm8995_priv *wm8995;
728 wm8995 = snd_soc_component_get_drvdata(component);
730 /* Bring up the AIF clocks first */
731 configure_aif_clock(component, 0);
732 configure_aif_clock(component, 1);
735 * Then switch CLK_SYS over to the higher of them; a change
736 * can only happen as a result of a clocking change which can
737 * only be made outside of DAPM so we can safely redo the
741 /* If they're equal it doesn't matter which is used */
742 if (wm8995->aifclk[0] == wm8995->aifclk[1])
745 if (wm8995->aifclk[0] < wm8995->aifclk[1])
746 new = WM8995_SYSCLK_SRC;
750 change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1,
751 WM8995_SYSCLK_SRC_MASK, new);
755 snd_soc_dapm_sync(dapm);
760 static int clk_sys_event(struct snd_soc_dapm_widget *w,
761 struct snd_kcontrol *kcontrol, int event)
763 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
766 case SND_SOC_DAPM_PRE_PMU:
767 return configure_clock(component);
769 case SND_SOC_DAPM_POST_PMD:
770 configure_clock(component);
777 static const char *sidetone_text[] = {
778 "ADC/DMIC1", "DMIC2",
781 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text);
783 static const struct snd_kcontrol_new sidetone1_mux =
784 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
786 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text);
788 static const struct snd_kcontrol_new sidetone2_mux =
789 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
791 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
792 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
794 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
798 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
799 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
801 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
805 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
806 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
808 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
812 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
813 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
815 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
819 static const struct snd_kcontrol_new dac1l_mix[] = {
820 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
822 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
824 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
826 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
828 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
832 static const struct snd_kcontrol_new dac1r_mix[] = {
833 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
835 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
837 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
839 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
841 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
845 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
846 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
848 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
850 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
852 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
854 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
858 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
859 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
861 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
863 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
865 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
867 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
871 static const struct snd_kcontrol_new in1l_pga =
872 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
874 static const struct snd_kcontrol_new in1r_pga =
875 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
877 static const char *adc_mux_text[] = {
882 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
884 static const struct snd_kcontrol_new adcl_mux =
885 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
887 static const struct snd_kcontrol_new adcr_mux =
888 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
890 static const char *spk_src_text[] = {
891 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
894 static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
896 static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
898 static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
900 static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
903 static const struct snd_kcontrol_new spk1l_mux =
904 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
905 static const struct snd_kcontrol_new spk1r_mux =
906 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
907 static const struct snd_kcontrol_new spk2l_mux =
908 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
909 static const struct snd_kcontrol_new spk2r_mux =
910 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
912 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
913 SND_SOC_DAPM_INPUT("DMIC1DAT"),
914 SND_SOC_DAPM_INPUT("DMIC2DAT"),
916 SND_SOC_DAPM_INPUT("IN1L"),
917 SND_SOC_DAPM_INPUT("IN1R"),
919 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
921 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
924 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0,
926 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0,
929 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
930 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
931 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
932 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
933 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
934 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
935 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
937 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
938 WM8995_POWER_MANAGEMENT_3, 9, 0),
939 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
940 WM8995_POWER_MANAGEMENT_3, 8, 0),
941 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
943 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
944 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
945 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
946 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
948 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
949 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
951 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
952 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
953 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
954 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
956 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
957 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
959 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
960 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
961 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
962 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
963 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
964 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
965 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
966 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
968 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
970 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
972 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
975 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
977 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
980 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
981 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
982 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
983 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
985 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
986 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
987 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
988 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
990 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
991 ARRAY_SIZE(dac1l_mix)),
992 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
993 ARRAY_SIZE(dac1r_mix)),
995 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
996 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
998 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
999 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1001 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
1002 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1004 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
1006 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
1008 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
1010 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
1013 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
1015 SND_SOC_DAPM_OUTPUT("HP1L"),
1016 SND_SOC_DAPM_OUTPUT("HP1R"),
1017 SND_SOC_DAPM_OUTPUT("SPK1L"),
1018 SND_SOC_DAPM_OUTPUT("SPK1R"),
1019 SND_SOC_DAPM_OUTPUT("SPK2L"),
1020 SND_SOC_DAPM_OUTPUT("SPK2R")
1023 static const struct snd_soc_dapm_route wm8995_intercon[] = {
1024 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1025 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1027 { "DSP1CLK", NULL, "CLK_SYS" },
1028 { "DSP2CLK", NULL, "CLK_SYS" },
1029 { "SYSDSPCLK", NULL, "CLK_SYS" },
1031 { "AIF1ADC1L", NULL, "AIF1CLK" },
1032 { "AIF1ADC1L", NULL, "DSP1CLK" },
1033 { "AIF1ADC1R", NULL, "AIF1CLK" },
1034 { "AIF1ADC1R", NULL, "DSP1CLK" },
1035 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
1037 { "AIF1ADC2L", NULL, "AIF1CLK" },
1038 { "AIF1ADC2L", NULL, "DSP1CLK" },
1039 { "AIF1ADC2R", NULL, "AIF1CLK" },
1040 { "AIF1ADC2R", NULL, "DSP1CLK" },
1041 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
1043 { "DMIC1L", NULL, "DMIC1DAT" },
1044 { "DMIC1L", NULL, "CLK_SYS" },
1045 { "DMIC1R", NULL, "DMIC1DAT" },
1046 { "DMIC1R", NULL, "CLK_SYS" },
1047 { "DMIC2L", NULL, "DMIC2DAT" },
1048 { "DMIC2L", NULL, "CLK_SYS" },
1049 { "DMIC2R", NULL, "DMIC2DAT" },
1050 { "DMIC2R", NULL, "CLK_SYS" },
1052 { "ADCL", NULL, "AIF1CLK" },
1053 { "ADCL", NULL, "DSP1CLK" },
1054 { "ADCL", NULL, "SYSDSPCLK" },
1056 { "ADCR", NULL, "AIF1CLK" },
1057 { "ADCR", NULL, "DSP1CLK" },
1058 { "ADCR", NULL, "SYSDSPCLK" },
1060 { "IN1L PGA", "IN1L Switch", "IN1L" },
1061 { "IN1R PGA", "IN1R Switch", "IN1R" },
1062 { "IN1L PGA", NULL, "LDO2" },
1063 { "IN1R PGA", NULL, "LDO2" },
1065 { "ADCL", NULL, "IN1L PGA" },
1066 { "ADCR", NULL, "IN1R PGA" },
1068 { "ADCL Mux", "ADC", "ADCL" },
1069 { "ADCL Mux", "DMIC", "DMIC1L" },
1070 { "ADCR Mux", "ADC", "ADCR" },
1071 { "ADCR Mux", "DMIC", "DMIC1R" },
1074 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1075 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1077 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1078 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1080 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1081 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1083 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1084 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1087 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
1088 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
1089 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
1090 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
1092 { "AIF1DAC1L", NULL, "AIF1CLK" },
1093 { "AIF1DAC1L", NULL, "DSP1CLK" },
1094 { "AIF1DAC1R", NULL, "AIF1CLK" },
1095 { "AIF1DAC1R", NULL, "DSP1CLK" },
1096 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
1098 { "AIF1DAC2L", NULL, "AIF1CLK" },
1099 { "AIF1DAC2L", NULL, "DSP1CLK" },
1100 { "AIF1DAC2R", NULL, "AIF1CLK" },
1101 { "AIF1DAC2R", NULL, "DSP1CLK" },
1102 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
1104 { "DAC1L", NULL, "AIF1CLK" },
1105 { "DAC1L", NULL, "DSP1CLK" },
1106 { "DAC1L", NULL, "SYSDSPCLK" },
1108 { "DAC1R", NULL, "AIF1CLK" },
1109 { "DAC1R", NULL, "DSP1CLK" },
1110 { "DAC1R", NULL, "SYSDSPCLK" },
1112 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
1113 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
1114 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
1115 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
1118 { "DAC1L", NULL, "DAC1L Mixer" },
1119 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1120 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1121 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1122 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1124 { "DAC1R", NULL, "DAC1R Mixer" },
1125 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1126 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1127 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1128 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1130 /* DAC2/AIF2 outputs */
1131 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1132 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1133 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1135 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1136 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1137 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1140 { "Headphone PGA", NULL, "DAC1L" },
1141 { "Headphone PGA", NULL, "DAC1R" },
1143 { "Headphone PGA", NULL, "DAC2L" },
1144 { "Headphone PGA", NULL, "DAC2R" },
1146 { "Headphone PGA", NULL, "Headphone Supply" },
1147 { "Headphone PGA", NULL, "CLK_SYS" },
1148 { "Headphone PGA", NULL, "LDO2" },
1150 { "HP1L", NULL, "Headphone PGA" },
1151 { "HP1R", NULL, "Headphone PGA" },
1153 { "SPK1L Driver", "DAC1L", "DAC1L" },
1154 { "SPK1L Driver", "DAC1R", "DAC1R" },
1155 { "SPK1L Driver", "DAC2L", "DAC2L" },
1156 { "SPK1L Driver", "DAC2R", "DAC2R" },
1157 { "SPK1L Driver", NULL, "CLK_SYS" },
1159 { "SPK1R Driver", "DAC1L", "DAC1L" },
1160 { "SPK1R Driver", "DAC1R", "DAC1R" },
1161 { "SPK1R Driver", "DAC2L", "DAC2L" },
1162 { "SPK1R Driver", "DAC2R", "DAC2R" },
1163 { "SPK1R Driver", NULL, "CLK_SYS" },
1165 { "SPK2L Driver", "DAC1L", "DAC1L" },
1166 { "SPK2L Driver", "DAC1R", "DAC1R" },
1167 { "SPK2L Driver", "DAC2L", "DAC2L" },
1168 { "SPK2L Driver", "DAC2R", "DAC2R" },
1169 { "SPK2L Driver", NULL, "CLK_SYS" },
1171 { "SPK2R Driver", "DAC1L", "DAC1L" },
1172 { "SPK2R Driver", "DAC1R", "DAC1R" },
1173 { "SPK2R Driver", "DAC2L", "DAC2L" },
1174 { "SPK2R Driver", "DAC2R", "DAC2R" },
1175 { "SPK2R Driver", NULL, "CLK_SYS" },
1177 { "SPK1L", NULL, "SPK1L Driver" },
1178 { "SPK1R", NULL, "SPK1R Driver" },
1179 { "SPK2L", NULL, "SPK2L Driver" },
1180 { "SPK2R", NULL, "SPK2R Driver" }
1183 static bool wm8995_readable(struct device *dev, unsigned int reg)
1186 case WM8995_SOFTWARE_RESET:
1187 case WM8995_POWER_MANAGEMENT_1:
1188 case WM8995_POWER_MANAGEMENT_2:
1189 case WM8995_POWER_MANAGEMENT_3:
1190 case WM8995_POWER_MANAGEMENT_4:
1191 case WM8995_POWER_MANAGEMENT_5:
1192 case WM8995_LEFT_LINE_INPUT_1_VOLUME:
1193 case WM8995_RIGHT_LINE_INPUT_1_VOLUME:
1194 case WM8995_LEFT_LINE_INPUT_CONTROL:
1195 case WM8995_DAC1_LEFT_VOLUME:
1196 case WM8995_DAC1_RIGHT_VOLUME:
1197 case WM8995_DAC2_LEFT_VOLUME:
1198 case WM8995_DAC2_RIGHT_VOLUME:
1199 case WM8995_OUTPUT_VOLUME_ZC_1:
1200 case WM8995_MICBIAS_1:
1201 case WM8995_MICBIAS_2:
1204 case WM8995_ACCESSORY_DETECT_MODE1:
1205 case WM8995_ACCESSORY_DETECT_MODE2:
1206 case WM8995_HEADPHONE_DETECT1:
1207 case WM8995_HEADPHONE_DETECT2:
1208 case WM8995_MIC_DETECT_1:
1209 case WM8995_MIC_DETECT_2:
1210 case WM8995_CHARGE_PUMP_1:
1211 case WM8995_CLASS_W_1:
1212 case WM8995_DC_SERVO_1:
1213 case WM8995_DC_SERVO_2:
1214 case WM8995_DC_SERVO_3:
1215 case WM8995_DC_SERVO_5:
1216 case WM8995_DC_SERVO_6:
1217 case WM8995_DC_SERVO_7:
1218 case WM8995_DC_SERVO_READBACK_0:
1219 case WM8995_ANALOGUE_HP_1:
1220 case WM8995_ANALOGUE_HP_2:
1221 case WM8995_CHIP_REVISION:
1222 case WM8995_CONTROL_INTERFACE_1:
1223 case WM8995_CONTROL_INTERFACE_2:
1224 case WM8995_WRITE_SEQUENCER_CTRL_1:
1225 case WM8995_WRITE_SEQUENCER_CTRL_2:
1226 case WM8995_AIF1_CLOCKING_1:
1227 case WM8995_AIF1_CLOCKING_2:
1228 case WM8995_AIF2_CLOCKING_1:
1229 case WM8995_AIF2_CLOCKING_2:
1230 case WM8995_CLOCKING_1:
1231 case WM8995_CLOCKING_2:
1232 case WM8995_AIF1_RATE:
1233 case WM8995_AIF2_RATE:
1234 case WM8995_RATE_STATUS:
1235 case WM8995_FLL1_CONTROL_1:
1236 case WM8995_FLL1_CONTROL_2:
1237 case WM8995_FLL1_CONTROL_3:
1238 case WM8995_FLL1_CONTROL_4:
1239 case WM8995_FLL1_CONTROL_5:
1240 case WM8995_FLL2_CONTROL_1:
1241 case WM8995_FLL2_CONTROL_2:
1242 case WM8995_FLL2_CONTROL_3:
1243 case WM8995_FLL2_CONTROL_4:
1244 case WM8995_FLL2_CONTROL_5:
1245 case WM8995_AIF1_CONTROL_1:
1246 case WM8995_AIF1_CONTROL_2:
1247 case WM8995_AIF1_MASTER_SLAVE:
1248 case WM8995_AIF1_BCLK:
1249 case WM8995_AIF1ADC_LRCLK:
1250 case WM8995_AIF1DAC_LRCLK:
1251 case WM8995_AIF1DAC_DATA:
1252 case WM8995_AIF1ADC_DATA:
1253 case WM8995_AIF2_CONTROL_1:
1254 case WM8995_AIF2_CONTROL_2:
1255 case WM8995_AIF2_MASTER_SLAVE:
1256 case WM8995_AIF2_BCLK:
1257 case WM8995_AIF2ADC_LRCLK:
1258 case WM8995_AIF2DAC_LRCLK:
1259 case WM8995_AIF2DAC_DATA:
1260 case WM8995_AIF2ADC_DATA:
1261 case WM8995_AIF1_ADC1_LEFT_VOLUME:
1262 case WM8995_AIF1_ADC1_RIGHT_VOLUME:
1263 case WM8995_AIF1_DAC1_LEFT_VOLUME:
1264 case WM8995_AIF1_DAC1_RIGHT_VOLUME:
1265 case WM8995_AIF1_ADC2_LEFT_VOLUME:
1266 case WM8995_AIF1_ADC2_RIGHT_VOLUME:
1267 case WM8995_AIF1_DAC2_LEFT_VOLUME:
1268 case WM8995_AIF1_DAC2_RIGHT_VOLUME:
1269 case WM8995_AIF1_ADC1_FILTERS:
1270 case WM8995_AIF1_ADC2_FILTERS:
1271 case WM8995_AIF1_DAC1_FILTERS_1:
1272 case WM8995_AIF1_DAC1_FILTERS_2:
1273 case WM8995_AIF1_DAC2_FILTERS_1:
1274 case WM8995_AIF1_DAC2_FILTERS_2:
1275 case WM8995_AIF1_DRC1_1:
1276 case WM8995_AIF1_DRC1_2:
1277 case WM8995_AIF1_DRC1_3:
1278 case WM8995_AIF1_DRC1_4:
1279 case WM8995_AIF1_DRC1_5:
1280 case WM8995_AIF1_DRC2_1:
1281 case WM8995_AIF1_DRC2_2:
1282 case WM8995_AIF1_DRC2_3:
1283 case WM8995_AIF1_DRC2_4:
1284 case WM8995_AIF1_DRC2_5:
1285 case WM8995_AIF1_DAC1_EQ_GAINS_1:
1286 case WM8995_AIF1_DAC1_EQ_GAINS_2:
1287 case WM8995_AIF1_DAC1_EQ_BAND_1_A:
1288 case WM8995_AIF1_DAC1_EQ_BAND_1_B:
1289 case WM8995_AIF1_DAC1_EQ_BAND_1_PG:
1290 case WM8995_AIF1_DAC1_EQ_BAND_2_A:
1291 case WM8995_AIF1_DAC1_EQ_BAND_2_B:
1292 case WM8995_AIF1_DAC1_EQ_BAND_2_C:
1293 case WM8995_AIF1_DAC1_EQ_BAND_2_PG:
1294 case WM8995_AIF1_DAC1_EQ_BAND_3_A:
1295 case WM8995_AIF1_DAC1_EQ_BAND_3_B:
1296 case WM8995_AIF1_DAC1_EQ_BAND_3_C:
1297 case WM8995_AIF1_DAC1_EQ_BAND_3_PG:
1298 case WM8995_AIF1_DAC1_EQ_BAND_4_A:
1299 case WM8995_AIF1_DAC1_EQ_BAND_4_B:
1300 case WM8995_AIF1_DAC1_EQ_BAND_4_C:
1301 case WM8995_AIF1_DAC1_EQ_BAND_4_PG:
1302 case WM8995_AIF1_DAC1_EQ_BAND_5_A:
1303 case WM8995_AIF1_DAC1_EQ_BAND_5_B:
1304 case WM8995_AIF1_DAC1_EQ_BAND_5_PG:
1305 case WM8995_AIF1_DAC2_EQ_GAINS_1:
1306 case WM8995_AIF1_DAC2_EQ_GAINS_2:
1307 case WM8995_AIF1_DAC2_EQ_BAND_1_A:
1308 case WM8995_AIF1_DAC2_EQ_BAND_1_B:
1309 case WM8995_AIF1_DAC2_EQ_BAND_1_PG:
1310 case WM8995_AIF1_DAC2_EQ_BAND_2_A:
1311 case WM8995_AIF1_DAC2_EQ_BAND_2_B:
1312 case WM8995_AIF1_DAC2_EQ_BAND_2_C:
1313 case WM8995_AIF1_DAC2_EQ_BAND_2_PG:
1314 case WM8995_AIF1_DAC2_EQ_BAND_3_A:
1315 case WM8995_AIF1_DAC2_EQ_BAND_3_B:
1316 case WM8995_AIF1_DAC2_EQ_BAND_3_C:
1317 case WM8995_AIF1_DAC2_EQ_BAND_3_PG:
1318 case WM8995_AIF1_DAC2_EQ_BAND_4_A:
1319 case WM8995_AIF1_DAC2_EQ_BAND_4_B:
1320 case WM8995_AIF1_DAC2_EQ_BAND_4_C:
1321 case WM8995_AIF1_DAC2_EQ_BAND_4_PG:
1322 case WM8995_AIF1_DAC2_EQ_BAND_5_A:
1323 case WM8995_AIF1_DAC2_EQ_BAND_5_B:
1324 case WM8995_AIF1_DAC2_EQ_BAND_5_PG:
1325 case WM8995_AIF2_ADC_LEFT_VOLUME:
1326 case WM8995_AIF2_ADC_RIGHT_VOLUME:
1327 case WM8995_AIF2_DAC_LEFT_VOLUME:
1328 case WM8995_AIF2_DAC_RIGHT_VOLUME:
1329 case WM8995_AIF2_ADC_FILTERS:
1330 case WM8995_AIF2_DAC_FILTERS_1:
1331 case WM8995_AIF2_DAC_FILTERS_2:
1332 case WM8995_AIF2_DRC_1:
1333 case WM8995_AIF2_DRC_2:
1334 case WM8995_AIF2_DRC_3:
1335 case WM8995_AIF2_DRC_4:
1336 case WM8995_AIF2_DRC_5:
1337 case WM8995_AIF2_EQ_GAINS_1:
1338 case WM8995_AIF2_EQ_GAINS_2:
1339 case WM8995_AIF2_EQ_BAND_1_A:
1340 case WM8995_AIF2_EQ_BAND_1_B:
1341 case WM8995_AIF2_EQ_BAND_1_PG:
1342 case WM8995_AIF2_EQ_BAND_2_A:
1343 case WM8995_AIF2_EQ_BAND_2_B:
1344 case WM8995_AIF2_EQ_BAND_2_C:
1345 case WM8995_AIF2_EQ_BAND_2_PG:
1346 case WM8995_AIF2_EQ_BAND_3_A:
1347 case WM8995_AIF2_EQ_BAND_3_B:
1348 case WM8995_AIF2_EQ_BAND_3_C:
1349 case WM8995_AIF2_EQ_BAND_3_PG:
1350 case WM8995_AIF2_EQ_BAND_4_A:
1351 case WM8995_AIF2_EQ_BAND_4_B:
1352 case WM8995_AIF2_EQ_BAND_4_C:
1353 case WM8995_AIF2_EQ_BAND_4_PG:
1354 case WM8995_AIF2_EQ_BAND_5_A:
1355 case WM8995_AIF2_EQ_BAND_5_B:
1356 case WM8995_AIF2_EQ_BAND_5_PG:
1357 case WM8995_DAC1_MIXER_VOLUMES:
1358 case WM8995_DAC1_LEFT_MIXER_ROUTING:
1359 case WM8995_DAC1_RIGHT_MIXER_ROUTING:
1360 case WM8995_DAC2_MIXER_VOLUMES:
1361 case WM8995_DAC2_LEFT_MIXER_ROUTING:
1362 case WM8995_DAC2_RIGHT_MIXER_ROUTING:
1363 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING:
1364 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING:
1365 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING:
1366 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING:
1367 case WM8995_DAC_SOFTMUTE:
1368 case WM8995_OVERSAMPLING:
1369 case WM8995_SIDETONE:
1379 case WM8995_GPIO_10:
1380 case WM8995_GPIO_11:
1381 case WM8995_GPIO_12:
1382 case WM8995_GPIO_13:
1383 case WM8995_GPIO_14:
1384 case WM8995_PULL_CONTROL_1:
1385 case WM8995_PULL_CONTROL_2:
1386 case WM8995_INTERRUPT_STATUS_1:
1387 case WM8995_INTERRUPT_STATUS_2:
1388 case WM8995_INTERRUPT_RAW_STATUS_2:
1389 case WM8995_INTERRUPT_STATUS_1_MASK:
1390 case WM8995_INTERRUPT_STATUS_2_MASK:
1391 case WM8995_INTERRUPT_CONTROL:
1392 case WM8995_LEFT_PDM_SPEAKER_1:
1393 case WM8995_RIGHT_PDM_SPEAKER_1:
1394 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE:
1395 case WM8995_LEFT_PDM_SPEAKER_2:
1396 case WM8995_RIGHT_PDM_SPEAKER_2:
1397 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE:
1404 static bool wm8995_volatile(struct device *dev, unsigned int reg)
1407 case WM8995_SOFTWARE_RESET:
1408 case WM8995_DC_SERVO_READBACK_0:
1409 case WM8995_INTERRUPT_STATUS_1:
1410 case WM8995_INTERRUPT_STATUS_2:
1411 case WM8995_INTERRUPT_CONTROL:
1412 case WM8995_ACCESSORY_DETECT_MODE1:
1413 case WM8995_ACCESSORY_DETECT_MODE2:
1414 case WM8995_HEADPHONE_DETECT1:
1415 case WM8995_HEADPHONE_DETECT2:
1416 case WM8995_RATE_STATUS:
1423 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
1425 struct snd_soc_component *component = dai->component;
1430 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
1433 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
1439 snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
1440 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
1444 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1446 struct snd_soc_component *component;
1450 component = dai->component;
1453 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1454 case SND_SOC_DAIFMT_CBS_CFS:
1456 case SND_SOC_DAIFMT_CBM_CFM:
1457 master = WM8995_AIF1_MSTR;
1460 dev_err(dai->dev, "Unknown master/slave configuration\n");
1465 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1466 case SND_SOC_DAIFMT_DSP_B:
1467 aif |= WM8995_AIF1_LRCLK_INV;
1469 case SND_SOC_DAIFMT_DSP_A:
1470 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
1472 case SND_SOC_DAIFMT_I2S:
1473 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
1475 case SND_SOC_DAIFMT_RIGHT_J:
1477 case SND_SOC_DAIFMT_LEFT_J:
1478 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
1481 dev_err(dai->dev, "Unknown dai format\n");
1485 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1486 case SND_SOC_DAIFMT_DSP_A:
1487 case SND_SOC_DAIFMT_DSP_B:
1488 /* frame inversion not valid for DSP modes */
1489 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1490 case SND_SOC_DAIFMT_NB_NF:
1492 case SND_SOC_DAIFMT_IB_NF:
1493 aif |= WM8995_AIF1_BCLK_INV;
1500 case SND_SOC_DAIFMT_I2S:
1501 case SND_SOC_DAIFMT_RIGHT_J:
1502 case SND_SOC_DAIFMT_LEFT_J:
1503 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1504 case SND_SOC_DAIFMT_NB_NF:
1506 case SND_SOC_DAIFMT_IB_IF:
1507 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1509 case SND_SOC_DAIFMT_IB_NF:
1510 aif |= WM8995_AIF1_BCLK_INV;
1512 case SND_SOC_DAIFMT_NB_IF:
1513 aif |= WM8995_AIF1_LRCLK_INV;
1523 snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1,
1524 WM8995_AIF1_BCLK_INV_MASK |
1525 WM8995_AIF1_LRCLK_INV_MASK |
1526 WM8995_AIF1_FMT_MASK, aif);
1527 snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE,
1528 WM8995_AIF1_MSTR_MASK, master);
1532 static const int srs[] = {
1533 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1537 static const int fs_ratios[] = {
1539 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1542 static const int bclk_divs[] = {
1543 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1546 static int wm8995_hw_params(struct snd_pcm_substream *substream,
1547 struct snd_pcm_hw_params *params,
1548 struct snd_soc_dai *dai)
1550 struct snd_soc_component *component;
1551 struct wm8995_priv *wm8995;
1559 int i, rate_val, best, best_val, cur_val;
1561 component = dai->component;
1562 wm8995 = snd_soc_component_get_drvdata(component);
1566 aif1_reg = WM8995_AIF1_CONTROL_1;
1567 bclk_reg = WM8995_AIF1_BCLK;
1568 rate_reg = WM8995_AIF1_RATE;
1569 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1570 wm8995->lrclk_shared[0] */) {
1571 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1573 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1574 dev_dbg(component->dev, "AIF1 using split LRCLK\n");
1578 aif1_reg = WM8995_AIF2_CONTROL_1;
1579 bclk_reg = WM8995_AIF2_BCLK;
1580 rate_reg = WM8995_AIF2_RATE;
1581 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1582 wm8995->lrclk_shared[1] */) {
1583 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1585 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1586 dev_dbg(component->dev, "AIF2 using split LRCLK\n");
1593 bclk_rate = snd_soc_params_to_bclk(params);
1598 switch (params_width(params)) {
1602 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1605 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1608 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1611 dev_err(dai->dev, "Unsupported word length %u\n",
1612 params_width(params));
1616 /* try to find a suitable sample rate */
1617 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1618 if (srs[i] == params_rate(params))
1620 if (i == ARRAY_SIZE(srs)) {
1621 dev_err(dai->dev, "Sample rate %d is not supported\n",
1622 params_rate(params));
1625 rate_val = i << WM8995_AIF1_SR_SHIFT;
1627 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1628 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1629 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1631 /* AIFCLK/fs ratio; look for a close match in either direction */
1633 best_val = abs((fs_ratios[1] * params_rate(params))
1634 - wm8995->aifclk[dai->id]);
1635 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1636 cur_val = abs((fs_ratios[i] * params_rate(params))
1637 - wm8995->aifclk[dai->id]);
1638 if (cur_val >= best_val)
1645 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1646 dai->id + 1, fs_ratios[best]);
1649 * We may not get quite the right frequency if using
1650 * approximate clocks so look for the closest match that is
1651 * higher than the target (we need to ensure that there enough
1652 * BCLKs to clock out the samples).
1656 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1657 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1658 if (cur_val < 0) /* BCLK table is sorted */
1662 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1664 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1665 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1666 bclk_divs[best], bclk_rate);
1668 lrclk = bclk_rate / params_rate(params);
1669 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1670 lrclk, bclk_rate / lrclk);
1672 snd_soc_component_update_bits(component, aif1_reg,
1673 WM8995_AIF1_WL_MASK, aif1);
1674 snd_soc_component_update_bits(component, bclk_reg,
1675 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1676 snd_soc_component_update_bits(component, lrclk_reg,
1677 WM8995_AIF1DAC_RATE_MASK, lrclk);
1678 snd_soc_component_update_bits(component, rate_reg,
1679 WM8995_AIF1_SR_MASK |
1680 WM8995_AIF1CLK_RATE_MASK, rate_val);
1684 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1686 struct snd_soc_component *component = codec_dai->component;
1689 switch (codec_dai->id) {
1691 reg = WM8995_AIF1_MASTER_SLAVE;
1692 mask = WM8995_AIF1_TRI;
1695 reg = WM8995_AIF2_MASTER_SLAVE;
1696 mask = WM8995_AIF2_TRI;
1699 reg = WM8995_POWER_MANAGEMENT_5;
1700 mask = WM8995_AIF3_TRI;
1711 return snd_soc_component_update_bits(component, reg, mask, val);
1714 /* The size in bits of the FLL divide multiplied by 10
1715 * to allow rounding later */
1716 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1726 static int wm8995_get_fll_config(struct fll_div *fll,
1727 int freq_in, int freq_out)
1730 unsigned int K, Ndiv, Nmod;
1732 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1734 /* Scale the input frequency down to <= 13.5MHz */
1735 fll->clk_ref_div = 0;
1736 while (freq_in > 13500000) {
1740 if (fll->clk_ref_div > 3)
1743 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1745 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1747 while (freq_out * (fll->outdiv + 1) < 90000000) {
1749 if (fll->outdiv > 63)
1752 freq_out *= fll->outdiv + 1;
1753 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1755 if (freq_in > 1000000) {
1756 fll->fll_fratio = 0;
1757 } else if (freq_in > 256000) {
1758 fll->fll_fratio = 1;
1760 } else if (freq_in > 128000) {
1761 fll->fll_fratio = 2;
1763 } else if (freq_in > 64000) {
1764 fll->fll_fratio = 3;
1767 fll->fll_fratio = 4;
1770 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1772 /* Now, calculate N.K */
1773 Ndiv = freq_out / freq_in;
1776 Nmod = freq_out % freq_in;
1777 pr_debug("Nmod=%d\n", Nmod);
1779 /* Calculate fractional part - scale up so we can round. */
1780 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1782 do_div(Kpart, freq_in);
1784 K = Kpart & 0xFFFFFFFF;
1789 /* Move down to proper range now rounding is done */
1792 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1797 static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1798 int src, unsigned int freq_in,
1799 unsigned int freq_out)
1801 struct snd_soc_component *component;
1802 struct wm8995_priv *wm8995;
1803 int reg_offset, ret;
1805 u16 reg, aif1, aif2;
1807 component = dai->component;
1808 wm8995 = snd_soc_component_get_drvdata(component);
1810 aif1 = snd_soc_component_read32(component, WM8995_AIF1_CLOCKING_1)
1811 & WM8995_AIF1CLK_ENA;
1813 aif2 = snd_soc_component_read32(component, WM8995_AIF2_CLOCKING_1)
1814 & WM8995_AIF2CLK_ENA;
1831 /* Allow no source specification when stopping */
1835 case WM8995_FLL_SRC_MCLK1:
1836 case WM8995_FLL_SRC_MCLK2:
1837 case WM8995_FLL_SRC_LRCLK:
1838 case WM8995_FLL_SRC_BCLK:
1844 /* Are we changing anything? */
1845 if (wm8995->fll[id].src == src &&
1846 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1849 /* If we're stopping the FLL redo the old config - no
1850 * registers will actually be written but we avoid GCC flow
1851 * analysis bugs spewing warnings.
1854 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1856 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1857 wm8995->fll[id].out);
1861 /* Gate the AIF clocks while we reclock */
1862 snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1863 WM8995_AIF1CLK_ENA_MASK, 0);
1864 snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1865 WM8995_AIF2CLK_ENA_MASK, 0);
1867 /* We always need to disable the FLL while reconfiguring */
1868 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1869 WM8995_FLL1_ENA_MASK, 0);
1871 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1872 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1873 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset,
1874 WM8995_FLL1_OUTDIV_MASK |
1875 WM8995_FLL1_FRATIO_MASK, reg);
1877 snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1879 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset,
1881 fll.n << WM8995_FLL1_N_SHIFT);
1883 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset,
1884 WM8995_FLL1_REFCLK_DIV_MASK |
1885 WM8995_FLL1_REFCLK_SRC_MASK,
1886 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1890 snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset,
1891 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1893 wm8995->fll[id].in = freq_in;
1894 wm8995->fll[id].out = freq_out;
1895 wm8995->fll[id].src = src;
1897 /* Enable any gated AIF clocks */
1898 snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1,
1899 WM8995_AIF1CLK_ENA_MASK, aif1);
1900 snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1,
1901 WM8995_AIF2CLK_ENA_MASK, aif2);
1903 configure_clock(component);
1908 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1909 int clk_id, unsigned int freq, int dir)
1911 struct snd_soc_component *component;
1912 struct wm8995_priv *wm8995;
1914 component = dai->component;
1915 wm8995 = snd_soc_component_get_drvdata(component);
1922 /* AIF3 shares clocking with AIF1/2 */
1927 case WM8995_SYSCLK_MCLK1:
1928 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1929 wm8995->mclk[0] = freq;
1930 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1933 case WM8995_SYSCLK_MCLK2:
1934 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2;
1935 wm8995->mclk[1] = freq;
1936 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1939 case WM8995_SYSCLK_FLL1:
1940 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1941 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1943 case WM8995_SYSCLK_FLL2:
1944 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1945 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1947 case WM8995_SYSCLK_OPCLK:
1949 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1953 configure_clock(component);
1958 static int wm8995_set_bias_level(struct snd_soc_component *component,
1959 enum snd_soc_bias_level level)
1961 struct wm8995_priv *wm8995;
1964 wm8995 = snd_soc_component_get_drvdata(component);
1966 case SND_SOC_BIAS_ON:
1967 case SND_SOC_BIAS_PREPARE:
1969 case SND_SOC_BIAS_STANDBY:
1970 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1971 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
1976 ret = regcache_sync(wm8995->regmap);
1978 dev_err(component->dev,
1979 "Failed to sync cache: %d\n", ret);
1983 snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1984 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1987 case SND_SOC_BIAS_OFF:
1988 snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1,
1989 WM8995_BG_ENA_MASK, 0);
1990 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies),
1998 static void wm8995_remove(struct snd_soc_component *component)
2000 struct wm8995_priv *wm8995;
2003 wm8995 = snd_soc_component_get_drvdata(component);
2005 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i)
2006 regulator_unregister_notifier(wm8995->supplies[i].consumer,
2007 &wm8995->disable_nb[i]);
2009 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2012 static int wm8995_probe(struct snd_soc_component *component)
2014 struct wm8995_priv *wm8995;
2018 wm8995 = snd_soc_component_get_drvdata(component);
2019 wm8995->component = component;
2021 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++)
2022 wm8995->supplies[i].supply = wm8995_supply_names[i];
2024 ret = regulator_bulk_get(component->dev, ARRAY_SIZE(wm8995->supplies),
2027 dev_err(component->dev, "Failed to request supplies: %d\n", ret);
2031 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0;
2032 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1;
2033 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2;
2034 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3;
2035 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4;
2036 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5;
2037 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6;
2038 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7;
2040 /* This should really be moved into the regulator core */
2041 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) {
2042 ret = regulator_register_notifier(wm8995->supplies[i].consumer,
2043 &wm8995->disable_nb[i]);
2045 dev_err(component->dev,
2046 "Failed to register regulator notifier: %d\n",
2051 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies),
2054 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
2058 ret = snd_soc_component_read32(component, WM8995_SOFTWARE_RESET);
2060 dev_err(component->dev, "Failed to read device ID: %d\n", ret);
2061 goto err_reg_enable;
2064 if (ret != 0x8995) {
2065 dev_err(component->dev, "Invalid device ID: %#x\n", ret);
2067 goto err_reg_enable;
2070 ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0);
2072 dev_err(component->dev, "Failed to issue reset: %d\n", ret);
2073 goto err_reg_enable;
2076 /* Latch volume updates (right only; we always do left then right). */
2077 snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME,
2078 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
2079 snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME,
2080 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
2081 snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME,
2082 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
2083 snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME,
2084 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
2085 snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME,
2086 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
2087 snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME,
2088 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
2089 snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME,
2090 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
2091 snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME,
2092 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
2093 snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
2094 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
2096 wm8995_update_class_w(component);
2101 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2103 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies);
2107 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2108 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2110 static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
2111 .set_sysclk = wm8995_set_dai_sysclk,
2112 .set_fmt = wm8995_set_dai_fmt,
2113 .hw_params = wm8995_hw_params,
2114 .digital_mute = wm8995_aif_mute,
2115 .set_pll = wm8995_set_fll,
2116 .set_tristate = wm8995_set_tristate,
2119 static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
2120 .set_sysclk = wm8995_set_dai_sysclk,
2121 .set_fmt = wm8995_set_dai_fmt,
2122 .hw_params = wm8995_hw_params,
2123 .digital_mute = wm8995_aif_mute,
2124 .set_pll = wm8995_set_fll,
2125 .set_tristate = wm8995_set_tristate,
2128 static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
2129 .set_tristate = wm8995_set_tristate,
2132 static struct snd_soc_dai_driver wm8995_dai[] = {
2134 .name = "wm8995-aif1",
2136 .stream_name = "AIF1 Playback",
2139 .rates = SNDRV_PCM_RATE_8000_96000,
2140 .formats = WM8995_FORMATS
2143 .stream_name = "AIF1 Capture",
2146 .rates = SNDRV_PCM_RATE_8000_48000,
2147 .formats = WM8995_FORMATS
2149 .ops = &wm8995_aif1_dai_ops
2152 .name = "wm8995-aif2",
2154 .stream_name = "AIF2 Playback",
2157 .rates = SNDRV_PCM_RATE_8000_96000,
2158 .formats = WM8995_FORMATS
2161 .stream_name = "AIF2 Capture",
2164 .rates = SNDRV_PCM_RATE_8000_48000,
2165 .formats = WM8995_FORMATS
2167 .ops = &wm8995_aif2_dai_ops
2170 .name = "wm8995-aif3",
2172 .stream_name = "AIF3 Playback",
2175 .rates = SNDRV_PCM_RATE_8000_96000,
2176 .formats = WM8995_FORMATS
2179 .stream_name = "AIF3 Capture",
2182 .rates = SNDRV_PCM_RATE_8000_48000,
2183 .formats = WM8995_FORMATS
2185 .ops = &wm8995_aif3_dai_ops
2189 static const struct snd_soc_component_driver soc_component_dev_wm8995 = {
2190 .probe = wm8995_probe,
2191 .remove = wm8995_remove,
2192 .set_bias_level = wm8995_set_bias_level,
2193 .controls = wm8995_snd_controls,
2194 .num_controls = ARRAY_SIZE(wm8995_snd_controls),
2195 .dapm_widgets = wm8995_dapm_widgets,
2196 .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets),
2197 .dapm_routes = wm8995_intercon,
2198 .num_dapm_routes = ARRAY_SIZE(wm8995_intercon),
2199 .use_pmdown_time = 1,
2201 .non_legacy_dai_naming = 1,
2204 static const struct regmap_config wm8995_regmap = {
2208 .max_register = WM8995_MAX_REGISTER,
2209 .reg_defaults = wm8995_reg_defaults,
2210 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults),
2211 .volatile_reg = wm8995_volatile,
2212 .readable_reg = wm8995_readable,
2213 .cache_type = REGCACHE_RBTREE,
2216 #if defined(CONFIG_SPI_MASTER)
2217 static int wm8995_spi_probe(struct spi_device *spi)
2219 struct wm8995_priv *wm8995;
2222 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL);
2226 spi_set_drvdata(spi, wm8995);
2228 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap);
2229 if (IS_ERR(wm8995->regmap)) {
2230 ret = PTR_ERR(wm8995->regmap);
2231 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
2235 ret = devm_snd_soc_register_component(&spi->dev,
2236 &soc_component_dev_wm8995, wm8995_dai,
2237 ARRAY_SIZE(wm8995_dai));
2241 static struct spi_driver wm8995_spi_driver = {
2245 .probe = wm8995_spi_probe,
2249 #if IS_ENABLED(CONFIG_I2C)
2250 static int wm8995_i2c_probe(struct i2c_client *i2c,
2251 const struct i2c_device_id *id)
2253 struct wm8995_priv *wm8995;
2256 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL);
2260 i2c_set_clientdata(i2c, wm8995);
2262 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap);
2263 if (IS_ERR(wm8995->regmap)) {
2264 ret = PTR_ERR(wm8995->regmap);
2265 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret);
2269 ret = devm_snd_soc_register_component(&i2c->dev,
2270 &soc_component_dev_wm8995, wm8995_dai,
2271 ARRAY_SIZE(wm8995_dai));
2273 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
2278 static const struct i2c_device_id wm8995_i2c_id[] = {
2283 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
2285 static struct i2c_driver wm8995_i2c_driver = {
2289 .probe = wm8995_i2c_probe,
2290 .id_table = wm8995_i2c_id
2294 static int __init wm8995_modinit(void)
2298 #if IS_ENABLED(CONFIG_I2C)
2299 ret = i2c_add_driver(&wm8995_i2c_driver);
2301 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
2305 #if defined(CONFIG_SPI_MASTER)
2306 ret = spi_register_driver(&wm8995_spi_driver);
2308 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
2315 module_init(wm8995_modinit);
2317 static void __exit wm8995_exit(void)
2319 #if IS_ENABLED(CONFIG_I2C)
2320 i2c_del_driver(&wm8995_i2c_driver);
2322 #if defined(CONFIG_SPI_MASTER)
2323 spi_unregister_driver(&wm8995_spi_driver);
2327 module_exit(wm8995_exit);
2329 MODULE_DESCRIPTION("ASoC WM8995 driver");
2330 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
2331 MODULE_LICENSE("GPL");