2 * wm0010.c -- WM0010 DSP Driver
4 * Copyright 2012 Wolfson Microelectronics PLC.
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqreturn.h>
19 #include <linux/init.h>
20 #include <linux/spi/spi.h>
21 #include <linux/firmware.h>
22 #include <linux/delay.h>
24 #include <linux/gpio.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/mutex.h>
27 #include <linux/workqueue.h>
29 #include <sound/soc.h>
30 #include <sound/wm0010.h>
32 #define DEVICE_ID_WM0010 10
34 /* We only support v1 of the .dfw INFO record */
35 #define INFO_VERSION 1
54 u8 tool_major_version;
55 u8 tool_minor_version;
71 static struct pll_clock_map {
73 int max_pll_spi_speed;
75 } pll_clock_map[] = { /* Dividers */
76 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
77 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
78 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
79 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
80 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
81 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
93 struct snd_soc_component *component;
98 struct wm0010_pdata pdata;
101 int gpio_reset_value;
103 struct regulator_bulk_data core_supplies[2];
104 struct regulator *dbvdd;
108 enum wm0010_state state;
113 int board_max_spi_speed;
119 struct completion boot_completion;
122 struct wm0010_spi_msg {
123 struct spi_message m;
124 struct spi_transfer t;
130 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
131 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
134 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
135 { "SDI2 Capture", NULL, "SDI1 Playback" },
136 { "SDI1 Capture", NULL, "SDI2 Playback" },
138 { "SDI1 Capture", NULL, "CLKIN" },
139 { "SDI2 Capture", NULL, "CLKIN" },
140 { "SDI1 Playback", NULL, "CLKIN" },
141 { "SDI2 Playback", NULL, "CLKIN" },
144 static const char *wm0010_state_to_str(enum wm0010_state state)
146 static const char * const state_to_str[] = {
154 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
156 return state_to_str[state];
159 /* Called with wm0010->lock held */
160 static void wm0010_halt(struct snd_soc_component *component)
162 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
164 enum wm0010_state state;
166 /* Fetch the wm0010 state */
167 spin_lock_irqsave(&wm0010->irq_lock, flags);
168 state = wm0010->state;
169 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
172 case WM0010_POWER_OFF:
173 /* If there's nothing to do, bail out */
175 case WM0010_OUT_OF_RESET:
178 case WM0010_FIRMWARE:
179 /* Remember to put chip back into reset */
180 gpio_set_value_cansleep(wm0010->gpio_reset,
181 wm0010->gpio_reset_value);
182 /* Disable the regulators */
183 regulator_disable(wm0010->dbvdd);
184 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
185 wm0010->core_supplies);
189 spin_lock_irqsave(&wm0010->irq_lock, flags);
190 wm0010->state = WM0010_POWER_OFF;
191 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
194 struct wm0010_boot_xfer {
195 struct list_head list;
196 struct snd_soc_component *component;
197 struct completion *done;
198 struct spi_message m;
199 struct spi_transfer t;
202 /* Called with wm0010->lock held */
203 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
205 enum wm0010_state state;
208 spin_lock_irqsave(&wm0010->irq_lock, flags);
209 state = wm0010->state;
210 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
212 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
213 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
215 wm0010->boot_failed = true;
218 static void wm0010_boot_xfer_complete(void *data)
220 struct wm0010_boot_xfer *xfer = data;
221 struct snd_soc_component *component = xfer->component;
222 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
223 u32 *out32 = xfer->t.rx_buf;
226 if (xfer->m.status != 0) {
227 dev_err(component->dev, "SPI transfer failed: %d\n",
229 wm0010_mark_boot_failure(wm0010);
231 complete(xfer->done);
235 for (i = 0; i < xfer->t.len / 4; i++) {
236 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
238 switch (be32_to_cpu(out32[i])) {
240 dev_err(component->dev,
241 "%d: ROM error reported in stage 2\n", i);
242 wm0010_mark_boot_failure(wm0010);
246 if (wm0010->state < WM0010_STAGE2)
248 dev_err(component->dev,
249 "%d: ROM bootloader running in stage 2\n", i);
250 wm0010_mark_boot_failure(wm0010);
254 dev_dbg(component->dev, "Stage2 loader running\n");
258 dev_dbg(component->dev, "CODE_HDR packet received\n");
262 dev_dbg(component->dev, "CODE_DATA packet received\n");
266 dev_dbg(component->dev, "Download complete\n");
270 dev_dbg(component->dev, "Application start\n");
274 dev_dbg(component->dev, "PLL packet received\n");
275 wm0010->pll_running = true;
279 dev_err(component->dev, "Device reports image too long\n");
280 wm0010_mark_boot_failure(wm0010);
284 dev_err(component->dev, "Device reports bad SPI packet\n");
285 wm0010_mark_boot_failure(wm0010);
289 dev_err(component->dev, "Device reports SPI read overflow\n");
290 wm0010_mark_boot_failure(wm0010);
294 dev_err(component->dev, "Device reports SPI underclock\n");
295 wm0010_mark_boot_failure(wm0010);
299 dev_err(component->dev, "Device reports bad header packet\n");
300 wm0010_mark_boot_failure(wm0010);
304 dev_err(component->dev, "Device reports invalid packet type\n");
305 wm0010_mark_boot_failure(wm0010);
309 dev_err(component->dev, "Device reports data before header error\n");
310 wm0010_mark_boot_failure(wm0010);
314 dev_err(component->dev, "Device reports invalid PLL packet\n");
318 dev_err(component->dev, "Device reports packet alignment error\n");
319 wm0010_mark_boot_failure(wm0010);
323 dev_err(component->dev, "Unrecognised return 0x%x\n",
324 be32_to_cpu(out32[i]));
325 wm0010_mark_boot_failure(wm0010);
329 if (wm0010->boot_failed)
334 complete(xfer->done);
337 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
341 for (i = 0; i < len / 8; i++)
342 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
345 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
347 struct spi_device *spi = to_spi_device(component->dev);
348 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
349 struct list_head xfer_list;
350 struct wm0010_boot_xfer *xfer;
352 struct completion done;
353 const struct firmware *fw;
354 const struct dfw_binrec *rec;
355 const struct dfw_inforec *inforec;
360 INIT_LIST_HEAD(&xfer_list);
362 ret = reject_firmware(&fw, name, component->dev);
364 dev_err(component->dev, "Failed to request application(%s): %d\n",
369 rec = (const struct dfw_binrec *)fw->data;
370 inforec = (const struct dfw_inforec *)rec->data;
372 dsp = inforec->dsp_target;
373 wm0010->boot_failed = false;
374 if (WARN_ON(!list_empty(&xfer_list)))
376 init_completion(&done);
378 /* First record should be INFO */
379 if (rec->command != DFW_CMD_INFO) {
380 dev_err(component->dev, "First record not INFO\r\n");
385 if (inforec->info_version != INFO_VERSION) {
386 dev_err(component->dev,
387 "Unsupported version (%02d) of INFO record\r\n",
388 inforec->info_version);
393 dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
394 inforec->info_version);
396 /* Check it's a DSP file */
397 if (dsp != DEVICE_ID_WM0010) {
398 dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
403 /* Skip the info record as we don't need to send it */
404 offset += ((rec->length) + 8);
405 rec = (void *)&rec->data[rec->length];
407 while (offset < fw->size) {
408 dev_dbg(component->dev,
409 "Packet: command %d, data length = 0x%x\r\n",
410 rec->command, rec->length);
411 len = rec->length + 8;
413 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
419 xfer->component = component;
420 list_add_tail(&xfer->list, &xfer_list);
422 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
427 xfer->t.rx_buf = out;
429 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
434 xfer->t.tx_buf = img;
436 byte_swap_64((u64 *)&rec->command, img, len);
438 spi_message_init(&xfer->m);
439 xfer->m.complete = wm0010_boot_xfer_complete;
440 xfer->m.context = xfer;
442 xfer->t.bits_per_word = 8;
444 if (!wm0010->pll_running) {
445 xfer->t.speed_hz = wm0010->sysclk / 6;
447 xfer->t.speed_hz = wm0010->max_spi_freq;
449 if (wm0010->board_max_spi_speed &&
450 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
451 xfer->t.speed_hz = wm0010->board_max_spi_speed;
454 /* Store max usable spi frequency for later use */
455 wm0010->max_spi_freq = xfer->t.speed_hz;
457 spi_message_add_tail(&xfer->t, &xfer->m);
459 offset += ((rec->length) + 8);
460 rec = (void *)&rec->data[rec->length];
462 if (offset >= fw->size) {
463 dev_dbg(component->dev, "All transfers scheduled\n");
467 ret = spi_async(spi, &xfer->m);
469 dev_err(component->dev, "Write failed: %d\n", ret);
473 if (wm0010->boot_failed) {
474 dev_dbg(component->dev, "Boot fail!\n");
480 wait_for_completion(&done);
485 while (!list_empty(&xfer_list)) {
486 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
488 kfree(xfer->t.rx_buf);
489 kfree(xfer->t.tx_buf);
490 list_del(&xfer->list);
495 release_firmware(fw);
499 static int wm0010_stage2_load(struct snd_soc_component *component)
501 struct spi_device *spi = to_spi_device(component->dev);
502 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
503 const struct firmware *fw;
504 struct spi_message m;
505 struct spi_transfer t;
511 ret = reject_firmware(&fw, "/*(DEBLOBBED)*/", component->dev);
513 dev_err(component->dev, "Failed to request stage2 loader: %d\n",
518 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
520 /* Copy to local buffer first as vmalloc causes problems for dma */
521 img = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
527 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
533 memcpy(img, &fw->data[0], fw->size);
535 spi_message_init(&m);
536 memset(&t, 0, sizeof(t));
541 t.speed_hz = wm0010->sysclk / 10;
542 spi_message_add_tail(&t, &m);
544 dev_dbg(component->dev, "Starting initial download at %dHz\n",
547 ret = spi_sync(spi, &m);
549 dev_err(component->dev, "Initial download failed: %d\n", ret);
553 /* Look for errors from the boot ROM */
554 for (i = 0; i < fw->size; i++) {
555 if (out[i] != 0x55) {
556 dev_err(component->dev, "Boot ROM error: %x in %d\n",
558 wm0010_mark_boot_failure(wm0010);
568 release_firmware(fw);
573 static int wm0010_boot(struct snd_soc_component *component)
575 struct spi_device *spi = to_spi_device(component->dev);
576 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
579 struct spi_message m;
580 struct spi_transfer t;
581 struct dfw_pllrec pll_rec;
587 spin_lock_irqsave(&wm0010->irq_lock, flags);
588 if (wm0010->state != WM0010_POWER_OFF)
589 dev_warn(wm0010->dev, "DSP already powered up!\n");
590 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
592 if (wm0010->sysclk > 26000000) {
593 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
598 mutex_lock(&wm0010->lock);
599 wm0010->pll_running = false;
601 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
603 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
604 wm0010->core_supplies);
606 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
608 mutex_unlock(&wm0010->lock);
612 ret = regulator_enable(wm0010->dbvdd);
614 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
619 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
620 spin_lock_irqsave(&wm0010->irq_lock, flags);
621 wm0010->state = WM0010_OUT_OF_RESET;
622 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
624 if (!wait_for_completion_timeout(&wm0010->boot_completion,
625 msecs_to_jiffies(20)))
626 dev_err(component->dev, "Failed to get interrupt from DSP\n");
628 spin_lock_irqsave(&wm0010->irq_lock, flags);
629 wm0010->state = WM0010_BOOTROM;
630 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
632 ret = wm0010_stage2_load(component);
636 if (!wait_for_completion_timeout(&wm0010->boot_completion,
637 msecs_to_jiffies(20)))
638 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
640 spin_lock_irqsave(&wm0010->irq_lock, flags);
641 wm0010->state = WM0010_STAGE2;
642 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
644 /* Only initialise PLL if max_spi_freq initialised */
645 if (wm0010->max_spi_freq) {
647 /* Initialise a PLL record */
648 memset(&pll_rec, 0, sizeof(pll_rec));
649 pll_rec.command = DFW_CMD_PLL;
650 pll_rec.length = (sizeof(pll_rec) - 8);
652 /* On wm0010 only the CLKCTRL1 value is used */
653 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
656 len = pll_rec.length + 8;
657 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
661 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
665 /* We need to re-order for 0010 */
666 byte_swap_64((u64 *)&pll_rec, img_swap, len);
668 spi_message_init(&m);
669 memset(&t, 0, sizeof(t));
674 t.speed_hz = wm0010->sysclk / 6;
675 spi_message_add_tail(&t, &m);
677 ret = spi_sync(spi, &m);
679 dev_err(component->dev, "First PLL write failed: %d\n", ret);
683 /* Use a second send of the message to get the return status */
684 ret = spi_sync(spi, &m);
686 dev_err(component->dev, "Second PLL write failed: %d\n", ret);
692 /* Look for PLL active code from the DSP */
693 for (i = 0; i < len / 4; i++) {
694 if (*p == 0x0e00ed0f) {
695 dev_dbg(component->dev, "PLL packet received\n");
696 wm0010->pll_running = true;
705 dev_dbg(component->dev, "Not enabling DSP PLL.");
707 ret = wm0010_firmware_load("/*(DEBLOBBED)*/", component);
712 spin_lock_irqsave(&wm0010->irq_lock, flags);
713 wm0010->state = WM0010_FIRMWARE;
714 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
716 mutex_unlock(&wm0010->lock);
725 /* Put the chip back into reset */
726 wm0010_halt(component);
727 mutex_unlock(&wm0010->lock);
731 mutex_unlock(&wm0010->lock);
732 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
733 wm0010->core_supplies);
738 static int wm0010_set_bias_level(struct snd_soc_component *component,
739 enum snd_soc_bias_level level)
741 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
744 case SND_SOC_BIAS_ON:
745 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
746 wm0010_boot(component);
748 case SND_SOC_BIAS_PREPARE:
750 case SND_SOC_BIAS_STANDBY:
751 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
752 mutex_lock(&wm0010->lock);
753 wm0010_halt(component);
754 mutex_unlock(&wm0010->lock);
757 case SND_SOC_BIAS_OFF:
764 static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
765 int clk_id, unsigned int freq, int dir)
767 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
770 wm0010->sysclk = freq;
772 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
773 wm0010->max_spi_freq = 0;
775 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
776 if (freq >= pll_clock_map[i].max_sysclk) {
777 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
778 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
786 static int wm0010_probe(struct snd_soc_component *component);
788 static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
789 .probe = wm0010_probe,
790 .set_bias_level = wm0010_set_bias_level,
791 .set_sysclk = wm0010_set_sysclk,
792 .dapm_widgets = wm0010_dapm_widgets,
793 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
794 .dapm_routes = wm0010_dapm_routes,
795 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
796 .use_pmdown_time = 1,
798 .non_legacy_dai_naming = 1,
801 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
802 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
803 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
804 SNDRV_PCM_FMTBIT_S32_LE)
806 static struct snd_soc_dai_driver wm0010_dai[] = {
808 .name = "wm0010-sdi1",
810 .stream_name = "SDI1 Playback",
813 .rates = WM0010_RATES,
814 .formats = WM0010_FORMATS,
817 .stream_name = "SDI1 Capture",
820 .rates = WM0010_RATES,
821 .formats = WM0010_FORMATS,
825 .name = "wm0010-sdi2",
827 .stream_name = "SDI2 Playback",
830 .rates = WM0010_RATES,
831 .formats = WM0010_FORMATS,
834 .stream_name = "SDI2 Capture",
837 .rates = WM0010_RATES,
838 .formats = WM0010_FORMATS,
843 static irqreturn_t wm0010_irq(int irq, void *data)
845 struct wm0010_priv *wm0010 = data;
847 switch (wm0010->state) {
848 case WM0010_OUT_OF_RESET:
851 spin_lock(&wm0010->irq_lock);
852 complete(&wm0010->boot_completion);
853 spin_unlock(&wm0010->irq_lock);
862 static int wm0010_probe(struct snd_soc_component *component)
864 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
866 wm0010->component = component;
871 static int wm0010_spi_probe(struct spi_device *spi)
873 unsigned long gpio_flags;
877 struct wm0010_priv *wm0010;
879 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
884 mutex_init(&wm0010->lock);
885 spin_lock_init(&wm0010->irq_lock);
887 spi_set_drvdata(spi, wm0010);
888 wm0010->dev = &spi->dev;
890 if (dev_get_platdata(&spi->dev))
891 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
892 sizeof(wm0010->pdata));
894 init_completion(&wm0010->boot_completion);
896 wm0010->core_supplies[0].supply = "AVDD";
897 wm0010->core_supplies[1].supply = "DCVDD";
898 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
899 wm0010->core_supplies);
901 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
906 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
907 if (IS_ERR(wm0010->dbvdd)) {
908 ret = PTR_ERR(wm0010->dbvdd);
909 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
913 if (wm0010->pdata.gpio_reset) {
914 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
916 if (wm0010->pdata.reset_active_high)
917 wm0010->gpio_reset_value = 1;
919 wm0010->gpio_reset_value = 0;
921 if (wm0010->gpio_reset_value)
922 gpio_flags = GPIOF_OUT_INIT_HIGH;
924 gpio_flags = GPIOF_OUT_INIT_LOW;
926 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
927 gpio_flags, "wm0010 reset");
930 "Failed to request GPIO for DSP reset: %d\n",
935 dev_err(wm0010->dev, "No reset GPIO configured\n");
939 wm0010->state = WM0010_POWER_OFF;
942 if (wm0010->pdata.irq_flags)
943 trigger = wm0010->pdata.irq_flags;
945 trigger = IRQF_TRIGGER_FALLING;
946 trigger |= IRQF_ONESHOT;
948 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
951 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
957 ret = irq_set_irq_wake(irq, 1);
959 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
964 if (spi->max_speed_hz)
965 wm0010->board_max_spi_speed = spi->max_speed_hz;
967 wm0010->board_max_spi_speed = 0;
969 ret = devm_snd_soc_register_component(&spi->dev,
970 &soc_component_dev_wm0010, wm0010_dai,
971 ARRAY_SIZE(wm0010_dai));
978 static int wm0010_spi_remove(struct spi_device *spi)
980 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
982 gpio_set_value_cansleep(wm0010->gpio_reset,
983 wm0010->gpio_reset_value);
985 irq_set_irq_wake(wm0010->irq, 0);
988 free_irq(wm0010->irq, wm0010);
993 static struct spi_driver wm0010_spi_driver = {
997 .probe = wm0010_spi_probe,
998 .remove = wm0010_spi_remove,
1001 module_spi_driver(wm0010_spi_driver);
1003 MODULE_DESCRIPTION("ASoC WM0010 driver");
1004 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1005 MODULE_LICENSE("GPL");