1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm0010.c -- WM0010 DSP Driver
5 * Copyright 2012 Wolfson Microelectronics PLC.
7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
9 * Scott Ling <sl@opensource.wolfsonmicro.com>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqreturn.h>
16 #include <linux/init.h>
17 #include <linux/spi/spi.h>
18 #include <linux/firmware.h>
19 #include <linux/delay.h>
21 #include <linux/gpio.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mutex.h>
24 #include <linux/workqueue.h>
26 #include <sound/soc.h>
27 #include <sound/wm0010.h>
29 #define DEVICE_ID_WM0010 10
31 /* We only support v1 of the .dfw INFO record */
32 #define INFO_VERSION 1
51 u8 tool_major_version;
52 u8 tool_minor_version;
68 static struct pll_clock_map {
70 int max_pll_spi_speed;
72 } pll_clock_map[] = { /* Dividers */
73 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
74 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
75 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
76 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
77 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
78 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
90 struct snd_soc_component *component;
95 struct wm0010_pdata pdata;
100 struct regulator_bulk_data core_supplies[2];
101 struct regulator *dbvdd;
105 enum wm0010_state state;
110 int board_max_spi_speed;
116 struct completion boot_completion;
119 struct wm0010_spi_msg {
120 struct spi_message m;
121 struct spi_transfer t;
127 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
128 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
131 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
132 { "SDI2 Capture", NULL, "SDI1 Playback" },
133 { "SDI1 Capture", NULL, "SDI2 Playback" },
135 { "SDI1 Capture", NULL, "CLKIN" },
136 { "SDI2 Capture", NULL, "CLKIN" },
137 { "SDI1 Playback", NULL, "CLKIN" },
138 { "SDI2 Playback", NULL, "CLKIN" },
141 static const char *wm0010_state_to_str(enum wm0010_state state)
143 static const char * const state_to_str[] = {
151 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
153 return state_to_str[state];
156 /* Called with wm0010->lock held */
157 static void wm0010_halt(struct snd_soc_component *component)
159 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
161 enum wm0010_state state;
163 /* Fetch the wm0010 state */
164 spin_lock_irqsave(&wm0010->irq_lock, flags);
165 state = wm0010->state;
166 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
169 case WM0010_POWER_OFF:
170 /* If there's nothing to do, bail out */
172 case WM0010_OUT_OF_RESET:
175 case WM0010_FIRMWARE:
176 /* Remember to put chip back into reset */
177 gpio_set_value_cansleep(wm0010->gpio_reset,
178 wm0010->gpio_reset_value);
179 /* Disable the regulators */
180 regulator_disable(wm0010->dbvdd);
181 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
182 wm0010->core_supplies);
186 spin_lock_irqsave(&wm0010->irq_lock, flags);
187 wm0010->state = WM0010_POWER_OFF;
188 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
191 struct wm0010_boot_xfer {
192 struct list_head list;
193 struct snd_soc_component *component;
194 struct completion *done;
195 struct spi_message m;
196 struct spi_transfer t;
199 /* Called with wm0010->lock held */
200 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
202 enum wm0010_state state;
205 spin_lock_irqsave(&wm0010->irq_lock, flags);
206 state = wm0010->state;
207 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
209 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
210 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
212 wm0010->boot_failed = true;
215 static void wm0010_boot_xfer_complete(void *data)
217 struct wm0010_boot_xfer *xfer = data;
218 struct snd_soc_component *component = xfer->component;
219 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
220 u32 *out32 = xfer->t.rx_buf;
223 if (xfer->m.status != 0) {
224 dev_err(component->dev, "SPI transfer failed: %d\n",
226 wm0010_mark_boot_failure(wm0010);
228 complete(xfer->done);
232 for (i = 0; i < xfer->t.len / 4; i++) {
233 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
235 switch (be32_to_cpu(out32[i])) {
237 dev_err(component->dev,
238 "%d: ROM error reported in stage 2\n", i);
239 wm0010_mark_boot_failure(wm0010);
243 if (wm0010->state < WM0010_STAGE2)
245 dev_err(component->dev,
246 "%d: ROM bootloader running in stage 2\n", i);
247 wm0010_mark_boot_failure(wm0010);
251 dev_dbg(component->dev, "Stage2 loader running\n");
255 dev_dbg(component->dev, "CODE_HDR packet received\n");
259 dev_dbg(component->dev, "CODE_DATA packet received\n");
263 dev_dbg(component->dev, "Download complete\n");
267 dev_dbg(component->dev, "Application start\n");
271 dev_dbg(component->dev, "PLL packet received\n");
272 wm0010->pll_running = true;
276 dev_err(component->dev, "Device reports image too long\n");
277 wm0010_mark_boot_failure(wm0010);
281 dev_err(component->dev, "Device reports bad SPI packet\n");
282 wm0010_mark_boot_failure(wm0010);
286 dev_err(component->dev, "Device reports SPI read overflow\n");
287 wm0010_mark_boot_failure(wm0010);
291 dev_err(component->dev, "Device reports SPI underclock\n");
292 wm0010_mark_boot_failure(wm0010);
296 dev_err(component->dev, "Device reports bad header packet\n");
297 wm0010_mark_boot_failure(wm0010);
301 dev_err(component->dev, "Device reports invalid packet type\n");
302 wm0010_mark_boot_failure(wm0010);
306 dev_err(component->dev, "Device reports data before header error\n");
307 wm0010_mark_boot_failure(wm0010);
311 dev_err(component->dev, "Device reports invalid PLL packet\n");
315 dev_err(component->dev, "Device reports packet alignment error\n");
316 wm0010_mark_boot_failure(wm0010);
320 dev_err(component->dev, "Unrecognised return 0x%x\n",
321 be32_to_cpu(out32[i]));
322 wm0010_mark_boot_failure(wm0010);
326 if (wm0010->boot_failed)
331 complete(xfer->done);
334 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
338 for (i = 0; i < len / 8; i++)
339 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
342 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
344 struct spi_device *spi = to_spi_device(component->dev);
345 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
346 struct list_head xfer_list;
347 struct wm0010_boot_xfer *xfer;
349 DECLARE_COMPLETION_ONSTACK(done);
350 const struct firmware *fw;
351 const struct dfw_binrec *rec;
352 const struct dfw_inforec *inforec;
357 INIT_LIST_HEAD(&xfer_list);
359 ret = reject_firmware(&fw, name, component->dev);
361 dev_err(component->dev, "Failed to request application(%s): %d\n",
366 rec = (const struct dfw_binrec *)fw->data;
367 inforec = (const struct dfw_inforec *)rec->data;
369 dsp = inforec->dsp_target;
370 wm0010->boot_failed = false;
371 if (WARN_ON(!list_empty(&xfer_list)))
374 /* First record should be INFO */
375 if (rec->command != DFW_CMD_INFO) {
376 dev_err(component->dev, "First record not INFO\r\n");
381 if (inforec->info_version != INFO_VERSION) {
382 dev_err(component->dev,
383 "Unsupported version (%02d) of INFO record\r\n",
384 inforec->info_version);
389 dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
390 inforec->info_version);
392 /* Check it's a DSP file */
393 if (dsp != DEVICE_ID_WM0010) {
394 dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
399 /* Skip the info record as we don't need to send it */
400 offset += ((rec->length) + 8);
401 rec = (void *)&rec->data[rec->length];
403 while (offset < fw->size) {
404 dev_dbg(component->dev,
405 "Packet: command %d, data length = 0x%x\r\n",
406 rec->command, rec->length);
407 len = rec->length + 8;
409 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
415 xfer->component = component;
416 list_add_tail(&xfer->list, &xfer_list);
418 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
423 xfer->t.rx_buf = out;
425 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
430 xfer->t.tx_buf = img;
432 byte_swap_64((u64 *)&rec->command, img, len);
434 spi_message_init(&xfer->m);
435 xfer->m.complete = wm0010_boot_xfer_complete;
436 xfer->m.context = xfer;
438 xfer->t.bits_per_word = 8;
440 if (!wm0010->pll_running) {
441 xfer->t.speed_hz = wm0010->sysclk / 6;
443 xfer->t.speed_hz = wm0010->max_spi_freq;
445 if (wm0010->board_max_spi_speed &&
446 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
447 xfer->t.speed_hz = wm0010->board_max_spi_speed;
450 /* Store max usable spi frequency for later use */
451 wm0010->max_spi_freq = xfer->t.speed_hz;
453 spi_message_add_tail(&xfer->t, &xfer->m);
455 offset += ((rec->length) + 8);
456 rec = (void *)&rec->data[rec->length];
458 if (offset >= fw->size) {
459 dev_dbg(component->dev, "All transfers scheduled\n");
463 ret = spi_async(spi, &xfer->m);
465 dev_err(component->dev, "Write failed: %d\n", ret);
469 if (wm0010->boot_failed) {
470 dev_dbg(component->dev, "Boot fail!\n");
476 wait_for_completion(&done);
481 while (!list_empty(&xfer_list)) {
482 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
484 kfree(xfer->t.rx_buf);
485 kfree(xfer->t.tx_buf);
486 list_del(&xfer->list);
491 release_firmware(fw);
495 static int wm0010_stage2_load(struct snd_soc_component *component)
497 struct spi_device *spi = to_spi_device(component->dev);
498 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
499 const struct firmware *fw;
500 struct spi_message m;
501 struct spi_transfer t;
507 ret = reject_firmware(&fw, "/*(DEBLOBBED)*/", component->dev);
509 dev_err(component->dev, "Failed to request stage2 loader: %d\n",
514 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
516 /* Copy to local buffer first as vmalloc causes problems for dma */
517 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
523 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
529 spi_message_init(&m);
530 memset(&t, 0, sizeof(t));
535 t.speed_hz = wm0010->sysclk / 10;
536 spi_message_add_tail(&t, &m);
538 dev_dbg(component->dev, "Starting initial download at %dHz\n",
541 ret = spi_sync(spi, &m);
543 dev_err(component->dev, "Initial download failed: %d\n", ret);
547 /* Look for errors from the boot ROM */
548 for (i = 0; i < fw->size; i++) {
549 if (out[i] != 0x55) {
550 dev_err(component->dev, "Boot ROM error: %x in %d\n",
552 wm0010_mark_boot_failure(wm0010);
562 release_firmware(fw);
567 static int wm0010_boot(struct snd_soc_component *component)
569 struct spi_device *spi = to_spi_device(component->dev);
570 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
573 struct spi_message m;
574 struct spi_transfer t;
575 struct dfw_pllrec pll_rec;
581 spin_lock_irqsave(&wm0010->irq_lock, flags);
582 if (wm0010->state != WM0010_POWER_OFF)
583 dev_warn(wm0010->dev, "DSP already powered up!\n");
584 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
586 if (wm0010->sysclk > 26000000) {
587 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
592 mutex_lock(&wm0010->lock);
593 wm0010->pll_running = false;
595 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
597 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
598 wm0010->core_supplies);
600 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
602 mutex_unlock(&wm0010->lock);
606 ret = regulator_enable(wm0010->dbvdd);
608 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
613 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
614 spin_lock_irqsave(&wm0010->irq_lock, flags);
615 wm0010->state = WM0010_OUT_OF_RESET;
616 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
618 if (!wait_for_completion_timeout(&wm0010->boot_completion,
619 msecs_to_jiffies(20)))
620 dev_err(component->dev, "Failed to get interrupt from DSP\n");
622 spin_lock_irqsave(&wm0010->irq_lock, flags);
623 wm0010->state = WM0010_BOOTROM;
624 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
626 ret = wm0010_stage2_load(component);
630 if (!wait_for_completion_timeout(&wm0010->boot_completion,
631 msecs_to_jiffies(20)))
632 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
634 spin_lock_irqsave(&wm0010->irq_lock, flags);
635 wm0010->state = WM0010_STAGE2;
636 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
638 /* Only initialise PLL if max_spi_freq initialised */
639 if (wm0010->max_spi_freq) {
641 /* Initialise a PLL record */
642 memset(&pll_rec, 0, sizeof(pll_rec));
643 pll_rec.command = DFW_CMD_PLL;
644 pll_rec.length = (sizeof(pll_rec) - 8);
646 /* On wm0010 only the CLKCTRL1 value is used */
647 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
650 len = pll_rec.length + 8;
651 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
655 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
659 /* We need to re-order for 0010 */
660 byte_swap_64((u64 *)&pll_rec, img_swap, len);
662 spi_message_init(&m);
663 memset(&t, 0, sizeof(t));
668 t.speed_hz = wm0010->sysclk / 6;
669 spi_message_add_tail(&t, &m);
671 ret = spi_sync(spi, &m);
673 dev_err(component->dev, "First PLL write failed: %d\n", ret);
677 /* Use a second send of the message to get the return status */
678 ret = spi_sync(spi, &m);
680 dev_err(component->dev, "Second PLL write failed: %d\n", ret);
686 /* Look for PLL active code from the DSP */
687 for (i = 0; i < len / 4; i++) {
688 if (*p == 0x0e00ed0f) {
689 dev_dbg(component->dev, "PLL packet received\n");
690 wm0010->pll_running = true;
699 dev_dbg(component->dev, "Not enabling DSP PLL.");
701 ret = wm0010_firmware_load("/*(DEBLOBBED)*/", component);
706 spin_lock_irqsave(&wm0010->irq_lock, flags);
707 wm0010->state = WM0010_FIRMWARE;
708 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
710 mutex_unlock(&wm0010->lock);
719 /* Put the chip back into reset */
720 wm0010_halt(component);
721 mutex_unlock(&wm0010->lock);
725 mutex_unlock(&wm0010->lock);
726 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
727 wm0010->core_supplies);
732 static int wm0010_set_bias_level(struct snd_soc_component *component,
733 enum snd_soc_bias_level level)
735 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
738 case SND_SOC_BIAS_ON:
739 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
740 wm0010_boot(component);
742 case SND_SOC_BIAS_PREPARE:
744 case SND_SOC_BIAS_STANDBY:
745 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
746 mutex_lock(&wm0010->lock);
747 wm0010_halt(component);
748 mutex_unlock(&wm0010->lock);
751 case SND_SOC_BIAS_OFF:
758 static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
759 int clk_id, unsigned int freq, int dir)
761 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
764 wm0010->sysclk = freq;
766 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
767 wm0010->max_spi_freq = 0;
769 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
770 if (freq >= pll_clock_map[i].max_sysclk) {
771 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
772 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
780 static int wm0010_probe(struct snd_soc_component *component);
782 static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
783 .probe = wm0010_probe,
784 .set_bias_level = wm0010_set_bias_level,
785 .set_sysclk = wm0010_set_sysclk,
786 .dapm_widgets = wm0010_dapm_widgets,
787 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
788 .dapm_routes = wm0010_dapm_routes,
789 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
790 .use_pmdown_time = 1,
792 .non_legacy_dai_naming = 1,
795 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
796 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
797 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
798 SNDRV_PCM_FMTBIT_S32_LE)
800 static struct snd_soc_dai_driver wm0010_dai[] = {
802 .name = "wm0010-sdi1",
804 .stream_name = "SDI1 Playback",
807 .rates = WM0010_RATES,
808 .formats = WM0010_FORMATS,
811 .stream_name = "SDI1 Capture",
814 .rates = WM0010_RATES,
815 .formats = WM0010_FORMATS,
819 .name = "wm0010-sdi2",
821 .stream_name = "SDI2 Playback",
824 .rates = WM0010_RATES,
825 .formats = WM0010_FORMATS,
828 .stream_name = "SDI2 Capture",
831 .rates = WM0010_RATES,
832 .formats = WM0010_FORMATS,
837 static irqreturn_t wm0010_irq(int irq, void *data)
839 struct wm0010_priv *wm0010 = data;
841 switch (wm0010->state) {
842 case WM0010_OUT_OF_RESET:
845 spin_lock(&wm0010->irq_lock);
846 complete(&wm0010->boot_completion);
847 spin_unlock(&wm0010->irq_lock);
856 static int wm0010_probe(struct snd_soc_component *component)
858 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
860 wm0010->component = component;
865 static int wm0010_spi_probe(struct spi_device *spi)
867 unsigned long gpio_flags;
871 struct wm0010_priv *wm0010;
873 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
878 mutex_init(&wm0010->lock);
879 spin_lock_init(&wm0010->irq_lock);
881 spi_set_drvdata(spi, wm0010);
882 wm0010->dev = &spi->dev;
884 if (dev_get_platdata(&spi->dev))
885 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
886 sizeof(wm0010->pdata));
888 init_completion(&wm0010->boot_completion);
890 wm0010->core_supplies[0].supply = "AVDD";
891 wm0010->core_supplies[1].supply = "DCVDD";
892 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
893 wm0010->core_supplies);
895 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
900 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
901 if (IS_ERR(wm0010->dbvdd)) {
902 ret = PTR_ERR(wm0010->dbvdd);
903 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
907 if (wm0010->pdata.gpio_reset) {
908 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
910 if (wm0010->pdata.reset_active_high)
911 wm0010->gpio_reset_value = 1;
913 wm0010->gpio_reset_value = 0;
915 if (wm0010->gpio_reset_value)
916 gpio_flags = GPIOF_OUT_INIT_HIGH;
918 gpio_flags = GPIOF_OUT_INIT_LOW;
920 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
921 gpio_flags, "wm0010 reset");
924 "Failed to request GPIO for DSP reset: %d\n",
929 dev_err(wm0010->dev, "No reset GPIO configured\n");
933 wm0010->state = WM0010_POWER_OFF;
936 if (wm0010->pdata.irq_flags)
937 trigger = wm0010->pdata.irq_flags;
939 trigger = IRQF_TRIGGER_FALLING;
940 trigger |= IRQF_ONESHOT;
942 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
945 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
951 ret = irq_set_irq_wake(irq, 1);
953 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
958 if (spi->max_speed_hz)
959 wm0010->board_max_spi_speed = spi->max_speed_hz;
961 wm0010->board_max_spi_speed = 0;
963 ret = devm_snd_soc_register_component(&spi->dev,
964 &soc_component_dev_wm0010, wm0010_dai,
965 ARRAY_SIZE(wm0010_dai));
972 static int wm0010_spi_remove(struct spi_device *spi)
974 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
976 gpio_set_value_cansleep(wm0010->gpio_reset,
977 wm0010->gpio_reset_value);
979 irq_set_irq_wake(wm0010->irq, 0);
982 free_irq(wm0010->irq, wm0010);
987 static struct spi_driver wm0010_spi_driver = {
991 .probe = wm0010_spi_probe,
992 .remove = wm0010_spi_remove,
995 module_spi_driver(wm0010_spi_driver);
997 MODULE_DESCRIPTION("ASoC WM0010 driver");
998 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
999 MODULE_LICENSE("GPL");