sound/soc/codecs/wcd939x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
   5  * Copyright (c) 2023, Linaro Limited
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/slab.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/device.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/kernel.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/component.h>
  17 #include <sound/tlv.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/of_graph.h>
  20 #include <linux/of.h>
  21 #include <sound/jack.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <linux/regmap.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/usb/typec_mux.h>
  29 #include <linux/usb/typec_altmode.h>
  30
  31 #include "wcd-clsh-v2.h"
  32 #include "wcd-mbhc-v2.h"
  33 #include "wcd939x.h"
  34
  35 #define WCD939X_MAX_MICBIAS             (4)
  36 #define WCD939X_MAX_SUPPLY              (4)
  37 #define WCD939X_MBHC_MAX_BUTTONS        (8)
  38 #define TX_ADC_MAX                      (4)
  39 #define WCD_MBHC_HS_V_MAX               1600
  40
  41 enum {
  42         WCD939X_VERSION_1_0 = 0,
  43         WCD939X_VERSION_1_1,
  44         WCD939X_VERSION_2_0,
  45 };
  46
  47 #define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  48                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  49                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  50                             SNDRV_PCM_RATE_384000)
  51 /* Fractional Rates */
  52 #define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  53                                  SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  54 #define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  55                          SNDRV_PCM_FMTBIT_S24_LE |\
  56                          SNDRV_PCM_FMTBIT_S24_3LE |\
  57                          SNDRV_PCM_FMTBIT_S32_LE)
  58
  59 /* Convert from vout ctl to micbias voltage in mV */
  60 #define WCD_VOUT_CTL_TO_MICB(v)         (1000 + (v) * 50)
  61 #define SWR_CLK_RATE_0P6MHZ             (600000)
  62 #define SWR_CLK_RATE_1P2MHZ             (1200000)
  63 #define SWR_CLK_RATE_2P4MHZ             (2400000)
  64 #define SWR_CLK_RATE_4P8MHZ             (4800000)
  65 #define SWR_CLK_RATE_9P6MHZ             (9600000)
  66 #define SWR_CLK_RATE_11P2896MHZ         (1128960)
  67
  68 #define ADC_MODE_VAL_HIFI               0x01
  69 #define ADC_MODE_VAL_LO_HIF             0x02
  70 #define ADC_MODE_VAL_NORMAL             0x03
  71 #define ADC_MODE_VAL_LP                 0x05
  72 #define ADC_MODE_VAL_ULP1               0x09
  73 #define ADC_MODE_VAL_ULP2               0x0B
  74
  75 /* Z value defined in milliohm */
  76 #define WCD939X_ZDET_VAL_32             (32000)
  77 #define WCD939X_ZDET_VAL_400            (400000)
  78 #define WCD939X_ZDET_VAL_1200           (1200000)
  79 #define WCD939X_ZDET_VAL_100K           (100000000)
  80
  81 /* Z floating defined in ohms */
  82 #define WCD939X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
  83 #define WCD939X_ZDET_NUM_MEASUREMENTS   (900)
  84 #define WCD939X_MBHC_GET_C1(c)          (((c) & 0xC000) >> 14)
  85 #define WCD939X_MBHC_GET_X1(x)          ((x) & 0x3FFF)
  86
  87 /* Z value compared in milliOhm */
  88 #define WCD939X_MBHC_IS_SECOND_RAMP_REQUIRED(z) false
  89 #define WCD939X_ANA_MBHC_ZDET_CONST     (1018 * 1024)
  90
  91 enum {
  92         WCD9390 = 0,
  93         WCD9395 = 5,
  94 };
  95
  96 enum {
  97         /* INTR_CTRL_INT_MASK_0 */
  98         WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  99         WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
 100         WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
 101         WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 102         WCD939X_IRQ_MBHC_SW_DET,
 103         WCD939X_IRQ_HPHR_OCP_INT,
 104         WCD939X_IRQ_HPHR_CNP_INT,
 105         WCD939X_IRQ_HPHL_OCP_INT,
 106
 107         /* INTR_CTRL_INT_MASK_1 */
 108         WCD939X_IRQ_HPHL_CNP_INT,
 109         WCD939X_IRQ_EAR_CNP_INT,
 110         WCD939X_IRQ_EAR_SCD_INT,
 111         WCD939X_IRQ_HPHL_PDM_WD_INT,
 112         WCD939X_IRQ_HPHR_PDM_WD_INT,
 113         WCD939X_IRQ_EAR_PDM_WD_INT,
 114
 115         /* INTR_CTRL_INT_MASK_2 */
 116         WCD939X_IRQ_MBHC_MOISTURE_INT,
 117         WCD939X_IRQ_HPHL_SURGE_DET_INT,
 118         WCD939X_IRQ_HPHR_SURGE_DET_INT,
 119         WCD939X_NUM_IRQS,
 120 };
 121
 122 enum {
 123         MICB_BIAS_DISABLE = 0,
 124         MICB_BIAS_ENABLE,
 125         MICB_BIAS_PULL_UP,
 126         MICB_BIAS_PULL_DOWN,
 127 };
 128
 129 enum {
 130         WCD_ADC1 = 0,
 131         WCD_ADC2,
 132         WCD_ADC3,
 133         WCD_ADC4,
 134         HPH_PA_DELAY,
 135 };
 136
 137 enum {
 138         ADC_MODE_INVALID = 0,
 139         ADC_MODE_HIFI,
 140         ADC_MODE_LO_HIF,
 141         ADC_MODE_NORMAL,
 142         ADC_MODE_LP,
 143         ADC_MODE_ULP1,
 144         ADC_MODE_ULP2,
 145 };
 146
 147 enum {
 148         AIF1_PB = 0,
 149         AIF1_CAP,
 150         NUM_CODEC_DAIS,
 151 };
 152
 153 static u8 tx_mode_bit[] = {
 154         [ADC_MODE_INVALID] = 0x00,
 155         [ADC_MODE_HIFI] = 0x01,
 156         [ADC_MODE_LO_HIF] = 0x02,
 157         [ADC_MODE_NORMAL] = 0x04,
 158         [ADC_MODE_LP] = 0x08,
 159         [ADC_MODE_ULP1] = 0x10,
 160         [ADC_MODE_ULP2] = 0x20,
 161 };
 162
 163 struct zdet_param {
 164         u16 ldo_ctl;
 165         u16 noff;
 166         u16 nshift;
 167         u16 btn5;
 168         u16 btn6;
 169         u16 btn7;
 170 };
 171
 172 struct wcd939x_priv {
 173         struct sdw_slave *tx_sdw_dev;
 174         struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
 175         struct device *txdev;
 176         struct device *rxdev;
 177         struct device_node *rxnode, *txnode;
 178         struct regmap *regmap;
 179         struct snd_soc_component *component;
 180         /* micb setup lock */
 181         struct mutex micb_lock;
 182         /* typec handling */
 183         bool typec_analog_mux;
 184 #if IS_ENABLED(CONFIG_TYPEC)
 185         struct typec_mux_dev *typec_mux;
 186         struct typec_switch_dev *typec_sw;
 187         enum typec_orientation typec_orientation;
 188         unsigned long typec_mode;
 189         struct typec_switch *typec_switch;
 190 #endif /* CONFIG_TYPEC */
 191         /* mbhc module */
 192         struct wcd_mbhc *wcd_mbhc;
 193         struct wcd_mbhc_config mbhc_cfg;
 194         struct wcd_mbhc_intr intr_ids;
 195         struct wcd_clsh_ctrl *clsh_info;
 196         struct irq_domain *virq;
 197         struct regmap_irq_chip *wcd_regmap_irq_chip;
 198         struct regmap_irq_chip_data *irq_chip;
 199         struct regulator_bulk_data supplies[WCD939X_MAX_SUPPLY];
 200         struct snd_soc_jack *jack;
 201         unsigned long status_mask;
 202         s32 micb_ref[WCD939X_MAX_MICBIAS];
 203         s32 pullup_ref[WCD939X_MAX_MICBIAS];
 204         u32 hph_mode;
 205         u32 tx_mode[TX_ADC_MAX];
 206         int variant;
 207         int reset_gpio;
 208         u32 micb1_mv;
 209         u32 micb2_mv;
 210         u32 micb3_mv;
 211         u32 micb4_mv;
 212         int hphr_pdm_wd_int;
 213         int hphl_pdm_wd_int;
 214         int ear_pdm_wd_int;
 215         bool comp1_enable;
 216         bool comp2_enable;
 217         bool ldoh;
 218 };
 219
 220 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
 221 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 222 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 223
 224 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
 225         WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80),
 226         WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40),
 227         WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20),
 228         WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
 229         WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08),
 230         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
 231         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04),
 232         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10),
 233         WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08),
 234         WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01),
 235         WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06),
 236         WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80),
 237         WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
 238         WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03),
 239         WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03),
 240         WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08),
 241         WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
 242         WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20),
 243         WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80),
 244         WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40),
 245         WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10),
 246         WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07),
 247         WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70),
 248         WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF),
 249         WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0),
 250         WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF),
 251         WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40),
 252         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80),
 253         WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0),
 254         WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
 255         WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02),
 256         WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01),
 257         WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70),
 258         WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20),
 259         WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40),
 260         WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10),
 261         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01),
 262         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01),
 263         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80),
 264         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20),
 265         WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08),
 266         WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40),
 267         WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80),
 268         WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF),
 269         WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F),
 270         WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10),
 271         WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04),
 272         WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02),
 273 };
 274
 275 static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
 276         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
 277         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
 278         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
 279         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
 280         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
 281         REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
 282         REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
 283         REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
 284         REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
 285         REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
 286         REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
 287         REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
 288         REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
 289         REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
 290         REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
 291         REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
 292         REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
 293 };
 294
 295 static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
 296         .name = "wcd939x",
 297         .irqs = wcd939x_irqs,
 298         .num_irqs = ARRAY_SIZE(wcd939x_irqs),
 299         .num_regs = 3,
 300         .status_base = WCD939X_DIGITAL_INTR_STATUS_0,
 301         .mask_base = WCD939X_DIGITAL_INTR_MASK_0,
 302         .ack_base = WCD939X_DIGITAL_INTR_CLEAR_0,
 303         .use_ack = 1,
 304         .runtime_pm = true,
 305         .irq_drv_data = NULL,
 306 };
 307
 308 static int wcd939x_get_clk_rate(int mode)
 309 {
 310         int rate;
 311
 312         switch (mode) {
 313         case ADC_MODE_ULP2:
 314                 rate = SWR_CLK_RATE_0P6MHZ;
 315                 break;
 316         case ADC_MODE_ULP1:
 317                 rate = SWR_CLK_RATE_1P2MHZ;
 318                 break;
 319         case ADC_MODE_LP:
 320                 rate = SWR_CLK_RATE_4P8MHZ;
 321                 break;
 322         case ADC_MODE_NORMAL:
 323         case ADC_MODE_LO_HIF:
 324         case ADC_MODE_HIFI:
 325         case ADC_MODE_INVALID:
 326         default:
 327                 rate = SWR_CLK_RATE_9P6MHZ;
 328                 break;
 329         }
 330
 331         return rate;
 332 }
 333
 334 static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
 335 {
 336         u8 mask = (bank ? 0xF0 : 0x0F);
 337         u8 val = 0;
 338
 339         switch (rate) {
 340         case SWR_CLK_RATE_0P6MHZ:
 341                 val = 6;
 342                 break;
 343         case SWR_CLK_RATE_1P2MHZ:
 344                 val = 5;
 345                 break;
 346         case SWR_CLK_RATE_2P4MHZ:
 347                 val = 3;
 348                 break;
 349         case SWR_CLK_RATE_4P8MHZ:
 350                 val = 1;
 351                 break;
 352         case SWR_CLK_RATE_9P6MHZ:
 353         default:
 354                 val = 0;
 355                 break;
 356         }
 357
 358         snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val);
 359
 360         return 0;
 361 }
 362
 363 static int wcd939x_io_init(struct snd_soc_component *component)
 364 {
 365         snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 366                                       WCD939X_BIAS_ANALOG_BIAS_EN, true);
 367         snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 368                                       WCD939X_BIAS_PRECHRG_EN, true);
 369
 370         /* 10 msec delay as per HW requirement */
 371         usleep_range(10000, 10010);
 372         snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 373                                       WCD939X_BIAS_PRECHRG_EN, false);
 374
 375         snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 376                                       WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15);
 377         snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 378                                       WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15);
 379         snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 380                                       WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
 381
 382         snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
 383                                       WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1);
 384         snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
 385                                       WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4);
 386
 387         snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP,
 388                                       WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8);
 389
 390         snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1,
 391                                       WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 392         snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1,
 393                                       WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 394         snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1,
 395                                       WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 396         snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1,
 397                                       WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 398         snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2,
 399                                       WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false);
 400
 401         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
 402                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
 403         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
 404                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
 405
 406         snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
 407                                       WCD939X_OCP_CTL_OCP_FSM_EN, true);
 408         snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
 409                                       WCD939X_OCP_CTL_SCD_OP_EN, true);
 410
 411         snd_soc_component_write(component, WCD939X_E_CFG0,
 412                                 WCD939X_CFG0_IDLE_STEREO |
 413                                 WCD939X_CFG0_AUTO_DISABLE_ANC);
 414
 415         return 0;
 416 }
 417
 418 static int wcd939x_sdw_connect_port(struct wcd939x_sdw_ch_info *ch_info,
 419                                     struct sdw_port_config *port_config,
 420                                     u8 enable)
 421 {
 422         u8 ch_mask, port_num;
 423
 424         port_num = ch_info->port_num;
 425         ch_mask = ch_info->ch_mask;
 426
 427         port_config->num = port_num;
 428
 429         if (enable)
 430                 port_config->ch_mask |= ch_mask;
 431         else
 432                 port_config->ch_mask &= ~ch_mask;
 433
 434         return 0;
 435 }
 436
 437 static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
 438 {
 439         return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id],
 440                                         &wcd->port_config[port_num - 1],
 441                                         enable);
 442 }
 443
 444 static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
 445                                       struct snd_kcontrol *kcontrol,
 446                                       int event)
 447 {
 448         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 449
 450         switch (event) {
 451         case SND_SOC_DAPM_PRE_PMU:
 452                 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 453                                               WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true);
 454
 455                 /* Analog path clock controls */
 456                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 457                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true);
 458                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 459                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
 460                                               true);
 461                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 462                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
 463                                               true);
 464
 465                 /* Digital path clock controls */
 466                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 467                                               WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true);
 468                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 469                                               WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true);
 470                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 471                                               WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true);
 472                 break;
 473         case SND_SOC_DAPM_POST_PMD:
 474                 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 475                                               WCD939X_RX_SUPPLIES_VNEG_EN, false);
 476                 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 477                                               WCD939X_RX_SUPPLIES_VPOS_EN, false);
 478
 479                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 480                                               WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false);
 481                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 482                                               WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false);
 483                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 484                                               WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false);
 485
 486                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 487                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
 488                                               false);
 489                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 490                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
 491                                               false);
 492                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 493                                               WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false);
 494
 495                 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 496                                               WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false);
 497
 498                 break;
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
 505                                         struct snd_kcontrol *kcontrol,
 506                                         int event)
 507 {
 508         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 509         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 510
 511         switch (event) {
 512         case SND_SOC_DAPM_PRE_PMU:
 513                 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
 514                                               WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
 515                                               false);
 516
 517                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 518                                               WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true);
 519                 break;
 520         case SND_SOC_DAPM_POST_PMU:
 521                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 522                                               WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d);
 523                 if (wcd939x->comp1_enable) {
 524                         snd_soc_component_write_field(component,
 525                                                       WCD939X_DIGITAL_CDC_COMP_CTL_0,
 526                                                       WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
 527                                                       true);
 528                          /* 5msec compander delay as per HW requirement */
 529                         if (!wcd939x->comp2_enable ||
 530                             snd_soc_component_read_field(component,
 531                                                          WCD939X_DIGITAL_CDC_COMP_CTL_0,
 532                                                          WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN))
 533                                 usleep_range(5000, 5010);
 534
 535                         snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 536                                                       WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
 537                                                       false);
 538                 } else {
 539                         snd_soc_component_write_field(component,
 540                                                       WCD939X_DIGITAL_CDC_COMP_CTL_0,
 541                                                       WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
 542                                                       false);
 543                         snd_soc_component_write_field(component, WCD939X_HPH_L_EN,
 544                                                       WCD939X_L_EN_GAIN_SOURCE_SEL, true);
 545                 }
 546                 break;
 547         case SND_SOC_DAPM_POST_PMD:
 548                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 549                                               WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1);
 550                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 551                                               WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false);
 552                 break;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
 559                                         struct snd_kcontrol *kcontrol,
 560                                         int event)
 561 {
 562         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 563         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 564
 565         dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
 566                 w->name, event);
 567
 568         switch (event) {
 569         case SND_SOC_DAPM_PRE_PMU:
 570                 snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
 571                                               WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
 572                                               false);
 573
 574                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 575                                               WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true);
 576                 break;
 577         case SND_SOC_DAPM_POST_PMU:
 578                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 579                                               WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d);
 580                 if (wcd939x->comp2_enable) {
 581                         snd_soc_component_write_field(component,
 582                                                       WCD939X_DIGITAL_CDC_COMP_CTL_0,
 583                                                       WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
 584                                                       true);
 585                         /* 5msec compander delay as per HW requirement */
 586                         if (!wcd939x->comp1_enable ||
 587                             snd_soc_component_read_field(component,
 588                                                          WCD939X_DIGITAL_CDC_COMP_CTL_0,
 589                                                          WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN))
 590                                 usleep_range(5000, 5010);
 591                         snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 592                                                       WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
 593                                                       false);
 594                 } else {
 595                         snd_soc_component_write_field(component,
 596                                                       WCD939X_DIGITAL_CDC_COMP_CTL_0,
 597                                                       WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
 598                                                       false);
 599                         snd_soc_component_write_field(component, WCD939X_HPH_R_EN,
 600                                                       WCD939X_R_EN_GAIN_SOURCE_SEL, true);
 601                 }
 602                 break;
 603         case SND_SOC_DAPM_POST_PMD:
 604                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 605                                               WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1);
 606                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 607                                               WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false);
 608                 break;
 609         }
 610
 611         return 0;
 612 }
 613
 614 static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
 615                                        struct snd_kcontrol *kcontrol,
 616                                        int event)
 617 {
 618         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 619         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 620
 621         switch (event) {
 622         case SND_SOC_DAPM_PRE_PMU:
 623                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL,
 624                                               WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true);
 625
 626                 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
 627                                               WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false);
 628
 629                 /* 5 msec delay as per HW requirement */
 630                 usleep_range(5000, 5010);
 631                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 632                                         WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
 633
 634                 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 635                                               WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 636                 break;
 637         case SND_SOC_DAPM_POST_PMD:
 638                 snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
 639                                               WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true);
 640                 break;
 641         }
 642
 643         return 0;
 644 }
 645
 646 static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
 647                                         struct snd_kcontrol *kcontrol,
 648                                         int event)
 649 {
 650         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 651         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 652         int hph_mode = wcd939x->hph_mode;
 653
 654         switch (event) {
 655         case SND_SOC_DAPM_PRE_PMU:
 656                 if (wcd939x->ldoh)
 657                         snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 658                                                       WCD939X_MODE_LDOH_EN, true);
 659
 660                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 661                                         WCD_CLSH_STATE_HPHR, hph_mode);
 662                 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
 663
 664                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
 665                         snd_soc_component_write_field(component,
 666                                         WCD939X_HPH_REFBUFF_LP_CTL,
 667                                         WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true);
 668                 if (hph_mode == CLS_H_LOHIFI)
 669                         snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 670                                                        WCD939X_HPH_PWR_LEVEL, 0);
 671
 672                 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 673                                               WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 674                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 675                                               WCD939X_HPH_HPHR_REF_ENABLE, true);
 676
 677                 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
 678                                                  WCD939X_HPH_HPHL_REF_ENABLE))
 679                         usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
 680
 681                 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 682                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
 683                                               WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3);
 684                 break;
 685         case SND_SOC_DAPM_POST_PMU:
 686                 /*
 687                  * 7ms sleep is required if compander is enabled as per
 688                  * HW requirement. If compander is disabled, then
 689                  * 20ms delay is required.
 690                  */
 691                 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 692                         if (!wcd939x->comp2_enable)
 693                                 usleep_range(20000, 20100);
 694                         else
 695                                 usleep_range(7000, 7100);
 696
 697                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
 698                             hph_mode == CLS_H_ULP)
 699                                 snd_soc_component_write_field(component,
 700                                                 WCD939X_HPH_REFBUFF_LP_CTL,
 701                                                 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 702                                                 false);
 703                         clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 704                 }
 705                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 706                                               WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
 707                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
 708                     hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
 709                         snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 710                                                       WCD939X_RX_SUPPLIES_REGULATOR_MODE,
 711                                                       true);
 712
 713                 enable_irq(wcd939x->hphr_pdm_wd_int);
 714                 break;
 715         case SND_SOC_DAPM_PRE_PMD:
 716                 disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
 717                 /*
 718                  * 7ms sleep is required if compander is enabled as per
 719                  * HW requirement. If compander is disabled, then
 720                  * 20ms delay is required.
 721                  */
 722                 if (!wcd939x->comp2_enable)
 723                         usleep_range(20000, 20100);
 724                 else
 725                         usleep_range(7000, 7100);
 726
 727                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 728                                               WCD939X_HPH_HPHR_ENABLE, false);
 729
 730                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 731                                       WCD_EVENT_PRE_HPHR_PA_OFF);
 732                 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 733                 break;
 734         case SND_SOC_DAPM_POST_PMD:
 735                 /*
 736                  * 7ms sleep is required if compander is enabled as per
 737                  * HW requirement. If compander is disabled, then
 738                  * 20ms delay is required.
 739                  */
 740                 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 741                         if (!wcd939x->comp2_enable)
 742                                 usleep_range(20000, 20100);
 743                         else
 744                                 usleep_range(7000, 7100);
 745                         clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 746                 }
 747                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 748                                       WCD_EVENT_POST_HPHR_PA_OFF);
 749
 750                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 751                                               WCD939X_HPH_HPHR_REF_ENABLE, false);
 752                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
 753                                               WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0);
 754
 755                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 756                                         WCD_CLSH_STATE_HPHR, hph_mode);
 757                 if (wcd939x->ldoh)
 758                         snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 759                                                       WCD939X_MODE_LDOH_EN, false);
 760                 break;
 761         }
 762
 763         return 0;
 764 }
 765
 766 static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
 767                                         struct snd_kcontrol *kcontrol,
 768                                         int event)
 769 {
 770         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 771         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 772         int hph_mode = wcd939x->hph_mode;
 773
 774         dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
 775                 w->name, event);
 776
 777         switch (event) {
 778         case SND_SOC_DAPM_PRE_PMU:
 779                 if (wcd939x->ldoh)
 780                         snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 781                                                       WCD939X_MODE_LDOH_EN, true);
 782                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 783                                         WCD_CLSH_STATE_HPHL, hph_mode);
 784                 wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
 785
 786                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
 787                         snd_soc_component_write_field(component,
 788                                                 WCD939X_HPH_REFBUFF_LP_CTL,
 789                                                 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 790                                                 true);
 791                 if (hph_mode == CLS_H_LOHIFI)
 792                         snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 793                                                        WCD939X_HPH_PWR_LEVEL, 0);
 794
 795                 snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 796                                               WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 797                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 798                                               WCD939X_HPH_HPHL_REF_ENABLE, true);
 799
 800                 if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
 801                                                  WCD939X_HPH_HPHR_REF_ENABLE))
 802                         usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
 803
 804                 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 805                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 806                                               WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
 807                 break;
 808         case SND_SOC_DAPM_POST_PMU:
 809                 /*
 810                  * 7ms sleep is required if compander is enabled as per
 811                  * HW requirement. If compander is disabled, then
 812                  * 20ms delay is required.
 813                  */
 814                 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 815                         if (!wcd939x->comp1_enable)
 816                                 usleep_range(20000, 20100);
 817                         else
 818                                 usleep_range(7000, 7100);
 819                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
 820                             hph_mode == CLS_H_ULP)
 821                                 snd_soc_component_write_field(component,
 822                                                 WCD939X_HPH_REFBUFF_LP_CTL,
 823                                                 WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 824                                                 false);
 825                         clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 826                 }
 827                 snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 828                                               WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
 829                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
 830                     hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
 831                         snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 832                                                       WCD939X_RX_SUPPLIES_REGULATOR_MODE,
 833                                                       true);
 834                 enable_irq(wcd939x->hphl_pdm_wd_int);
 835                 break;
 836         case SND_SOC_DAPM_PRE_PMD:
 837                 disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
 838                 /*
 839                  * 7ms sleep is required if compander is enabled as per
 840                  * HW requirement. If compander is disabled, then
 841                  * 20ms delay is required.
 842                  */
 843                 if (!wcd939x->comp1_enable)
 844                         usleep_range(20000, 20100);
 845                 else
 846                         usleep_range(7000, 7100);
 847
 848                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 849                                               WCD939X_HPH_HPHL_ENABLE, false);
 850
 851                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
 852                 set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 853                 break;
 854         case SND_SOC_DAPM_POST_PMD:
 855                 /*
 856                  * 7ms sleep is required if compander is enabled as per
 857                  * HW requirement. If compander is disabled, then
 858                  * 20ms delay is required.
 859                  */
 860                 if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 861                         if (!wcd939x->comp1_enable)
 862                                 usleep_range(21000, 21100);
 863                         else
 864                                 usleep_range(7000, 7100);
 865                         clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 866                 }
 867                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 868                                       WCD_EVENT_POST_HPHL_PA_OFF);
 869                 snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 870                                               WCD939X_HPH_HPHL_REF_ENABLE, false);
 871                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 872                                               WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
 873                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 874                                         WCD_CLSH_STATE_HPHL, hph_mode);
 875                 if (wcd939x->ldoh)
 876                         snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 877                                                       WCD939X_MODE_LDOH_EN, false);
 878                 break;
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 885                                        struct snd_kcontrol *kcontrol, int event)
 886 {
 887         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 888         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 889
 890         switch (event) {
 891         case SND_SOC_DAPM_PRE_PMU:
 892                 /* Enable watchdog interrupt for HPHL */
 893                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 894                                               WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
 895                 /* For EAR, use CLASS_AB regulator mode */
 896                 snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 897                                               WCD939X_RX_SUPPLIES_REGULATOR_MODE, true);
 898                 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
 899                                               WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true);
 900                 break;
 901         case SND_SOC_DAPM_POST_PMU:
 902                 /* 6 msec delay as per HW requirement */
 903                 usleep_range(6000, 6010);
 904                 enable_irq(wcd939x->ear_pdm_wd_int);
 905                 break;
 906         case SND_SOC_DAPM_PRE_PMD:
 907                 disable_irq_nosync(wcd939x->ear_pdm_wd_int);
 908                 break;
 909         case SND_SOC_DAPM_POST_PMD:
 910                 snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
 911                                               WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG,
 912                                               false);
 913                 /* 7 msec delay as per HW requirement */
 914                 usleep_range(7000, 7010);
 915                 snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 916                                               WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
 917                 wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 918                                         WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
 919                 break;
 920         }
 921
 922         return 0;
 923 }
 924
 925 /* TX Controls */
 926
 927 static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
 928                                      struct snd_kcontrol *kcontrol,
 929                                      int event)
 930 {
 931         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 932         u16 dmic_clk_reg, dmic_clk_en_reg;
 933         u8 dmic_clk_en_mask;
 934         u8 dmic_ctl_mask;
 935         u8 dmic_clk_mask;
 936
 937         switch (w->shift) {
 938         case 0:
 939         case 1:
 940                 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
 941                 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL;
 942                 dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN;
 943                 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE;
 944                 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL;
 945                 break;
 946         case 2:
 947         case 3:
 948                 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
 949                 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL;
 950                 dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN;
 951                 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE;
 952                 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL;
 953                 break;
 954         case 4:
 955         case 5:
 956                 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
 957                 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL;
 958                 dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN;
 959                 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE;
 960                 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL;
 961                 break;
 962         case 6:
 963         case 7:
 964                 dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
 965                 dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL;
 966                 dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN;
 967                 dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE;
 968                 dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL;
 969                 break;
 970         default:
 971                 dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__);
 972                 return -EINVAL;
 973         }
 974
 975         switch (event) {
 976         case SND_SOC_DAPM_PRE_PMU:
 977                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
 978                                               dmic_ctl_mask, false);
 979                 /* 250us sleep as per HW requirement */
 980                 usleep_range(250, 260);
 981                 if (w->shift == 2)
 982                         snd_soc_component_write_field(component,
 983                                                       WCD939X_DIGITAL_CDC_DMIC2_CTL,
 984                                                       WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
 985                                                       true);
 986                 /* Setting DMIC clock rate to 2.4MHz */
 987                 snd_soc_component_write_field(component, dmic_clk_reg,
 988                                               dmic_clk_mask, 3);
 989                 snd_soc_component_write_field(component, dmic_clk_en_reg,
 990                                               dmic_clk_en_mask, true);
 991                 /* enable clock scaling */
 992                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 993                                               WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
 994                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 995                                               WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true);
 996                 break;
 997         case SND_SOC_DAPM_POST_PMD:
 998                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
 999                                               dmic_ctl_mask, 1);
1000                 if (w->shift == 2)
1001                         snd_soc_component_write_field(component,
1002                                                       WCD939X_DIGITAL_CDC_DMIC2_CTL,
1003                                                       WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
1004                                                       false);
1005                 snd_soc_component_write_field(component, dmic_clk_en_reg,
1006                                               dmic_clk_en_mask, 0);
1007                 break;
1008         }
1009         return 0;
1010 }
1011
1012 static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
1013                                struct snd_kcontrol *kcontrol, int event)
1014 {
1015         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1016         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1017         int bank;
1018         int rate;
1019
1020         bank = wcd939x_swr_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev);
1021
1022         switch (event) {
1023         case SND_SOC_DAPM_PRE_PMU:
1024                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1025                         int mode = 0;
1026
1027                         if (test_bit(WCD_ADC1, &wcd939x->status_mask))
1028                                 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
1029                         if (test_bit(WCD_ADC2, &wcd939x->status_mask))
1030                                 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
1031                         if (test_bit(WCD_ADC3, &wcd939x->status_mask))
1032                                 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
1033                         if (test_bit(WCD_ADC4, &wcd939x->status_mask))
1034                                 mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
1035
1036                         if (mode)
1037                                 rate = wcd939x_get_clk_rate(ffs(mode) - 1);
1038                         else
1039                                 rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1040                         wcd939x_set_swr_clk_rate(component, rate, bank);
1041                         wcd939x_set_swr_clk_rate(component, rate, !bank);
1042                 }
1043                 break;
1044         case SND_SOC_DAPM_POST_PMD:
1045                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1046                         rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1047                         wcd939x_set_swr_clk_rate(component, rate, !bank);
1048                         wcd939x_set_swr_clk_rate(component, rate, bank);
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int wcd939x_get_adc_mode(int val)
1057 {
1058         int ret = 0;
1059
1060         switch (val) {
1061         case ADC_MODE_INVALID:
1062                 ret = ADC_MODE_VAL_NORMAL;
1063                 break;
1064         case ADC_MODE_HIFI:
1065                 ret = ADC_MODE_VAL_HIFI;
1066                 break;
1067         case ADC_MODE_LO_HIF:
1068                 ret = ADC_MODE_VAL_LO_HIF;
1069                 break;
1070         case ADC_MODE_NORMAL:
1071                 ret = ADC_MODE_VAL_NORMAL;
1072                 break;
1073         case ADC_MODE_LP:
1074                 ret = ADC_MODE_VAL_LP;
1075                 break;
1076         case ADC_MODE_ULP1:
1077                 ret = ADC_MODE_VAL_ULP1;
1078                 break;
1079         case ADC_MODE_ULP2:
1080                 ret = ADC_MODE_VAL_ULP2;
1081                 break;
1082         default:
1083                 ret = -EINVAL;
1084                 break;
1085         }
1086         return ret;
1087 }
1088
1089 static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
1090                                     struct snd_kcontrol *kcontrol, int event)
1091 {
1092         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1093         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1094
1095         switch (event) {
1096         case SND_SOC_DAPM_PRE_PMU:
1097                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1098                                               WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true);
1099                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1100                                               WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1101                                               true);
1102                 set_bit(w->shift, &wcd939x->status_mask);
1103                 break;
1104         case SND_SOC_DAPM_POST_PMD:
1105                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1106                                               WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1107                                               false);
1108                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1109                                               WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN,
1110                                               false);
1111                 clear_bit(w->shift, &wcd939x->status_mask);
1112                 break;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static void wcd939x_tx_channel_config(struct snd_soc_component *component,
1119                                       int channel, bool init)
1120 {
1121         int reg, mask;
1122
1123         switch (channel) {
1124         case 0:
1125                 reg = WCD939X_ANA_TX_CH2;
1126                 mask = WCD939X_TX_CH2_HPF1_INIT;
1127                 break;
1128         case 1:
1129                 reg = WCD939X_ANA_TX_CH2;
1130                 mask = WCD939X_TX_CH2_HPF2_INIT;
1131                 break;
1132         case 2:
1133                 reg = WCD939X_ANA_TX_CH4;
1134                 mask = WCD939X_TX_CH4_HPF3_INIT;
1135                 break;
1136         case 3:
1137                 reg = WCD939X_ANA_TX_CH4;
1138                 mask = WCD939X_TX_CH4_HPF4_INIT;
1139                 break;
1140         default:
1141                 return;
1142         }
1143
1144         snd_soc_component_write_field(component, reg, mask, init);
1145 }
1146
1147 static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w,
1148                                   struct snd_kcontrol *kcontrol, int event)
1149 {
1150         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1151         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1152         int mode;
1153
1154         switch (event) {
1155         case SND_SOC_DAPM_PRE_PMU:
1156                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1157                                               WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true);
1158                 snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1159                                               WCD939X_CDC_REQ_CTL_NO_NOTCH, false);
1160
1161                 wcd939x_tx_channel_config(component, w->shift, true);
1162                 mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
1163                 if (mode < 0) {
1164                         dev_info(component->dev, "Invalid ADC mode\n");
1165                         return -EINVAL;
1166                 }
1167
1168                 switch (w->shift) {
1169                 case 0:
1170                         snd_soc_component_write_field(component,
1171                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1172                                                       WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1173                                                       mode);
1174                         snd_soc_component_write_field(component,
1175                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1176                                                       WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1177                                                       true);
1178                         break;
1179                 case 1:
1180                         snd_soc_component_write_field(component,
1181                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1182                                                       WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1183                                                       mode);
1184                         snd_soc_component_write_field(component,
1185                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1186                                                       WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1187                                                       true);
1188                         break;
1189                 case 2:
1190                         snd_soc_component_write_field(component,
1191                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1192                                                       WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1193                                                       mode);
1194                         snd_soc_component_write_field(component,
1195                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1196                                                       WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1197                                                       true);
1198                         break;
1199                 case 3:
1200                         snd_soc_component_write_field(component,
1201                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1202                                                       WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1203                                                       mode);
1204                         snd_soc_component_write_field(component,
1205                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1206                                                       WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1207                                                       true);
1208                         break;
1209                 default:
1210                         break;
1211                 }
1212
1213                 wcd939x_tx_channel_config(component, w->shift, false);
1214                 break;
1215         case SND_SOC_DAPM_POST_PMD:
1216                 switch (w->shift) {
1217                 case 0:
1218                         snd_soc_component_write_field(component,
1219                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1220                                                       WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1221                                                       false);
1222                         snd_soc_component_write_field(component,
1223                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1224                                                       WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1225                                                       false);
1226                         break;
1227                 case 1:
1228                         snd_soc_component_write_field(component,
1229                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1230                                                       WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1231                                                       false);
1232                         snd_soc_component_write_field(component,
1233                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1234                                                       WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1235                                                       false);
1236                         break;
1237                 case 2:
1238                         snd_soc_component_write_field(component,
1239                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1240                                                       WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1241                                                       false);
1242                         snd_soc_component_write_field(component,
1243                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1244                                                       WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1245                                                       false);
1246                         break;
1247                 case 3:
1248                         snd_soc_component_write_field(component,
1249                                                       WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1250                                                       WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1251                                                       false);
1252                         snd_soc_component_write_field(component,
1253                                                       WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1254                                                       WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1255                                                       false);
1256                         break;
1257                 default:
1258                         break;
1259                 }
1260                 break;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int wcd939x_micbias_control(struct snd_soc_component *component,
1267                                    int micb_num, int req, bool is_dapm)
1268 {
1269         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1270         int micb_index = micb_num - 1;
1271         u16 micb_field;
1272         u16 micb_reg;
1273
1274         switch (micb_num) {
1275         case MIC_BIAS_1:
1276                 micb_reg = WCD939X_ANA_MICB1;
1277                 micb_field = WCD939X_MICB1_ENABLE;
1278                 break;
1279         case MIC_BIAS_2:
1280                 micb_reg = WCD939X_ANA_MICB2;
1281                 micb_field = WCD939X_MICB2_ENABLE;
1282                 break;
1283         case MIC_BIAS_3:
1284                 micb_reg = WCD939X_ANA_MICB3;
1285                 micb_field = WCD939X_MICB3_ENABLE;
1286                 break;
1287         case MIC_BIAS_4:
1288                 micb_reg = WCD939X_ANA_MICB4;
1289                 micb_field = WCD939X_MICB4_ENABLE;
1290                 break;
1291         default:
1292                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
1293                         __func__, micb_num);
1294                 return -EINVAL;
1295         }
1296
1297         switch (req) {
1298         case MICB_PULLUP_ENABLE:
1299                 wcd939x->pullup_ref[micb_index]++;
1300                 if (wcd939x->pullup_ref[micb_index] == 1 &&
1301                     wcd939x->micb_ref[micb_index] == 0)
1302                         snd_soc_component_write_field(component, micb_reg,
1303                                                       micb_field, MICB_BIAS_PULL_UP);
1304                 break;
1305         case MICB_PULLUP_DISABLE:
1306                 if (wcd939x->pullup_ref[micb_index] > 0)
1307                         wcd939x->pullup_ref[micb_index]--;
1308                 if (wcd939x->pullup_ref[micb_index] == 0 &&
1309                     wcd939x->micb_ref[micb_index] == 0)
1310                         snd_soc_component_write_field(component, micb_reg,
1311                                                       micb_field, MICB_BIAS_DISABLE);
1312                 break;
1313         case MICB_ENABLE:
1314                 wcd939x->micb_ref[micb_index]++;
1315                 if (wcd939x->micb_ref[micb_index] == 1) {
1316                         snd_soc_component_write_field(component,
1317                                                 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1318                                                 WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true);
1319                         snd_soc_component_write_field(component,
1320                                                 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1321                                                 WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true);
1322                         snd_soc_component_write_field(component,
1323                                                 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1324                                                 WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true);
1325                         snd_soc_component_write_field(component,
1326                                                 WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1327                                                 WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true);
1328                         snd_soc_component_write_field(component,
1329                                                 WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1330                                                 WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1331                                                 true);
1332                         snd_soc_component_write_field(component,
1333                                                 WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL,
1334                                                 WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN,
1335                                                 true);
1336                         snd_soc_component_write_field(component,
1337                                                 WCD939X_MICB1_TEST_CTL_2,
1338                                                 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1339                         snd_soc_component_write_field(component,
1340                                                 WCD939X_MICB2_TEST_CTL_2,
1341                                                 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1342                         snd_soc_component_write_field(component,
1343                                                 WCD939X_MICB3_TEST_CTL_2,
1344                                                 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1345                         snd_soc_component_write_field(component,
1346                                                 WCD939X_MICB4_TEST_CTL_2,
1347                                                 WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1348                         snd_soc_component_write_field(component, micb_reg, micb_field,
1349                                                       MICB_BIAS_ENABLE);
1350                         if (micb_num == MIC_BIAS_2)
1351                                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1352                                                       WCD_EVENT_POST_MICBIAS_2_ON);
1353                 }
1354                 if (micb_num == MIC_BIAS_2 && is_dapm)
1355                         wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1356                                               WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1357                 break;
1358         case MICB_DISABLE:
1359                 if (wcd939x->micb_ref[micb_index] > 0)
1360                         wcd939x->micb_ref[micb_index]--;
1361
1362                 if (wcd939x->micb_ref[micb_index] == 0 &&
1363                     wcd939x->pullup_ref[micb_index] > 0)
1364                         snd_soc_component_write_field(component, micb_reg,
1365                                                       micb_field, MICB_BIAS_PULL_UP);
1366                 else if (wcd939x->micb_ref[micb_index] == 0 &&
1367                          wcd939x->pullup_ref[micb_index] == 0) {
1368                         if (micb_num  == MIC_BIAS_2)
1369                                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1370                                                       WCD_EVENT_PRE_MICBIAS_2_OFF);
1371
1372                         snd_soc_component_write_field(component, micb_reg,
1373                                                       micb_field, MICB_BIAS_DISABLE);
1374                         if (micb_num  == MIC_BIAS_2)
1375                                 wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1376                                                       WCD_EVENT_POST_MICBIAS_2_OFF);
1377                 }
1378                 if (is_dapm && micb_num  == MIC_BIAS_2)
1379                         wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1380                                               WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1381                 break;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1388                                         struct snd_kcontrol *kcontrol,
1389                                         int event)
1390 {
1391         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1392         int micb_num = w->shift;
1393
1394         switch (event) {
1395         case SND_SOC_DAPM_PRE_PMU:
1396                 wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true);
1397                 break;
1398         case SND_SOC_DAPM_POST_PMU:
1399                 /* 1 msec delay as per HW requirement */
1400                 usleep_range(1000, 1100);
1401                 break;
1402         case SND_SOC_DAPM_POST_PMD:
1403                 wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true);
1404                 break;
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1411                                                struct snd_kcontrol *kcontrol,
1412                                                int event)
1413 {
1414         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1415         int micb_num = w->shift;
1416
1417         switch (event) {
1418         case SND_SOC_DAPM_PRE_PMU:
1419                 wcd939x_micbias_control(component, micb_num,
1420                                         MICB_PULLUP_ENABLE, true);
1421                 break;
1422         case SND_SOC_DAPM_POST_PMU:
1423                 /* 1 msec delay as per HW requirement */
1424                 usleep_range(1000, 1100);
1425                 break;
1426         case SND_SOC_DAPM_POST_PMD:
1427                 wcd939x_micbias_control(component, micb_num,
1428                                         MICB_PULLUP_DISABLE, true);
1429                 break;
1430         }
1431
1432         return 0;
1433 }
1434
1435 static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
1436                                struct snd_ctl_elem_value *ucontrol)
1437 {
1438         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1439         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1440         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1441         int path = e->shift_l;
1442
1443         ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path];
1444
1445         return 0;
1446 }
1447
1448 static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
1449                                struct snd_ctl_elem_value *ucontrol)
1450 {
1451         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1452         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1453         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1454         int path = e->shift_l;
1455
1456         if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0])
1457                 return 0;
1458
1459         wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1460
1461         return 1;
1462 }
1463
1464 /* RX Controls */
1465
1466 static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1467                                    struct snd_ctl_elem_value *ucontrol)
1468 {
1469         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1470         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1471
1472         ucontrol->value.integer.value[0] = wcd939x->hph_mode;
1473
1474         return 0;
1475 }
1476
1477 static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1478                                    struct snd_ctl_elem_value *ucontrol)
1479 {
1480         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1481         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1482         u32 mode_val;
1483
1484         mode_val = ucontrol->value.enumerated.item[0];
1485
1486         if (mode_val == wcd939x->hph_mode)
1487                 return 0;
1488
1489         if (wcd939x->variant == WCD9390) {
1490                 switch (mode_val) {
1491                 case CLS_H_NORMAL:
1492                 case CLS_H_LP:
1493                 case CLS_AB:
1494                 case CLS_H_LOHIFI:
1495                 case CLS_H_ULP:
1496                 case CLS_AB_LP:
1497                 case CLS_AB_LOHIFI:
1498                         wcd939x->hph_mode = mode_val;
1499                         return 1;
1500                 }
1501         } else {
1502                 switch (mode_val) {
1503                 case CLS_H_NORMAL:
1504                 case CLS_H_HIFI:
1505                 case CLS_H_LP:
1506                 case CLS_AB:
1507                 case CLS_H_LOHIFI:
1508                 case CLS_H_ULP:
1509                 case CLS_AB_HIFI:
1510                 case CLS_AB_LP:
1511                 case CLS_AB_LOHIFI:
1512                         wcd939x->hph_mode = mode_val;
1513                         return 1;
1514                 }
1515         }
1516
1517         dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1518         return -EINVAL;
1519 }
1520
1521 static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
1522                                  struct snd_ctl_elem_value *ucontrol)
1523 {
1524         struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1525         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1526         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1527
1528         if (mc->shift)
1529                 ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0;
1530         else
1531                 ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0;
1532
1533         return 0;
1534 }
1535
1536 static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
1537                                  struct snd_ctl_elem_value *ucontrol)
1538 {
1539         struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1540         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1541         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1542         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB];
1543         bool value = !!ucontrol->value.integer.value[0];
1544         int portidx = wcd->ch_info[mc->reg].port_num;
1545
1546         if (mc->shift)
1547                 wcd939x->comp2_enable = value;
1548         else
1549                 wcd939x->comp1_enable = value;
1550
1551         if (value)
1552                 wcd939x_connect_port(wcd, portidx, mc->reg, true);
1553         else
1554                 wcd939x_connect_port(wcd, portidx, mc->reg, false);
1555
1556         return 1;
1557 }
1558
1559 static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
1560                             struct snd_ctl_elem_value *ucontrol)
1561 {
1562         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1563         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1564
1565         ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0;
1566
1567         return 0;
1568 }
1569
1570 static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
1571                             struct snd_ctl_elem_value *ucontrol)
1572 {
1573         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1574         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1575
1576         if (wcd939x->ldoh == !!ucontrol->value.integer.value[0])
1577                 return 0;
1578
1579         wcd939x->ldoh = !!ucontrol->value.integer.value[0];
1580
1581         return 1;
1582 }
1583
1584 static const char * const tx_mode_mux_text_wcd9390[] = {
1585         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1586 };
1587
1588 static const struct soc_enum tx0_mode_mux_enum_wcd9390 =
1589         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1590                         tx_mode_mux_text_wcd9390);
1591
1592 static const struct soc_enum tx1_mode_mux_enum_wcd9390 =
1593         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1594                         tx_mode_mux_text_wcd9390);
1595
1596 static const struct soc_enum tx2_mode_mux_enum_wcd9390 =
1597         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1598                         tx_mode_mux_text_wcd9390);
1599
1600 static const struct soc_enum tx3_mode_mux_enum_wcd9390 =
1601         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1602                         tx_mode_mux_text_wcd9390);
1603
1604 static const char * const tx_mode_mux_text[] = {
1605         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1606         "ADC_ULP1", "ADC_ULP2",
1607 };
1608
1609 static const struct soc_enum tx0_mode_mux_enum =
1610         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
1611                         tx_mode_mux_text);
1612
1613 static const struct soc_enum tx1_mode_mux_enum =
1614         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
1615                         tx_mode_mux_text);
1616
1617 static const struct soc_enum tx2_mode_mux_enum =
1618         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
1619                         tx_mode_mux_text);
1620
1621 static const struct soc_enum tx3_mode_mux_enum =
1622         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
1623                         tx_mode_mux_text);
1624
1625 static const char * const rx_hph_mode_mux_text_wcd9390[] = {
1626         "CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
1627         "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
1628         "CLS_AB_LOHIFI",
1629 };
1630
1631 static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
1632         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
1633                             rx_hph_mode_mux_text_wcd9390);
1634
1635 static const char * const rx_hph_mode_mux_text[] = {
1636         "CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
1637         "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
1638 };
1639
1640 static const struct soc_enum rx_hph_mode_mux_enum =
1641         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
1642                             rx_hph_mode_mux_text);
1643
1644 static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
1645         SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL,
1646                        2, 0x10, 0, ear_pa_gain),
1647
1648         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
1649                      wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1650
1651         SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390,
1652                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1653         SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390,
1654                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1655         SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390,
1656                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1657         SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390,
1658                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1659 };
1660
1661 static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
1662         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1663                      wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1664
1665         SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum,
1666                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1667         SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum,
1668                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1669         SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum,
1670                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1671         SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum,
1672                      wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1673 };
1674
1675 static const struct snd_kcontrol_new adc1_switch[] = {
1676         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1677 };
1678
1679 static const struct snd_kcontrol_new adc2_switch[] = {
1680         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1681 };
1682
1683 static const struct snd_kcontrol_new adc3_switch[] = {
1684         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1685 };
1686
1687 static const struct snd_kcontrol_new adc4_switch[] = {
1688         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1689 };
1690
1691 static const struct snd_kcontrol_new dmic1_switch[] = {
1692         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1693 };
1694
1695 static const struct snd_kcontrol_new dmic2_switch[] = {
1696         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1697 };
1698
1699 static const struct snd_kcontrol_new dmic3_switch[] = {
1700         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1701 };
1702
1703 static const struct snd_kcontrol_new dmic4_switch[] = {
1704         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1705 };
1706
1707 static const struct snd_kcontrol_new dmic5_switch[] = {
1708         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1709 };
1710
1711 static const struct snd_kcontrol_new dmic6_switch[] = {
1712         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1713 };
1714
1715 static const struct snd_kcontrol_new dmic7_switch[] = {
1716         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1717 };
1718
1719 static const struct snd_kcontrol_new dmic8_switch[] = {
1720         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1721 };
1722
1723 static const struct snd_kcontrol_new ear_rdac_switch[] = {
1724         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1725 };
1726
1727 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
1728         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1729 };
1730
1731 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
1732         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1733 };
1734
1735 static const char * const adc1_mux_text[] = {
1736         "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
1737 };
1738
1739 static const struct soc_enum adc1_enum =
1740         SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0,
1741                         ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
1742
1743 static const struct snd_kcontrol_new tx_adc1_mux =
1744         SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
1745
1746 static const char * const adc2_mux_text[] = {
1747         "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
1748 };
1749
1750 static const struct soc_enum adc2_enum =
1751         SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3,
1752                         ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
1753
1754 static const struct snd_kcontrol_new tx_adc2_mux =
1755         SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
1756
1757 static const char * const adc3_mux_text[] = {
1758         "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
1759 };
1760
1761 static const struct soc_enum adc3_enum =
1762         SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0,
1763                         ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
1764
1765 static const struct snd_kcontrol_new tx_adc3_mux =
1766         SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
1767
1768 static const char * const adc4_mux_text[] = {
1769         "CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
1770 };
1771
1772 static const struct soc_enum adc4_enum =
1773         SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3,
1774                         ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
1775
1776 static const struct snd_kcontrol_new tx_adc4_mux =
1777         SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
1778
1779 static const char * const rdac3_mux_text[] = {
1780         "RX3", "RX1"
1781 };
1782
1783 static const struct soc_enum rdac3_enum =
1784         SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0,
1785                         ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
1786
1787 static const struct snd_kcontrol_new rx_rdac3_mux =
1788         SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
1789
1790 static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol,
1791                                 struct snd_ctl_elem_value *ucontrol)
1792 {
1793         struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1794         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1795         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1796         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1797         unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1798
1799         ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0;
1800
1801         return 0;
1802 }
1803
1804 static const char *version_to_str(u32 version)
1805 {
1806         switch (version) {
1807         case WCD939X_VERSION_1_0:
1808                 return __stringify(WCD939X_1_0);
1809         case WCD939X_VERSION_1_1:
1810                 return __stringify(WCD939X_1_1);
1811         case WCD939X_VERSION_2_0:
1812                 return __stringify(WCD939X_2_0);
1813         }
1814         return NULL;
1815 }
1816
1817 static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol,
1818                                 struct snd_ctl_elem_value *ucontrol)
1819 {
1820         struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1821         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1822         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1823         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1824         unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1825
1826         wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0];
1827
1828         wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]);
1829
1830         return 1;
1831 }
1832
1833 /* MBHC Related */
1834
1835 static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component,
1836                                    bool enable)
1837 {
1838         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1,
1839                                       WCD939X_CTL_1_RCO_EN, enable);
1840 }
1841
1842 static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1843                                            bool enable)
1844 {
1845         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
1846                                       WCD939X_MBHC_ELECT_BIAS_EN, enable);
1847 }
1848
1849 static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component,
1850                                          int *btn_low, int *btn_high,
1851                                          int num_btn, bool is_micbias)
1852 {
1853         int i, vth;
1854
1855         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1856                 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1857                         __func__, num_btn);
1858                 return;
1859         }
1860
1861         for (i = 0; i < num_btn; i++) {
1862                 vth = (btn_high[i] * 2) / 25;
1863                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i,
1864                                               WCD939X_MBHC_BTN0_VTH, vth);
1865                 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1866                         __func__, i, btn_high[i], vth);
1867         }
1868 }
1869
1870 static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1871 {
1872
1873         if (micb_num == MIC_BIAS_2) {
1874                 u8 val;
1875
1876                 val = FIELD_GET(WCD939X_MICB2_ENABLE,
1877                                 snd_soc_component_read(component, WCD939X_ANA_MICB2));
1878                 if (val == MICB_BIAS_ENABLE)
1879                         return true;
1880         }
1881
1882         return false;
1883 }
1884
1885 static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1886                                                int pull_up_cur)
1887 {
1888         /* Default pull up current to 2uA */
1889         if (pull_up_cur > HS_PULLUP_I_OFF ||
1890             pull_up_cur < HS_PULLUP_I_3P0_UA ||
1891             pull_up_cur == HS_PULLUP_I_DEFAULT)
1892                 pull_up_cur = HS_PULLUP_I_2P0_UA;
1893
1894         dev_dbg(component->dev, "%s: HS pull up current:%d\n",
1895                 __func__, pull_up_cur);
1896
1897         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT,
1898                                       WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur);
1899 }
1900
1901 static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component,
1902                                         int micb_num, int req)
1903 {
1904         return wcd939x_micbias_control(component, micb_num, req, false);
1905 }
1906
1907 static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1908                                            bool enable)
1909 {
1910         if (enable) {
1911                 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1912                                               WCD939X_MICB2_RAMP_SHIFT_CTL, 3);
1913                 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1914                                               WCD939X_MICB2_RAMP_RAMP_ENABLE, true);
1915         } else {
1916                 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1917                                               WCD939X_MICB2_RAMP_RAMP_ENABLE, false);
1918                 snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1919                                               WCD939X_MICB2_RAMP_SHIFT_CTL, 0);
1920         }
1921 }
1922
1923 static int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
1924 {
1925         /* min micbias voltage is 1V and maximum is 2.85V */
1926         if (micb_mv < 1000 || micb_mv > 2850) {
1927                 pr_err("%s: unsupported micbias voltage\n", __func__);
1928                 return -EINVAL;
1929         }
1930
1931         return (micb_mv - 1000) / 50;
1932 }
1933
1934 static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1935                                             int req_volt, int micb_num)
1936 {
1937         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1938         unsigned int micb_en_field, micb_vout_ctl_field;
1939         unsigned int micb_reg, cur_vout_ctl, micb_en;
1940         int req_vout_ctl;
1941         int ret = 0;
1942
1943         switch (micb_num) {
1944         case MIC_BIAS_1:
1945                 micb_reg = WCD939X_ANA_MICB1;
1946                 micb_en_field = WCD939X_MICB1_ENABLE;
1947                 micb_vout_ctl_field = WCD939X_MICB1_VOUT_CTL;
1948                 break;
1949         case MIC_BIAS_2:
1950                 micb_reg = WCD939X_ANA_MICB2;
1951                 micb_en_field = WCD939X_MICB2_ENABLE;
1952                 micb_vout_ctl_field = WCD939X_MICB2_VOUT_CTL;
1953                 break;
1954         case MIC_BIAS_3:
1955                 micb_reg = WCD939X_ANA_MICB3;
1956                 micb_en_field = WCD939X_MICB3_ENABLE;
1957                 micb_vout_ctl_field = WCD939X_MICB1_VOUT_CTL;
1958                 break;
1959         case MIC_BIAS_4:
1960                 micb_reg = WCD939X_ANA_MICB4;
1961                 micb_en_field = WCD939X_MICB4_ENABLE;
1962                 micb_vout_ctl_field = WCD939X_MICB2_VOUT_CTL;
1963                 break;
1964         default:
1965                 return -EINVAL;
1966         }
1967         mutex_lock(&wcd939x->micb_lock);
1968
1969         /*
1970          * If requested micbias voltage is same as current micbias
1971          * voltage, then just return. Otherwise, adjust voltage as
1972          * per requested value. If micbias is already enabled, then
1973          * to avoid slow micbias ramp-up or down enable pull-up
1974          * momentarily, change the micbias value and then re-enable
1975          * micbias.
1976          */
1977         micb_en = snd_soc_component_read_field(component, micb_reg,
1978                                                micb_en_field);
1979         cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1980                                                     micb_vout_ctl_field);
1981
1982         req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
1983         if (req_vout_ctl < 0) {
1984                 ret = req_vout_ctl;
1985                 goto exit;
1986         }
1987
1988         if (cur_vout_ctl == req_vout_ctl) {
1989                 ret = 0;
1990                 goto exit;
1991         }
1992
1993         dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
1994                 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
1995                  req_volt, micb_en);
1996
1997         if (micb_en == MICB_BIAS_ENABLE)
1998                 snd_soc_component_write_field(component, micb_reg,
1999                                               micb_en_field, MICB_BIAS_PULL_DOWN);
2000
2001         snd_soc_component_write_field(component, micb_reg,
2002                                       micb_vout_ctl_field, req_vout_ctl);
2003
2004         if (micb_en == MICB_BIAS_ENABLE) {
2005                 snd_soc_component_write_field(component, micb_reg,
2006                                               micb_en_field, MICB_BIAS_ENABLE);
2007                 /*
2008                  * Add 2ms delay as per HW requirement after enabling
2009                  * micbias
2010                  */
2011                 usleep_range(2000, 2100);
2012         }
2013
2014 exit:
2015         mutex_unlock(&wcd939x->micb_lock);
2016         return ret;
2017 }
2018
2019 static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2020                                                 int micb_num, bool req_en)
2021 {
2022         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2023         int micb_mv;
2024
2025         if (micb_num != MIC_BIAS_2)
2026                 return -EINVAL;
2027         /*
2028          * If device tree micbias level is already above the minimum
2029          * voltage needed to detect threshold microphone, then do
2030          * not change the micbias, just return.
2031          */
2032         if (wcd939x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2033                 return 0;
2034
2035         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->micb2_mv;
2036
2037         return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2038 }
2039
2040 /* Selected by WCD939X_MBHC_GET_C1() */
2041 static const s16 wcd939x_wcd_mbhc_d1_a[4] = {
2042         0, 30, 30, 6
2043 };
2044
2045 /* Selected by zdet_param.noff */
2046 static const int wcd939x_mbhc_mincode_param[] = {
2047         3277, 1639, 820, 410, 205, 103, 52, 26
2048 };
2049
2050 static const struct zdet_param wcd939x_mbhc_zdet_param = {
2051         .ldo_ctl = 4,
2052         .noff = 0,
2053         .nshift = 6,
2054         .btn5 = 0x18,
2055         .btn6 = 0x60,
2056         .btn7 = 0x78,
2057 };
2058
2059 static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component,
2060                                            int32_t *zdet)
2061 {
2062         const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2063         s32 x1, d1, denom;
2064         int val;
2065         s16 c1;
2066         int i;
2067
2068         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2069                                       WCD939X_MBHC_ZDET_ZDET_CHG_EN, true);
2070         for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) {
2071                 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2072                                                    WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2073                 if (val & BIT(7))
2074                         break;
2075         }
2076         val = val << 8;
2077         val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2078                                             WCD939X_MBHC_RESULT_1_Z_RESULT_LSB);
2079         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2080                                       WCD939X_MBHC_ZDET_ZDET_CHG_EN, false);
2081         x1 = WCD939X_MBHC_GET_X1(val);
2082         c1 = WCD939X_MBHC_GET_C1(val);
2083
2084         /* If ramp is not complete, give additional 5ms */
2085         if (c1 < 2 && x1)
2086                 mdelay(5);
2087
2088         if (!c1 || !x1) {
2089                 dev_dbg(component->dev,
2090                         "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2091                         __func__, c1, x1);
2092                 goto ramp_down;
2093         }
2094
2095         d1 = wcd939x_wcd_mbhc_d1_a[c1];
2096         denom = (x1 * d1) - (1 << (14 - zdet_param->noff));
2097         if (denom > 0)
2098                 *zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom;
2099         else if (x1 <  wcd939x_mbhc_mincode_param[zdet_param->noff])
2100                 *zdet = WCD939X_ZDET_FLOATING_IMPEDANCE;
2101
2102         dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2103                 __func__, d1, c1, x1, *zdet);
2104 ramp_down:
2105         i = 0;
2106         while (x1) {
2107                 val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2108                                                    WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8;
2109                 val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2110                                                     WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2111                 x1 = WCD939X_MBHC_GET_X1(val);
2112                 i++;
2113                 if (i == WCD939X_ZDET_NUM_MEASUREMENTS)
2114                         break;
2115         }
2116 }
2117
2118 static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component,
2119                                    s32 *zl, int32_t *zr)
2120 {
2121         const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2122         s32 zdet = 0;
2123
2124         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2125                                       WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl);
2126         snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH,
2127                                       zdet_param->btn5);
2128         snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH,
2129                                       zdet_param->btn6);
2130         snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH,
2131                                       zdet_param->btn7);
2132         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2133                                       WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff);
2134         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2135                                       WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift);
2136         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2137                                       WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */
2138
2139         if (!zl)
2140                 goto z_right;
2141
2142         /* Start impedance measurement for HPH_L */
2143         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2144                                       WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true);
2145         dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
2146                 __func__, zdet_param->noff);
2147         wcd939x_mbhc_get_result_params(component, &zdet);
2148         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2149                                       WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false);
2150
2151         *zl = zdet;
2152
2153 z_right:
2154         if (!zr)
2155                 return;
2156
2157         /* Start impedance measurement for HPH_R */
2158         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2159                                       WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true);
2160         dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
2161                 __func__, zdet_param->noff);
2162         wcd939x_mbhc_get_result_params(component, &zdet);
2163         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2164                                       WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false);
2165
2166         *zr = zdet;
2167 }
2168
2169 static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2170                                        s32 *z_val, int flag_l_r)
2171 {
2172         int q1_cal;
2173         s16 q1;
2174
2175         q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r);
2176         if (q1 & BIT(7))
2177                 q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10));
2178         else
2179                 q1_cal = (10000 + (q1 * 10));
2180
2181         if (q1_cal > 0)
2182                 *z_val = ((*z_val) * 10000) / q1_cal;
2183 }
2184
2185 static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2186                                             u32 *zl, uint32_t *zr)
2187 {
2188         struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
2189         unsigned int reg0, reg1, reg2, reg3, reg4;
2190         int z_mono, z_diff1, z_diff2;
2191         bool is_fsm_disable = false;
2192         s32 z1l, z1r, z1ls;
2193
2194         reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5);
2195         reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6);
2196         reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7);
2197         reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK);
2198         reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL);
2199
2200         if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT,
2201                                          WCD939X_MBHC_ELECT_FSM_EN)) {
2202                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2203                                               WCD939X_MBHC_ELECT_FSM_EN, false);
2204                 is_fsm_disable = true;
2205         }
2206
2207         /* For NO-jack, disable L_DET_EN before Z-det measurements */
2208         if (wcd939x->mbhc_cfg.hphl_swh)
2209                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2210                                               WCD939X_MBHC_MECH_L_DET_EN, false);
2211
2212         /* Turn off 100k pull down on HPHL */
2213         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2214                                       WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND,
2215                                       false);
2216
2217         /*
2218          * Disable surge protection before impedance detection.
2219          * This is done to give correct value for high impedance.
2220          */
2221         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2222                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
2223         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2224                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
2225
2226         /* 1ms delay needed after disable surge protection */
2227         usleep_range(1000, 1010);
2228
2229         /* First get impedance on Left */
2230         wcd939x_mbhc_zdet_ramp(component, &z1l, NULL);
2231         if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) {
2232                 *zl = WCD939X_ZDET_FLOATING_IMPEDANCE;
2233         } else {
2234                 *zl = z1l / 1000;
2235                 wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0);
2236         }
2237         dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2238                 __func__, *zl);
2239
2240         /* Start of right impedance ramp and calculation */
2241         wcd939x_mbhc_zdet_ramp(component, NULL, &z1r);
2242         if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) {
2243                 *zr = WCD939X_ZDET_FLOATING_IMPEDANCE;
2244         } else {
2245                 *zr = z1r / 1000;
2246                 wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1);
2247         }
2248         dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2249                 __func__, *zr);
2250
2251         /* Mono/stereo detection */
2252         if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE &&
2253             *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) {
2254                 dev_dbg(component->dev,
2255                         "%s: plug type is invalid or extension cable\n",
2256                         __func__);
2257                 goto zdet_complete;
2258         }
2259
2260         if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2261             *zr == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2262             (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) ||
2263             (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) {
2264                 dev_dbg(component->dev,
2265                         "%s: Mono plug type with one ch floating or shorted to GND\n",
2266                         __func__);
2267                 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2268                 goto zdet_complete;
2269         }
2270
2271         snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2272                                       WCD939X_R_ATEST_HPH_GND_OVR, true);
2273         snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2274                                       WCD939X_PA_CTL2_HPHPA_GND_R, true);
2275         wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL);
2276         snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2277                                       WCD939X_PA_CTL2_HPHPA_GND_R, false);
2278         snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2279                                       WCD939X_R_ATEST_HPH_GND_OVR, false);
2280
2281         z1ls /= 1000;
2282         wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
2283
2284         /* Parallel of left Z and 9 ohm pull down resistor */
2285         z_mono = (*zl * 9) / (*zl + 9);
2286         z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls;
2287         z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl;
2288         if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) {
2289                 dev_dbg(component->dev, "%s: stereo plug type detected\n",
2290                         __func__);
2291                 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
2292         } else {
2293                 dev_dbg(component->dev, "%s: MONO plug type detected\n",
2294                         __func__);
2295                 wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2296         }
2297
2298         /* Enable surge protection again after impedance detection */
2299         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2300                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true);
2301         snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2302                                       WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true);
2303
2304 zdet_complete:
2305         snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0);
2306         snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1);
2307         snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2);
2308
2309         /* Turn on 100k pull down on HPHL */
2310         snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2311                                       WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true);
2312
2313         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2314         if (wcd939x->mbhc_cfg.hphl_swh)
2315                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2316                                               WCD939X_MBHC_MECH_L_DET_EN, true);
2317
2318         snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2319         snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3);
2320
2321         if (is_fsm_disable)
2322                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2323                                               WCD939X_MBHC_ELECT_FSM_EN, true);
2324 }
2325
2326 static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2327                                       bool enable)
2328 {
2329         if (enable) {
2330                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2331                                               WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2332                                               true);
2333                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2334                                               WCD939X_MBHC_MECH_GND_DET_EN, true);
2335         } else {
2336                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2337                                               WCD939X_MBHC_MECH_GND_DET_EN, false);
2338                 snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2339                                               WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2340                                               false);
2341         }
2342 }
2343
2344 static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2345                                             bool enable)
2346 {
2347         snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2348                                       WCD939X_PA_CTL2_HPHPA_GND_R, enable);
2349         snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2350                                       WCD939X_PA_CTL2_HPHPA_GND_L, enable);
2351 }
2352
2353 static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component)
2354 {
2355         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2356
2357         if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2358                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2359                                               WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2360                 return;
2361         }
2362
2363         /* Do not enable moisture detection if jack type is NC */
2364         if (!wcd939x->mbhc_cfg.hphl_swh) {
2365                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2366                         __func__);
2367                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2368                                               WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2369                 return;
2370         }
2371
2372         snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2373                                       WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref);
2374 }
2375
2376 static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
2377 {
2378         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2379
2380         if (enable)
2381                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2382                                               WCD939X_CTL_2_M_RTH_CTL,
2383                                               wcd939x->mbhc_cfg.moist_rref);
2384         else
2385                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2386                                               WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2387 }
2388
2389 static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component)
2390 {
2391         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2392         bool ret = false;
2393
2394         if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2395                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2396                                               WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2397                 goto done;
2398         }
2399
2400         /* Do not enable moisture detection if jack type is NC */
2401         if (!wcd939x->mbhc_cfg.hphl_swh) {
2402                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2403                         __func__);
2404                 snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2405                                               WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2406                 goto done;
2407         }
2408
2409         /*
2410          * If moisture_en is already enabled, then skip to plug type
2411          * detection.
2412          */
2413         if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2,
2414                                          WCD939X_CTL_2_M_RTH_CTL))
2415                 goto done;
2416
2417         wcd939x_mbhc_moisture_detect_en(component, true);
2418
2419         /* Read moisture comparator status, invert of status bit */
2420         ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS,
2421                                             WCD939X_FSM_STATUS_HS_M_COMP_STATUS);
2422 done:
2423         return ret;
2424 }
2425
2426 static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
2427                                                bool enable)
2428 {
2429         snd_soc_component_write_field(component,
2430                                       WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
2431                                       WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING,
2432                                       enable);
2433 }
2434
2435 static const struct wcd_mbhc_cb mbhc_cb = {
2436         .clk_setup = wcd939x_mbhc_clk_setup,
2437         .mbhc_bias = wcd939x_mbhc_mbhc_bias_control,
2438         .set_btn_thr = wcd939x_mbhc_program_btn_thr,
2439         .micbias_enable_status = wcd939x_mbhc_micb_en_status,
2440         .hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control,
2441         .mbhc_micbias_control = wcd939x_mbhc_request_micbias,
2442         .mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control,
2443         .mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic,
2444         .compute_impedance = wcd939x_wcd_mbhc_calc_impedance,
2445         .mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl,
2446         .hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl,
2447         .mbhc_moisture_config = wcd939x_mbhc_moisture_config,
2448         .mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status,
2449         .mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl,
2450         .mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en,
2451 };
2452
2453 static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol,
2454                                 struct snd_ctl_elem_value *ucontrol)
2455 {
2456         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2457         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2458
2459         ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc);
2460
2461         return 0;
2462 }
2463
2464 static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2465                                      struct snd_ctl_elem_value *ucontrol)
2466 {
2467         struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
2468         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2469         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2470         bool hphr = mc->shift;
2471         u32 zl, zr;
2472
2473         wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr);
2474         dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2475         ucontrol->value.integer.value[0] = hphr ? zr : zl;
2476
2477         return 0;
2478 }
2479
2480 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2481         SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
2482                        wcd939x_get_hph_type, NULL),
2483 };
2484
2485 static const struct snd_kcontrol_new impedance_detect_controls[] = {
2486         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
2487                        wcd939x_hph_impedance_get, NULL),
2488         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
2489                        wcd939x_hph_impedance_get, NULL),
2490 };
2491
2492 static int wcd939x_mbhc_init(struct snd_soc_component *component)
2493 {
2494         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2495         struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids;
2496
2497         intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2498                                                      WCD939X_IRQ_MBHC_SW_DET);
2499         intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2500                                                             WCD939X_IRQ_MBHC_BUTTON_PRESS_DET);
2501         intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2502                                                               WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET);
2503         intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2504                                                          WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2505         intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2506                                                          WCD939X_IRQ_MBHC_ELECT_INS_REM_DET);
2507         intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2508                                                      WCD939X_IRQ_HPHL_OCP_INT);
2509         intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2510                                                       WCD939X_IRQ_HPHR_OCP_INT);
2511
2512         wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2513         if (IS_ERR(wcd939x->wcd_mbhc))
2514                 return PTR_ERR(wcd939x->wcd_mbhc);
2515
2516         snd_soc_add_component_controls(component, impedance_detect_controls,
2517                                        ARRAY_SIZE(impedance_detect_controls));
2518         snd_soc_add_component_controls(component, hph_type_detect_controls,
2519                                        ARRAY_SIZE(hph_type_detect_controls));
2520
2521         return 0;
2522 }
2523
2524 static void wcd939x_mbhc_deinit(struct snd_soc_component *component)
2525 {
2526         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2527
2528         wcd_mbhc_deinit(wcd939x->wcd_mbhc);
2529 }
2530
2531 /* END MBHC */
2532
2533 static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
2534         /* RX Path */
2535         SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0,
2536                        wcd939x_get_compander, wcd939x_set_compander),
2537         SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0,
2538                        wcd939x_get_compander, wcd939x_set_compander),
2539         SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0,
2540                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2541         SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0,
2542                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2543         SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0,
2544                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2545         SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0,
2546                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2547         SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0,
2548                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2549         SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0,
2550                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2551         SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain),
2552         SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain),
2553         SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2554                        wcd939x_ldoh_get, wcd939x_ldoh_put),
2555
2556         /* TX Path */
2557         SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0,
2558                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2559         SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0,
2560                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2561         SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0,
2562                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2563         SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0,
2564                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2565         SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0,
2566                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2567         SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0,
2568                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2569         SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0,
2570                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2571         SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0,
2572                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2573         SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0,
2574                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2575         SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0,
2576                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2577         SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0,
2578                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2579         SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0,
2580                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2581         SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0,
2582                        wcd939x_get_swr_port, wcd939x_set_swr_port),
2583         SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0,
2584                        analog_gain),
2585         SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0,
2586                        analog_gain),
2587         SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0,
2588                        analog_gain),
2589         SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0,
2590                        analog_gain),
2591 };
2592
2593 static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
2594         /*input widgets*/
2595         SND_SOC_DAPM_INPUT("AMIC1"),
2596         SND_SOC_DAPM_INPUT("AMIC2"),
2597         SND_SOC_DAPM_INPUT("AMIC3"),
2598         SND_SOC_DAPM_INPUT("AMIC4"),
2599         SND_SOC_DAPM_INPUT("AMIC5"),
2600
2601         SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2602         SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2603         SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2604         SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2605         SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2606
2607         /* TX widgets */
2608         SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2609                            wcd939x_codec_enable_adc,
2610                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2611         SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2612                            wcd939x_codec_enable_adc,
2613                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2614         SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2615                            wcd939x_codec_enable_adc,
2616                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2617         SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2618                            wcd939x_codec_enable_adc,
2619                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2620         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2621                            wcd939x_codec_enable_dmic,
2622                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2623         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2624                            wcd939x_codec_enable_dmic,
2625                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2626         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2627                            wcd939x_codec_enable_dmic,
2628                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2629         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2630                            wcd939x_codec_enable_dmic,
2631                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2632         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2633                            wcd939x_codec_enable_dmic,
2634                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2635         SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2636                            wcd939x_codec_enable_dmic,
2637                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2638         SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2639                            wcd939x_codec_enable_dmic,
2640                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2641         SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2642                            wcd939x_codec_enable_dmic,
2643                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2644
2645         SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0,
2646                              wcd939x_adc_enable_req,
2647                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2648         SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0,
2649                              wcd939x_adc_enable_req,
2650                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2651         SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0,
2652                              wcd939x_adc_enable_req,
2653                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2654         SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2655                              wcd939x_adc_enable_req,
2656                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2657
2658         SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux),
2659         SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2660         SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2661         SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2662
2663         /* tx mixers */
2664         SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2665                              adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl,
2666                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2667         SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
2668                              adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl,
2669                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2670         SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0,
2671                              adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
2672                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2673         SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0,
2674                              adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
2675                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2676         SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0,
2677                              dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl,
2678                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2679         SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0,
2680                              dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl,
2681                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2682         SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0,
2683                              dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl,
2684                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2685         SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0,
2686                              dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl,
2687                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2688         SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0,
2689                              dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl,
2690                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2691         SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0,
2692                              dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl,
2693                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2694         SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0,
2695                              dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl,
2696                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2697         SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0,
2698                              dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl,
2699                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2700
2701         /* micbias widgets */
2702         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2703                             wcd939x_codec_enable_micbias,
2704                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2705                             SND_SOC_DAPM_POST_PMD),
2706         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2707                             wcd939x_codec_enable_micbias,
2708                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2709                             SND_SOC_DAPM_POST_PMD),
2710         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2711                             wcd939x_codec_enable_micbias,
2712                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2713                             SND_SOC_DAPM_POST_PMD),
2714         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2715                             wcd939x_codec_enable_micbias,
2716                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2717                             SND_SOC_DAPM_POST_PMD),
2718
2719         /* micbias pull up widgets */
2720         SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2721                             wcd939x_codec_enable_micbias_pullup,
2722                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2723                             SND_SOC_DAPM_POST_PMD),
2724         SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2725                             wcd939x_codec_enable_micbias_pullup,
2726                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2727                             SND_SOC_DAPM_POST_PMD),
2728         SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2729                             wcd939x_codec_enable_micbias_pullup,
2730                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2731                             SND_SOC_DAPM_POST_PMD),
2732         SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2733                             wcd939x_codec_enable_micbias_pullup,
2734                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2735                             SND_SOC_DAPM_POST_PMD),
2736
2737         /* output widgets tx */
2738         SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2739         SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2740         SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2741         SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
2742         SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2743         SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2744         SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2745         SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2746         SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2747         SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2748         SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
2749         SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
2750
2751         SND_SOC_DAPM_INPUT("IN1_HPHL"),
2752         SND_SOC_DAPM_INPUT("IN2_HPHR"),
2753         SND_SOC_DAPM_INPUT("IN3_EAR"),
2754
2755         /* rx widgets */
2756         SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0,
2757                            wcd939x_codec_enable_ear_pa,
2758                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2759                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2760         SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0,
2761                            wcd939x_codec_enable_hphl_pa,
2762                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2763                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2764         SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0,
2765                            wcd939x_codec_enable_hphr_pa,
2766                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2767                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2768
2769         SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2770                            wcd939x_codec_hphl_dac_event,
2771                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2772                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2773         SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2774                            wcd939x_codec_hphr_dac_event,
2775                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2776                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2777         SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2778                            wcd939x_codec_ear_dac_event,
2779                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2780                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2781
2782         SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2783
2784         SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2785         SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2786                             wcd939x_codec_enable_rxclk,
2787                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2788                             SND_SOC_DAPM_POST_PMD),
2789
2790         SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2791
2792         SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2793         SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2794         SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2795
2796         /* rx mixer widgets */
2797         SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2798                            ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2799         SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2800                            hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2801         SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2802                            hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2803
2804         /* output widgets rx */
2805         SND_SOC_DAPM_OUTPUT("EAR"),
2806         SND_SOC_DAPM_OUTPUT("HPHL"),
2807         SND_SOC_DAPM_OUTPUT("HPHR"),
2808 };
2809
2810 static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
2811         /* TX Path */
2812         {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
2813         {"ADC1_MIXER", "Switch", "ADC1 REQ"},
2814         {"ADC1 REQ", NULL, "ADC1"},
2815         {"ADC1", NULL, "ADC1 MUX"},
2816         {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
2817         {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
2818         {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
2819         {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
2820         {"ADC1 MUX", "CH1_AMIC5", "AMIC5"},
2821
2822         {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
2823         {"ADC2_MIXER", "Switch", "ADC2 REQ"},
2824         {"ADC2 REQ", NULL, "ADC2"},
2825         {"ADC2", NULL, "ADC2 MUX"},
2826         {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
2827         {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
2828         {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
2829         {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
2830         {"ADC2 MUX", "CH2_AMIC5", "AMIC5"},
2831
2832         {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
2833         {"ADC3_MIXER", "Switch", "ADC3 REQ"},
2834         {"ADC3 REQ", NULL, "ADC3"},
2835         {"ADC3", NULL, "ADC3 MUX"},
2836         {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
2837         {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
2838         {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
2839         {"ADC3 MUX", "CH3_AMIC5", "AMIC5"},
2840
2841         {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
2842         {"ADC4_MIXER", "Switch", "ADC4 REQ"},
2843         {"ADC4 REQ", NULL, "ADC4"},
2844         {"ADC4", NULL, "ADC4 MUX"},
2845         {"ADC4 MUX", "CH4_AMIC1", "AMIC1"},
2846         {"ADC4 MUX", "CH4_AMIC3", "AMIC3"},
2847         {"ADC4 MUX", "CH4_AMIC4", "AMIC4"},
2848         {"ADC4 MUX", "CH4_AMIC5", "AMIC5"},
2849
2850         {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
2851         {"DMIC1_MIXER", "Switch", "DMIC1"},
2852
2853         {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
2854         {"DMIC2_MIXER", "Switch", "DMIC2"},
2855
2856         {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
2857         {"DMIC3_MIXER", "Switch", "DMIC3"},
2858
2859         {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
2860         {"DMIC4_MIXER", "Switch", "DMIC4"},
2861
2862         {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
2863         {"DMIC5_MIXER", "Switch", "DMIC5"},
2864
2865         {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
2866         {"DMIC6_MIXER", "Switch", "DMIC6"},
2867
2868         {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
2869         {"DMIC7_MIXER", "Switch", "DMIC7"},
2870
2871         {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
2872         {"DMIC8_MIXER", "Switch", "DMIC8"},
2873
2874         /* RX Path */
2875         {"IN1_HPHL", NULL, "VDD_BUCK"},
2876         {"IN1_HPHL", NULL, "CLS_H_PORT"},
2877
2878         {"RX1", NULL, "IN1_HPHL"},
2879         {"RX1", NULL, "RXCLK"},
2880         {"RDAC1", NULL, "RX1"},
2881         {"HPHL_RDAC", "Switch", "RDAC1"},
2882         {"HPHL PGA", NULL, "HPHL_RDAC"},
2883         {"HPHL", NULL, "HPHL PGA"},
2884
2885         {"IN2_HPHR", NULL, "VDD_BUCK"},
2886         {"IN2_HPHR", NULL, "CLS_H_PORT"},
2887         {"RX2", NULL, "IN2_HPHR"},
2888         {"RDAC2", NULL, "RX2"},
2889         {"RX2", NULL, "RXCLK"},
2890         {"HPHR_RDAC", "Switch", "RDAC2"},
2891         {"HPHR PGA", NULL, "HPHR_RDAC"},
2892         {"HPHR", NULL, "HPHR PGA"},
2893
2894         {"IN3_EAR", NULL, "VDD_BUCK"},
2895         {"RX3", NULL, "IN3_EAR"},
2896         {"RX3", NULL, "RXCLK"},
2897
2898         {"RDAC3_MUX", "RX3", "RX3"},
2899         {"RDAC3_MUX", "RX1", "RX1"},
2900         {"RDAC3", NULL, "RDAC3_MUX"},
2901         {"EAR_RDAC", "Switch", "RDAC3"},
2902         {"EAR PGA", NULL, "EAR_RDAC"},
2903         {"EAR", NULL, "EAR PGA"},
2904 };
2905
2906 static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x)
2907 {
2908         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2909
2910         /* set micbias voltage */
2911         vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb1_mv);
2912         vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb2_mv);
2913         vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb3_mv);
2914         vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb4_mv);
2915         if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
2916                 return -EINVAL;
2917
2918         regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1,
2919                            WCD939X_MICB1_VOUT_CTL, vout_ctl_1);
2920         regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2,
2921                            WCD939X_MICB2_VOUT_CTL, vout_ctl_2);
2922         regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3,
2923                            WCD939X_MICB3_VOUT_CTL, vout_ctl_3);
2924         regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4,
2925                            WCD939X_MICB4_VOUT_CTL, vout_ctl_4);
2926
2927         return 0;
2928 }
2929
2930 static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
2931 {
2932         /*
2933          * HPHR/HPHL/EAR Watchdog interrupt threaded handler
2934          *
2935          * Watchdog interrupts are expected to be enabled when switching
2936          * on the HPHL/R and EAR RX PGA in order to make sure the interrupts
2937          * are acked by the regmap_irq handler to allow PDM sync.
2938          * We could leave those interrupts masked but we would not have
2939          * any valid way to enable/disable them without violating irq layers.
2940          *
2941          * The HPHR/HPHL/EAR Watchdog interrupts are handled
2942          * by regmap_irq, so requesting a threaded handler is the
2943          * safest way to be able to ack those interrupts without
2944          * colliding with the regmap_irq setup.
2945          */
2946
2947         return IRQ_HANDLED;
2948 }
2949
2950 /*
2951  * Setup a virtual interrupt domain to hook regmap_irq
2952  * The root domain will have a single interrupt which mapping
2953  * will trigger the regmap_irq handler.
2954  *
2955  * root:
2956  *   wcd_irq_chip
2957  *     [0] wcd939x_regmap_irq_chip
2958  *       [0] MBHC_BUTTON_PRESS_DET
2959  *       [1] MBHC_BUTTON_RELEASE_DET
2960  *       ...
2961  *       [16] HPHR_SURGE_DET_INT
2962  *
2963  * Interrupt trigger:
2964  *   soundwire_interrupt_callback()
2965  *   \-handle_nested_irq(0)
2966  *     \- regmap_irq_thread()
2967  *         \- handle_nested_irq(i)
2968  */
2969 static struct irq_chip wcd_irq_chip = {
2970         .name = "WCD939x",
2971 };
2972
2973 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2974                             irq_hw_number_t hw)
2975 {
2976         irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2977         irq_set_nested_thread(virq, 1);
2978         irq_set_noprobe(virq);
2979
2980         return 0;
2981 }
2982
2983 static const struct irq_domain_ops wcd_domain_ops = {
2984         .map = wcd_irq_chip_map,
2985 };
2986
2987 static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev)
2988 {
2989         wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
2990         if (!(wcd->virq)) {
2991                 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2992                 return -EINVAL;
2993         }
2994
2995         return devm_regmap_add_irq_chip(dev, wcd->regmap,
2996                                         irq_create_mapping(wcd->virq, 0),
2997                                         IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip,
2998                                         &wcd->irq_chip);
2999 }
3000
3001 static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
3002 {
3003         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3004         struct sdw_slave *tx_sdw_dev = wcd939x->tx_sdw_dev;
3005         struct device *dev = component->dev;
3006         unsigned long time_left;
3007         int ret, i;
3008
3009         time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
3010                                                 msecs_to_jiffies(2000));
3011         if (!time_left) {
3012                 dev_err(dev, "soundwire device init timeout\n");
3013                 return -ETIMEDOUT;
3014         }
3015
3016         snd_soc_component_init_regmap(component, wcd939x->regmap);
3017
3018         ret = pm_runtime_resume_and_get(dev);
3019         if (ret < 0)
3020                 return ret;
3021
3022         wcd939x->variant = snd_soc_component_read_field(component,
3023                                                         WCD939X_DIGITAL_EFUSE_REG_0,
3024                                                         WCD939X_EFUSE_REG_0_WCD939X_ID);
3025
3026         wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X);
3027         if (IS_ERR(wcd939x->clsh_info)) {
3028                 pm_runtime_put(dev);
3029                 return PTR_ERR(wcd939x->clsh_info);
3030         }
3031
3032         wcd939x_io_init(component);
3033
3034         /* Set all interrupts as edge triggered */
3035         for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
3036                 regmap_write(wcd939x->regmap,
3037                              (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0);
3038
3039         pm_runtime_put(dev);
3040
3041         /* Request for watchdog interrupt */
3042         wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3043                                                        WCD939X_IRQ_HPHR_PDM_WD_INT);
3044         wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3045                                                        WCD939X_IRQ_HPHL_PDM_WD_INT);
3046         wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3047                                                       WCD939X_IRQ_EAR_PDM_WD_INT);
3048
3049         ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3050                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3051                                    "HPHR PDM WD INT", wcd939x);
3052         if (ret) {
3053                 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3054                 goto err_free_clsh_ctrl;
3055         }
3056
3057         ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3058                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3059                                    "HPHL PDM WD INT", wcd939x);
3060         if (ret) {
3061                 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3062                 goto err_free_hphr_pdm_wd_int;
3063         }
3064
3065         ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3066                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3067                                    "AUX PDM WD INT", wcd939x);
3068         if (ret) {
3069                 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3070                 goto err_free_hphl_pdm_wd_int;
3071         }
3072
3073         /* Disable watchdog interrupt for HPH and AUX */
3074         disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
3075         disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
3076         disable_irq_nosync(wcd939x->ear_pdm_wd_int);
3077
3078         switch (wcd939x->variant) {
3079         case WCD9390:
3080                 ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
3081                                                      ARRAY_SIZE(wcd9390_snd_controls));
3082                 if (ret < 0) {
3083                         dev_err(component->dev,
3084                                 "%s: Failed to add snd ctrls for variant: %d\n",
3085                                 __func__, wcd939x->variant);
3086                         goto err_free_ear_pdm_wd_int;
3087                 }
3088                 break;
3089         case WCD9395:
3090                 ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
3091                                                      ARRAY_SIZE(wcd9395_snd_controls));
3092                 if (ret < 0) {
3093                         dev_err(component->dev,
3094                                 "%s: Failed to add snd ctrls for variant: %d\n",
3095                                 __func__, wcd939x->variant);
3096                         goto err_free_ear_pdm_wd_int;
3097                 }
3098                 break;
3099         default:
3100                 break;
3101         }
3102
3103         ret = wcd939x_mbhc_init(component);
3104         if (ret) {
3105                 dev_err(component->dev,  "mbhc initialization failed\n");
3106                 goto err_free_ear_pdm_wd_int;
3107         }
3108
3109         return 0;
3110
3111 err_free_ear_pdm_wd_int:
3112         free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3113 err_free_hphl_pdm_wd_int:
3114         free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3115 err_free_hphr_pdm_wd_int:
3116         free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3117 err_free_clsh_ctrl:
3118         wcd_clsh_ctrl_free(wcd939x->clsh_info);
3119
3120         return ret;
3121 }
3122
3123 static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
3124 {
3125         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3126
3127         wcd939x_mbhc_deinit(component);
3128
3129         free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3130         free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3131         free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3132
3133         wcd_clsh_ctrl_free(wcd939x->clsh_info);
3134 }
3135
3136 static int wcd939x_codec_set_jack(struct snd_soc_component *comp,
3137                                   struct snd_soc_jack *jack, void *data)
3138 {
3139         struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev);
3140
3141         if (jack)
3142                 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
3143
3144         wcd_mbhc_stop(wcd->wcd_mbhc);
3145
3146         return 0;
3147 }
3148
3149 static const struct snd_soc_component_driver soc_codec_dev_wcd939x = {
3150         .name = "wcd939x_codec",
3151         .probe = wcd939x_soc_codec_probe,
3152         .remove = wcd939x_soc_codec_remove,
3153         .controls = wcd939x_snd_controls,
3154         .num_controls = ARRAY_SIZE(wcd939x_snd_controls),
3155         .dapm_widgets = wcd939x_dapm_widgets,
3156         .num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
3157         .dapm_routes = wcd939x_audio_map,
3158         .num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
3159         .set_jack = wcd939x_codec_set_jack,
3160         .endianness = 1,
3161 };
3162
3163 #if IS_ENABLED(CONFIG_TYPEC)
3164 /* Get USB-C plug orientation to provide swap event for MBHC */
3165 static int wcd939x_typec_switch_set(struct typec_switch_dev *sw,
3166                                     enum typec_orientation orientation)
3167 {
3168         struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw);
3169
3170         wcd939x->typec_orientation = orientation;
3171
3172         return 0;
3173 }
3174
3175 static int wcd939x_typec_mux_set(struct typec_mux_dev *mux,
3176                                  struct typec_mux_state *state)
3177 {
3178         struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux);
3179         unsigned int previous_mode = wcd939x->typec_mode;
3180
3181         if (!wcd939x->wcd_mbhc)
3182                 return -EINVAL;
3183
3184         if (wcd939x->typec_mode != state->mode) {
3185                 wcd939x->typec_mode = state->mode;
3186
3187                 if (wcd939x->typec_mode == TYPEC_MODE_AUDIO)
3188                         return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc);
3189                 else if (previous_mode == TYPEC_MODE_AUDIO)
3190                         return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc);
3191         }
3192
3193         return 0;
3194 }
3195 #endif /* CONFIG_TYPEC */
3196
3197 static void wcd939x_dt_parse_micbias_info(struct device *dev, struct wcd939x_priv *wcd)
3198 {
3199         struct device_node *np = dev->of_node;
3200         u32 prop_val = 0;
3201         int rc = 0;
3202
3203         rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
3204         if (!rc)
3205                 wcd->micb1_mv = prop_val / 1000;
3206         else
3207                 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3208
3209         rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
3210         if (!rc)
3211                 wcd->micb2_mv = prop_val / 1000;
3212         else
3213                 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3214
3215         rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3216         if (!rc)
3217                 wcd->micb3_mv = prop_val / 1000;
3218         else
3219                 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3220
3221         rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
3222         if (!rc)
3223                 wcd->micb4_mv = prop_val / 1000;
3224         else
3225                 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3226 }
3227
3228 #if IS_ENABLED(CONFIG_TYPEC)
3229 static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component, bool active)
3230 {
3231         struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3232
3233         if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch)
3234                 return false;
3235
3236         /* Report inversion via Type Switch of USBSS */
3237         typec_switch_set(wcd939x->typec_switch,
3238                          wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ?
3239                                 TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE);
3240
3241         return true;
3242 }
3243 #endif /* CONFIG_TYPEC */
3244
3245 static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev)
3246 {
3247         struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg;
3248 #if IS_ENABLED(CONFIG_TYPEC)
3249         struct device_node *np;
3250 #endif /* CONFIG_TYPEC */
3251         int ret;
3252
3253         wcd939x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
3254         if (wcd939x->reset_gpio < 0)
3255                 return dev_err_probe(dev, wcd939x->reset_gpio,
3256                                      "Failed to get reset gpio\n");
3257
3258         wcd939x->supplies[0].supply = "vdd-rxtx";
3259         wcd939x->supplies[1].supply = "vdd-io";
3260         wcd939x->supplies[2].supply = "vdd-buck";
3261         wcd939x->supplies[3].supply = "vdd-mic-bias";
3262
3263         ret = regulator_bulk_get(dev, WCD939X_MAX_SUPPLY, wcd939x->supplies);
3264         if (ret)
3265                 return dev_err_probe(dev, ret, "Failed to get supplies\n");
3266
3267         ret = regulator_bulk_enable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3268         if (ret) {
3269                 regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3270                 return dev_err_probe(dev, ret, "Failed to enable supplies\n");
3271         }
3272
3273         wcd939x_dt_parse_micbias_info(dev, wcd939x);
3274
3275         cfg->mbhc_micbias = MIC_BIAS_2;
3276         cfg->anc_micbias = MIC_BIAS_2;
3277         cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
3278         cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS;
3279         cfg->micb_mv = wcd939x->micb2_mv;
3280         cfg->linein_th = 5000;
3281         cfg->hs_thr = 1700;
3282         cfg->hph_thr = 50;
3283
3284         wcd_dt_parse_mbhc_data(dev, cfg);
3285
3286 #if IS_ENABLED(CONFIG_TYPEC)
3287         /*
3288          * Is node has a port and a valid remote endpoint
3289          * consider HP lines are connected to the USBSS part
3290          */
3291         np = of_graph_get_remote_node(dev->of_node, 0, 0);
3292         if (np) {
3293                 wcd939x->typec_analog_mux = true;
3294                 cfg->typec_analog_mux = true;
3295                 cfg->swap_gnd_mic = wcd939x_swap_gnd_mic;
3296         }
3297 #endif /* CONFIG_TYPEC */
3298
3299         return 0;
3300 }
3301
3302 static int wcd939x_reset(struct wcd939x_priv *wcd939x)
3303 {
3304         gpio_direction_output(wcd939x->reset_gpio, 0);
3305         /* 20us sleep required after pulling the reset gpio to LOW */
3306         usleep_range(20, 30);
3307         gpio_set_value(wcd939x->reset_gpio, 1);
3308         /* 20us sleep required after pulling the reset gpio to HIGH */
3309         usleep_range(20, 30);
3310
3311         return 0;
3312 }
3313
3314 static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream,
3315                                    struct snd_pcm_hw_params *params,
3316                                 struct snd_soc_dai *dai)
3317 {
3318         struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3319         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3320
3321         return wcd939x_sdw_hw_params(wcd, substream, params, dai);
3322 }
3323
3324 static int wcd939x_codec_free(struct snd_pcm_substream *substream,
3325                               struct snd_soc_dai *dai)
3326 {
3327         struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3328         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3329
3330         return wcd939x_sdw_free(wcd, substream, dai);
3331 }
3332
3333 static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3334                                         void *stream, int direction)
3335 {
3336         struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3337         struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3338
3339         return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3340 }
3341
3342 static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = {
3343         .hw_params = wcd939x_codec_hw_params,
3344         .hw_free = wcd939x_codec_free,
3345         .set_stream = wcd939x_codec_set_sdw_stream,
3346 };
3347
3348 static struct snd_soc_dai_driver wcd939x_dais[] = {
3349         [0] = {
3350                 .name = "wcd939x-sdw-rx",
3351                 .playback = {
3352                         .stream_name = "WCD AIF1 Playback",
3353                         .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3354                         .formats = WCD939X_FORMATS,
3355                         .rate_max = 384000,
3356                         .rate_min = 8000,
3357                         .channels_min = 1,
3358                         .channels_max = 2,
3359                 },
3360                 .ops = &wcd939x_sdw_dai_ops,
3361         },
3362         [1] = {
3363                 .name = "wcd939x-sdw-tx",
3364                 .capture = {
3365                         .stream_name = "WCD AIF1 Capture",
3366                         .rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3367                         .formats = WCD939X_FORMATS,
3368                         .rate_min = 8000,
3369                         .rate_max = 384000,
3370                         .channels_min = 1,
3371                         .channels_max = 4,
3372                 },
3373                 .ops = &wcd939x_sdw_dai_ops,
3374         },
3375 };
3376
3377 static int wcd939x_bind(struct device *dev)
3378 {
3379         struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3380         unsigned int version, id1, status1;
3381         int ret;
3382
3383 #if IS_ENABLED(CONFIG_TYPEC)
3384         /*
3385          * Get USBSS type-c switch to send gnd/mic swap events
3386          * typec_switch is fetched now to avoid a probe deadlock since
3387          * the USBSS depends on the typec_mux register in wcd939x_probe()
3388          */
3389         if (wcd939x->typec_analog_mux) {
3390                 wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode);
3391                 if (IS_ERR(wcd939x->typec_switch))
3392                         return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch),
3393                                              "failed to acquire orientation-switch\n");
3394         }
3395 #endif /* CONFIG_TYPEC */
3396
3397         ret = component_bind_all(dev, wcd939x);
3398         if (ret) {
3399                 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3400                         __func__, ret);
3401                 goto err_put_typec_switch;
3402         }
3403
3404         wcd939x->rxdev = wcd939x_sdw_device_get(wcd939x->rxnode);
3405         if (!wcd939x->rxdev) {
3406                 dev_err(dev, "could not find slave with matching of node\n");
3407                 ret = -EINVAL;
3408                 goto err_unbind;
3409         }
3410         wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev);
3411         wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x;
3412
3413         wcd939x->txdev = wcd939x_sdw_device_get(wcd939x->txnode);
3414         if (!wcd939x->txdev) {
3415                 dev_err(dev, "could not find txslave with matching of node\n");
3416                 ret = -EINVAL;
3417                 goto err_put_rxdev;
3418         }
3419         wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev);
3420         wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x;
3421         wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev);
3422
3423         /*
3424          * As TX is main CSR reg interface, which should not be suspended first.
3425          * explicitly add the dependency link
3426          */
3427         if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS |
3428                             DL_FLAG_PM_RUNTIME)) {
3429                 dev_err(dev, "could not devlink tx and rx\n");
3430                 ret = -EINVAL;
3431                 goto err_put_txdev;
3432         }
3433
3434         if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS |
3435                                         DL_FLAG_PM_RUNTIME)) {
3436                 dev_err(dev, "could not devlink wcd and tx\n");
3437                 ret = -EINVAL;
3438                 goto err_remove_rxtx_link;
3439         }
3440
3441         if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS |
3442                                         DL_FLAG_PM_RUNTIME)) {
3443                 dev_err(dev, "could not devlink wcd and rx\n");
3444                 ret = -EINVAL;
3445                 goto err_remove_tx_link;
3446         }
3447
3448         /* Get regmap from TX SoundWire device */
3449         wcd939x->regmap = wcd939x_swr_get_regmap(wcd939x->sdw_priv[AIF1_CAP]);
3450         if (IS_ERR(wcd939x->regmap)) {
3451                 dev_err(dev, "could not get TX device regmap\n");
3452                 ret = PTR_ERR(wcd939x->regmap);
3453                 goto err_remove_rx_link;
3454         }
3455
3456         ret = wcd939x_irq_init(wcd939x, dev);
3457         if (ret) {
3458                 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3459                 goto err_remove_rx_link;
3460         }
3461
3462         wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq;
3463         wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq;
3464
3465         ret = wcd939x_set_micbias_data(wcd939x);
3466         if (ret < 0) {
3467                 dev_err(dev, "%s: bad micbias pdata\n", __func__);
3468                 goto err_remove_rx_link;
3469         }
3470
3471         /* Check WCD9395 version */
3472         regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1);
3473         regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1);
3474
3475         if (id1 == 0)
3476                 version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
3477         else
3478                 version = WCD939X_VERSION_2_0;
3479
3480         dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version));
3481
3482         ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
3483                                          wcd939x_dais, ARRAY_SIZE(wcd939x_dais));
3484         if (ret) {
3485                 dev_err(dev, "%s: Codec registration failed\n",
3486                         __func__);
3487                 goto err_remove_rx_link;
3488         }
3489
3490         return 0;
3491
3492 err_remove_rx_link:
3493         device_link_remove(dev, wcd939x->rxdev);
3494 err_remove_tx_link:
3495         device_link_remove(dev, wcd939x->txdev);
3496 err_remove_rxtx_link:
3497         device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3498 err_put_txdev:
3499         put_device(wcd939x->txdev);
3500 err_put_rxdev:
3501         put_device(wcd939x->rxdev);
3502 err_unbind:
3503         component_unbind_all(dev, wcd939x);
3504 err_put_typec_switch:
3505 #if IS_ENABLED(CONFIG_TYPEC)
3506         if (wcd939x->typec_analog_mux)
3507                 typec_switch_put(wcd939x->typec_switch);
3508 #endif /* CONFIG_TYPEC */
3509
3510         return ret;
3511 }
3512
3513 static void wcd939x_unbind(struct device *dev)
3514 {
3515         struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3516
3517         snd_soc_unregister_component(dev);
3518         device_link_remove(dev, wcd939x->txdev);
3519         device_link_remove(dev, wcd939x->rxdev);
3520         device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3521         put_device(wcd939x->txdev);
3522         put_device(wcd939x->rxdev);
3523         component_unbind_all(dev, wcd939x);
3524 }
3525
3526 static const struct component_master_ops wcd939x_comp_ops = {
3527         .bind   = wcd939x_bind,
3528         .unbind = wcd939x_unbind,
3529 };
3530
3531 static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x,
3532                                         struct device *dev,
3533                                         struct component_match **matchptr)
3534 {
3535         struct device_node *np = dev->of_node;
3536
3537         wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3538         if (!wcd939x->rxnode) {
3539                 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3540                 return -ENODEV;
3541         }
3542
3543         of_node_get(wcd939x->rxnode);
3544         component_match_add_release(dev, matchptr, component_release_of,
3545                                     component_compare_of, wcd939x->rxnode);
3546
3547         wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3548         if (!wcd939x->txnode) {
3549                 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3550                 return -ENODEV;
3551         }
3552         of_node_get(wcd939x->txnode);
3553         component_match_add_release(dev, matchptr, component_release_of,
3554                                     component_compare_of, wcd939x->txnode);
3555         return 0;
3556 }
3557
3558 static int wcd939x_probe(struct platform_device *pdev)
3559 {
3560         struct component_match *match = NULL;
3561         struct wcd939x_priv *wcd939x = NULL;
3562         struct device *dev = &pdev->dev;
3563         int ret;
3564
3565         wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
3566                                GFP_KERNEL);
3567         if (!wcd939x)
3568                 return -ENOMEM;
3569
3570         dev_set_drvdata(dev, wcd939x);
3571         mutex_init(&wcd939x->micb_lock);
3572
3573         ret = wcd939x_populate_dt_data(wcd939x, dev);
3574         if (ret) {
3575                 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3576                 return -EINVAL;
3577         }
3578
3579 #if IS_ENABLED(CONFIG_TYPEC)
3580         /*
3581          * Is USBSS is used to mux analog lines,
3582          * register a typec mux/switch to get typec events
3583          */
3584         if (wcd939x->typec_analog_mux) {
3585                 struct typec_mux_desc mux_desc = {
3586                         .drvdata = wcd939x,
3587                         .fwnode = dev_fwnode(dev),
3588                         .set = wcd939x_typec_mux_set,
3589                 };
3590                 struct typec_switch_desc sw_desc = {
3591                         .drvdata = wcd939x,
3592                         .fwnode = dev_fwnode(dev),
3593                         .set = wcd939x_typec_switch_set,
3594                 };
3595
3596                 wcd939x->typec_mux = typec_mux_register(dev, &mux_desc);
3597                 if (IS_ERR(wcd939x->typec_mux)) {
3598                         ret = dev_err_probe(dev, PTR_ERR(wcd939x->typec_mux),
3599                                             "failed to register typec mux\n");
3600                         goto err_disable_regulators;
3601                 }
3602
3603                 wcd939x->typec_sw = typec_switch_register(dev, &sw_desc);
3604                 if (IS_ERR(wcd939x->typec_sw)) {
3605                         ret = dev_err_probe(dev, PTR_ERR(wcd939x->typec_sw),
3606                                             "failed to register typec switch\n");
3607                         goto err_unregister_typec_mux;
3608                 }
3609         }
3610 #endif /* CONFIG_TYPEC */
3611
3612         ret = wcd939x_add_slave_components(wcd939x, dev, &match);
3613         if (ret)
3614                 goto err_unregister_typec_switch;
3615
3616         wcd939x_reset(wcd939x);
3617
3618         ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match);
3619         if (ret)
3620                 goto err_disable_regulators;
3621
3622         pm_runtime_set_autosuspend_delay(dev, 1000);
3623         pm_runtime_use_autosuspend(dev);
3624         pm_runtime_mark_last_busy(dev);
3625         pm_runtime_set_active(dev);
3626         pm_runtime_enable(dev);
3627         pm_runtime_idle(dev);
3628
3629         return 0;
3630
3631 #if IS_ENABLED(CONFIG_TYPEC)
3632 err_unregister_typec_mux:
3633         if (wcd939x->typec_analog_mux)
3634                 typec_mux_unregister(wcd939x->typec_mux);
3635 #endif /* CONFIG_TYPEC */
3636
3637 err_unregister_typec_switch:
3638 #if IS_ENABLED(CONFIG_TYPEC)
3639         if (wcd939x->typec_analog_mux)
3640                 typec_switch_unregister(wcd939x->typec_sw);
3641 #endif /* CONFIG_TYPEC */
3642
3643 err_disable_regulators:
3644         regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3645         regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3646
3647         return ret;
3648 }
3649
3650 static void wcd939x_remove(struct platform_device *pdev)
3651 {
3652         struct device *dev = &pdev->dev;
3653         struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3654
3655         component_master_del(dev, &wcd939x_comp_ops);
3656
3657         pm_runtime_disable(dev);
3658         pm_runtime_set_suspended(dev);
3659         pm_runtime_dont_use_autosuspend(dev);
3660
3661         regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3662         regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3663 }
3664
3665 #if defined(CONFIG_OF)
3666 static const struct of_device_id wcd939x_dt_match[] = {
3667         { .compatible = "qcom,wcd9390-codec" },
3668         { .compatible = "qcom,wcd9395-codec" },
3669         {}
3670 };
3671 MODULE_DEVICE_TABLE(of, wcd939x_dt_match);
3672 #endif
3673
3674 static struct platform_driver wcd939x_codec_driver = {
3675         .probe = wcd939x_probe,
3676         .remove_new = wcd939x_remove,
3677         .driver = {
3678                 .name = "wcd939x_codec",
3679                 .of_match_table = of_match_ptr(wcd939x_dt_match),
3680                 .suppress_bind_attrs = true,
3681         },
3682 };
3683
3684 module_platform_driver(wcd939x_codec_driver);
3685 MODULE_DESCRIPTION("WCD939X Codec driver");
3686 MODULE_LICENSE("GPL");