sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/kernel.h>
   8 #include <linux/mfd/wcd934x/registers.h>
   9 #include <linux/mfd/wcd934x/wcd934x.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/slimbus.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/tlv.h>
  23 #include "wcd-clsh-v2.h"
  24 #include "wcd-mbhc-v2.h"
  25
  26 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  27                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  28                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  29 /* Fractional Rates */
  30 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  31                                  SNDRV_PCM_RATE_176400)
  32 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  33                                     SNDRV_PCM_FMTBIT_S24_LE)
  34
  35 /* slave port water mark level
  36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  37  */
  38 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  39 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  40 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  41 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  42 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  43 #define SLAVE_PORT_ENABLE               1
  44 #define SLAVE_PORT_DISABLE              0
  45 #define WCD934X_SLIM_WATER_MARK_VAL \
  46         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  47          (SLAVE_PORT_ENABLE))
  48
  49 #define WCD934X_SLIM_NUM_PORT_REG       3
  50 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  51 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  52 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  53 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  54
  55 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  56 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  57
  58 /* Only valid for 9.6 MHz mclk */
  59 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  60 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  61
  62 /* Only valid for 12.288 MHz mclk */
  63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  64
  65 #define WCD934X_DMIC_CLK_DIV_2          0x0
  66 #define WCD934X_DMIC_CLK_DIV_3          0x1
  67 #define WCD934X_DMIC_CLK_DIV_4          0x2
  68 #define WCD934X_DMIC_CLK_DIV_6          0x3
  69 #define WCD934X_DMIC_CLK_DIV_8          0x4
  70 #define WCD934X_DMIC_CLK_DIV_16         0x5
  71 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  72
  73 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  74 #define CF_MIN_3DB_4HZ                  0x0
  75 #define CF_MIN_3DB_75HZ                 0x1
  76 #define CF_MIN_3DB_150HZ                0x2
  77
  78 #define WCD934X_RX_START                16
  79 #define WCD934X_NUM_INTERPOLATORS       9
  80 #define WCD934X_RX_PATH_CTL_OFFSET      20
  81 #define WCD934X_MAX_VALID_ADC_MUX       13
  82 #define WCD934X_INVALID_ADC_MUX         9
  83
  84 #define WCD934X_SLIM_RX_CH(p) \
  85         {.port = p + WCD934X_RX_START, .shift = p,}
  86
  87 #define WCD934X_SLIM_TX_CH(p) \
  88         {.port = p, .shift = p,}
  89
  90 /* Feature masks to distinguish codec version */
  91 #define DSD_DISABLED_MASK   0
  92 #define SLNQ_DISABLED_MASK  1
  93
  94 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  95 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  96
  97 /* As fine version info cannot be retrieved before wcd probe.
  98  * Define three coarse versions for possible future use before wcd probe.
  99  */
 100 #define WCD_VERSION_WCD9340_1_0     0x400
 101 #define WCD_VERSION_WCD9341_1_0     0x410
 102 #define WCD_VERSION_WCD9340_1_1     0x401
 103 #define WCD_VERSION_WCD9341_1_1     0x411
 104 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 106 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 108 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 109 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 110
 111 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 112 #define WCD934X_DEC_PWR_LVL_LP          0x02
 113 #define WCD934X_DEC_PWR_LVL_HP          0x04
 114 #define WCD934X_DEC_PWR_LVL_DF          0x00
 115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 116
 117 #define WCD934X_DEF_MICBIAS_MV  1800
 118 #define WCD934X_MAX_MICBIAS_MV  2850
 119
 120 #define WCD_IIR_FILTER_SIZE     (sizeof(u32) * BAND_MAX)
 121
 122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 123 { \
 124         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 125         .info = wcd934x_iir_filter_info, \
 126         .get = wcd934x_get_iir_band_audio_mixer, \
 127         .put = wcd934x_put_iir_band_audio_mixer, \
 128         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 129                 .iir_idx = iidx, \
 130                 .band_idx = bidx, \
 131                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 132         } \
 133 }
 134
 135 /* Z value defined in milliohm */
 136 #define WCD934X_ZDET_VAL_32             32000
 137 #define WCD934X_ZDET_VAL_400            400000
 138 #define WCD934X_ZDET_VAL_1200           1200000
 139 #define WCD934X_ZDET_VAL_100K           100000000
 140 /* Z floating defined in ohms */
 141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
 142
 143 #define WCD934X_ZDET_NUM_MEASUREMENTS   900
 144 #define WCD934X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
 145 #define WCD934X_MBHC_GET_X1(x)          (x & 0x3FFF)
 146 /* Z value compared in milliOhm */
 147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
 148 #define WCD934X_MBHC_ZDET_CONST         (86 * 16384)
 149 #define WCD934X_MBHC_MOISTURE_RREF      R_24_KOHM
 150 #define WCD934X_MBHC_MAX_BUTTONS        (8)
 151 #define WCD_MBHC_HS_V_MAX           1600
 152
 153 #define WCD934X_INTERPOLATOR_PATH(id)                   \
 154         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 155         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 156         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 157         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 158         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 159         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 160         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 161         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 162         {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},  \
 163         {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},  \
 164         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 165         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 166         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 167         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 168         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 169         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 170         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 171         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 172         {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},  \
 173         {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},  \
 174         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 175         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 176         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 177         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 178         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 179         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 180         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 181         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 182         {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},          \
 183         {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},          \
 184         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
 185         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
 186         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
 187         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 188         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 189         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 190         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 191         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 192         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 193         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 194         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 195         {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
 196         {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
 197         {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},        \
 198         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},      \
 199         {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},       \
 200         {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},     \
 201         {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},  \
 202         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
 203
 204 #define WCD934X_INTERPOLATOR_MIX2(id)                   \
 205         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
 206         {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
 207
 208 #define WCD934X_SLIM_RX_AIF_PATH(id)    \
 209         {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},     \
 210         {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},     \
 211         {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},     \
 212         {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
 213         {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
 214
 215 #define WCD934X_ADC_MUX(id) \
 216         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id },       \
 217         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id },       \
 218         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 219         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 220         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 221         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 222         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 223         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 224         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 225         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 226         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 227         {"AMIC MUX" #id, "ADC4", "ADC4"}
 228
 229 #define WCD934X_IIR_INP_MUX(id) \
 230         {"IIR" #id, NULL, "IIR" #id " INP0 MUX"},       \
 231         {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},    \
 232         {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},    \
 233         {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},    \
 234         {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},    \
 235         {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},    \
 236         {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},    \
 237         {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},    \
 238         {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},    \
 239         {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},    \
 240         {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},     \
 241         {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},     \
 242         {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},     \
 243         {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},     \
 244         {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},     \
 245         {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},     \
 246         {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},     \
 247         {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},     \
 248         {"IIR" #id, NULL, "IIR" #id " INP1 MUX"},       \
 249         {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},    \
 250         {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},    \
 251         {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},    \
 252         {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},    \
 253         {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},    \
 254         {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},    \
 255         {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},    \
 256         {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},    \
 257         {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},    \
 258         {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},     \
 259         {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},     \
 260         {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},     \
 261         {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},     \
 262         {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},     \
 263         {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},     \
 264         {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},     \
 265         {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},     \
 266         {"IIR" #id, NULL, "IIR" #id " INP2 MUX"},       \
 267         {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},    \
 268         {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},    \
 269         {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},    \
 270         {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},    \
 271         {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},    \
 272         {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},    \
 273         {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},    \
 274         {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},    \
 275         {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},    \
 276         {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},     \
 277         {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},     \
 278         {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},     \
 279         {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},     \
 280         {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},     \
 281         {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},     \
 282         {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},     \
 283         {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},     \
 284         {"IIR" #id, NULL, "IIR" #id " INP3 MUX"},       \
 285         {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},    \
 286         {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},    \
 287         {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},    \
 288         {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},    \
 289         {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},    \
 290         {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},    \
 291         {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},    \
 292         {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},    \
 293         {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},    \
 294         {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},     \
 295         {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},     \
 296         {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},     \
 297         {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},     \
 298         {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},     \
 299         {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},     \
 300         {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},     \
 301         {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
 302
 303 #define WCD934X_SLIM_TX_AIF_PATH(id)    \
 304         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 305         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 306         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 307         {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
 308
 309 #define WCD934X_MAX_MICBIAS     MIC_BIAS_4
 310
 311 enum {
 312         SIDO_SOURCE_INTERNAL,
 313         SIDO_SOURCE_RCO_BG,
 314 };
 315
 316 enum {
 317         INTERP_EAR = 0,
 318         INTERP_HPHL,
 319         INTERP_HPHR,
 320         INTERP_LO1,
 321         INTERP_LO2,
 322         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 323         INTERP_LO4_NA,
 324         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 325         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 326         INTERP_MAX,
 327 };
 328
 329 enum {
 330         WCD934X_RX0 = 0,
 331         WCD934X_RX1,
 332         WCD934X_RX2,
 333         WCD934X_RX3,
 334         WCD934X_RX4,
 335         WCD934X_RX5,
 336         WCD934X_RX6,
 337         WCD934X_RX7,
 338         WCD934X_RX8,
 339         WCD934X_RX9,
 340         WCD934X_RX10,
 341         WCD934X_RX11,
 342         WCD934X_RX12,
 343         WCD934X_RX_MAX,
 344 };
 345
 346 enum {
 347         WCD934X_TX0 = 0,
 348         WCD934X_TX1,
 349         WCD934X_TX2,
 350         WCD934X_TX3,
 351         WCD934X_TX4,
 352         WCD934X_TX5,
 353         WCD934X_TX6,
 354         WCD934X_TX7,
 355         WCD934X_TX8,
 356         WCD934X_TX9,
 357         WCD934X_TX10,
 358         WCD934X_TX11,
 359         WCD934X_TX12,
 360         WCD934X_TX13,
 361         WCD934X_TX14,
 362         WCD934X_TX15,
 363         WCD934X_TX_MAX,
 364 };
 365
 366 struct wcd934x_slim_ch {
 367         u32 ch_num;
 368         u16 port;
 369         u16 shift;
 370         struct list_head list;
 371 };
 372
 373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 374         WCD934X_SLIM_TX_CH(0),
 375         WCD934X_SLIM_TX_CH(1),
 376         WCD934X_SLIM_TX_CH(2),
 377         WCD934X_SLIM_TX_CH(3),
 378         WCD934X_SLIM_TX_CH(4),
 379         WCD934X_SLIM_TX_CH(5),
 380         WCD934X_SLIM_TX_CH(6),
 381         WCD934X_SLIM_TX_CH(7),
 382         WCD934X_SLIM_TX_CH(8),
 383         WCD934X_SLIM_TX_CH(9),
 384         WCD934X_SLIM_TX_CH(10),
 385         WCD934X_SLIM_TX_CH(11),
 386         WCD934X_SLIM_TX_CH(12),
 387         WCD934X_SLIM_TX_CH(13),
 388         WCD934X_SLIM_TX_CH(14),
 389         WCD934X_SLIM_TX_CH(15),
 390 };
 391
 392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 393         WCD934X_SLIM_RX_CH(0),   /* 16 */
 394         WCD934X_SLIM_RX_CH(1),   /* 17 */
 395         WCD934X_SLIM_RX_CH(2),
 396         WCD934X_SLIM_RX_CH(3),
 397         WCD934X_SLIM_RX_CH(4),
 398         WCD934X_SLIM_RX_CH(5),
 399         WCD934X_SLIM_RX_CH(6),
 400         WCD934X_SLIM_RX_CH(7),
 401         WCD934X_SLIM_RX_CH(8),
 402         WCD934X_SLIM_RX_CH(9),
 403         WCD934X_SLIM_RX_CH(10),
 404         WCD934X_SLIM_RX_CH(11),
 405         WCD934X_SLIM_RX_CH(12),
 406 };
 407
 408 /* Codec supports 2 IIR filters */
 409 enum {
 410         IIR0 = 0,
 411         IIR1,
 412         IIR_MAX,
 413 };
 414
 415 /* Each IIR has 5 Filter Stages */
 416 enum {
 417         BAND1 = 0,
 418         BAND2,
 419         BAND3,
 420         BAND4,
 421         BAND5,
 422         BAND_MAX,
 423 };
 424
 425 enum {
 426         COMPANDER_1, /* HPH_L */
 427         COMPANDER_2, /* HPH_R */
 428         COMPANDER_3, /* LO1_DIFF */
 429         COMPANDER_4, /* LO2_DIFF */
 430         COMPANDER_5, /* LO3_SE - not used in Tavil */
 431         COMPANDER_6, /* LO4_SE - not used in Tavil */
 432         COMPANDER_7, /* SWR SPK CH1 */
 433         COMPANDER_8, /* SWR SPK CH2 */
 434         COMPANDER_MAX,
 435 };
 436
 437 enum {
 438         AIF1_PB = 0,
 439         AIF1_CAP,
 440         AIF2_PB,
 441         AIF2_CAP,
 442         AIF3_PB,
 443         AIF3_CAP,
 444         AIF4_PB,
 445         AIF4_VIFEED,
 446         AIF4_MAD_TX,
 447         NUM_CODEC_DAIS,
 448 };
 449
 450 enum {
 451         INTn_1_INP_SEL_ZERO = 0,
 452         INTn_1_INP_SEL_DEC0,
 453         INTn_1_INP_SEL_DEC1,
 454         INTn_1_INP_SEL_IIR0,
 455         INTn_1_INP_SEL_IIR1,
 456         INTn_1_INP_SEL_RX0,
 457         INTn_1_INP_SEL_RX1,
 458         INTn_1_INP_SEL_RX2,
 459         INTn_1_INP_SEL_RX3,
 460         INTn_1_INP_SEL_RX4,
 461         INTn_1_INP_SEL_RX5,
 462         INTn_1_INP_SEL_RX6,
 463         INTn_1_INP_SEL_RX7,
 464 };
 465
 466 enum {
 467         INTn_2_INP_SEL_ZERO = 0,
 468         INTn_2_INP_SEL_RX0,
 469         INTn_2_INP_SEL_RX1,
 470         INTn_2_INP_SEL_RX2,
 471         INTn_2_INP_SEL_RX3,
 472         INTn_2_INP_SEL_RX4,
 473         INTn_2_INP_SEL_RX5,
 474         INTn_2_INP_SEL_RX6,
 475         INTn_2_INP_SEL_RX7,
 476         INTn_2_INP_SEL_PROXIMITY,
 477 };
 478
 479 enum {
 480         INTERP_MAIN_PATH,
 481         INTERP_MIX_PATH,
 482 };
 483
 484 struct interp_sample_rate {
 485         int sample_rate;
 486         int rate_val;
 487 };
 488
 489 static struct interp_sample_rate sr_val_tbl[] = {
 490         {8000, 0x0},
 491         {16000, 0x1},
 492         {32000, 0x3},
 493         {48000, 0x4},
 494         {96000, 0x5},
 495         {192000, 0x6},
 496         {384000, 0x7},
 497         {44100, 0x9},
 498         {88200, 0xA},
 499         {176400, 0xB},
 500         {352800, 0xC},
 501 };
 502
 503 struct wcd934x_mbhc_zdet_param {
 504         u16 ldo_ctl;
 505         u16 noff;
 506         u16 nshift;
 507         u16 btn5;
 508         u16 btn6;
 509         u16 btn7;
 510 };
 511
 512 struct wcd_slim_codec_dai_data {
 513         struct list_head slim_ch_list;
 514         struct slim_stream_config sconfig;
 515         struct slim_stream_runtime *sruntime;
 516 };
 517
 518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 519         {
 520                 .name = "WCD9335-IFC-DEV",
 521                 .range_min =  0x0,
 522                 .range_max = 0xffff,
 523                 .selector_reg = 0x800,
 524                 .selector_mask = 0xfff,
 525                 .selector_shift = 0,
 526                 .window_start = 0x800,
 527                 .window_len = 0x400,
 528         },
 529 };
 530
 531 static struct regmap_config wcd934x_ifc_regmap_config = {
 532         .reg_bits = 16,
 533         .val_bits = 8,
 534         .max_register = 0xffff,
 535         .ranges = wcd934x_ifc_ranges,
 536         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 537 };
 538
 539 struct wcd934x_codec {
 540         struct device *dev;
 541         struct clk_hw hw;
 542         struct clk *extclk;
 543         struct regmap *regmap;
 544         struct regmap *if_regmap;
 545         struct slim_device *sdev;
 546         struct slim_device *sidev;
 547         struct wcd_clsh_ctrl *clsh_ctrl;
 548         struct snd_soc_component *component;
 549         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 550         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 551         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 552         int rate;
 553         u32 version;
 554         u32 hph_mode;
 555         int num_rx_port;
 556         int num_tx_port;
 557         u32 tx_port_value[WCD934X_TX_MAX];
 558         u32 rx_port_value[WCD934X_RX_MAX];
 559         int sido_input_src;
 560         int dmic_0_1_clk_cnt;
 561         int dmic_2_3_clk_cnt;
 562         int dmic_4_5_clk_cnt;
 563         int dmic_sample_rate;
 564         int comp_enabled[COMPANDER_MAX];
 565         int sysclk_users;
 566         struct mutex sysclk_mutex;
 567         /* mbhc module */
 568         struct wcd_mbhc *mbhc;
 569         struct wcd_mbhc_config mbhc_cfg;
 570         struct wcd_mbhc_intr intr_ids;
 571         bool mbhc_started;
 572         struct mutex micb_lock;
 573         u32 micb_ref[WCD934X_MAX_MICBIAS];
 574         u32 pullup_ref[WCD934X_MAX_MICBIAS];
 575         u32 micb1_mv;
 576         u32 micb2_mv;
 577         u32 micb3_mv;
 578         u32 micb4_mv;
 579 };
 580
 581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 582
 583 struct wcd_iir_filter_ctl {
 584         unsigned int iir_idx;
 585         unsigned int band_idx;
 586         struct soc_bytes_ext bytes_ext;
 587 };
 588
 589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 593
 594 /* Cutoff frequency for high pass filter */
 595 static const char * const cf_text[] = {
 596         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 597 };
 598
 599 static const char * const rx_cf_text[] = {
 600         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 601         "CF_NEG_3DB_0P48HZ"
 602 };
 603
 604 static const char * const rx_hph_mode_mux_text[] = {
 605         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 606         "Class-H Hi-Fi Low Power"
 607 };
 608
 609 static const char *const slim_rx_mux_text[] = {
 610         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 611 };
 612
 613 static const char * const rx_int0_7_mix_mux_text[] = {
 614         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 615         "RX6", "RX7", "PROXIMITY"
 616 };
 617
 618 static const char * const rx_int_mix_mux_text[] = {
 619         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 620         "RX6", "RX7"
 621 };
 622
 623 static const char * const rx_prim_mix_text[] = {
 624         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 625         "RX3", "RX4", "RX5", "RX6", "RX7"
 626 };
 627
 628 static const char * const rx_sidetone_mix_text[] = {
 629         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 630 };
 631
 632 static const char * const iir_inp_mux_text[] = {
 633         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
 634         "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
 635 };
 636
 637 static const char * const rx_int_dem_inp_mux_text[] = {
 638         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 639 };
 640
 641 static const char * const rx_int0_1_interp_mux_text[] = {
 642         "ZERO", "RX INT0_1 MIX1",
 643 };
 644
 645 static const char * const rx_int1_1_interp_mux_text[] = {
 646         "ZERO", "RX INT1_1 MIX1",
 647 };
 648
 649 static const char * const rx_int2_1_interp_mux_text[] = {
 650         "ZERO", "RX INT2_1 MIX1",
 651 };
 652
 653 static const char * const rx_int3_1_interp_mux_text[] = {
 654         "ZERO", "RX INT3_1 MIX1",
 655 };
 656
 657 static const char * const rx_int4_1_interp_mux_text[] = {
 658         "ZERO", "RX INT4_1 MIX1",
 659 };
 660
 661 static const char * const rx_int7_1_interp_mux_text[] = {
 662         "ZERO", "RX INT7_1 MIX1",
 663 };
 664
 665 static const char * const rx_int8_1_interp_mux_text[] = {
 666         "ZERO", "RX INT8_1 MIX1",
 667 };
 668
 669 static const char * const rx_int0_2_interp_mux_text[] = {
 670         "ZERO", "RX INT0_2 MUX",
 671 };
 672
 673 static const char * const rx_int1_2_interp_mux_text[] = {
 674         "ZERO", "RX INT1_2 MUX",
 675 };
 676
 677 static const char * const rx_int2_2_interp_mux_text[] = {
 678         "ZERO", "RX INT2_2 MUX",
 679 };
 680
 681 static const char * const rx_int3_2_interp_mux_text[] = {
 682         "ZERO", "RX INT3_2 MUX",
 683 };
 684
 685 static const char * const rx_int4_2_interp_mux_text[] = {
 686         "ZERO", "RX INT4_2 MUX",
 687 };
 688
 689 static const char * const rx_int7_2_interp_mux_text[] = {
 690         "ZERO", "RX INT7_2 MUX",
 691 };
 692
 693 static const char * const rx_int8_2_interp_mux_text[] = {
 694         "ZERO", "RX INT8_2 MUX",
 695 };
 696
 697 static const char * const dmic_mux_text[] = {
 698         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
 699 };
 700
 701 static const char * const amic_mux_text[] = {
 702         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
 703 };
 704
 705 static const char * const amic4_5_sel_text[] = {
 706         "AMIC4", "AMIC5"
 707 };
 708
 709 static const char * const adc_mux_text[] = {
 710         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 711 };
 712
 713 static const char * const cdc_if_tx0_mux_text[] = {
 714         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 715 };
 716
 717 static const char * const cdc_if_tx1_mux_text[] = {
 718         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 719 };
 720
 721 static const char * const cdc_if_tx2_mux_text[] = {
 722         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 723 };
 724
 725 static const char * const cdc_if_tx3_mux_text[] = {
 726         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 727 };
 728
 729 static const char * const cdc_if_tx4_mux_text[] = {
 730         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 731 };
 732
 733 static const char * const cdc_if_tx5_mux_text[] = {
 734         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 735 };
 736
 737 static const char * const cdc_if_tx6_mux_text[] = {
 738         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 739 };
 740
 741 static const char * const cdc_if_tx7_mux_text[] = {
 742         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 743 };
 744
 745 static const char * const cdc_if_tx8_mux_text[] = {
 746         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 747 };
 748
 749 static const char * const cdc_if_tx9_mux_text[] = {
 750         "ZERO", "DEC7", "DEC7_192"
 751 };
 752
 753 static const char * const cdc_if_tx10_mux_text[] = {
 754         "ZERO", "DEC6", "DEC6_192"
 755 };
 756
 757 static const char * const cdc_if_tx11_mux_text[] = {
 758         "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
 759 };
 760
 761 static const char * const cdc_if_tx11_inp1_mux_text[] = {
 762         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
 763         "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
 764 };
 765
 766 static const char * const cdc_if_tx13_mux_text[] = {
 767         "CDC_DEC_5", "MAD_BRDCST"
 768 };
 769
 770 static const char * const cdc_if_tx13_inp1_mux_text[] = {
 771         "ZERO", "DEC5", "DEC5_192"
 772 };
 773
 774 static const struct soc_enum cf_dec0_enum =
 775         SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 776
 777 static const struct soc_enum cf_dec1_enum =
 778         SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 779
 780 static const struct soc_enum cf_dec2_enum =
 781         SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 782
 783 static const struct soc_enum cf_dec3_enum =
 784         SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 785
 786 static const struct soc_enum cf_dec4_enum =
 787         SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 788
 789 static const struct soc_enum cf_dec5_enum =
 790         SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 791
 792 static const struct soc_enum cf_dec6_enum =
 793         SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 794
 795 static const struct soc_enum cf_dec7_enum =
 796         SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 797
 798 static const struct soc_enum cf_dec8_enum =
 799         SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 800
 801 static const struct soc_enum cf_int0_1_enum =
 802         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 803
 804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
 805                      rx_cf_text);
 806
 807 static const struct soc_enum cf_int1_1_enum =
 808         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 809
 810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
 811                      rx_cf_text);
 812
 813 static const struct soc_enum cf_int2_1_enum =
 814         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 815
 816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
 817                      rx_cf_text);
 818
 819 static const struct soc_enum cf_int3_1_enum =
 820         SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 821
 822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
 823                             rx_cf_text);
 824
 825 static const struct soc_enum cf_int4_1_enum =
 826         SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 827
 828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
 829                             rx_cf_text);
 830
 831 static const struct soc_enum cf_int7_1_enum =
 832         SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 833
 834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
 835                             rx_cf_text);
 836
 837 static const struct soc_enum cf_int8_1_enum =
 838         SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 839
 840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
 841                             rx_cf_text);
 842
 843 static const struct soc_enum rx_hph_mode_mux_enum =
 844         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 845                             rx_hph_mode_mux_text);
 846
 847 static const struct soc_enum slim_rx_mux_enum =
 848         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 849
 850 static const struct soc_enum rx_int0_2_mux_chain_enum =
 851         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 852                         rx_int0_7_mix_mux_text);
 853
 854 static const struct soc_enum rx_int1_2_mux_chain_enum =
 855         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 856                         rx_int_mix_mux_text);
 857
 858 static const struct soc_enum rx_int2_2_mux_chain_enum =
 859         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 860                         rx_int_mix_mux_text);
 861
 862 static const struct soc_enum rx_int3_2_mux_chain_enum =
 863         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 864                         rx_int_mix_mux_text);
 865
 866 static const struct soc_enum rx_int4_2_mux_chain_enum =
 867         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 868                         rx_int_mix_mux_text);
 869
 870 static const struct soc_enum rx_int7_2_mux_chain_enum =
 871         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 872                         rx_int0_7_mix_mux_text);
 873
 874 static const struct soc_enum rx_int8_2_mux_chain_enum =
 875         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 876                         rx_int_mix_mux_text);
 877
 878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 879         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 880                         rx_prim_mix_text);
 881
 882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 883         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 884                         rx_prim_mix_text);
 885
 886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 887         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 888                         rx_prim_mix_text);
 889
 890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 891         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 892                         rx_prim_mix_text);
 893
 894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 895         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 896                         rx_prim_mix_text);
 897
 898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 899         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 900                         rx_prim_mix_text);
 901
 902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 903         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 904                         rx_prim_mix_text);
 905
 906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 907         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 908                         rx_prim_mix_text);
 909
 910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 911         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 912                         rx_prim_mix_text);
 913
 914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 915         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 916                         rx_prim_mix_text);
 917
 918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 919         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 920                         rx_prim_mix_text);
 921
 922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 923         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 924                         rx_prim_mix_text);
 925
 926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 927         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 928                         rx_prim_mix_text);
 929
 930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 931         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 932                         rx_prim_mix_text);
 933
 934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 935         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 936                         rx_prim_mix_text);
 937
 938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 939         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 940                         rx_prim_mix_text);
 941
 942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 943         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 944                         rx_prim_mix_text);
 945
 946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 947         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 948                         rx_prim_mix_text);
 949
 950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 951         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 952                         rx_prim_mix_text);
 953
 954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 955         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 956                         rx_prim_mix_text);
 957
 958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 959         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 960                         rx_prim_mix_text);
 961
 962 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
 963         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
 964                         rx_sidetone_mix_text);
 965
 966 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
 967         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
 968                         rx_sidetone_mix_text);
 969
 970 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
 971         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
 972                         rx_sidetone_mix_text);
 973
 974 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
 975         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
 976                         rx_sidetone_mix_text);
 977
 978 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
 979         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
 980                         rx_sidetone_mix_text);
 981
 982 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
 983         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
 984                         rx_sidetone_mix_text);
 985
 986 static const struct soc_enum iir0_inp0_mux_enum =
 987         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
 988                         0, 18, iir_inp_mux_text);
 989
 990 static const struct soc_enum iir0_inp1_mux_enum =
 991         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
 992                         0, 18, iir_inp_mux_text);
 993
 994 static const struct soc_enum iir0_inp2_mux_enum =
 995         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
 996                         0, 18, iir_inp_mux_text);
 997
 998 static const struct soc_enum iir0_inp3_mux_enum =
 999         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
1000                         0, 18, iir_inp_mux_text);
1001
1002 static const struct soc_enum iir1_inp0_mux_enum =
1003         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
1004                         0, 18, iir_inp_mux_text);
1005
1006 static const struct soc_enum iir1_inp1_mux_enum =
1007         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
1008                         0, 18, iir_inp_mux_text);
1009
1010 static const struct soc_enum iir1_inp2_mux_enum =
1011         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
1012                         0, 18, iir_inp_mux_text);
1013
1014 static const struct soc_enum iir1_inp3_mux_enum =
1015         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
1016                         0, 18, iir_inp_mux_text);
1017
1018 static const struct soc_enum rx_int0_dem_inp_mux_enum =
1019         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1020                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1021                         rx_int_dem_inp_mux_text);
1022
1023 static const struct soc_enum rx_int1_dem_inp_mux_enum =
1024         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1025                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1026                         rx_int_dem_inp_mux_text);
1027
1028 static const struct soc_enum rx_int2_dem_inp_mux_enum =
1029         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1030                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
1031                         rx_int_dem_inp_mux_text);
1032
1033 static const struct soc_enum tx_adc_mux0_enum =
1034         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1035                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1036 static const struct soc_enum tx_adc_mux1_enum =
1037         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1038                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1039 static const struct soc_enum tx_adc_mux2_enum =
1040         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1041                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1042 static const struct soc_enum tx_adc_mux3_enum =
1043         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1044                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1045 static const struct soc_enum tx_adc_mux4_enum =
1046         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1047                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1048 static const struct soc_enum tx_adc_mux5_enum =
1049         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1050                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1051 static const struct soc_enum tx_adc_mux6_enum =
1052         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1053                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1054 static const struct soc_enum tx_adc_mux7_enum =
1055         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1056                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1057 static const struct soc_enum tx_adc_mux8_enum =
1058         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1059                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1060
1061 static const struct soc_enum rx_int0_1_interp_mux_enum =
1062         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1063                         rx_int0_1_interp_mux_text);
1064
1065 static const struct soc_enum rx_int1_1_interp_mux_enum =
1066         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1067                         rx_int1_1_interp_mux_text);
1068
1069 static const struct soc_enum rx_int2_1_interp_mux_enum =
1070         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1071                         rx_int2_1_interp_mux_text);
1072
1073 static const struct soc_enum rx_int3_1_interp_mux_enum =
1074         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_1_interp_mux_text);
1075
1076 static const struct soc_enum rx_int4_1_interp_mux_enum =
1077         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_1_interp_mux_text);
1078
1079 static const struct soc_enum rx_int7_1_interp_mux_enum =
1080         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_1_interp_mux_text);
1081
1082 static const struct soc_enum rx_int8_1_interp_mux_enum =
1083         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_1_interp_mux_text);
1084
1085 static const struct soc_enum rx_int0_2_interp_mux_enum =
1086         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int0_2_interp_mux_text);
1087
1088 static const struct soc_enum rx_int1_2_interp_mux_enum =
1089         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int1_2_interp_mux_text);
1090
1091 static const struct soc_enum rx_int2_2_interp_mux_enum =
1092         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int2_2_interp_mux_text);
1093
1094 static const struct soc_enum rx_int3_2_interp_mux_enum =
1095         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_2_interp_mux_text);
1096
1097 static const struct soc_enum rx_int4_2_interp_mux_enum =
1098         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_2_interp_mux_text);
1099
1100 static const struct soc_enum rx_int7_2_interp_mux_enum =
1101         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_2_interp_mux_text);
1102
1103 static const struct soc_enum rx_int8_2_interp_mux_enum =
1104         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_2_interp_mux_text);
1105
1106 static const struct soc_enum tx_dmic_mux0_enum =
1107         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1108                         dmic_mux_text);
1109
1110 static const struct soc_enum tx_dmic_mux1_enum =
1111         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1112                         dmic_mux_text);
1113
1114 static const struct soc_enum tx_dmic_mux2_enum =
1115         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1116                         dmic_mux_text);
1117
1118 static const struct soc_enum tx_dmic_mux3_enum =
1119         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1120                         dmic_mux_text);
1121
1122 static const struct soc_enum tx_dmic_mux4_enum =
1123         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1124                         dmic_mux_text);
1125
1126 static const struct soc_enum tx_dmic_mux5_enum =
1127         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1128                         dmic_mux_text);
1129
1130 static const struct soc_enum tx_dmic_mux6_enum =
1131         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1132                         dmic_mux_text);
1133
1134 static const struct soc_enum tx_dmic_mux7_enum =
1135         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1136                         dmic_mux_text);
1137
1138 static const struct soc_enum tx_dmic_mux8_enum =
1139         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1140                         dmic_mux_text);
1141
1142 static const struct soc_enum tx_amic_mux0_enum =
1143         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1144                         amic_mux_text);
1145 static const struct soc_enum tx_amic_mux1_enum =
1146         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1147                         amic_mux_text);
1148 static const struct soc_enum tx_amic_mux2_enum =
1149         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1150                         amic_mux_text);
1151 static const struct soc_enum tx_amic_mux3_enum =
1152         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1153                         amic_mux_text);
1154 static const struct soc_enum tx_amic_mux4_enum =
1155         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1156                         amic_mux_text);
1157 static const struct soc_enum tx_amic_mux5_enum =
1158         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1159                         amic_mux_text);
1160 static const struct soc_enum tx_amic_mux6_enum =
1161         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1162                         amic_mux_text);
1163 static const struct soc_enum tx_amic_mux7_enum =
1164         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1165                         amic_mux_text);
1166 static const struct soc_enum tx_amic_mux8_enum =
1167         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1168                         amic_mux_text);
1169
1170 static const struct soc_enum tx_amic4_5_enum =
1171         SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1172
1173 static const struct soc_enum cdc_if_tx0_mux_enum =
1174         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1175                         ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1176 static const struct soc_enum cdc_if_tx1_mux_enum =
1177         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1178                         ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1179 static const struct soc_enum cdc_if_tx2_mux_enum =
1180         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1181                         ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1182 static const struct soc_enum cdc_if_tx3_mux_enum =
1183         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1184                         ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1185 static const struct soc_enum cdc_if_tx4_mux_enum =
1186         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1187                         ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1188 static const struct soc_enum cdc_if_tx5_mux_enum =
1189         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1190                         ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1191 static const struct soc_enum cdc_if_tx6_mux_enum =
1192         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1193                         ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1194 static const struct soc_enum cdc_if_tx7_mux_enum =
1195         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1196                         ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1197 static const struct soc_enum cdc_if_tx8_mux_enum =
1198         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1199                         ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1200 static const struct soc_enum cdc_if_tx9_mux_enum =
1201         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1202                         ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1203 static const struct soc_enum cdc_if_tx10_mux_enum =
1204         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1205                         ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1207         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1208                         ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1209                         cdc_if_tx11_inp1_mux_text);
1210 static const struct soc_enum cdc_if_tx11_mux_enum =
1211         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1212                         ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1214         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1215                         ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1216                         cdc_if_tx13_inp1_mux_text);
1217 static const struct soc_enum cdc_if_tx13_mux_enum =
1218         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1219                         ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1220
1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1222         WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1223         WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1224         WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1225         WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1226         WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1227         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1228         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1229         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1230         WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1231         WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1232         WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1233         WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1234         WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1235         WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1236         WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1237         WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1238         WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1239         WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1240         WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1241         WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1242         WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1243         WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1244         WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1245         WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1246         WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1247         WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1248         WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1249         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1250         WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1251         WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1252         WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1253         WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1254         WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1255         WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1256         WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1257         WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1258         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1259         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1260         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1261         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1262         WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1263         WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1264         WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1265         WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1266         WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1267         WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1268         WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1269         WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1270 };
1271
1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1273 {
1274         if (sido_src == wcd->sido_input_src)
1275                 return 0;
1276
1277         if (sido_src == SIDO_SOURCE_RCO_BG) {
1278                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1279                                    WCD934X_ANA_RCO_BG_EN_MASK,
1280                                    WCD934X_ANA_RCO_BG_ENABLE);
1281                 usleep_range(100, 110);
1282         }
1283         wcd->sido_input_src = sido_src;
1284
1285         return 0;
1286 }
1287
1288 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1289 {
1290         mutex_lock(&wcd->sysclk_mutex);
1291
1292         if (++wcd->sysclk_users != 1) {
1293                 mutex_unlock(&wcd->sysclk_mutex);
1294                 return 0;
1295         }
1296         mutex_unlock(&wcd->sysclk_mutex);
1297
1298         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1299                            WCD934X_ANA_BIAS_EN_MASK,
1300                            WCD934X_ANA_BIAS_EN);
1301         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302                            WCD934X_ANA_PRECHRG_EN_MASK,
1303                            WCD934X_ANA_PRECHRG_EN);
1304         /*
1305          * 1ms delay is required after pre-charge is enabled
1306          * as per HW requirement
1307          */
1308         usleep_range(1000, 1100);
1309         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1310                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1311         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1312                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1313
1314         /*
1315          * In data clock contrl register is changed
1316          * to CLK_SYS_MCLK_PRG
1317          */
1318
1319         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1320                            WCD934X_EXT_CLK_BUF_EN_MASK,
1321                            WCD934X_EXT_CLK_BUF_EN);
1322         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1323                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
1324                            WCD934X_EXT_CLK_DIV_BY_2);
1325         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1326                            WCD934X_MCLK_SRC_MASK,
1327                            WCD934X_MCLK_SRC_EXT_CLK);
1328         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1329                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1330         regmap_update_bits(wcd->regmap,
1331                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1332                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1333                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1334         regmap_update_bits(wcd->regmap,
1335                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1336                            WCD934X_MCLK_EN_MASK,
1337                            WCD934X_MCLK_EN);
1338         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1339                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1340         /*
1341          * 10us sleep is required after clock is enabled
1342          * as per HW requirement
1343          */
1344         usleep_range(10, 15);
1345
1346         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1347
1348         return 0;
1349 }
1350
1351 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1352 {
1353         mutex_lock(&wcd->sysclk_mutex);
1354         if (--wcd->sysclk_users != 0) {
1355                 mutex_unlock(&wcd->sysclk_mutex);
1356                 return 0;
1357         }
1358         mutex_unlock(&wcd->sysclk_mutex);
1359
1360         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1361                            WCD934X_EXT_CLK_BUF_EN_MASK |
1362                            WCD934X_MCLK_EN_MASK, 0x0);
1363         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1364                            WCD934X_ANA_BIAS_EN_MASK, 0);
1365         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1366                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1367
1368         return 0;
1369 }
1370
1371 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1372 {
1373         int ret = 0;
1374
1375         if (enable) {
1376                 ret = clk_prepare_enable(wcd->extclk);
1377
1378                 if (ret) {
1379                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
1380                                 __func__);
1381                         return ret;
1382                 }
1383                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1384         } else {
1385                 int val;
1386
1387                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1388                             &val);
1389
1390                 /* Don't disable clock if soundwire using it.*/
1391                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1392                         return 0;
1393
1394                 wcd934x_disable_ana_bias_and_syclk(wcd);
1395                 clk_disable_unprepare(wcd->extclk);
1396         }
1397
1398         return ret;
1399 }
1400
1401 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1402                                      struct snd_kcontrol *kc, int event)
1403 {
1404         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1405         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1406
1407         switch (event) {
1408         case SND_SOC_DAPM_PRE_PMU:
1409                 return __wcd934x_cdc_mclk_enable(wcd, true);
1410         case SND_SOC_DAPM_POST_PMD:
1411                 return __wcd934x_cdc_mclk_enable(wcd, false);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1418 {
1419         int val1, val2, ver, ret;
1420         struct regmap *regmap;
1421         u16 id_minor;
1422         u32 version_mask = 0;
1423
1424         regmap = wcd->regmap;
1425         ver = 0;
1426
1427         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1428                                (u8 *)&id_minor, sizeof(u16));
1429
1430         if (ret)
1431                 return ret;
1432
1433         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1434         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1435
1436         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1437         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1438
1439         switch (version_mask) {
1440         case DSD_DISABLED | SLNQ_DISABLED:
1441                 if (id_minor == 0)
1442                         ver = WCD_VERSION_WCD9340_1_0;
1443                 else if (id_minor == 0x01)
1444                         ver = WCD_VERSION_WCD9340_1_1;
1445                 break;
1446         case SLNQ_DISABLED:
1447                 if (id_minor == 0)
1448                         ver = WCD_VERSION_WCD9341_1_0;
1449                 else if (id_minor == 0x01)
1450                         ver = WCD_VERSION_WCD9341_1_1;
1451                 break;
1452         }
1453
1454         wcd->version = ver;
1455         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1456
1457         return 0;
1458 }
1459
1460 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1461 {
1462         int rc, val;
1463
1464         __wcd934x_cdc_mclk_enable(wcd, true);
1465
1466         regmap_update_bits(wcd->regmap,
1467                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1468                            WCD934X_EFUSE_SENSE_STATE_MASK,
1469                            WCD934X_EFUSE_SENSE_STATE_DEF);
1470         regmap_update_bits(wcd->regmap,
1471                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1472                            WCD934X_EFUSE_SENSE_EN_MASK,
1473                            WCD934X_EFUSE_SENSE_ENABLE);
1474         /*
1475          * 5ms sleep required after enabling efuse control
1476          * before checking the status.
1477          */
1478         usleep_range(5000, 5500);
1479         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1480
1481         rc = regmap_read(wcd->regmap,
1482                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1483         if (rc || (!(val & 0x01)))
1484                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1485                      __func__, val, rc);
1486
1487         __wcd934x_cdc_mclk_enable(wcd, false);
1488 }
1489
1490 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1491 {
1492         if (enable) {
1493                 __wcd934x_cdc_mclk_enable(wcd, true);
1494                 regmap_update_bits(wcd->regmap,
1495                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1496                                    WCD934X_CDC_SWR_CLK_EN_MASK,
1497                                    WCD934X_CDC_SWR_CLK_ENABLE);
1498         } else {
1499                 regmap_update_bits(wcd->regmap,
1500                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1501                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1502                 __wcd934x_cdc_mclk_enable(wcd, false);
1503         }
1504
1505         return 0;
1506 }
1507
1508 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1509                                               u8 rate_val, u32 rate)
1510 {
1511         struct snd_soc_component *comp = dai->component;
1512         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1513         struct wcd934x_slim_ch *ch;
1514         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1515         int inp, j;
1516
1517         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1518                 inp = ch->shift + INTn_1_INP_SEL_RX0;
1519                 /*
1520                  * Loop through all interpolator MUX inputs and find out
1521                  * to which interpolator input, the slim rx port
1522                  * is connected
1523                  */
1524                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1525                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1526                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1527                                 continue;
1528
1529                         cfg0 = snd_soc_component_read(comp,
1530                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1531                         cfg1 = snd_soc_component_read(comp,
1532                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1533
1534                         inp0_sel = cfg0 &
1535                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1536                         inp1_sel = (cfg0 >> 4) &
1537                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1538                         inp2_sel = (cfg1 >> 4) &
1539                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1540
1541                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1542                             (inp2_sel == inp)) {
1543                                 /* rate is in Hz */
1544                                 /*
1545                                  * Ear and speaker primary path does not support
1546                                  * native sample rates
1547                                  */
1548                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1549                                      j == INTERP_SPKR2) && rate == 44100)
1550                                         dev_err(wcd->dev,
1551                                                 "Cannot set 44.1KHz on INT%d\n",
1552                                                 j);
1553                                 else
1554                                         snd_soc_component_update_bits(comp,
1555                                               WCD934X_CDC_RX_PATH_CTL(j),
1556                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1557                                               rate_val);
1558                         }
1559                 }
1560         }
1561
1562         return 0;
1563 }
1564
1565 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1566                                              int rate_val, u32 rate)
1567 {
1568         struct snd_soc_component *component = dai->component;
1569         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1570         struct wcd934x_slim_ch *ch;
1571         int val, j;
1572
1573         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1574                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1575                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1576                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1577                                 continue;
1578                         val = snd_soc_component_read(component,
1579                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1580                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1581
1582                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1583                                 /*
1584                                  * Ear mix path supports only 48, 96, 192,
1585                                  * 384KHz only
1586                                  */
1587                                 if ((j == INTERP_EAR) &&
1588                                     (rate_val < 0x4 ||
1589                                      rate_val > 0x7)) {
1590                                         dev_err(component->dev,
1591                                                 "Invalid rate for AIF_PB DAI(%d)\n",
1592                                                 dai->id);
1593                                         return -EINVAL;
1594                                 }
1595
1596                                 snd_soc_component_update_bits(component,
1597                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
1598                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1599                                               rate_val);
1600                         }
1601                 }
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1608                                          u32 sample_rate)
1609 {
1610         int rate_val = 0;
1611         int i, ret;
1612
1613         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1614                 if (sample_rate == sr_val_tbl[i].sample_rate) {
1615                         rate_val = sr_val_tbl[i].rate_val;
1616                         break;
1617                 }
1618         }
1619         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1620                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1621                 return -EINVAL;
1622         }
1623
1624         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1625                                                  sample_rate);
1626         if (ret)
1627                 return ret;
1628         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1629                                                 sample_rate);
1630
1631         return ret;
1632 }
1633
1634 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1635                                       u8 rate_val, u32 rate)
1636 {
1637         struct snd_soc_component *comp = dai->component;
1638         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1639         u8 shift = 0, shift_val = 0, tx_mux_sel;
1640         struct wcd934x_slim_ch *ch;
1641         int tx_port, tx_port_reg;
1642         int decimator = -1;
1643
1644         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1645                 tx_port = ch->port;
1646                 /* Find the SB TX MUX input - which decimator is connected */
1647                 switch (tx_port) {
1648                 case 0 ...  3:
1649                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1650                         shift = (tx_port << 1);
1651                         shift_val = 0x03;
1652                         break;
1653                 case 4 ... 7:
1654                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1655                         shift = ((tx_port - 4) << 1);
1656                         shift_val = 0x03;
1657                         break;
1658                 case 8 ... 10:
1659                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1660                         shift = ((tx_port - 8) << 1);
1661                         shift_val = 0x03;
1662                         break;
1663                 case 11:
1664                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1665                         shift = 0;
1666                         shift_val = 0x0F;
1667                         break;
1668                 case 13:
1669                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1670                         shift = 4;
1671                         shift_val = 0x03;
1672                         break;
1673                 default:
1674                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1675                                 tx_port, dai->id);
1676                         return -EINVAL;
1677                 }
1678
1679                 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1680                                                       (shift_val << shift);
1681
1682                 tx_mux_sel = tx_mux_sel >> shift;
1683                 switch (tx_port) {
1684                 case 0 ... 8:
1685                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1686                                 decimator = tx_port;
1687                         break;
1688                 case 9 ... 10:
1689                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1690                                 decimator = ((tx_port == 9) ? 7 : 6);
1691                         break;
1692                 case 11:
1693                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1694                                 decimator = tx_mux_sel - 1;
1695                         break;
1696                 case 13:
1697                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1698                                 decimator = 5;
1699                         break;
1700                 default:
1701                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1702                                 tx_port);
1703                         return -EINVAL;
1704                 }
1705
1706                 snd_soc_component_update_bits(comp,
1707                                       WCD934X_CDC_TX_PATH_CTL(decimator),
1708                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1709                                       rate_val);
1710         }
1711
1712         return 0;
1713 }
1714
1715 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1716                                       struct wcd_slim_codec_dai_data *dai_data,
1717                                       int direction)
1718 {
1719         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1720         struct slim_stream_config *cfg = &dai_data->sconfig;
1721         struct wcd934x_slim_ch *ch;
1722         u16 payload = 0;
1723         int ret, i;
1724
1725         cfg->ch_count = 0;
1726         cfg->direction = direction;
1727         cfg->port_mask = 0;
1728
1729         /* Configure slave interface device */
1730         list_for_each_entry(ch, slim_ch_list, list) {
1731                 cfg->ch_count++;
1732                 payload |= 1 << ch->shift;
1733                 cfg->port_mask |= BIT(ch->port);
1734         }
1735
1736         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1737         if (!cfg->chs)
1738                 return -ENOMEM;
1739
1740         i = 0;
1741         list_for_each_entry(ch, slim_ch_list, list) {
1742                 cfg->chs[i++] = ch->ch_num;
1743                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1744                         /* write to interface device */
1745                         ret = regmap_write(wcd->if_regmap,
1746                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1747                            payload);
1748
1749                         if (ret < 0)
1750                                 goto err;
1751
1752                         /* configure the slave port for water mark and enable*/
1753                         ret = regmap_write(wcd->if_regmap,
1754                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1755                                         WCD934X_SLIM_WATER_MARK_VAL);
1756                         if (ret < 0)
1757                                 goto err;
1758                 } else {
1759                         ret = regmap_write(wcd->if_regmap,
1760                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1761                                 payload & 0x00FF);
1762                         if (ret < 0)
1763                                 goto err;
1764
1765                         /* ports 8,9 */
1766                         ret = regmap_write(wcd->if_regmap,
1767                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1768                                 (payload & 0xFF00) >> 8);
1769                         if (ret < 0)
1770                                 goto err;
1771
1772                         /* configure the slave port for water mark and enable*/
1773                         ret = regmap_write(wcd->if_regmap,
1774                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1775                                         WCD934X_SLIM_WATER_MARK_VAL);
1776
1777                         if (ret < 0)
1778                                 goto err;
1779                 }
1780         }
1781
1782         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1783
1784         return 0;
1785
1786 err:
1787         dev_err(wcd->dev, "Error Setting slim hw params\n");
1788         kfree(cfg->chs);
1789         cfg->chs = NULL;
1790
1791         return ret;
1792 }
1793
1794 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1795                              struct snd_pcm_hw_params *params,
1796                              struct snd_soc_dai *dai)
1797 {
1798         struct wcd934x_codec *wcd;
1799         int ret, tx_fs_rate = 0;
1800
1801         wcd = snd_soc_component_get_drvdata(dai->component);
1802
1803         switch (substream->stream) {
1804         case SNDRV_PCM_STREAM_PLAYBACK:
1805                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1806                 if (ret) {
1807                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1808                                 params_rate(params));
1809                         return ret;
1810                 }
1811                 switch (params_width(params)) {
1812                 case 16 ... 24:
1813                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1814                         break;
1815                 default:
1816                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1817                                 params_width(params));
1818                         return -EINVAL;
1819                 }
1820                 break;
1821
1822         case SNDRV_PCM_STREAM_CAPTURE:
1823                 switch (params_rate(params)) {
1824                 case 8000:
1825                         tx_fs_rate = 0;
1826                         break;
1827                 case 16000:
1828                         tx_fs_rate = 1;
1829                         break;
1830                 case 32000:
1831                         tx_fs_rate = 3;
1832                         break;
1833                 case 48000:
1834                         tx_fs_rate = 4;
1835                         break;
1836                 case 96000:
1837                         tx_fs_rate = 5;
1838                         break;
1839                 case 192000:
1840                         tx_fs_rate = 6;
1841                         break;
1842                 case 384000:
1843                         tx_fs_rate = 7;
1844                         break;
1845                 default:
1846                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1847                                 params_rate(params));
1848                         return -EINVAL;
1849
1850                 }
1851
1852                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1853                                                  params_rate(params));
1854                 if (ret < 0) {
1855                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1856                         return ret;
1857                 }
1858                 switch (params_width(params)) {
1859                 case 16 ... 32:
1860                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1861                         break;
1862                 default:
1863                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1864                                 params_width(params));
1865                         return -EINVAL;
1866                 }
1867                 break;
1868         default:
1869                 dev_err(wcd->dev, "Invalid stream type %d\n",
1870                         substream->stream);
1871                 return -EINVAL;
1872         }
1873
1874         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1875
1876         return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1877 }
1878
1879 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1880                            struct snd_soc_dai *dai)
1881 {
1882         struct wcd_slim_codec_dai_data *dai_data;
1883         struct wcd934x_codec *wcd;
1884
1885         wcd = snd_soc_component_get_drvdata(dai->component);
1886
1887         dai_data = &wcd->dai[dai->id];
1888
1889         kfree(dai_data->sconfig.chs);
1890
1891         return 0;
1892 }
1893
1894 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1895                            struct snd_soc_dai *dai)
1896 {
1897         struct wcd_slim_codec_dai_data *dai_data;
1898         struct wcd934x_codec *wcd;
1899         struct slim_stream_config *cfg;
1900
1901         wcd = snd_soc_component_get_drvdata(dai->component);
1902
1903         dai_data = &wcd->dai[dai->id];
1904
1905         switch (cmd) {
1906         case SNDRV_PCM_TRIGGER_START:
1907         case SNDRV_PCM_TRIGGER_RESUME:
1908         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1909                 cfg = &dai_data->sconfig;
1910                 slim_stream_prepare(dai_data->sruntime, cfg);
1911                 slim_stream_enable(dai_data->sruntime);
1912                 break;
1913         case SNDRV_PCM_TRIGGER_STOP:
1914         case SNDRV_PCM_TRIGGER_SUSPEND:
1915         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1916                 slim_stream_unprepare(dai_data->sruntime);
1917                 slim_stream_disable(dai_data->sruntime);
1918                 break;
1919         default:
1920                 break;
1921         }
1922
1923         return 0;
1924 }
1925
1926 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1927                                    unsigned int tx_num, unsigned int *tx_slot,
1928                                    unsigned int rx_num, unsigned int *rx_slot)
1929 {
1930         struct wcd934x_codec *wcd;
1931         int i;
1932
1933         wcd = snd_soc_component_get_drvdata(dai->component);
1934
1935         if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1936                 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1937                         tx_num, rx_num);
1938                 return -EINVAL;
1939         }
1940
1941         if (!tx_slot || !rx_slot) {
1942                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1943                         tx_slot, rx_slot);
1944                 return -EINVAL;
1945         }
1946
1947         wcd->num_rx_port = rx_num;
1948         for (i = 0; i < rx_num; i++) {
1949                 wcd->rx_chs[i].ch_num = rx_slot[i];
1950                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1951         }
1952
1953         wcd->num_tx_port = tx_num;
1954         for (i = 0; i < tx_num; i++) {
1955                 wcd->tx_chs[i].ch_num = tx_slot[i];
1956                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1963                                    unsigned int *tx_num, unsigned int *tx_slot,
1964                                    unsigned int *rx_num, unsigned int *rx_slot)
1965 {
1966         struct wcd934x_slim_ch *ch;
1967         struct wcd934x_codec *wcd;
1968         int i = 0;
1969
1970         wcd = snd_soc_component_get_drvdata(dai->component);
1971
1972         switch (dai->id) {
1973         case AIF1_PB:
1974         case AIF2_PB:
1975         case AIF3_PB:
1976         case AIF4_PB:
1977                 if (!rx_slot || !rx_num) {
1978                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1979                                 rx_slot, rx_num);
1980                         return -EINVAL;
1981                 }
1982
1983                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1984                         rx_slot[i++] = ch->ch_num;
1985
1986                 *rx_num = i;
1987                 break;
1988         case AIF1_CAP:
1989         case AIF2_CAP:
1990         case AIF3_CAP:
1991                 if (!tx_slot || !tx_num) {
1992                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1993                                 tx_slot, tx_num);
1994                         return -EINVAL;
1995                 }
1996
1997                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1998                         tx_slot[i++] = ch->ch_num;
1999
2000                 *tx_num = i;
2001                 break;
2002         default:
2003                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2004                 break;
2005         }
2006
2007         return 0;
2008 }
2009
2010 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
2011         .hw_params = wcd934x_hw_params,
2012         .hw_free = wcd934x_hw_free,
2013         .trigger = wcd934x_trigger,
2014         .set_channel_map = wcd934x_set_channel_map,
2015         .get_channel_map = wcd934x_get_channel_map,
2016 };
2017
2018 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
2019         [0] = {
2020                 .name = "wcd934x_rx1",
2021                 .id = AIF1_PB,
2022                 .playback = {
2023                         .stream_name = "AIF1 Playback",
2024                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2025                         .formats = WCD934X_FORMATS_S16_S24_LE,
2026                         .rate_max = 192000,
2027                         .rate_min = 8000,
2028                         .channels_min = 1,
2029                         .channels_max = 2,
2030                 },
2031                 .ops = &wcd934x_dai_ops,
2032         },
2033         [1] = {
2034                 .name = "wcd934x_tx1",
2035                 .id = AIF1_CAP,
2036                 .capture = {
2037                         .stream_name = "AIF1 Capture",
2038                         .rates = WCD934X_RATES_MASK,
2039                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2040                         .rate_min = 8000,
2041                         .rate_max = 192000,
2042                         .channels_min = 1,
2043                         .channels_max = 4,
2044                 },
2045                 .ops = &wcd934x_dai_ops,
2046         },
2047         [2] = {
2048                 .name = "wcd934x_rx2",
2049                 .id = AIF2_PB,
2050                 .playback = {
2051                         .stream_name = "AIF2 Playback",
2052                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2053                         .formats = WCD934X_FORMATS_S16_S24_LE,
2054                         .rate_min = 8000,
2055                         .rate_max = 192000,
2056                         .channels_min = 1,
2057                         .channels_max = 2,
2058                 },
2059                 .ops = &wcd934x_dai_ops,
2060         },
2061         [3] = {
2062                 .name = "wcd934x_tx2",
2063                 .id = AIF2_CAP,
2064                 .capture = {
2065                         .stream_name = "AIF2 Capture",
2066                         .rates = WCD934X_RATES_MASK,
2067                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2068                         .rate_min = 8000,
2069                         .rate_max = 192000,
2070                         .channels_min = 1,
2071                         .channels_max = 4,
2072                 },
2073                 .ops = &wcd934x_dai_ops,
2074         },
2075         [4] = {
2076                 .name = "wcd934x_rx3",
2077                 .id = AIF3_PB,
2078                 .playback = {
2079                         .stream_name = "AIF3 Playback",
2080                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2081                         .formats = WCD934X_FORMATS_S16_S24_LE,
2082                         .rate_min = 8000,
2083                         .rate_max = 192000,
2084                         .channels_min = 1,
2085                         .channels_max = 2,
2086                 },
2087                 .ops = &wcd934x_dai_ops,
2088         },
2089         [5] = {
2090                 .name = "wcd934x_tx3",
2091                 .id = AIF3_CAP,
2092                 .capture = {
2093                         .stream_name = "AIF3 Capture",
2094                         .rates = WCD934X_RATES_MASK,
2095                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2096                         .rate_min = 8000,
2097                         .rate_max = 192000,
2098                         .channels_min = 1,
2099                         .channels_max = 4,
2100                 },
2101                 .ops = &wcd934x_dai_ops,
2102         },
2103         [6] = {
2104                 .name = "wcd934x_rx4",
2105                 .id = AIF4_PB,
2106                 .playback = {
2107                         .stream_name = "AIF4 Playback",
2108                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2109                         .formats = WCD934X_FORMATS_S16_S24_LE,
2110                         .rate_min = 8000,
2111                         .rate_max = 192000,
2112                         .channels_min = 1,
2113                         .channels_max = 2,
2114                 },
2115                 .ops = &wcd934x_dai_ops,
2116         },
2117 };
2118
2119 static int swclk_gate_enable(struct clk_hw *hw)
2120 {
2121         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2122 }
2123
2124 static void swclk_gate_disable(struct clk_hw *hw)
2125 {
2126         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2127 }
2128
2129 static int swclk_gate_is_enabled(struct clk_hw *hw)
2130 {
2131         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2132         int ret, val;
2133
2134         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2135         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2136
2137         return ret;
2138 }
2139
2140 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2141                                        unsigned long parent_rate)
2142 {
2143         return parent_rate / 2;
2144 }
2145
2146 static const struct clk_ops swclk_gate_ops = {
2147         .prepare = swclk_gate_enable,
2148         .unprepare = swclk_gate_disable,
2149         .is_enabled = swclk_gate_is_enabled,
2150         .recalc_rate = swclk_recalc_rate,
2151
2152 };
2153
2154 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2155 {
2156         struct clk *parent = wcd->extclk;
2157         struct device *dev = wcd->dev;
2158         struct device_node *np = dev->parent->of_node;
2159         const char *parent_clk_name = NULL;
2160         const char *clk_name = "mclk";
2161         struct clk_hw *hw;
2162         struct clk_init_data init;
2163         int ret;
2164
2165         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2166                 return NULL;
2167
2168         parent_clk_name = __clk_get_name(parent);
2169
2170         of_property_read_string(np, "clock-output-names", &clk_name);
2171
2172         init.name = clk_name;
2173         init.ops = &swclk_gate_ops;
2174         init.flags = 0;
2175         init.parent_names = &parent_clk_name;
2176         init.num_parents = 1;
2177         wcd->hw.init = &init;
2178
2179         hw = &wcd->hw;
2180         ret = devm_clk_hw_register(wcd->dev->parent, hw);
2181         if (ret)
2182                 return ERR_PTR(ret);
2183
2184         ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2185         if (ret)
2186                 return ERR_PTR(ret);
2187
2188         return NULL;
2189 }
2190
2191 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2192                                    u32 *micb_mv)
2193 {
2194         int mv;
2195
2196         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2197                 dev_err(dev, "%s value not found, using default\n", micbias);
2198                 mv = WCD934X_DEF_MICBIAS_MV;
2199         } else {
2200                 /* convert it to milli volts */
2201                 mv = mv/1000;
2202         }
2203
2204         if (mv < 1000 || mv > 2850) {
2205                 dev_err(dev, "%s value not in valid range, using default\n",
2206                         micbias);
2207                 mv = WCD934X_DEF_MICBIAS_MV;
2208         }
2209
2210         *micb_mv = mv;
2211
2212         return (mv - 1000) / 50;
2213 }
2214
2215 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2216 {
2217         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2218         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2219         u32 def_dmic_rate, dmic_clk_drv;
2220
2221         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2222                                              "qcom,micbias1-microvolt",
2223                                              &wcd->micb1_mv);
2224         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2225                                              "qcom,micbias2-microvolt",
2226                                              &wcd->micb2_mv);
2227         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2228                                              "qcom,micbias3-microvolt",
2229                                              &wcd->micb3_mv);
2230         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2231                                              "qcom,micbias4-microvolt",
2232                                              &wcd->micb4_mv);
2233
2234         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2235                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
2236         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2237                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
2238         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2239                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
2240         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2241                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
2242
2243         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2244                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2245         else
2246                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2247
2248         wcd->dmic_sample_rate = def_dmic_rate;
2249
2250         dmic_clk_drv = 0;
2251         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2252                                       0x0C, dmic_clk_drv << 2);
2253
2254         return 0;
2255 }
2256
2257 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2258 {
2259         struct regmap *rm = wcd->regmap;
2260
2261         /* set SPKR rate to FS_2P4_3P072 */
2262         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2263         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2264
2265         /* Take DMICs out of reset */
2266         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2267 }
2268
2269 static int wcd934x_comp_init(struct snd_soc_component *component)
2270 {
2271         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2272
2273         wcd934x_hw_init(wcd);
2274         wcd934x_enable_efuse_sensing(wcd);
2275         wcd934x_get_version(wcd);
2276
2277         return 0;
2278 }
2279
2280 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2281 {
2282         struct wcd934x_codec *wcd = data;
2283         unsigned long status = 0;
2284         int i, j, port_id;
2285         unsigned int val, int_val = 0;
2286         irqreturn_t ret = IRQ_NONE;
2287         bool tx;
2288         unsigned short reg = 0;
2289
2290         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2291              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2292                 regmap_read(wcd->if_regmap, i, &val);
2293                 status |= ((u32)val << (8 * j));
2294         }
2295
2296         for_each_set_bit(j, &status, 32) {
2297                 tx = false;
2298                 port_id = j;
2299
2300                 if (j >= 16) {
2301                         tx = true;
2302                         port_id = j - 16;
2303                 }
2304
2305                 regmap_read(wcd->if_regmap,
2306                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2307                 if (val) {
2308                         if (!tx)
2309                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2310                                         (port_id / 8);
2311                         else
2312                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2313                                         (port_id / 8);
2314                         regmap_read(wcd->if_regmap, reg, &int_val);
2315                 }
2316
2317                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2318                         dev_err_ratelimited(wcd->dev,
2319                                             "overflow error on %s port %d, value %x\n",
2320                                             (tx ? "TX" : "RX"), port_id, val);
2321
2322                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2323                         dev_err_ratelimited(wcd->dev,
2324                                             "underflow error on %s port %d, value %x\n",
2325                                             (tx ? "TX" : "RX"), port_id, val);
2326
2327                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2328                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2329                         if (!tx)
2330                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2331                                         (port_id / 8);
2332                         else
2333                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2334                                         (port_id / 8);
2335                         regmap_read(
2336                                 wcd->if_regmap, reg, &int_val);
2337                         if (int_val & (1 << (port_id % 8))) {
2338                                 int_val = int_val ^ (1 << (port_id % 8));
2339                                 regmap_write(wcd->if_regmap,
2340                                              reg, int_val);
2341                         }
2342                 }
2343
2344                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2345                         dev_err_ratelimited(wcd->dev,
2346                                             "Port Closed %s port %d, value %x\n",
2347                                             (tx ? "TX" : "RX"), port_id, val);
2348
2349                 regmap_write(wcd->if_regmap,
2350                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2351                                 BIT(j % 8));
2352                 ret = IRQ_HANDLED;
2353         }
2354
2355         return ret;
2356 }
2357
2358 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2359                                    bool enable)
2360 {
2361         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2362                                       WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2363 }
2364
2365 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2366                                            bool enable)
2367 {
2368         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2369                                       WCD934X_ANA_MBHC_BIAS_EN, enable);
2370 }
2371
2372 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2373                                          int *btn_low, int *btn_high,
2374                                          int num_btn, bool is_micbias)
2375 {
2376         int i, vth;
2377
2378         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2379                 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2380                         __func__, num_btn);
2381                 return;
2382         }
2383
2384         for (i = 0; i < num_btn; i++) {
2385                 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2386                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2387                                            WCD934X_MBHC_BTN_VTH_MASK, vth);
2388         }
2389 }
2390
2391 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2392 {
2393         u8 val;
2394
2395         if (micb_num == MIC_BIAS_2) {
2396                 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2397                                                    WCD934X_ANA_MICB2_ENABLE_MASK);
2398                 if (val == WCD934X_MICB_ENABLE)
2399                         return true;
2400         }
2401         return false;
2402 }
2403
2404 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2405                                                enum mbhc_hs_pullup_iref pull_up_cur)
2406 {
2407         /* Default pull up current to 2uA */
2408         if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2409             pull_up_cur == I_DEFAULT)
2410                 pull_up_cur = I_2P0_UA;
2411
2412
2413         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2414                                       WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2415 }
2416
2417 static int wcd934x_micbias_control(struct snd_soc_component *component,
2418                             int micb_num, int req, bool is_dapm)
2419 {
2420         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2421         int micb_index = micb_num - 1;
2422         u16 micb_reg;
2423
2424         switch (micb_num) {
2425         case MIC_BIAS_1:
2426                 micb_reg = WCD934X_ANA_MICB1;
2427                 break;
2428         case MIC_BIAS_2:
2429                 micb_reg = WCD934X_ANA_MICB2;
2430                 break;
2431         case MIC_BIAS_3:
2432                 micb_reg = WCD934X_ANA_MICB3;
2433                 break;
2434         case MIC_BIAS_4:
2435                 micb_reg = WCD934X_ANA_MICB4;
2436                 break;
2437         default:
2438                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2439                         __func__, micb_num);
2440                 return -EINVAL;
2441         }
2442         mutex_lock(&wcd934x->micb_lock);
2443
2444         switch (req) {
2445         case MICB_PULLUP_ENABLE:
2446                 wcd934x->pullup_ref[micb_index]++;
2447                 if ((wcd934x->pullup_ref[micb_index] == 1) &&
2448                     (wcd934x->micb_ref[micb_index] == 0))
2449                         snd_soc_component_write_field(component, micb_reg,
2450                                                       WCD934X_ANA_MICB_EN_MASK,
2451                                                       WCD934X_MICB_PULL_UP);
2452                 break;
2453         case MICB_PULLUP_DISABLE:
2454                 if (wcd934x->pullup_ref[micb_index] > 0)
2455                         wcd934x->pullup_ref[micb_index]--;
2456
2457                 if ((wcd934x->pullup_ref[micb_index] == 0) &&
2458                     (wcd934x->micb_ref[micb_index] == 0))
2459                         snd_soc_component_write_field(component, micb_reg,
2460                                                       WCD934X_ANA_MICB_EN_MASK, 0);
2461                 break;
2462         case MICB_ENABLE:
2463                 wcd934x->micb_ref[micb_index]++;
2464                 if (wcd934x->micb_ref[micb_index] == 1) {
2465                         snd_soc_component_write_field(component, micb_reg,
2466                                                       WCD934X_ANA_MICB_EN_MASK,
2467                                                       WCD934X_MICB_ENABLE);
2468                         if (micb_num  == MIC_BIAS_2)
2469                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2470                                                       WCD_EVENT_POST_MICBIAS_2_ON);
2471                 }
2472
2473                 if (micb_num  == MIC_BIAS_2 && is_dapm)
2474                         wcd_mbhc_event_notify(wcd934x->mbhc,
2475                                               WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2476                 break;
2477         case MICB_DISABLE:
2478                 if (wcd934x->micb_ref[micb_index] > 0)
2479                         wcd934x->micb_ref[micb_index]--;
2480
2481                 if ((wcd934x->micb_ref[micb_index] == 0) &&
2482                     (wcd934x->pullup_ref[micb_index] > 0))
2483                         snd_soc_component_write_field(component, micb_reg,
2484                                                       WCD934X_ANA_MICB_EN_MASK,
2485                                                       WCD934X_MICB_PULL_UP);
2486                 else if ((wcd934x->micb_ref[micb_index] == 0) &&
2487                          (wcd934x->pullup_ref[micb_index] == 0)) {
2488                         if (micb_num  == MIC_BIAS_2)
2489                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2490                                                       WCD_EVENT_PRE_MICBIAS_2_OFF);
2491
2492                         snd_soc_component_write_field(component, micb_reg,
2493                                                       WCD934X_ANA_MICB_EN_MASK, 0);
2494                         if (micb_num  == MIC_BIAS_2)
2495                                 wcd_mbhc_event_notify(wcd934x->mbhc,
2496                                                       WCD_EVENT_POST_MICBIAS_2_OFF);
2497                 }
2498                 if (is_dapm && micb_num  == MIC_BIAS_2)
2499                         wcd_mbhc_event_notify(wcd934x->mbhc,
2500                                               WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2501                 break;
2502         }
2503
2504         mutex_unlock(&wcd934x->micb_lock);
2505
2506         return 0;
2507 }
2508
2509 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2510                                         int micb_num, int req)
2511 {
2512         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2513         int ret;
2514
2515         if (req == MICB_ENABLE)
2516                 __wcd934x_cdc_mclk_enable(wcd, true);
2517
2518         ret = wcd934x_micbias_control(component, micb_num, req, false);
2519
2520         if (req == MICB_DISABLE)
2521                 __wcd934x_cdc_mclk_enable(wcd, false);
2522
2523         return ret;
2524 }
2525
2526 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2527                                            bool enable)
2528 {
2529         if (enable) {
2530                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2531                                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2532                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2533                                     WCD934X_RAMP_EN_MASK, 1);
2534         } else {
2535                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2536                                     WCD934X_RAMP_EN_MASK, 0);
2537                 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2538                                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2539         }
2540 }
2541
2542 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2543 {
2544         /* min micbias voltage is 1V and maximum is 2.85V */
2545         if (micb_mv < 1000 || micb_mv > 2850)
2546                 return -EINVAL;
2547
2548         return (micb_mv - 1000) / 50;
2549 }
2550
2551 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2552                                             int req_volt, int micb_num)
2553 {
2554         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2555         int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2556
2557         switch (micb_num) {
2558         case MIC_BIAS_1:
2559                 micb_reg = WCD934X_ANA_MICB1;
2560                 break;
2561         case MIC_BIAS_2:
2562                 micb_reg = WCD934X_ANA_MICB2;
2563                 break;
2564         case MIC_BIAS_3:
2565                 micb_reg = WCD934X_ANA_MICB3;
2566                 break;
2567         case MIC_BIAS_4:
2568                 micb_reg = WCD934X_ANA_MICB4;
2569                 break;
2570         default:
2571                 return -EINVAL;
2572         }
2573         mutex_lock(&wcd934x->micb_lock);
2574         /*
2575          * If requested micbias voltage is same as current micbias
2576          * voltage, then just return. Otherwise, adjust voltage as
2577          * per requested value. If micbias is already enabled, then
2578          * to avoid slow micbias ramp-up or down enable pull-up
2579          * momentarily, change the micbias value and then re-enable
2580          * micbias.
2581          */
2582         micb_en = snd_soc_component_read_field(component, micb_reg,
2583                                                 WCD934X_ANA_MICB_EN_MASK);
2584         cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2585                                                     WCD934X_MICB_VAL_MASK);
2586
2587         req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2588         if (req_vout_ctl < 0) {
2589                 ret = -EINVAL;
2590                 goto exit;
2591         }
2592
2593         if (cur_vout_ctl == req_vout_ctl) {
2594                 ret = 0;
2595                 goto exit;
2596         }
2597
2598         if (micb_en == WCD934X_MICB_ENABLE)
2599                 snd_soc_component_write_field(component, micb_reg,
2600                                               WCD934X_ANA_MICB_EN_MASK,
2601                                               WCD934X_MICB_PULL_UP);
2602
2603         snd_soc_component_write_field(component, micb_reg,
2604                                       WCD934X_MICB_VAL_MASK,
2605                                       req_vout_ctl);
2606
2607         if (micb_en == WCD934X_MICB_ENABLE) {
2608                 snd_soc_component_write_field(component, micb_reg,
2609                                               WCD934X_ANA_MICB_EN_MASK,
2610                                               WCD934X_MICB_ENABLE);
2611                 /*
2612                  * Add 2ms delay as per HW requirement after enabling
2613                  * micbias
2614                  */
2615                 usleep_range(2000, 2100);
2616         }
2617 exit:
2618         mutex_unlock(&wcd934x->micb_lock);
2619         return ret;
2620 }
2621
2622 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2623                                                 int micb_num, bool req_en)
2624 {
2625         struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2626         int rc, micb_mv;
2627
2628         if (micb_num != MIC_BIAS_2)
2629                 return -EINVAL;
2630         /*
2631          * If device tree micbias level is already above the minimum
2632          * voltage needed to detect threshold microphone, then do
2633          * not change the micbias, just return.
2634          */
2635         if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2636                 return 0;
2637
2638         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2639
2640         rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2641
2642         return rc;
2643 }
2644
2645 static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2646                                                 s16 *d1_a, u16 noff,
2647                                                 int32_t *zdet)
2648 {
2649         int i;
2650         int val, val1;
2651         s16 c1;
2652         s32 x1, d1;
2653         int32_t denom;
2654         int minCode_param[] = {
2655                         3277, 1639, 820, 410, 205, 103, 52, 26
2656         };
2657
2658         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2659         for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2660                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2661                 if (val & 0x80)
2662                         break;
2663         }
2664         val = val << 0x8;
2665         regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2666         val |= val1;
2667         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2668         x1 = WCD934X_MBHC_GET_X1(val);
2669         c1 = WCD934X_MBHC_GET_C1(val);
2670         /* If ramp is not complete, give additional 5ms */
2671         if ((c1 < 2) && x1)
2672                 usleep_range(5000, 5050);
2673
2674         if (!c1 || !x1) {
2675                 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2676                         __func__, c1, x1);
2677                 goto ramp_down;
2678         }
2679         d1 = d1_a[c1];
2680         denom = (x1 * d1) - (1 << (14 - noff));
2681         if (denom > 0)
2682                 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2683         else if (x1 < minCode_param[noff])
2684                 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2685
2686         dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2687                 __func__, d1, c1, x1, *zdet);
2688 ramp_down:
2689         i = 0;
2690
2691         while (x1) {
2692                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2693                 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2694                 val = val << 0x08;
2695                 val |= val1;
2696                 x1 = WCD934X_MBHC_GET_X1(val);
2697                 i++;
2698                 if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2699                         break;
2700         }
2701 }
2702
2703 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2704                                  struct wcd934x_mbhc_zdet_param *zdet_param,
2705                                  int32_t *zl, int32_t *zr, s16 *d1_a)
2706 {
2707         struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2708         int32_t zdet = 0;
2709
2710         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2711                                 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2712         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2713                                     WCD934X_VTH_MASK, zdet_param->btn5);
2714         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2715                                       WCD934X_VTH_MASK, zdet_param->btn6);
2716         snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2717                                      WCD934X_VTH_MASK, zdet_param->btn7);
2718         snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2719                                 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2720         snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2721                                 0x0F, zdet_param->nshift);
2722
2723         if (!zl)
2724                 goto z_right;
2725         /* Start impedance measurement for HPH_L */
2726         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2727         wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2728         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2729
2730         *zl = zdet;
2731
2732 z_right:
2733         if (!zr)
2734                 return;
2735         /* Start impedance measurement for HPH_R */
2736         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2737         wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2738         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2739
2740         *zr = zdet;
2741 }
2742
2743 static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2744                                               int32_t *z_val, int flag_l_r)
2745 {
2746         s16 q1;
2747         int q1_cal;
2748
2749         if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2750                 q1 = snd_soc_component_read(component,
2751                         WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2752         else
2753                 q1 = snd_soc_component_read(component,
2754                         WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2755         if (q1 & 0x80)
2756                 q1_cal = (10000 - ((q1 & 0x7F) * 25));
2757         else
2758                 q1_cal = (10000 + (q1 * 25));
2759         if (q1_cal > 0)
2760                 *z_val = ((*z_val) * 10000) / q1_cal;
2761 }
2762
2763 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2764                                             uint32_t *zl, uint32_t *zr)
2765 {
2766         struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2767         s16 reg0, reg1, reg2, reg3, reg4;
2768         int32_t z1L, z1R, z1Ls;
2769         int zMono, z_diff1, z_diff2;
2770         bool is_fsm_disable = false;
2771         struct wcd934x_mbhc_zdet_param zdet_param[] = {
2772                 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2773                 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2774                 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2775                 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2776         };
2777         struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2778         s16 d1_a[][4] = {
2779                 {0, 30, 90, 30},
2780                 {0, 30, 30, 5},
2781                 {0, 30, 30, 5},
2782                 {0, 30, 30, 5},
2783         };
2784         s16 *d1 = NULL;
2785
2786         reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2787         reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2788         reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2789         reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2790         reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2791
2792         if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2793                 is_fsm_disable = true;
2794                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2795         }
2796
2797         /* For NO-jack, disable L_DET_EN before Z-det measurements */
2798         if (wcd934x->mbhc_cfg.hphl_swh)
2799                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2800
2801         /* Turn off 100k pull down on HPHL */
2802         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2803
2804         /* First get impedance on Left */
2805         d1 = d1_a[1];
2806         zdet_param_ptr = &zdet_param[1];
2807         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2808
2809         if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2810                 goto left_ch_impedance;
2811
2812         /* Second ramp for left ch */
2813         if (z1L < WCD934X_ZDET_VAL_32) {
2814                 zdet_param_ptr = &zdet_param[0];
2815                 d1 = d1_a[0];
2816         } else if ((z1L > WCD934X_ZDET_VAL_400) &&
2817                   (z1L <= WCD934X_ZDET_VAL_1200)) {
2818                 zdet_param_ptr = &zdet_param[2];
2819                 d1 = d1_a[2];
2820         } else if (z1L > WCD934X_ZDET_VAL_1200) {
2821                 zdet_param_ptr = &zdet_param[3];
2822                 d1 = d1_a[3];
2823         }
2824         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2825
2826 left_ch_impedance:
2827         if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2828                 (z1L > WCD934X_ZDET_VAL_100K)) {
2829                 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2830                 zdet_param_ptr = &zdet_param[1];
2831                 d1 = d1_a[1];
2832         } else {
2833                 *zl = z1L/1000;
2834                 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2835         }
2836         dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2837                 __func__, *zl);
2838
2839         /* Start of right impedance ramp and calculation */
2840         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2841         if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2842                 if (((z1R > WCD934X_ZDET_VAL_1200) &&
2843                         (zdet_param_ptr->noff == 0x6)) ||
2844                         ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2845                         goto right_ch_impedance;
2846                 /* Second ramp for right ch */
2847                 if (z1R < WCD934X_ZDET_VAL_32) {
2848                         zdet_param_ptr = &zdet_param[0];
2849                         d1 = d1_a[0];
2850                 } else if ((z1R > WCD934X_ZDET_VAL_400) &&
2851                         (z1R <= WCD934X_ZDET_VAL_1200)) {
2852                         zdet_param_ptr = &zdet_param[2];
2853                         d1 = d1_a[2];
2854                 } else if (z1R > WCD934X_ZDET_VAL_1200) {
2855                         zdet_param_ptr = &zdet_param[3];
2856                         d1 = d1_a[3];
2857                 }
2858                 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2859         }
2860 right_ch_impedance:
2861         if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2862                 (z1R > WCD934X_ZDET_VAL_100K)) {
2863                 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2864         } else {
2865                 *zr = z1R/1000;
2866                 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2867         }
2868         dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2869                 __func__, *zr);
2870
2871         /* Mono/stereo detection */
2872         if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2873                 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2874                 dev_dbg(component->dev,
2875                         "%s: plug type is invalid or extension cable\n",
2876                         __func__);
2877                 goto zdet_complete;
2878         }
2879         if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2880             (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2881             ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2882             ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2883                 dev_dbg(component->dev,
2884                         "%s: Mono plug type with one ch floating or shorted to GND\n",
2885                         __func__);
2886                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2887                 goto zdet_complete;
2888         }
2889         snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2890                                       WCD934X_HPHPA_GND_OVR_MASK, 1);
2891         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2892                                       WCD934X_HPHPA_GND_R_MASK, 1);
2893         if (*zl < (WCD934X_ZDET_VAL_32/1000))
2894                 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2895         else
2896                 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2897         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2898                                       WCD934X_HPHPA_GND_R_MASK, 0);
2899         snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2900                                       WCD934X_HPHPA_GND_OVR_MASK, 0);
2901         z1Ls /= 1000;
2902         wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2903         /* Parallel of left Z and 9 ohm pull down resistor */
2904         zMono = ((*zl) * 9) / ((*zl) + 9);
2905         z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2906         z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2907         if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2908                 dev_err(component->dev, "%s: stereo plug type detected\n",
2909                         __func__);
2910                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2911         } else {
2912                 dev_err(component->dev, "%s: MONO plug type detected\n",
2913                         __func__);
2914                 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2915         }
2916
2917 zdet_complete:
2918         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2919         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2920         snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2921         /* Turn on 100k pull down on HPHL */
2922         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2923
2924         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2925         if (wcd934x->mbhc_cfg.hphl_swh)
2926                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2927
2928         snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2929         snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2930         if (is_fsm_disable)
2931                 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2932 }
2933
2934 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2935                         bool enable)
2936 {
2937         if (enable) {
2938                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2939                                               WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2940                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2941                                               WCD934X_MBHC_GND_DET_EN_MASK, 1);
2942         } else {
2943                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2944                                               WCD934X_MBHC_GND_DET_EN_MASK, 0);
2945                 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2946                                               WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2947         }
2948 }
2949
2950 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2951                                           bool enable)
2952 {
2953         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2954                                       WCD934X_HPHPA_GND_R_MASK, enable);
2955         snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2956                                       WCD934X_HPHPA_GND_L_MASK, enable);
2957 }
2958
2959 static const struct wcd_mbhc_cb mbhc_cb = {
2960         .clk_setup = wcd934x_mbhc_clk_setup,
2961         .mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2962         .set_btn_thr = wcd934x_mbhc_program_btn_thr,
2963         .micbias_enable_status = wcd934x_mbhc_micb_en_status,
2964         .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2965         .mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2966         .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2967         .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2968         .compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2969         .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2970         .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2971 };
2972
2973 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2974                               struct snd_ctl_elem_value *ucontrol)
2975 {
2976         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2977         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2978
2979         ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
2980
2981         return 0;
2982 }
2983
2984 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2985                                    struct snd_ctl_elem_value *ucontrol)
2986 {
2987         uint32_t zl, zr;
2988         bool hphr;
2989         struct soc_mixer_control *mc;
2990         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2991         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2992
2993         mc = (struct soc_mixer_control *)(kcontrol->private_value);
2994         hphr = mc->shift;
2995         wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
2996         dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2997         ucontrol->value.integer.value[0] = hphr ? zr : zl;
2998
2999         return 0;
3000 }
3001 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3002         SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3003                        wcd934x_get_hph_type, NULL),
3004 };
3005
3006 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3007         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3008                        wcd934x_hph_impedance_get, NULL),
3009         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3010                        wcd934x_hph_impedance_get, NULL),
3011 };
3012
3013 static int wcd934x_mbhc_init(struct snd_soc_component *component)
3014 {
3015         struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
3016         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3017         struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
3018
3019         intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
3020                                                      WCD934X_IRQ_MBHC_SW_DET);
3021         intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3022                                                             WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3023         intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3024                                                               WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3025         intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3026                                                          WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3027         intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3028                                                          WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3029         intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3030                                                      WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3031         intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3032                                                       WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3033
3034         wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3035         if (IS_ERR(wcd->mbhc)) {
3036                 wcd->mbhc = NULL;
3037                 return -EINVAL;
3038         }
3039
3040         snd_soc_add_component_controls(component, impedance_detect_controls,
3041                                        ARRAY_SIZE(impedance_detect_controls));
3042         snd_soc_add_component_controls(component, hph_type_detect_controls,
3043                                        ARRAY_SIZE(hph_type_detect_controls));
3044
3045         return 0;
3046 }
3047 static int wcd934x_comp_probe(struct snd_soc_component *component)
3048 {
3049         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3050         int i;
3051
3052         snd_soc_component_init_regmap(component, wcd->regmap);
3053         wcd->component = component;
3054
3055         /* Class-H Init*/
3056         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3057         if (IS_ERR(wcd->clsh_ctrl))
3058                 return PTR_ERR(wcd->clsh_ctrl);
3059
3060         /* Default HPH Mode to Class-H Low HiFi */
3061         wcd->hph_mode = CLS_H_LOHIFI;
3062
3063         wcd934x_comp_init(component);
3064
3065         for (i = 0; i < NUM_CODEC_DAIS; i++)
3066                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3067
3068         wcd934x_init_dmic(component);
3069
3070         if (wcd934x_mbhc_init(component))
3071                 dev_err(component->dev, "Failed to Initialize MBHC\n");
3072
3073         return 0;
3074 }
3075
3076 static void wcd934x_comp_remove(struct snd_soc_component *comp)
3077 {
3078         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3079
3080         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3081 }
3082
3083 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3084                                    int clk_id, int source,
3085                                    unsigned int freq, int dir)
3086 {
3087         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3088         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3089
3090         wcd->rate = freq;
3091
3092         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3093                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3094
3095         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3096                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3097                                       val);
3098
3099         return clk_set_rate(wcd->extclk, freq);
3100 }
3101
3102 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3103                                    int iir_idx, int band_idx, int coeff_idx)
3104 {
3105         u32 value = 0;
3106         int reg, b2_reg;
3107
3108         /* Address does not automatically update if reading */
3109         reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3110         b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3111
3112         snd_soc_component_write(component, reg,
3113                                 ((band_idx * BAND_MAX + coeff_idx) *
3114                                  sizeof(uint32_t)) & 0x7F);
3115
3116         value |= snd_soc_component_read(component, b2_reg);
3117         snd_soc_component_write(component, reg,
3118                                 ((band_idx * BAND_MAX + coeff_idx)
3119                                  * sizeof(uint32_t) + 1) & 0x7F);
3120
3121         value |= (snd_soc_component_read(component, b2_reg) << 8);
3122         snd_soc_component_write(component, reg,
3123                                 ((band_idx * BAND_MAX + coeff_idx)
3124                                  * sizeof(uint32_t) + 2) & 0x7F);
3125
3126         value |= (snd_soc_component_read(component, b2_reg) << 16);
3127         snd_soc_component_write(component, reg,
3128                 ((band_idx * BAND_MAX + coeff_idx)
3129                 * sizeof(uint32_t) + 3) & 0x7F);
3130
3131         /* Mask bits top 2 bits since they are reserved */
3132         value |= (snd_soc_component_read(component, b2_reg) << 24);
3133         return value;
3134 }
3135
3136 static void set_iir_band_coeff(struct snd_soc_component *component,
3137                                int iir_idx, int band_idx, uint32_t value)
3138 {
3139         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3140
3141         snd_soc_component_write(component, reg, (value & 0xFF));
3142         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3143         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3144         /* Mask top 2 bits, 7-8 are reserved */
3145         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3146 }
3147
3148 static int wcd934x_put_iir_band_audio_mixer(
3149                                         struct snd_kcontrol *kcontrol,
3150                                         struct snd_ctl_elem_value *ucontrol)
3151 {
3152         struct snd_soc_component *component =
3153                         snd_soc_kcontrol_component(kcontrol);
3154         struct wcd_iir_filter_ctl *ctl =
3155                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3156         struct soc_bytes_ext *params = &ctl->bytes_ext;
3157         int iir_idx = ctl->iir_idx;
3158         int band_idx = ctl->band_idx;
3159         u32 coeff[BAND_MAX];
3160         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3161
3162         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3163
3164         /* Mask top bit it is reserved */
3165         /* Updates addr automatically for each B2 write */
3166         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3167                                                  sizeof(uint32_t)) & 0x7F);
3168
3169         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3170         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3171         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3172         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3173         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3174
3175         return 0;
3176 }
3177
3178 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3179                                     struct snd_ctl_elem_value *ucontrol)
3180 {
3181         struct snd_soc_component *component =
3182                         snd_soc_kcontrol_component(kcontrol);
3183         struct wcd_iir_filter_ctl *ctl =
3184                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3185         struct soc_bytes_ext *params = &ctl->bytes_ext;
3186         int iir_idx = ctl->iir_idx;
3187         int band_idx = ctl->band_idx;
3188         u32 coeff[BAND_MAX];
3189
3190         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3191         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3192         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3193         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3194         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3195
3196         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3197
3198         return 0;
3199 }
3200
3201 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3202                                    struct snd_ctl_elem_info *ucontrol)
3203 {
3204         struct wcd_iir_filter_ctl *ctl =
3205                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3206         struct soc_bytes_ext *params = &ctl->bytes_ext;
3207
3208         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3209         ucontrol->count = params->max;
3210
3211         return 0;
3212 }
3213
3214 static int wcd934x_compander_get(struct snd_kcontrol *kc,
3215                                  struct snd_ctl_elem_value *ucontrol)
3216 {
3217         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3218         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3219         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3220
3221         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3222
3223         return 0;
3224 }
3225
3226 static int wcd934x_compander_set(struct snd_kcontrol *kc,
3227                                  struct snd_ctl_elem_value *ucontrol)
3228 {
3229         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3230         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3231         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3232         int value = ucontrol->value.integer.value[0];
3233         int sel;
3234
3235         if (wcd->comp_enabled[comp] == value)
3236                 return 0;
3237
3238         wcd->comp_enabled[comp] = value;
3239         sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3240                 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3241
3242         /* Any specific register configuration for compander */
3243         switch (comp) {
3244         case COMPANDER_1:
3245                 /* Set Gain Source Select based on compander enable/disable */
3246                 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3247                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
3248                                               sel);
3249                 break;
3250         case COMPANDER_2:
3251                 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3252                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
3253                                               sel);
3254                 break;
3255         case COMPANDER_3:
3256         case COMPANDER_4:
3257         case COMPANDER_7:
3258         case COMPANDER_8:
3259                 break;
3260         default:
3261                 return 0;
3262         }
3263
3264         return 1;
3265 }
3266
3267 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3268                                    struct snd_ctl_elem_value *ucontrol)
3269 {
3270         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3271         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3272
3273         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3274
3275         return 0;
3276 }
3277
3278 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3279                                    struct snd_ctl_elem_value *ucontrol)
3280 {
3281         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3282         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3283         u32 mode_val;
3284
3285         mode_val = ucontrol->value.enumerated.item[0];
3286
3287         if (mode_val == wcd->hph_mode)
3288                 return 0;
3289
3290         if (mode_val == 0) {
3291                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3292                 mode_val = CLS_H_LOHIFI;
3293         }
3294         wcd->hph_mode = mode_val;
3295
3296         return 1;
3297 }
3298
3299 static int slim_rx_mux_get(struct snd_kcontrol *kc,
3300                            struct snd_ctl_elem_value *ucontrol)
3301 {
3302         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3303         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3304         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3305
3306         ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3307
3308         return 0;
3309 }
3310
3311 static int slim_rx_mux_to_dai_id(int mux)
3312 {
3313         int aif_id;
3314
3315         switch (mux) {
3316         case 1:
3317                 aif_id = AIF1_PB;
3318                 break;
3319         case 2:
3320                 aif_id = AIF2_PB;
3321                 break;
3322         case 3:
3323                 aif_id = AIF3_PB;
3324                 break;
3325         case 4:
3326                 aif_id = AIF4_PB;
3327                 break;
3328         default:
3329                 aif_id = -1;
3330                 break;
3331         }
3332
3333         return aif_id;
3334 }
3335
3336 static int slim_rx_mux_put(struct snd_kcontrol *kc,
3337                            struct snd_ctl_elem_value *ucontrol)
3338 {
3339         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3340         struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3341         struct soc_enum *e = (struct soc_enum *)kc->private_value;
3342         struct snd_soc_dapm_update *update = NULL;
3343         struct wcd934x_slim_ch *ch, *c;
3344         u32 port_id = w->shift;
3345         bool found = false;
3346         int mux_idx;
3347         int prev_mux_idx = wcd->rx_port_value[port_id];
3348         int aif_id;
3349
3350         mux_idx = ucontrol->value.enumerated.item[0];
3351
3352         if (mux_idx == prev_mux_idx)
3353                 return 0;
3354
3355         switch(mux_idx) {
3356         case 0:
3357                 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3358                 if (aif_id < 0)
3359                         return 0;
3360
3361                 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3362                         if (ch->port == port_id + WCD934X_RX_START) {
3363                                 found = true;
3364                                 list_del_init(&ch->list);
3365                                 break;
3366                         }
3367                 }
3368                 if (!found)
3369                         return 0;
3370
3371                 break;
3372         case 1 ... 4:
3373                 aif_id = slim_rx_mux_to_dai_id(mux_idx);
3374                 if (aif_id < 0)
3375                         return 0;
3376
3377                 if (list_empty(&wcd->rx_chs[port_id].list)) {
3378                         list_add_tail(&wcd->rx_chs[port_id].list,
3379                                       &wcd->dai[aif_id].slim_ch_list);
3380                 } else {
3381                         dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3382                         return 0;
3383                 }
3384                 break;
3385
3386         default:
3387                 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3388                 goto err;
3389         }
3390
3391         wcd->rx_port_value[port_id] = mux_idx;
3392         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3393                                       e, update);
3394
3395         return 1;
3396 err:
3397         return -EINVAL;
3398 }
3399
3400 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3401                                        struct snd_ctl_elem_value *ucontrol)
3402 {
3403         struct soc_enum *e = (struct soc_enum *)kc->private_value;
3404         struct snd_soc_component *component;
3405         int reg, val, ret;
3406
3407         component = snd_soc_dapm_kcontrol_component(kc);
3408         val = ucontrol->value.enumerated.item[0];
3409         if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3410                 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3411         else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3412                 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3413         else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3414                 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3415         else
3416                 return -EINVAL;
3417
3418         /* Set Look Ahead Delay */
3419         if (val)
3420                 snd_soc_component_update_bits(component, reg,
3421                                               WCD934X_RX_DLY_ZN_EN_MASK,
3422                                               WCD934X_RX_DLY_ZN_ENABLE);
3423         else
3424                 snd_soc_component_update_bits(component, reg,
3425                                               WCD934X_RX_DLY_ZN_EN_MASK,
3426                                               WCD934X_RX_DLY_ZN_DISABLE);
3427
3428         ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
3429
3430         return ret;
3431 }
3432
3433 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3434                                 struct snd_ctl_elem_value *ucontrol)
3435 {
3436         struct snd_soc_component *comp;
3437         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3438         unsigned int val;
3439         u16 mic_sel_reg = 0;
3440         u8 mic_sel;
3441
3442         comp = snd_soc_dapm_kcontrol_component(kcontrol);
3443
3444         val = ucontrol->value.enumerated.item[0];
3445         if (val > e->items - 1)
3446                 return -EINVAL;
3447
3448         switch (e->reg) {
3449         case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3450                 if (e->shift_l == 0)
3451                         mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3452                 else if (e->shift_l == 2)
3453                         mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3454                 else if (e->shift_l == 4)
3455                         mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3456                 break;
3457         case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3458                 if (e->shift_l == 0)
3459                         mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3460                 else if (e->shift_l == 2)
3461                         mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3462                 break;
3463         case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3464                 if (e->shift_l == 0)
3465                         mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3466                 else if (e->shift_l == 2)
3467                         mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3468                 break;
3469         case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3470                 if (e->shift_l == 0)
3471                         mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3472                 else if (e->shift_l == 2)
3473                         mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3474                 break;
3475         default:
3476                 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3477                         __func__, e->reg);
3478                 return -EINVAL;
3479         }
3480
3481         /* ADC: 0, DMIC: 1 */
3482         mic_sel = val ? 0x0 : 0x1;
3483         if (mic_sel_reg)
3484                 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3485                                               mic_sel << 7);
3486
3487         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3488 }
3489
3490 static const struct snd_kcontrol_new rx_int0_2_mux =
3491         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3492
3493 static const struct snd_kcontrol_new rx_int1_2_mux =
3494         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3495
3496 static const struct snd_kcontrol_new rx_int2_2_mux =
3497         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3498
3499 static const struct snd_kcontrol_new rx_int3_2_mux =
3500         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3501
3502 static const struct snd_kcontrol_new rx_int4_2_mux =
3503         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3504
3505 static const struct snd_kcontrol_new rx_int7_2_mux =
3506         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3507
3508 static const struct snd_kcontrol_new rx_int8_2_mux =
3509         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3510
3511 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3512         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3513
3514 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3515         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3516
3517 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3518         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3519
3520 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3521         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3522
3523 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3524         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3525
3526 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3527         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3528
3529 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3530         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3531
3532 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3533         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3534
3535 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3536         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3537
3538 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3539         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3540
3541 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3542         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3543
3544 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3545         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3546
3547 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3548         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3549
3550 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3551         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3552
3553 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3554         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3555
3556 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3557         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3558
3559 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3560         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3561
3562 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3563         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3564
3565 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3566         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3567
3568 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3569         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3570
3571 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3572         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3573
3574 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3575         SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3576
3577 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3578         SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3579
3580 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3581         SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3582
3583 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3584         SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3585
3586 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3587         SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3588
3589 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3590         SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3591
3592 static const struct snd_kcontrol_new iir0_inp0_mux =
3593         SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3594 static const struct snd_kcontrol_new iir0_inp1_mux =
3595         SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3596 static const struct snd_kcontrol_new iir0_inp2_mux =
3597         SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3598 static const struct snd_kcontrol_new iir0_inp3_mux =
3599         SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3600
3601 static const struct snd_kcontrol_new iir1_inp0_mux =
3602         SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3603 static const struct snd_kcontrol_new iir1_inp1_mux =
3604         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3605 static const struct snd_kcontrol_new iir1_inp2_mux =
3606         SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3607 static const struct snd_kcontrol_new iir1_inp3_mux =
3608         SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3609
3610 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3611         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3612                           slim_rx_mux_get, slim_rx_mux_put),
3613         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3614                           slim_rx_mux_get, slim_rx_mux_put),
3615         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3616                           slim_rx_mux_get, slim_rx_mux_put),
3617         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3618                           slim_rx_mux_get, slim_rx_mux_put),
3619         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3620                           slim_rx_mux_get, slim_rx_mux_put),
3621         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3622                           slim_rx_mux_get, slim_rx_mux_put),
3623         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3624                           slim_rx_mux_get, slim_rx_mux_put),
3625         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3626                           slim_rx_mux_get, slim_rx_mux_put),
3627 };
3628
3629 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3630         SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3631 };
3632
3633 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3634         SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3635 };
3636
3637 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3638         SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3639 };
3640
3641 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3642         SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3643 };
3644
3645 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3646         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3647                           snd_soc_dapm_get_enum_double,
3648                           wcd934x_int_dem_inp_mux_put);
3649
3650 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3651         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3652                           snd_soc_dapm_get_enum_double,
3653                           wcd934x_int_dem_inp_mux_put);
3654
3655 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3656         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3657                           snd_soc_dapm_get_enum_double,
3658                           wcd934x_int_dem_inp_mux_put);
3659
3660 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3661         SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3662
3663 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3664         SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3665
3666 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3667         SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3668
3669 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3670         SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3671
3672 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3673         SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3674
3675 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3676         SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3677
3678 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3679         SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3680
3681 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3682         SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3683
3684 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3685         SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3686
3687 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3688         SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3689
3690 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3691         SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3692
3693 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3694         SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3695
3696 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3697         SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3698
3699 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3700         SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3701
3702 static const struct snd_kcontrol_new tx_dmic_mux0 =
3703         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3704
3705 static const struct snd_kcontrol_new tx_dmic_mux1 =
3706         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3707
3708 static const struct snd_kcontrol_new tx_dmic_mux2 =
3709         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3710
3711 static const struct snd_kcontrol_new tx_dmic_mux3 =
3712         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3713
3714 static const struct snd_kcontrol_new tx_dmic_mux4 =
3715         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3716
3717 static const struct snd_kcontrol_new tx_dmic_mux5 =
3718         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3719
3720 static const struct snd_kcontrol_new tx_dmic_mux6 =
3721         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3722
3723 static const struct snd_kcontrol_new tx_dmic_mux7 =
3724         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3725
3726 static const struct snd_kcontrol_new tx_dmic_mux8 =
3727         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3728
3729 static const struct snd_kcontrol_new tx_amic_mux0 =
3730         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3731
3732 static const struct snd_kcontrol_new tx_amic_mux1 =
3733         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3734
3735 static const struct snd_kcontrol_new tx_amic_mux2 =
3736         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3737
3738 static const struct snd_kcontrol_new tx_amic_mux3 =
3739         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3740
3741 static const struct snd_kcontrol_new tx_amic_mux4 =
3742         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3743
3744 static const struct snd_kcontrol_new tx_amic_mux5 =
3745         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3746
3747 static const struct snd_kcontrol_new tx_amic_mux6 =
3748         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3749
3750 static const struct snd_kcontrol_new tx_amic_mux7 =
3751         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3752
3753 static const struct snd_kcontrol_new tx_amic_mux8 =
3754         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3755
3756 static const struct snd_kcontrol_new tx_amic4_5 =
3757         SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3758
3759 static const struct snd_kcontrol_new tx_adc_mux0_mux =
3760         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3761                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3762 static const struct snd_kcontrol_new tx_adc_mux1_mux =
3763         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3764                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3765 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3766         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3767                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3768 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3769         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3770                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3771 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3772         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3773                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3774 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3775         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3776                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3777 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3778         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3779                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3780 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3781         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3782                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3783 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3784         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3785                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3786
3787 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3788         SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3789 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3790         SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3791 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3792         SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3793 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3794         SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3795 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3796         SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3797 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3798         SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3799 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3800         SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3801 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3802         SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3803 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3804         SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3805 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3806         SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3807 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3808         SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3809 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3810         SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3811 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3812         SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3813 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3814         SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3815 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3816         SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3817
3818 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3819                              struct snd_ctl_elem_value *ucontrol)
3820 {
3821         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3822         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3823         struct soc_mixer_control *mixer =
3824                         (struct soc_mixer_control *)kc->private_value;
3825         int port_id = mixer->shift;
3826
3827         ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3828
3829         return 0;
3830 }
3831
3832 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3833                              struct snd_ctl_elem_value *ucontrol)
3834 {
3835         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3836         struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3837         struct snd_soc_dapm_update *update = NULL;
3838         struct soc_mixer_control *mixer =
3839                         (struct soc_mixer_control *)kc->private_value;
3840         int enable = ucontrol->value.integer.value[0];
3841         struct wcd934x_slim_ch *ch, *c;
3842         int dai_id = widget->shift;
3843         int port_id = mixer->shift;
3844
3845         /* only add to the list if value not set */
3846         if (enable == wcd->tx_port_value[port_id])
3847                 return 0;
3848
3849         if (enable) {
3850                 if (list_empty(&wcd->tx_chs[port_id].list)) {
3851                         list_add_tail(&wcd->tx_chs[port_id].list,
3852                                       &wcd->dai[dai_id].slim_ch_list);
3853                 } else {
3854                         dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3855                         return 0;
3856                 }
3857          } else {
3858                 bool found = false;
3859
3860                 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3861                         if (ch->port == port_id) {
3862                                 found = true;
3863                                 list_del_init(&wcd->tx_chs[port_id].list);
3864                                 break;
3865                         }
3866                 }
3867                 if (!found)
3868                         return 0;
3869          }
3870
3871         wcd->tx_port_value[port_id] = enable;
3872         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3873
3874         return 1;
3875 }
3876
3877 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3878         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3879                        slim_tx_mixer_get, slim_tx_mixer_put),
3880         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3881                        slim_tx_mixer_get, slim_tx_mixer_put),
3882         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3883                        slim_tx_mixer_get, slim_tx_mixer_put),
3884         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3885                        slim_tx_mixer_get, slim_tx_mixer_put),
3886         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3887                        slim_tx_mixer_get, slim_tx_mixer_put),
3888         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3889                        slim_tx_mixer_get, slim_tx_mixer_put),
3890         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3891                        slim_tx_mixer_get, slim_tx_mixer_put),
3892         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3893                        slim_tx_mixer_get, slim_tx_mixer_put),
3894         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3895                        slim_tx_mixer_get, slim_tx_mixer_put),
3896         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3897                        slim_tx_mixer_get, slim_tx_mixer_put),
3898         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3899                        slim_tx_mixer_get, slim_tx_mixer_put),
3900         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3901                        slim_tx_mixer_get, slim_tx_mixer_put),
3902         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3903                        slim_tx_mixer_get, slim_tx_mixer_put),
3904 };
3905
3906 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3907         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3908                        slim_tx_mixer_get, slim_tx_mixer_put),
3909         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3910                        slim_tx_mixer_get, slim_tx_mixer_put),
3911         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3912                        slim_tx_mixer_get, slim_tx_mixer_put),
3913         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3914                        slim_tx_mixer_get, slim_tx_mixer_put),
3915         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3916                        slim_tx_mixer_get, slim_tx_mixer_put),
3917         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3918                        slim_tx_mixer_get, slim_tx_mixer_put),
3919         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3920                        slim_tx_mixer_get, slim_tx_mixer_put),
3921         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3922                        slim_tx_mixer_get, slim_tx_mixer_put),
3923         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3924                        slim_tx_mixer_get, slim_tx_mixer_put),
3925         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3926                        slim_tx_mixer_get, slim_tx_mixer_put),
3927         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3928                        slim_tx_mixer_get, slim_tx_mixer_put),
3929         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3930                        slim_tx_mixer_get, slim_tx_mixer_put),
3931         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3932                        slim_tx_mixer_get, slim_tx_mixer_put),
3933 };
3934
3935 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3936         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3937                        slim_tx_mixer_get, slim_tx_mixer_put),
3938         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3939                        slim_tx_mixer_get, slim_tx_mixer_put),
3940         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3941                        slim_tx_mixer_get, slim_tx_mixer_put),
3942         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3943                        slim_tx_mixer_get, slim_tx_mixer_put),
3944         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3945                        slim_tx_mixer_get, slim_tx_mixer_put),
3946         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3947                        slim_tx_mixer_get, slim_tx_mixer_put),
3948         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3949                        slim_tx_mixer_get, slim_tx_mixer_put),
3950         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3951                        slim_tx_mixer_get, slim_tx_mixer_put),
3952         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3953                        slim_tx_mixer_get, slim_tx_mixer_put),
3954         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3955                        slim_tx_mixer_get, slim_tx_mixer_put),
3956         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3957                        slim_tx_mixer_get, slim_tx_mixer_put),
3958         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3959                        slim_tx_mixer_get, slim_tx_mixer_put),
3960         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3961                        slim_tx_mixer_get, slim_tx_mixer_put),
3962 };
3963
3964 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3965         /* Gain Controls */
3966         SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3967         SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3968         SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3969         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3970                        3, 16, 1, line_gain),
3971         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3972                        3, 16, 1, line_gain),
3973
3974         SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3975         SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3976         SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3977         SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3978
3979         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3980                           -84, 40, digital_gain), /* -84dB min - 40dB max */
3981         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3982                           -84, 40, digital_gain),
3983         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3984                           -84, 40, digital_gain),
3985         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3986                           -84, 40, digital_gain),
3987         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3988                           -84, 40, digital_gain),
3989         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3990                           -84, 40, digital_gain),
3991         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3992                           -84, 40, digital_gain),
3993         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3994                           WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3995                           -84, 40, digital_gain),
3996         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3997                           WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3998                           -84, 40, digital_gain),
3999         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
4000                           WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
4001                           -84, 40, digital_gain),
4002         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
4003                           WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
4004                           -84, 40, digital_gain),
4005         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
4006                           WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
4007                           -84, 40, digital_gain),
4008         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
4009                           WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
4010                           -84, 40, digital_gain),
4011         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4012                           WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4013                           -84, 40, digital_gain),
4014
4015         SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4016                           -84, 40, digital_gain),
4017         SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4018                           -84, 40, digital_gain),
4019         SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4020                           -84, 40, digital_gain),
4021         SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4022                           -84, 40, digital_gain),
4023         SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4024                           -84, 40, digital_gain),
4025         SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4026                           -84, 40, digital_gain),
4027         SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4028                           -84, 40, digital_gain),
4029         SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4030                           -84, 40, digital_gain),
4031         SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4032                           -84, 40, digital_gain),
4033
4034         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4035                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4036                           digital_gain),
4037         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4038                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4039                           digital_gain),
4040         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4041                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4042                           digital_gain),
4043         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4044                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4045                           digital_gain),
4046         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4047                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4048                           digital_gain),
4049         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4050                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4051                           digital_gain),
4052         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4053                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4054                           digital_gain),
4055         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4056                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4057                           digital_gain),
4058
4059         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4060         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4061         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4062         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4063         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4064         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4065         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4066         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4067         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4068
4069         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4070         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4071         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4072         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4073         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4074         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4075         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4076         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4077         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4078         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4079         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4080         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4081         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4082         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4083
4084         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4085                      wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4086
4087         SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4088                    0, 1, 0),
4089         SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4090                    1, 1, 0),
4091         SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4092                    2, 1, 0),
4093         SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4094                    3, 1, 0),
4095         SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4096                    4, 1, 0),
4097         SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4098                    0, 1, 0),
4099         SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4100                    1, 1, 0),
4101         SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4102                    2, 1, 0),
4103         SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4104                    3, 1, 0),
4105         SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4106                    4, 1, 0),
4107         WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4108         WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4109         WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4110         WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4111         WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4112
4113         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4114         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4115         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4116         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4117         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4118
4119         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4120                        wcd934x_compander_get, wcd934x_compander_set),
4121         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4122                        wcd934x_compander_get, wcd934x_compander_set),
4123         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4124                        wcd934x_compander_get, wcd934x_compander_set),
4125         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4126                        wcd934x_compander_get, wcd934x_compander_set),
4127         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4128                        wcd934x_compander_get, wcd934x_compander_set),
4129         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4130                        wcd934x_compander_get, wcd934x_compander_set),
4131 };
4132
4133 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4134                                           struct snd_soc_component *component)
4135 {
4136         int port_num = 0;
4137         unsigned short reg = 0;
4138         unsigned int val = 0;
4139         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4140         struct wcd934x_slim_ch *ch;
4141
4142         list_for_each_entry(ch, &dai->slim_ch_list, list) {
4143                 if (ch->port >= WCD934X_RX_START) {
4144                         port_num = ch->port - WCD934X_RX_START;
4145                         reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4146                 } else {
4147                         port_num = ch->port;
4148                         reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4149                 }
4150
4151                 regmap_read(wcd->if_regmap, reg, &val);
4152                 if (!(val & BIT(port_num % 8)))
4153                         regmap_write(wcd->if_regmap, reg,
4154                                      val | BIT(port_num % 8));
4155         }
4156 }
4157
4158 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4159                                      struct snd_kcontrol *kc, int event)
4160 {
4161         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4162         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4163         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4164
4165         switch (event) {
4166         case SND_SOC_DAPM_POST_PMU:
4167                 wcd934x_codec_enable_int_port(dai, comp);
4168                 break;
4169         }
4170
4171         return 0;
4172 }
4173
4174 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4175                                       u16 interp_idx, int event)
4176 {
4177         u16 hd2_scale_reg;
4178         u16 hd2_enable_reg = 0;
4179
4180         switch (interp_idx) {
4181         case INTERP_HPHL:
4182                 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4183                 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4184                 break;
4185         case INTERP_HPHR:
4186                 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4187                 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4188                 break;
4189         default:
4190                 return;
4191         }
4192
4193         if (SND_SOC_DAPM_EVENT_ON(event)) {
4194                 snd_soc_component_update_bits(component, hd2_scale_reg,
4195                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4196                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4197                 snd_soc_component_update_bits(component, hd2_enable_reg,
4198                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4199                                       WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4200         }
4201
4202         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4203                 snd_soc_component_update_bits(component, hd2_enable_reg,
4204                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4205                                       WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4206                 snd_soc_component_update_bits(component, hd2_scale_reg,
4207                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4208                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4209         }
4210 }
4211
4212 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4213                                              u16 interp_idx, int event)
4214 {
4215         u8 hph_dly_mask;
4216         u16 hph_lut_bypass_reg = 0;
4217
4218         switch (interp_idx) {
4219         case INTERP_HPHL:
4220                 hph_dly_mask = 1;
4221                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4222                 break;
4223         case INTERP_HPHR:
4224                 hph_dly_mask = 2;
4225                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4226                 break;
4227         default:
4228                 return;
4229         }
4230
4231         if (SND_SOC_DAPM_EVENT_ON(event)) {
4232                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4233                                               hph_dly_mask, 0x0);
4234                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4235                                               WCD934X_HPH_LUT_BYPASS_MASK,
4236                                               WCD934X_HPH_LUT_BYPASS_ENABLE);
4237         }
4238
4239         if (SND_SOC_DAPM_EVENT_OFF(event)) {
4240                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4241                                               hph_dly_mask, hph_dly_mask);
4242                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4243                                               WCD934X_HPH_LUT_BYPASS_MASK,
4244                                               WCD934X_HPH_LUT_BYPASS_DISABLE);
4245         }
4246 }
4247
4248 static int wcd934x_config_compander(struct snd_soc_component *comp,
4249                                     int interp_n, int event)
4250 {
4251         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4252         int compander;
4253         u16 comp_ctl0_reg, rx_path_cfg0_reg;
4254
4255         /* EAR does not have compander */
4256         if (!interp_n)
4257                 return 0;
4258
4259         compander = interp_n - 1;
4260         if (!wcd->comp_enabled[compander])
4261                 return 0;
4262
4263         comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4264         rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4265
4266         switch (event) {
4267         case SND_SOC_DAPM_PRE_PMU:
4268                 /* Enable Compander Clock */
4269                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4270                                               WCD934X_COMP_CLK_EN_MASK,
4271                                               WCD934X_COMP_CLK_ENABLE);
4272                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4273                                               WCD934X_COMP_SOFT_RST_MASK,
4274                                               WCD934X_COMP_SOFT_RST_ENABLE);
4275                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4276                                               WCD934X_COMP_SOFT_RST_MASK,
4277                                               WCD934X_COMP_SOFT_RST_DISABLE);
4278                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4279                                               WCD934X_HPH_CMP_EN_MASK,
4280                                               WCD934X_HPH_CMP_ENABLE);
4281                 break;
4282         case SND_SOC_DAPM_POST_PMD:
4283                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4284                                               WCD934X_HPH_CMP_EN_MASK,
4285                                               WCD934X_HPH_CMP_DISABLE);
4286                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4287                                               WCD934X_COMP_HALT_MASK,
4288                                               WCD934X_COMP_HALT);
4289                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4290                                               WCD934X_COMP_SOFT_RST_MASK,
4291                                               WCD934X_COMP_SOFT_RST_ENABLE);
4292                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4293                                               WCD934X_COMP_SOFT_RST_MASK,
4294                                               WCD934X_COMP_SOFT_RST_DISABLE);
4295                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4296                                               WCD934X_COMP_CLK_EN_MASK, 0x0);
4297                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4298                                               WCD934X_COMP_SOFT_RST_MASK, 0x0);
4299                 break;
4300         }
4301
4302         return 0;
4303 }
4304
4305 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4306                                          struct snd_kcontrol *kc, int event)
4307 {
4308         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4309         int interp_idx = w->shift;
4310         u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4311
4312         switch (event) {
4313         case SND_SOC_DAPM_PRE_PMU:
4314                 /* Clk enable */
4315                 snd_soc_component_update_bits(comp, main_reg,
4316                                              WCD934X_RX_CLK_EN_MASK,
4317                                              WCD934X_RX_CLK_ENABLE);
4318                 wcd934x_codec_hd2_control(comp, interp_idx, event);
4319                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4320                 wcd934x_config_compander(comp, interp_idx, event);
4321                 break;
4322         case SND_SOC_DAPM_POST_PMD:
4323                 wcd934x_config_compander(comp, interp_idx, event);
4324                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4325                 wcd934x_codec_hd2_control(comp, interp_idx, event);
4326                 /* Clk Disable */
4327                 snd_soc_component_update_bits(comp, main_reg,
4328                                              WCD934X_RX_CLK_EN_MASK, 0);
4329                 /* Reset enable and disable */
4330                 snd_soc_component_update_bits(comp, main_reg,
4331                                               WCD934X_RX_RESET_MASK,
4332                                               WCD934X_RX_RESET_ENABLE);
4333                 snd_soc_component_update_bits(comp, main_reg,
4334                                               WCD934X_RX_RESET_MASK,
4335                                               WCD934X_RX_RESET_DISABLE);
4336                 /* Reset rate to 48K*/
4337                 snd_soc_component_update_bits(comp, main_reg,
4338                                               WCD934X_RX_PCM_RATE_MASK,
4339                                               WCD934X_RX_PCM_RATE_F_48K);
4340                 break;
4341         }
4342
4343         return 0;
4344 }
4345
4346 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4347                                          struct snd_kcontrol *kc, int event)
4348 {
4349         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4350         int offset_val = 0;
4351         u16 gain_reg, mix_reg;
4352         int val = 0;
4353
4354         gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4355                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4356         mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4357                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4358
4359         switch (event) {
4360         case SND_SOC_DAPM_PRE_PMU:
4361                 /* Clk enable */
4362                 snd_soc_component_update_bits(comp, mix_reg,
4363                                               WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4364                                               WCD934X_CDC_RX_MIX_CLK_ENABLE);
4365                 break;
4366
4367         case SND_SOC_DAPM_POST_PMU:
4368                 val = snd_soc_component_read(comp, gain_reg);
4369                 val += offset_val;
4370                 snd_soc_component_write(comp, gain_reg, val);
4371                 break;
4372         }
4373
4374         return 0;
4375 }
4376
4377 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4378                                       struct snd_kcontrol *kcontrol, int event)
4379 {
4380         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4381         int reg = w->reg;
4382
4383         switch (event) {
4384         case SND_SOC_DAPM_POST_PMU:
4385                 /* B1 GAIN */
4386                 snd_soc_component_write(comp, reg,
4387                                         snd_soc_component_read(comp, reg));
4388                 /* B2 GAIN */
4389                 reg++;
4390                 snd_soc_component_write(comp, reg,
4391                                         snd_soc_component_read(comp, reg));
4392                 /* B3 GAIN */
4393                 reg++;
4394                 snd_soc_component_write(comp, reg,
4395                                         snd_soc_component_read(comp, reg));
4396                 /* B4 GAIN */
4397                 reg++;
4398                 snd_soc_component_write(comp, reg,
4399                                         snd_soc_component_read(comp, reg));
4400                 /* B5 GAIN */
4401                 reg++;
4402                 snd_soc_component_write(comp, reg,
4403                                         snd_soc_component_read(comp, reg));
4404                 break;
4405         default:
4406                 break;
4407         }
4408         return 0;
4409 }
4410
4411 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4412                                           struct snd_kcontrol *kcontrol,
4413                                           int event)
4414 {
4415         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4416         u16 gain_reg;
4417
4418         gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4419                                                  WCD934X_RX_PATH_CTL_OFFSET);
4420
4421         switch (event) {
4422         case SND_SOC_DAPM_POST_PMU:
4423                 snd_soc_component_write(comp, gain_reg,
4424                                 snd_soc_component_read(comp, gain_reg));
4425                 break;
4426         }
4427
4428         return 0;
4429 }
4430
4431 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4432                                        struct snd_kcontrol *kc, int event)
4433 {
4434         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4435         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4436
4437         switch (event) {
4438         case SND_SOC_DAPM_PRE_PMU:
4439                 /* Disable AutoChop timer during power up */
4440                 snd_soc_component_update_bits(comp,
4441                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4442                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4443                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4444                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4445
4446                 break;
4447         case SND_SOC_DAPM_POST_PMD:
4448                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4449                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4450                 break;
4451         }
4452
4453         return 0;
4454 }
4455
4456 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4457                                         struct snd_kcontrol *kcontrol,
4458                                         int event)
4459 {
4460         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4461         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4462         int hph_mode = wcd->hph_mode;
4463         u8 dem_inp;
4464
4465         switch (event) {
4466         case SND_SOC_DAPM_PRE_PMU:
4467                 /* Read DEM INP Select */
4468                 dem_inp = snd_soc_component_read(comp,
4469                                    WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4470
4471                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4472                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4473                         return -EINVAL;
4474                 }
4475                 if (hph_mode != CLS_H_LP)
4476                         /* Ripple freq control enable */
4477                         snd_soc_component_update_bits(comp,
4478                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4479                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4480                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4481                 /* Disable AutoChop timer during power up */
4482                 snd_soc_component_update_bits(comp,
4483                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4484                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4485                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4486                                         WCD_CLSH_STATE_HPHL, hph_mode);
4487
4488                 break;
4489         case SND_SOC_DAPM_POST_PMD:
4490                 /* 1000us required as per HW requirement */
4491                 usleep_range(1000, 1100);
4492                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4493                                         WCD_CLSH_STATE_HPHL, hph_mode);
4494                 if (hph_mode != CLS_H_LP)
4495                         /* Ripple freq control disable */
4496                         snd_soc_component_update_bits(comp,
4497                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4498                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4499
4500                 break;
4501         default:
4502                 break;
4503         }
4504
4505         return 0;
4506 }
4507
4508 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4509                                         struct snd_kcontrol *kcontrol,
4510                                         int event)
4511 {
4512         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4513         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4514         int hph_mode = wcd->hph_mode;
4515         u8 dem_inp;
4516
4517         switch (event) {
4518         case SND_SOC_DAPM_PRE_PMU:
4519                 dem_inp = snd_soc_component_read(comp,
4520                                         WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4521                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4522                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4523                         return -EINVAL;
4524                 }
4525                 if (hph_mode != CLS_H_LP)
4526                         /* Ripple freq control enable */
4527                         snd_soc_component_update_bits(comp,
4528                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4529                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4530                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4531                 /* Disable AutoChop timer during power up */
4532                 snd_soc_component_update_bits(comp,
4533                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4534                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4535                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4536                                         WCD_CLSH_STATE_HPHR,
4537                              hph_mode);
4538                 break;
4539         case SND_SOC_DAPM_POST_PMD:
4540                 /* 1000us required as per HW requirement */
4541                 usleep_range(1000, 1100);
4542
4543                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4544                                         WCD_CLSH_STATE_HPHR, hph_mode);
4545                 if (hph_mode != CLS_H_LP)
4546                         /* Ripple freq control disable */
4547                         snd_soc_component_update_bits(comp,
4548                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4549                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4550                 break;
4551         default:
4552                 break;
4553         }
4554
4555         return 0;
4556 }
4557
4558 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4559                                            struct snd_kcontrol *kc, int event)
4560 {
4561         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4562         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4563
4564         switch (event) {
4565         case SND_SOC_DAPM_PRE_PMU:
4566                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4567                                         WCD_CLSH_STATE_LO, CLS_AB);
4568                 break;
4569         case SND_SOC_DAPM_POST_PMD:
4570                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4571                                         WCD_CLSH_STATE_LO, CLS_AB);
4572                 break;
4573         }
4574
4575         return 0;
4576 }
4577
4578 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4579                                         struct snd_kcontrol *kcontrol,
4580                                         int event)
4581 {
4582         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4583         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4584
4585         switch (event) {
4586         case SND_SOC_DAPM_POST_PMU:
4587                 /*
4588                  * 7ms sleep is required after PA is enabled as per
4589                  * HW requirement. If compander is disabled, then
4590                  * 20ms delay is needed.
4591                  */
4592                 usleep_range(20000, 20100);
4593
4594                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4595                                               WCD934X_HPH_OCP_DET_MASK,
4596                                               WCD934X_HPH_OCP_DET_ENABLE);
4597                 /* Remove Mute on primary path */
4598                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4599                                       WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4600                                       0);
4601                 /* Enable GM3 boost */
4602                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4603                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
4604                                               WCD934X_HPH_GM3_BOOST_ENABLE);
4605                 /* Enable AutoChop timer at the end of power up */
4606                 snd_soc_component_update_bits(comp,
4607                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4608                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4609                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4610                 /* Remove mix path mute */
4611                 snd_soc_component_update_bits(comp,
4612                                 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4613                                 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4614                 break;
4615         case SND_SOC_DAPM_PRE_PMD:
4616                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4617                 /* Enable DSD Mute before PA disable */
4618                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4619                                               WCD934X_HPH_OCP_DET_MASK,
4620                                               WCD934X_HPH_OCP_DET_DISABLE);
4621                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4622                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4623                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4624                 snd_soc_component_update_bits(comp,
4625                                               WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4626                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4627                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4628                 break;
4629         case SND_SOC_DAPM_POST_PMD:
4630                 /*
4631                  * 5ms sleep is required after PA disable. If compander is
4632                  * disabled, then 20ms delay is needed after PA disable.
4633                  */
4634                 usleep_range(20000, 20100);
4635                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4636                 break;
4637         }
4638
4639         return 0;
4640 }
4641
4642 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4643                                         struct snd_kcontrol *kcontrol,
4644                                         int event)
4645 {
4646         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4647         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4648
4649         switch (event) {
4650         case SND_SOC_DAPM_POST_PMU:
4651                 /*
4652                  * 7ms sleep is required after PA is enabled as per
4653                  * HW requirement. If compander is disabled, then
4654                  * 20ms delay is needed.
4655                  */
4656                 usleep_range(20000, 20100);
4657                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4658                                               WCD934X_HPH_OCP_DET_MASK,
4659                                               WCD934X_HPH_OCP_DET_ENABLE);
4660                 /* Remove mute */
4661                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4662                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4663                                               0);
4664                 /* Enable GM3 boost */
4665                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4666                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
4667                                               WCD934X_HPH_GM3_BOOST_ENABLE);
4668                 /* Enable AutoChop timer at the end of power up */
4669                 snd_soc_component_update_bits(comp,
4670                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4671                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4672                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4673                 /* Remove mix path mute if it is enabled */
4674                 if ((snd_soc_component_read(comp,
4675                                       WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4676                         snd_soc_component_update_bits(comp,
4677                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4678                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4679                                               WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4680                 break;
4681         case SND_SOC_DAPM_PRE_PMD:
4682                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4683                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4684                                               WCD934X_HPH_OCP_DET_MASK,
4685                                               WCD934X_HPH_OCP_DET_DISABLE);
4686                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4687                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4688                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4689                 snd_soc_component_update_bits(comp,
4690                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4691                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4692                                               WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4693                 break;
4694         case SND_SOC_DAPM_POST_PMD:
4695                 /*
4696                  * 5ms sleep is required after PA disable. If compander is
4697                  * disabled, then 20ms delay is needed after PA disable.
4698                  */
4699                 usleep_range(20000, 20100);
4700                 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4701                 break;
4702         }
4703
4704         return 0;
4705 }
4706
4707 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4708                                         unsigned int dmic,
4709                                       struct wcd934x_codec *wcd)
4710 {
4711         u8 tx_stream_fs;
4712         u8 adc_mux_index = 0, adc_mux_sel = 0;
4713         bool dec_found = false;
4714         u16 adc_mux_ctl_reg, tx_fs_reg;
4715         u32 dmic_fs;
4716
4717         while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4718                 if (adc_mux_index < 4) {
4719                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4720                                                 (adc_mux_index * 2);
4721                 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4722                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4723                                                 adc_mux_index - 4;
4724                 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4725                         ++adc_mux_index;
4726                         continue;
4727                 }
4728                 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4729                                & 0xF8) >> 3) - 1;
4730
4731                 if (adc_mux_sel == dmic) {
4732                         dec_found = true;
4733                         break;
4734                 }
4735
4736                 ++adc_mux_index;
4737         }
4738
4739         if (dec_found && adc_mux_index <= 8) {
4740                 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4741                 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4742                 if (tx_stream_fs <= 4)  {
4743                         if (wcd->dmic_sample_rate <=
4744                                         WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
4745                                 dmic_fs = wcd->dmic_sample_rate;
4746                         else
4747                                 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
4748                 } else
4749                         dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4750         } else {
4751                 dmic_fs = wcd->dmic_sample_rate;
4752         }
4753
4754         return dmic_fs;
4755 }
4756
4757 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4758                                    u32 mclk_rate, u32 dmic_clk_rate)
4759 {
4760         u32 div_factor;
4761         u8 dmic_ctl_val;
4762
4763         /* Default value to return in case of error */
4764         if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4765                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4766         else
4767                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4768
4769         if (dmic_clk_rate == 0) {
4770                 dev_err(comp->dev,
4771                         "%s: dmic_sample_rate cannot be 0\n",
4772                         __func__);
4773                 goto done;
4774         }
4775
4776         div_factor = mclk_rate / dmic_clk_rate;
4777         switch (div_factor) {
4778         case 2:
4779                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4780                 break;
4781         case 3:
4782                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4783                 break;
4784         case 4:
4785                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4786                 break;
4787         case 6:
4788                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4789                 break;
4790         case 8:
4791                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4792                 break;
4793         case 16:
4794                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4795                 break;
4796         default:
4797                 dev_err(comp->dev,
4798                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4799                         __func__, div_factor, mclk_rate, dmic_clk_rate);
4800                 break;
4801         }
4802
4803 done:
4804         return dmic_ctl_val;
4805 }
4806
4807 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4808                                      struct snd_kcontrol *kcontrol, int event)
4809 {
4810         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4811         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4812         u8  dmic_clk_en = 0x01;
4813         u16 dmic_clk_reg;
4814         s32 *dmic_clk_cnt;
4815         u8 dmic_rate_val, dmic_rate_shift = 1;
4816         unsigned int dmic;
4817         u32 dmic_sample_rate;
4818         int ret;
4819         char *wname;
4820
4821         wname = strpbrk(w->name, "012345");
4822         if (!wname) {
4823                 dev_err(comp->dev, "%s: widget not found\n", __func__);
4824                 return -EINVAL;
4825         }
4826
4827         ret = kstrtouint(wname, 10, &dmic);
4828         if (ret < 0) {
4829                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4830                         __func__);
4831                 return -EINVAL;
4832         }
4833
4834         switch (dmic) {
4835         case 0:
4836         case 1:
4837                 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4838                 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4839                 break;
4840         case 2:
4841         case 3:
4842                 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4843                 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4844                 break;
4845         case 4:
4846         case 5:
4847                 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4848                 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4849                 break;
4850         default:
4851                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4852                         __func__);
4853                 return -EINVAL;
4854         }
4855
4856         switch (event) {
4857         case SND_SOC_DAPM_PRE_PMU:
4858                 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4859                                                                 wcd);
4860                 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4861                                                          dmic_sample_rate);
4862                 (*dmic_clk_cnt)++;
4863                 if (*dmic_clk_cnt == 1) {
4864                         dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4865                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4866                                                       WCD934X_DMIC_RATE_MASK,
4867                                                       dmic_rate_val);
4868                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4869                                                       dmic_clk_en, dmic_clk_en);
4870                 }
4871
4872                 break;
4873         case SND_SOC_DAPM_POST_PMD:
4874                 (*dmic_clk_cnt)--;
4875                 if (*dmic_clk_cnt == 0)
4876                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4877                                                       dmic_clk_en, 0);
4878                 break;
4879         }
4880
4881         return 0;
4882 }
4883
4884 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4885                                          int adc_mux_n)
4886 {
4887         u16 mask, shift, adc_mux_in_reg;
4888         u16 amic_mux_sel_reg;
4889         bool is_amic;
4890
4891         if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4892             adc_mux_n == WCD934X_INVALID_ADC_MUX)
4893                 return 0;
4894
4895         if (adc_mux_n < 3) {
4896                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4897                                  adc_mux_n;
4898                 mask = 0x03;
4899                 shift = 0;
4900                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4901                                    2 * adc_mux_n;
4902         } else if (adc_mux_n < 4) {
4903                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4904                 mask = 0x03;
4905                 shift = 0;
4906                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4907                                    2 * adc_mux_n;
4908         } else if (adc_mux_n < 7) {
4909                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4910                                  (adc_mux_n - 4);
4911                 mask = 0x0C;
4912                 shift = 2;
4913                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4914                                    adc_mux_n - 4;
4915         } else if (adc_mux_n < 8) {
4916                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4917                 mask = 0x0C;
4918                 shift = 2;
4919                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4920                                    adc_mux_n - 4;
4921         } else if (adc_mux_n < 12) {
4922                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4923                                  ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4924                                   (adc_mux_n - 9));
4925                 mask = 0x30;
4926                 shift = 4;
4927                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4928                                    adc_mux_n - 4;
4929         } else if (adc_mux_n < 13) {
4930                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4931                 mask = 0x30;
4932                 shift = 4;
4933                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4934                                    adc_mux_n - 4;
4935         } else {
4936                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4937                 mask = 0xC0;
4938                 shift = 6;
4939                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4940                                    adc_mux_n - 4;
4941         }
4942
4943         is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4944                      & mask) >> shift) == 1);
4945         if (!is_amic)
4946                 return 0;
4947
4948         return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4949 }
4950
4951 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4952                                             int amic)
4953 {
4954         u16 pwr_level_reg = 0;
4955
4956         switch (amic) {
4957         case 1:
4958         case 2:
4959                 pwr_level_reg = WCD934X_ANA_AMIC1;
4960                 break;
4961
4962         case 3:
4963         case 4:
4964                 pwr_level_reg = WCD934X_ANA_AMIC3;
4965                 break;
4966         default:
4967                 break;
4968         }
4969
4970         return pwr_level_reg;
4971 }
4972
4973 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4974                                     struct snd_kcontrol *kcontrol, int event)
4975 {
4976         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4977         unsigned int decimator;
4978         char *dec_adc_mux_name = NULL;
4979         char *widget_name = NULL;
4980         char *wname;
4981         int ret = 0, amic_n;
4982         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4983         u16 tx_gain_ctl_reg;
4984         char *dec;
4985         u8 hpf_coff_freq;
4986
4987         widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4988         if (!widget_name)
4989                 return -ENOMEM;
4990
4991         wname = widget_name;
4992         dec_adc_mux_name = strsep(&widget_name, " ");
4993         if (!dec_adc_mux_name) {
4994                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4995                         __func__, w->name);
4996                 ret =  -EINVAL;
4997                 goto out;
4998         }
4999         dec_adc_mux_name = widget_name;
5000
5001         dec = strpbrk(dec_adc_mux_name, "012345678");
5002         if (!dec) {
5003                 dev_err(comp->dev, "%s: decimator index not found\n",
5004                         __func__);
5005                 ret =  -EINVAL;
5006                 goto out;
5007         }
5008
5009         ret = kstrtouint(dec, 10, &decimator);
5010         if (ret < 0) {
5011                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5012                         __func__, wname);
5013                 ret =  -EINVAL;
5014                 goto out;
5015         }
5016
5017         tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5018         hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5019         dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5020         tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5021
5022         switch (event) {
5023         case SND_SOC_DAPM_PRE_PMU:
5024                 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5025                 if (amic_n)
5026                         pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5027                                                                  amic_n);
5028
5029                 if (!pwr_level_reg)
5030                         break;
5031
5032                 switch ((snd_soc_component_read(comp, pwr_level_reg) &
5033                                       WCD934X_AMIC_PWR_LVL_MASK) >>
5034                                       WCD934X_AMIC_PWR_LVL_SHIFT) {
5035                 case WCD934X_AMIC_PWR_LEVEL_LP:
5036                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5037                                         WCD934X_DEC_PWR_LVL_MASK,
5038                                         WCD934X_DEC_PWR_LVL_LP);
5039                         break;
5040                 case WCD934X_AMIC_PWR_LEVEL_HP:
5041                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5042                                         WCD934X_DEC_PWR_LVL_MASK,
5043                                         WCD934X_DEC_PWR_LVL_HP);
5044                         break;
5045                 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5046                 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5047                 default:
5048                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5049                                         WCD934X_DEC_PWR_LVL_MASK,
5050                                         WCD934X_DEC_PWR_LVL_DF);
5051                         break;
5052                 }
5053                 break;
5054         case SND_SOC_DAPM_POST_PMU:
5055                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5056                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5057                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5058                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5059                                                       TX_HPF_CUT_OFF_FREQ_MASK,
5060                                                       CF_MIN_3DB_150HZ << 5);
5061                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5062                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5063                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5064                         /*
5065                          * Minimum 1 clk cycle delay is required as per
5066                          * HW spec.
5067                          */
5068                         usleep_range(1000, 1010);
5069                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5070                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5071                                       0);
5072                 }
5073                 /* apply gain after decimator is enabled */
5074                 snd_soc_component_write(comp, tx_gain_ctl_reg,
5075                                         snd_soc_component_read(comp,
5076                                                          tx_gain_ctl_reg));
5077                 break;
5078         case SND_SOC_DAPM_PRE_PMD:
5079                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5080                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5081
5082                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5083                         snd_soc_component_update_bits(comp, dec_cfg_reg,
5084                                                       TX_HPF_CUT_OFF_FREQ_MASK,
5085                                                       hpf_coff_freq << 5);
5086                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5087                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5088                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5089                                 /*
5090                                  * Minimum 1 clk cycle delay is required as per
5091                                  * HW spec.
5092                                  */
5093                         usleep_range(1000, 1010);
5094                         snd_soc_component_update_bits(comp, hpf_gate_reg,
5095                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5096                                       0);
5097                 }
5098                 break;
5099         case SND_SOC_DAPM_POST_PMD:
5100                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5101                                               0x10, 0x00);
5102                 snd_soc_component_update_bits(comp, dec_cfg_reg,
5103                                               WCD934X_DEC_PWR_LVL_MASK,
5104                                               WCD934X_DEC_PWR_LVL_DF);
5105                 break;
5106         }
5107 out:
5108         kfree(wname);
5109         return ret;
5110 }
5111
5112 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5113                                       u16 amic_reg, bool set)
5114 {
5115         u8 mask = 0x20;
5116         u8 val;
5117
5118         if (amic_reg == WCD934X_ANA_AMIC1 ||
5119             amic_reg == WCD934X_ANA_AMIC3)
5120                 mask = 0x40;
5121
5122         val = set ? mask : 0x00;
5123
5124         switch (amic_reg) {
5125         case WCD934X_ANA_AMIC1:
5126         case WCD934X_ANA_AMIC2:
5127                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5128                                               mask, val);
5129                 break;
5130         case WCD934X_ANA_AMIC3:
5131         case WCD934X_ANA_AMIC4:
5132                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5133                                               mask, val);
5134                 break;
5135         default:
5136                 break;
5137         }
5138 }
5139
5140 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5141                                     struct snd_kcontrol *kcontrol, int event)
5142 {
5143         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5144
5145         switch (event) {
5146         case SND_SOC_DAPM_PRE_PMU:
5147                 wcd934x_codec_set_tx_hold(comp, w->reg, true);
5148                 break;
5149         default:
5150                 break;
5151         }
5152
5153         return 0;
5154 }
5155
5156 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5157                                         struct snd_kcontrol *kcontrol,
5158                                         int event)
5159 {
5160         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5161         int micb_num = w->shift;
5162
5163         switch (event) {
5164         case SND_SOC_DAPM_PRE_PMU:
5165                 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5166                 break;
5167         case SND_SOC_DAPM_POST_PMU:
5168                 /* 1 msec delay as per HW requirement */
5169                 usleep_range(1000, 1100);
5170                 break;
5171         case SND_SOC_DAPM_POST_PMD:
5172                 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5173                 break;
5174         }
5175
5176         return 0;
5177 }
5178
5179 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5180         /* Analog Outputs */
5181         SND_SOC_DAPM_OUTPUT("EAR"),
5182         SND_SOC_DAPM_OUTPUT("HPHL"),
5183         SND_SOC_DAPM_OUTPUT("HPHR"),
5184         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5185         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5186         SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5187         SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5188         SND_SOC_DAPM_OUTPUT("ANC EAR"),
5189         SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5190         SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5191         SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5192         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5193         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5194         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5195                               AIF1_PB, 0, wcd934x_codec_enable_slim,
5196                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5197         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5198                               AIF2_PB, 0, wcd934x_codec_enable_slim,
5199                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5200         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5201                               AIF3_PB, 0, wcd934x_codec_enable_slim,
5202                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5203         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5204                               AIF4_PB, 0, wcd934x_codec_enable_slim,
5205                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5206
5207         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5208                          &slim_rx_mux[WCD934X_RX0]),
5209         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5210                          &slim_rx_mux[WCD934X_RX1]),
5211         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5212                          &slim_rx_mux[WCD934X_RX2]),
5213         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5214                          &slim_rx_mux[WCD934X_RX3]),
5215         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5216                          &slim_rx_mux[WCD934X_RX4]),
5217         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5218                          &slim_rx_mux[WCD934X_RX5]),
5219         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5220                          &slim_rx_mux[WCD934X_RX6]),
5221         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5222                          &slim_rx_mux[WCD934X_RX7]),
5223
5224         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5225         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5226         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5227         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5228         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5229         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5230         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5231         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5232
5233         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5234                            &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5235                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5236                            SND_SOC_DAPM_POST_PMD),
5237         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5238                            &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5239                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5240                            SND_SOC_DAPM_POST_PMD),
5241         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5242                            &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5243                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5244                            SND_SOC_DAPM_POST_PMD),
5245         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5246                            &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5247                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5248                            SND_SOC_DAPM_POST_PMD),
5249         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5250                            &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5251                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5252                            SND_SOC_DAPM_POST_PMD),
5253         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5254                            &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5255                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5256                            SND_SOC_DAPM_POST_PMD),
5257         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5258                            &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5259                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5260                            SND_SOC_DAPM_POST_PMD),
5261
5262         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5263                          &rx_int0_1_mix_inp0_mux),
5264         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5265                          &rx_int0_1_mix_inp1_mux),
5266         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5267                          &rx_int0_1_mix_inp2_mux),
5268         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5269                          &rx_int1_1_mix_inp0_mux),
5270         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5271                          &rx_int1_1_mix_inp1_mux),
5272         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5273                          &rx_int1_1_mix_inp2_mux),
5274         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5275                          &rx_int2_1_mix_inp0_mux),
5276         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5277                          &rx_int2_1_mix_inp1_mux),
5278         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5279                          &rx_int2_1_mix_inp2_mux),
5280         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5281                          &rx_int3_1_mix_inp0_mux),
5282         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5283                          &rx_int3_1_mix_inp1_mux),
5284         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5285                          &rx_int3_1_mix_inp2_mux),
5286         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5287                          &rx_int4_1_mix_inp0_mux),
5288         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5289                          &rx_int4_1_mix_inp1_mux),
5290         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5291                          &rx_int4_1_mix_inp2_mux),
5292         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5293                            &rx_int7_1_mix_inp0_mux),
5294         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5295                            &rx_int7_1_mix_inp1_mux),
5296         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5297                            &rx_int7_1_mix_inp2_mux),
5298         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5299                            &rx_int8_1_mix_inp0_mux),
5300         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5301                            &rx_int8_1_mix_inp1_mux),
5302         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5303                            &rx_int8_1_mix_inp2_mux),
5304         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5305         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5306         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5307         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5308                            rx_int1_asrc_switch,
5309                            ARRAY_SIZE(rx_int1_asrc_switch)),
5310         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5311         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5312                            rx_int2_asrc_switch,
5313                            ARRAY_SIZE(rx_int2_asrc_switch)),
5314         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5315         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5316                            rx_int3_asrc_switch,
5317                            ARRAY_SIZE(rx_int3_asrc_switch)),
5318         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5319         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5320                            rx_int4_asrc_switch,
5321                            ARRAY_SIZE(rx_int4_asrc_switch)),
5322         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5323         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5324         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5325         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5326         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5327         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5328         SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5329         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5330         SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5331         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5332         SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5333         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5334         SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5335
5336         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5337         SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5338                              NULL, 0, NULL, 0),
5339         SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5340                              NULL, 0, NULL, 0),
5341         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5342                            0,  &rx_int0_mix2_inp_mux, NULL,
5343                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5344         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5345                            0, &rx_int1_mix2_inp_mux,  NULL,
5346                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5347         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5348                            0, &rx_int2_mix2_inp_mux, NULL,
5349                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5350         SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5351                            0, &rx_int3_mix2_inp_mux, NULL,
5352                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5353         SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5354                            0, &rx_int4_mix2_inp_mux, NULL,
5355                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5356         SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5357                            0, &rx_int7_mix2_inp_mux, NULL,
5358                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5359
5360         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5361         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5362         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5363         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5364         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5365         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5366         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5367         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5368
5369         SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5370                            0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5371                            SND_SOC_DAPM_POST_PMU),
5372         SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5373                            1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5374                            SND_SOC_DAPM_POST_PMU),
5375         SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5376                            4, 0, NULL, 0),
5377         SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5378                            4, 0, NULL, 0),
5379         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5380                          &rx_int0_dem_inp_mux),
5381         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5382                          &rx_int1_dem_inp_mux),
5383         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5384                          &rx_int2_dem_inp_mux),
5385
5386         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5387                            &rx_int0_1_interp_mux,
5388                            wcd934x_codec_enable_main_path,
5389                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5390                            SND_SOC_DAPM_POST_PMD),
5391         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5392                            &rx_int1_1_interp_mux,
5393                            wcd934x_codec_enable_main_path,
5394                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5395                            SND_SOC_DAPM_POST_PMD),
5396         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5397                            &rx_int2_1_interp_mux,
5398                            wcd934x_codec_enable_main_path,
5399                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5400                            SND_SOC_DAPM_POST_PMD),
5401         SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5402                            &rx_int3_1_interp_mux,
5403                            wcd934x_codec_enable_main_path,
5404                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5405                            SND_SOC_DAPM_POST_PMD),
5406         SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5407                            &rx_int4_1_interp_mux,
5408                            wcd934x_codec_enable_main_path,
5409                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5410                            SND_SOC_DAPM_POST_PMD),
5411         SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5412                            &rx_int7_1_interp_mux,
5413                            wcd934x_codec_enable_main_path,
5414                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5415                            SND_SOC_DAPM_POST_PMD),
5416         SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5417                            &rx_int8_1_interp_mux,
5418                            wcd934x_codec_enable_main_path,
5419                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5420                            SND_SOC_DAPM_POST_PMD),
5421
5422         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5423                          &rx_int0_2_interp_mux),
5424         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5425                          &rx_int1_2_interp_mux),
5426         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5427                          &rx_int2_2_interp_mux),
5428         SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5429                          &rx_int3_2_interp_mux),
5430         SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5431                          &rx_int4_2_interp_mux),
5432         SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5433                          &rx_int7_2_interp_mux),
5434         SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5435                          &rx_int8_2_interp_mux),
5436         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5437                            0, 0, wcd934x_codec_ear_dac_event,
5438                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5439                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5440         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5441                            5, 0, wcd934x_codec_hphl_dac_event,
5442                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5443                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5444         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5445                            4, 0, wcd934x_codec_hphr_dac_event,
5446                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5447                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5448         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5449                            0, 0, wcd934x_codec_lineout_dac_event,
5450                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5451         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5452                            0, 0, wcd934x_codec_lineout_dac_event,
5453                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5454         SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5455         SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5456                            wcd934x_codec_enable_hphl_pa,
5457                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5458                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5459         SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5460                            wcd934x_codec_enable_hphr_pa,
5461                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5462                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5463         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5464                            NULL, 0),
5465         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5466                            NULL, 0),
5467         SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5468                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5469         SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5470                          0, 0, NULL, 0),
5471         SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5472                             0, 0, NULL, 0),
5473         SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5474                          0, 0, NULL, 0),
5475         SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5476                             0, 0, NULL, 0),
5477         SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5478                             wcd934x_codec_enable_interp_clk,
5479                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5480         SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5481                             wcd934x_codec_enable_interp_clk,
5482                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5483         SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5484                             wcd934x_codec_enable_interp_clk,
5485                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5486         SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5487                             wcd934x_codec_enable_interp_clk,
5488                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5489         SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5490                             wcd934x_codec_enable_interp_clk,
5491                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5492         SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5493                             wcd934x_codec_enable_interp_clk,
5494                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5495         SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5496                             wcd934x_codec_enable_interp_clk,
5497                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5498         SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5499                             0, 0, NULL, 0),
5500         SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5501                             0, 0, NULL, 0),
5502         SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5503                             0, 0, NULL, 0),
5504         SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5505                             0, 0, NULL, 0),
5506         SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5507                             0, 0, NULL, 0),
5508         SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5509                             0, 0, NULL, 0),
5510         SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5511                             0, 0, NULL, 0),
5512         SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5513                             wcd934x_codec_enable_mclk,
5514                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5515
5516         /* TX */
5517         SND_SOC_DAPM_INPUT("AMIC1"),
5518         SND_SOC_DAPM_INPUT("AMIC2"),
5519         SND_SOC_DAPM_INPUT("AMIC3"),
5520         SND_SOC_DAPM_INPUT("AMIC4"),
5521         SND_SOC_DAPM_INPUT("AMIC5"),
5522         SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5523         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5524         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5525         SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5526         SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5527         SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5528
5529         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5530                                AIF1_CAP, 0, wcd934x_codec_enable_slim,
5531                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5532         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5533                                AIF2_CAP, 0, wcd934x_codec_enable_slim,
5534                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5535         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5536                                AIF3_CAP, 0, wcd934x_codec_enable_slim,
5537                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5538
5539         SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5540         SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5541         SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5542         SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5543         SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5544         SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5545         SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5546         SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5547         SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5548         SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5549         SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5550         SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5551         SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5552
5553         /* Digital Mic Inputs */
5554         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5555                            wcd934x_codec_enable_dmic,
5556                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5557         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5558                            wcd934x_codec_enable_dmic,
5559                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5560         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5561                            wcd934x_codec_enable_dmic,
5562                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5563         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5564                            wcd934x_codec_enable_dmic,
5565                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5566         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5567                            wcd934x_codec_enable_dmic,
5568                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5569         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5570                            wcd934x_codec_enable_dmic,
5571                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5572         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5573         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5574         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5575         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5576         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5577         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5578         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5579         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5580         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5581         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5582         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5583         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5584         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5585         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5586         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5587         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5588         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5589         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5590         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5591                            &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5592                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5593                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5594         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5595                            &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5596                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5597                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5598         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5599                            &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5600                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5601                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5602         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5603                            &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5604                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5605                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5606         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5607                            &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5608                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5609                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5610         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5611                            &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5612                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5613                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5614         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5615                            &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5616                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5617                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5618         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5619                            &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5620                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5621                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5622         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5623                            &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5624                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5625                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5626         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5627                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5628         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5629                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5630         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5631                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5632         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5633                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5634         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5635                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5636                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5637         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5638                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5639                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5640         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5641                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5642                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5643         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5644                             wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5645                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5646
5647         SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5648         SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5649                          &cdc_if_tx0_mux),
5650         SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5651                          &cdc_if_tx1_mux),
5652         SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5653                          &cdc_if_tx2_mux),
5654         SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5655                          &cdc_if_tx3_mux),
5656         SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5657                          &cdc_if_tx4_mux),
5658         SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5659                          &cdc_if_tx5_mux),
5660         SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5661                          &cdc_if_tx6_mux),
5662         SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5663                          &cdc_if_tx7_mux),
5664         SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5665                          &cdc_if_tx8_mux),
5666         SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5667                          &cdc_if_tx9_mux),
5668         SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5669                          &cdc_if_tx10_mux),
5670         SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5671                          &cdc_if_tx11_mux),
5672         SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5673                          &cdc_if_tx11_inp1_mux),
5674         SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5675                          &cdc_if_tx13_mux),
5676         SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5677                          &cdc_if_tx13_inp1_mux),
5678         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5679                            aif1_slim_cap_mixer,
5680                            ARRAY_SIZE(aif1_slim_cap_mixer)),
5681         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5682                            aif2_slim_cap_mixer,
5683                            ARRAY_SIZE(aif2_slim_cap_mixer)),
5684         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5685                            aif3_slim_cap_mixer,
5686                            ARRAY_SIZE(aif3_slim_cap_mixer)),
5687 };
5688
5689 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5690         /* RX0-RX7 */
5691         WCD934X_SLIM_RX_AIF_PATH(0),
5692         WCD934X_SLIM_RX_AIF_PATH(1),
5693         WCD934X_SLIM_RX_AIF_PATH(2),
5694         WCD934X_SLIM_RX_AIF_PATH(3),
5695         WCD934X_SLIM_RX_AIF_PATH(4),
5696         WCD934X_SLIM_RX_AIF_PATH(5),
5697         WCD934X_SLIM_RX_AIF_PATH(6),
5698         WCD934X_SLIM_RX_AIF_PATH(7),
5699
5700         /* RX0 Ear out */
5701         WCD934X_INTERPOLATOR_PATH(0),
5702         WCD934X_INTERPOLATOR_MIX2(0),
5703         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5704         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5705         {"RX INT0 DAC", NULL, "RX_BIAS"},
5706         {"EAR PA", NULL, "RX INT0 DAC"},
5707         {"EAR", NULL, "EAR PA"},
5708
5709         /* RX1 Headphone left */
5710         WCD934X_INTERPOLATOR_PATH(1),
5711         WCD934X_INTERPOLATOR_MIX2(1),
5712         {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5713         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5714         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5715         {"RX INT1 DAC", NULL, "RX_BIAS"},
5716         {"HPHL PA", NULL, "RX INT1 DAC"},
5717         {"HPHL", NULL, "HPHL PA"},
5718
5719         /* RX2 Headphone right */
5720         WCD934X_INTERPOLATOR_PATH(2),
5721         WCD934X_INTERPOLATOR_MIX2(2),
5722         {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5723         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5724         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5725         {"RX INT2 DAC", NULL, "RX_BIAS"},
5726         {"HPHR PA", NULL, "RX INT2 DAC"},
5727         {"HPHR", NULL, "HPHR PA"},
5728
5729         /* RX3 HIFi LineOut1 */
5730         WCD934X_INTERPOLATOR_PATH(3),
5731         WCD934X_INTERPOLATOR_MIX2(3),
5732         {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5733         {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5734         {"RX INT3 DAC", NULL, "RX_BIAS"},
5735         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5736         {"LINEOUT1", NULL, "LINEOUT1 PA"},
5737
5738         /* RX4 HIFi LineOut2 */
5739         WCD934X_INTERPOLATOR_PATH(4),
5740         WCD934X_INTERPOLATOR_MIX2(4),
5741         {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5742         {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5743         {"RX INT4 DAC", NULL, "RX_BIAS"},
5744         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5745         {"LINEOUT2", NULL, "LINEOUT2 PA"},
5746
5747         /* RX7 Speaker Left Out PA */
5748         WCD934X_INTERPOLATOR_PATH(7),
5749         WCD934X_INTERPOLATOR_MIX2(7),
5750         {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5751         {"RX INT7 CHAIN", NULL, "RX_BIAS"},
5752         {"RX INT7 CHAIN", NULL, "SBOOST0"},
5753         {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5754         {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5755
5756         /* RX8 Speaker Right Out PA */
5757         WCD934X_INTERPOLATOR_PATH(8),
5758         {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5759         {"RX INT8 CHAIN", NULL, "RX_BIAS"},
5760         {"RX INT8 CHAIN", NULL, "SBOOST1"},
5761         {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5762         {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5763
5764         /* Tx */
5765         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5766         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5767         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5768
5769         WCD934X_SLIM_TX_AIF_PATH(0),
5770         WCD934X_SLIM_TX_AIF_PATH(1),
5771         WCD934X_SLIM_TX_AIF_PATH(2),
5772         WCD934X_SLIM_TX_AIF_PATH(3),
5773         WCD934X_SLIM_TX_AIF_PATH(4),
5774         WCD934X_SLIM_TX_AIF_PATH(5),
5775         WCD934X_SLIM_TX_AIF_PATH(6),
5776         WCD934X_SLIM_TX_AIF_PATH(7),
5777         WCD934X_SLIM_TX_AIF_PATH(8),
5778
5779         WCD934X_ADC_MUX(0),
5780         WCD934X_ADC_MUX(1),
5781         WCD934X_ADC_MUX(2),
5782         WCD934X_ADC_MUX(3),
5783         WCD934X_ADC_MUX(4),
5784         WCD934X_ADC_MUX(5),
5785         WCD934X_ADC_MUX(6),
5786         WCD934X_ADC_MUX(7),
5787         WCD934X_ADC_MUX(8),
5788
5789         {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5790         {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5791         {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5792         {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5793         {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5794         {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5795         {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5796         {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5797         {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5798
5799         {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5800         {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5801
5802         { "DMIC0", NULL, "DMIC0 Pin" },
5803         { "DMIC1", NULL, "DMIC1 Pin" },
5804         { "DMIC2", NULL, "DMIC2 Pin" },
5805         { "DMIC3", NULL, "DMIC3 Pin" },
5806         { "DMIC4", NULL, "DMIC4 Pin" },
5807         { "DMIC5", NULL, "DMIC5 Pin" },
5808
5809         {"ADC1", NULL, "AMIC1"},
5810         {"ADC2", NULL, "AMIC2"},
5811         {"ADC3", NULL, "AMIC3"},
5812         {"ADC4", NULL, "AMIC4_5 SEL"},
5813
5814         WCD934X_IIR_INP_MUX(0),
5815         WCD934X_IIR_INP_MUX(1),
5816
5817         {"SRC0", NULL, "IIR0"},
5818         {"SRC1", NULL, "IIR1"},
5819 };
5820
5821 static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5822                                   struct snd_soc_jack *jack, void *data)
5823 {
5824         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5825         int ret = 0;
5826
5827         if (!wcd->mbhc)
5828                 return -ENOTSUPP;
5829
5830         if (jack && !wcd->mbhc_started) {
5831                 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5832                 wcd->mbhc_started = true;
5833         } else if (wcd->mbhc_started) {
5834                 wcd_mbhc_stop(wcd->mbhc);
5835                 wcd->mbhc_started = false;
5836         }
5837
5838         return ret;
5839 }
5840
5841 static const struct snd_soc_component_driver wcd934x_component_drv = {
5842         .probe = wcd934x_comp_probe,
5843         .remove = wcd934x_comp_remove,
5844         .set_sysclk = wcd934x_comp_set_sysclk,
5845         .controls = wcd934x_snd_controls,
5846         .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5847         .dapm_widgets = wcd934x_dapm_widgets,
5848         .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5849         .dapm_routes = wcd934x_audio_map,
5850         .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5851         .set_jack = wcd934x_codec_set_jack,
5852 };
5853
5854 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5855 {
5856         struct device *dev = &wcd->sdev->dev;
5857         struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5858         struct device_node *ifc_dev_np;
5859
5860         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5861         if (!ifc_dev_np) {
5862                 dev_err(dev, "No Interface device found\n");
5863                 return -EINVAL;
5864         }
5865
5866         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5867         of_node_put(ifc_dev_np);
5868         if (!wcd->sidev) {
5869                 dev_err(dev, "Unable to get SLIM Interface device\n");
5870                 return -EINVAL;
5871         }
5872
5873         slim_get_logical_addr(wcd->sidev);
5874         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5875                                   &wcd934x_ifc_regmap_config);
5876         if (IS_ERR(wcd->if_regmap)) {
5877                 dev_err(dev, "Failed to allocate ifc register map\n");
5878                 return PTR_ERR(wcd->if_regmap);
5879         }
5880
5881         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5882                              &wcd->dmic_sample_rate);
5883
5884         cfg->mbhc_micbias = MIC_BIAS_2;
5885         cfg->anc_micbias = MIC_BIAS_2;
5886         cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5887         cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5888         cfg->micb_mv = wcd->micb2_mv;
5889         cfg->linein_th = 5000;
5890         cfg->hs_thr = 1700;
5891         cfg->hph_thr = 50;
5892
5893         wcd_dt_parse_mbhc_data(dev, cfg);
5894
5895
5896         return 0;
5897 }
5898
5899 static int wcd934x_codec_probe(struct platform_device *pdev)
5900 {
5901         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5902         struct wcd934x_codec *wcd;
5903         struct device *dev = &pdev->dev;
5904         int ret, irq;
5905
5906         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5907         if (!wcd)
5908                 return -ENOMEM;
5909
5910         wcd->dev = dev;
5911         wcd->regmap = data->regmap;
5912         wcd->extclk = data->extclk;
5913         wcd->sdev = to_slim_device(data->dev);
5914         mutex_init(&wcd->sysclk_mutex);
5915         mutex_init(&wcd->micb_lock);
5916
5917         ret = wcd934x_codec_parse_data(wcd);
5918         if (ret) {
5919                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5920                 return ret;
5921         }
5922
5923         /* set default rate 9P6MHz */
5924         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5925                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5926                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5927         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5928         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5929
5930         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5931         if (irq < 0) {
5932                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5933                 return irq;
5934         }
5935
5936         ret = devm_request_threaded_irq(dev, irq, NULL,
5937                                         wcd934x_slim_irq_handler,
5938                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5939                                         "slim", wcd);
5940         if (ret) {
5941                 dev_err(dev, "Failed to request slimbus irq\n");
5942                 return ret;
5943         }
5944
5945         wcd934x_register_mclk_output(wcd);
5946         platform_set_drvdata(pdev, wcd);
5947
5948         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5949                                                wcd934x_slim_dais,
5950                                                ARRAY_SIZE(wcd934x_slim_dais));
5951 }
5952
5953 static const struct platform_device_id wcd934x_driver_id[] = {
5954         {
5955                 .name = "wcd934x-codec",
5956         },
5957         {},
5958 };
5959 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5960
5961 static struct platform_driver wcd934x_codec_driver = {
5962         .probe  = &wcd934x_codec_probe,
5963         .id_table = wcd934x_driver_id,
5964         .driver = {
5965                 .name   = "wcd934x-codec",
5966         }
5967 };
5968
5969 MODULE_ALIAS("platform:wcd934x-codec");
5970 module_platform_driver(wcd934x_codec_driver);
5971 MODULE_DESCRIPTION("WCD934x codec driver");
5972 MODULE_LICENSE("GPL v2");