sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/kernel.h>
   8 #include <linux/mfd/wcd934x/registers.h>
   9 #include <linux/mfd/wcd934x/wcd934x.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/slimbus.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/tlv.h>
  23 #include "wcd-clsh-v2.h"
  24
  25 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  26                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  27                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  28 /* Fractional Rates */
  29 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  30                                  SNDRV_PCM_RATE_176400)
  31 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  32                                     SNDRV_PCM_FMTBIT_S24_LE)
  33
  34 /* slave port water mark level
  35  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  36  */
  37 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  38 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  39 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  40 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  41 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  42 #define SLAVE_PORT_ENABLE               1
  43 #define SLAVE_PORT_DISABLE              0
  44 #define WCD934X_SLIM_WATER_MARK_VAL \
  45         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  46          (SLAVE_PORT_ENABLE))
  47
  48 #define WCD934X_SLIM_NUM_PORT_REG       3
  49 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  50 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  51 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  52 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  53
  54 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  55 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  56
  57 /* Only valid for 9.6 MHz mclk */
  58 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  59 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  60
  61 /* Only valid for 12.288 MHz mclk */
  62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  63
  64 #define WCD934X_DMIC_CLK_DIV_2          0x0
  65 #define WCD934X_DMIC_CLK_DIV_3          0x1
  66 #define WCD934X_DMIC_CLK_DIV_4          0x2
  67 #define WCD934X_DMIC_CLK_DIV_6          0x3
  68 #define WCD934X_DMIC_CLK_DIV_8          0x4
  69 #define WCD934X_DMIC_CLK_DIV_16         0x5
  70 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  71
  72 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  73 #define CF_MIN_3DB_4HZ                  0x0
  74 #define CF_MIN_3DB_75HZ                 0x1
  75 #define CF_MIN_3DB_150HZ                0x2
  76
  77 #define WCD934X_RX_START                16
  78 #define WCD934X_NUM_INTERPOLATORS       9
  79 #define WCD934X_RX_PATH_CTL_OFFSET      20
  80 #define WCD934X_MAX_VALID_ADC_MUX       13
  81 #define WCD934X_INVALID_ADC_MUX         9
  82
  83 #define WCD934X_SLIM_RX_CH(p) \
  84         {.port = p + WCD934X_RX_START, .shift = p,}
  85
  86 #define WCD934X_SLIM_TX_CH(p) \
  87         {.port = p, .shift = p,}
  88
  89 /* Feature masks to distinguish codec version */
  90 #define DSD_DISABLED_MASK   0
  91 #define SLNQ_DISABLED_MASK  1
  92
  93 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  94 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  95
  96 /* As fine version info cannot be retrieved before wcd probe.
  97  * Define three coarse versions for possible future use before wcd probe.
  98  */
  99 #define WCD_VERSION_WCD9340_1_0     0x400
 100 #define WCD_VERSION_WCD9341_1_0     0x410
 101 #define WCD_VERSION_WCD9340_1_1     0x401
 102 #define WCD_VERSION_WCD9341_1_1     0x411
 103 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 104 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 105 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 106 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 107 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 108 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 109
 110 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 111 #define WCD934X_DEC_PWR_LVL_LP          0x02
 112 #define WCD934X_DEC_PWR_LVL_HP          0x04
 113 #define WCD934X_DEC_PWR_LVL_DF          0x00
 114 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 115
 116 #define WCD934X_DEF_MICBIAS_MV  1800
 117 #define WCD934X_MAX_MICBIAS_MV  2850
 118
 119 #define WCD_IIR_FILTER_SIZE     (sizeof(u32) * BAND_MAX)
 120
 121 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 122 { \
 123         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 124         .info = wcd934x_iir_filter_info, \
 125         .get = wcd934x_get_iir_band_audio_mixer, \
 126         .put = wcd934x_put_iir_band_audio_mixer, \
 127         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 128                 .iir_idx = iidx, \
 129                 .band_idx = bidx, \
 130                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 131         } \
 132 }
 133
 134 #define WCD934X_INTERPOLATOR_PATH(id)                   \
 135         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 136         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 137         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 138         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 139         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 140         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 141         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 142         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 143         {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},  \
 144         {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},  \
 145         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 146         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 147         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 148         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 149         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 150         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 151         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 152         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 153         {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},  \
 154         {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},  \
 155         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 156         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 157         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 158         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 159         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 160         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 161         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 162         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 163         {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},          \
 164         {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},          \
 165         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
 166         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
 167         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
 168         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 169         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 170         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 171         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 172         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 173         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 174         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 175         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 176         {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
 177         {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
 178         {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},        \
 179         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},      \
 180         {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},       \
 181         {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},     \
 182         {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},  \
 183         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
 184
 185 #define WCD934X_INTERPOLATOR_MIX2(id)                   \
 186         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
 187         {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
 188
 189 #define WCD934X_SLIM_RX_AIF_PATH(id)    \
 190         {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},     \
 191         {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},     \
 192         {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},     \
 193         {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
 194         {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
 195
 196 #define WCD934X_ADC_MUX(id) \
 197         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id },       \
 198         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id },       \
 199         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 200         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 201         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 202         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 203         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 204         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 205         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 206         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 207         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 208         {"AMIC MUX" #id, "ADC4", "ADC4"}
 209
 210 #define WCD934X_IIR_INP_MUX(id) \
 211         {"IIR" #id, NULL, "IIR" #id " INP0 MUX"},       \
 212         {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},    \
 213         {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},    \
 214         {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},    \
 215         {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},    \
 216         {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},    \
 217         {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},    \
 218         {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},    \
 219         {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},    \
 220         {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},    \
 221         {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},     \
 222         {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},     \
 223         {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},     \
 224         {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},     \
 225         {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},     \
 226         {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},     \
 227         {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},     \
 228         {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},     \
 229         {"IIR" #id, NULL, "IIR" #id " INP1 MUX"},       \
 230         {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},    \
 231         {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},    \
 232         {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},    \
 233         {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},    \
 234         {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},    \
 235         {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},    \
 236         {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},    \
 237         {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},    \
 238         {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},    \
 239         {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},     \
 240         {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},     \
 241         {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},     \
 242         {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},     \
 243         {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},     \
 244         {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},     \
 245         {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},     \
 246         {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},     \
 247         {"IIR" #id, NULL, "IIR" #id " INP2 MUX"},       \
 248         {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},    \
 249         {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},    \
 250         {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},    \
 251         {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},    \
 252         {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},    \
 253         {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},    \
 254         {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},    \
 255         {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},    \
 256         {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},    \
 257         {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},     \
 258         {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},     \
 259         {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},     \
 260         {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},     \
 261         {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},     \
 262         {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},     \
 263         {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},     \
 264         {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},     \
 265         {"IIR" #id, NULL, "IIR" #id " INP3 MUX"},       \
 266         {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},    \
 267         {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},    \
 268         {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},    \
 269         {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},    \
 270         {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},    \
 271         {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},    \
 272         {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},    \
 273         {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},    \
 274         {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},    \
 275         {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},     \
 276         {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},     \
 277         {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},     \
 278         {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},     \
 279         {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},     \
 280         {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},     \
 281         {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},     \
 282         {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
 283
 284 #define WCD934X_SLIM_TX_AIF_PATH(id)    \
 285         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 286         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 287         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 288         {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
 289
 290 enum {
 291         MIC_BIAS_1 = 1,
 292         MIC_BIAS_2,
 293         MIC_BIAS_3,
 294         MIC_BIAS_4
 295 };
 296
 297 enum {
 298         SIDO_SOURCE_INTERNAL,
 299         SIDO_SOURCE_RCO_BG,
 300 };
 301
 302 enum {
 303         INTERP_EAR = 0,
 304         INTERP_HPHL,
 305         INTERP_HPHR,
 306         INTERP_LO1,
 307         INTERP_LO2,
 308         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 309         INTERP_LO4_NA,
 310         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 311         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 312         INTERP_MAX,
 313 };
 314
 315 enum {
 316         WCD934X_RX0 = 0,
 317         WCD934X_RX1,
 318         WCD934X_RX2,
 319         WCD934X_RX3,
 320         WCD934X_RX4,
 321         WCD934X_RX5,
 322         WCD934X_RX6,
 323         WCD934X_RX7,
 324         WCD934X_RX8,
 325         WCD934X_RX9,
 326         WCD934X_RX10,
 327         WCD934X_RX11,
 328         WCD934X_RX12,
 329         WCD934X_RX_MAX,
 330 };
 331
 332 enum {
 333         WCD934X_TX0 = 0,
 334         WCD934X_TX1,
 335         WCD934X_TX2,
 336         WCD934X_TX3,
 337         WCD934X_TX4,
 338         WCD934X_TX5,
 339         WCD934X_TX6,
 340         WCD934X_TX7,
 341         WCD934X_TX8,
 342         WCD934X_TX9,
 343         WCD934X_TX10,
 344         WCD934X_TX11,
 345         WCD934X_TX12,
 346         WCD934X_TX13,
 347         WCD934X_TX14,
 348         WCD934X_TX15,
 349         WCD934X_TX_MAX,
 350 };
 351
 352 struct wcd934x_slim_ch {
 353         u32 ch_num;
 354         u16 port;
 355         u16 shift;
 356         struct list_head list;
 357 };
 358
 359 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 360         WCD934X_SLIM_TX_CH(0),
 361         WCD934X_SLIM_TX_CH(1),
 362         WCD934X_SLIM_TX_CH(2),
 363         WCD934X_SLIM_TX_CH(3),
 364         WCD934X_SLIM_TX_CH(4),
 365         WCD934X_SLIM_TX_CH(5),
 366         WCD934X_SLIM_TX_CH(6),
 367         WCD934X_SLIM_TX_CH(7),
 368         WCD934X_SLIM_TX_CH(8),
 369         WCD934X_SLIM_TX_CH(9),
 370         WCD934X_SLIM_TX_CH(10),
 371         WCD934X_SLIM_TX_CH(11),
 372         WCD934X_SLIM_TX_CH(12),
 373         WCD934X_SLIM_TX_CH(13),
 374         WCD934X_SLIM_TX_CH(14),
 375         WCD934X_SLIM_TX_CH(15),
 376 };
 377
 378 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 379         WCD934X_SLIM_RX_CH(0),   /* 16 */
 380         WCD934X_SLIM_RX_CH(1),   /* 17 */
 381         WCD934X_SLIM_RX_CH(2),
 382         WCD934X_SLIM_RX_CH(3),
 383         WCD934X_SLIM_RX_CH(4),
 384         WCD934X_SLIM_RX_CH(5),
 385         WCD934X_SLIM_RX_CH(6),
 386         WCD934X_SLIM_RX_CH(7),
 387         WCD934X_SLIM_RX_CH(8),
 388         WCD934X_SLIM_RX_CH(9),
 389         WCD934X_SLIM_RX_CH(10),
 390         WCD934X_SLIM_RX_CH(11),
 391         WCD934X_SLIM_RX_CH(12),
 392 };
 393
 394 /* Codec supports 2 IIR filters */
 395 enum {
 396         IIR0 = 0,
 397         IIR1,
 398         IIR_MAX,
 399 };
 400
 401 /* Each IIR has 5 Filter Stages */
 402 enum {
 403         BAND1 = 0,
 404         BAND2,
 405         BAND3,
 406         BAND4,
 407         BAND5,
 408         BAND_MAX,
 409 };
 410
 411 enum {
 412         COMPANDER_1, /* HPH_L */
 413         COMPANDER_2, /* HPH_R */
 414         COMPANDER_3, /* LO1_DIFF */
 415         COMPANDER_4, /* LO2_DIFF */
 416         COMPANDER_5, /* LO3_SE - not used in Tavil */
 417         COMPANDER_6, /* LO4_SE - not used in Tavil */
 418         COMPANDER_7, /* SWR SPK CH1 */
 419         COMPANDER_8, /* SWR SPK CH2 */
 420         COMPANDER_MAX,
 421 };
 422
 423 enum {
 424         AIF1_PB = 0,
 425         AIF1_CAP,
 426         AIF2_PB,
 427         AIF2_CAP,
 428         AIF3_PB,
 429         AIF3_CAP,
 430         AIF4_PB,
 431         AIF4_VIFEED,
 432         AIF4_MAD_TX,
 433         NUM_CODEC_DAIS,
 434 };
 435
 436 enum {
 437         INTn_1_INP_SEL_ZERO = 0,
 438         INTn_1_INP_SEL_DEC0,
 439         INTn_1_INP_SEL_DEC1,
 440         INTn_1_INP_SEL_IIR0,
 441         INTn_1_INP_SEL_IIR1,
 442         INTn_1_INP_SEL_RX0,
 443         INTn_1_INP_SEL_RX1,
 444         INTn_1_INP_SEL_RX2,
 445         INTn_1_INP_SEL_RX3,
 446         INTn_1_INP_SEL_RX4,
 447         INTn_1_INP_SEL_RX5,
 448         INTn_1_INP_SEL_RX6,
 449         INTn_1_INP_SEL_RX7,
 450 };
 451
 452 enum {
 453         INTn_2_INP_SEL_ZERO = 0,
 454         INTn_2_INP_SEL_RX0,
 455         INTn_2_INP_SEL_RX1,
 456         INTn_2_INP_SEL_RX2,
 457         INTn_2_INP_SEL_RX3,
 458         INTn_2_INP_SEL_RX4,
 459         INTn_2_INP_SEL_RX5,
 460         INTn_2_INP_SEL_RX6,
 461         INTn_2_INP_SEL_RX7,
 462         INTn_2_INP_SEL_PROXIMITY,
 463 };
 464
 465 enum {
 466         INTERP_MAIN_PATH,
 467         INTERP_MIX_PATH,
 468 };
 469
 470 struct interp_sample_rate {
 471         int sample_rate;
 472         int rate_val;
 473 };
 474
 475 static struct interp_sample_rate sr_val_tbl[] = {
 476         {8000, 0x0},
 477         {16000, 0x1},
 478         {32000, 0x3},
 479         {48000, 0x4},
 480         {96000, 0x5},
 481         {192000, 0x6},
 482         {384000, 0x7},
 483         {44100, 0x9},
 484         {88200, 0xA},
 485         {176400, 0xB},
 486         {352800, 0xC},
 487 };
 488
 489 struct wcd_slim_codec_dai_data {
 490         struct list_head slim_ch_list;
 491         struct slim_stream_config sconfig;
 492         struct slim_stream_runtime *sruntime;
 493 };
 494
 495 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 496         {
 497                 .name = "WCD9335-IFC-DEV",
 498                 .range_min =  0x0,
 499                 .range_max = 0xffff,
 500                 .selector_reg = 0x800,
 501                 .selector_mask = 0xfff,
 502                 .selector_shift = 0,
 503                 .window_start = 0x800,
 504                 .window_len = 0x400,
 505         },
 506 };
 507
 508 static struct regmap_config wcd934x_ifc_regmap_config = {
 509         .reg_bits = 16,
 510         .val_bits = 8,
 511         .max_register = 0xffff,
 512         .ranges = wcd934x_ifc_ranges,
 513         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 514 };
 515
 516 struct wcd934x_codec {
 517         struct device *dev;
 518         struct clk_hw hw;
 519         struct clk *extclk;
 520         struct regmap *regmap;
 521         struct regmap *if_regmap;
 522         struct slim_device *sdev;
 523         struct slim_device *sidev;
 524         struct wcd_clsh_ctrl *clsh_ctrl;
 525         struct snd_soc_component *component;
 526         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 527         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 528         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 529         int rate;
 530         u32 version;
 531         u32 hph_mode;
 532         int num_rx_port;
 533         int num_tx_port;
 534         u32 tx_port_value[WCD934X_TX_MAX];
 535         u32 rx_port_value[WCD934X_RX_MAX];
 536         int sido_input_src;
 537         int dmic_0_1_clk_cnt;
 538         int dmic_2_3_clk_cnt;
 539         int dmic_4_5_clk_cnt;
 540         int dmic_sample_rate;
 541         int comp_enabled[COMPANDER_MAX];
 542         int sysclk_users;
 543         struct mutex sysclk_mutex;
 544 };
 545
 546 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 547
 548 struct wcd_iir_filter_ctl {
 549         unsigned int iir_idx;
 550         unsigned int band_idx;
 551         struct soc_bytes_ext bytes_ext;
 552 };
 553
 554 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 555 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 556 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 557 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 558
 559 /* Cutoff frequency for high pass filter */
 560 static const char * const cf_text[] = {
 561         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 562 };
 563
 564 static const char * const rx_cf_text[] = {
 565         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 566         "CF_NEG_3DB_0P48HZ"
 567 };
 568
 569 static const char * const rx_hph_mode_mux_text[] = {
 570         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 571         "Class-H Hi-Fi Low Power"
 572 };
 573
 574 static const char *const slim_rx_mux_text[] = {
 575         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 576 };
 577
 578 static const char * const rx_int0_7_mix_mux_text[] = {
 579         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 580         "RX6", "RX7", "PROXIMITY"
 581 };
 582
 583 static const char * const rx_int_mix_mux_text[] = {
 584         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 585         "RX6", "RX7"
 586 };
 587
 588 static const char * const rx_prim_mix_text[] = {
 589         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 590         "RX3", "RX4", "RX5", "RX6", "RX7"
 591 };
 592
 593 static const char * const rx_sidetone_mix_text[] = {
 594         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 595 };
 596
 597 static const char * const iir_inp_mux_text[] = {
 598         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
 599         "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
 600 };
 601
 602 static const char * const rx_int_dem_inp_mux_text[] = {
 603         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 604 };
 605
 606 static const char * const rx_int0_1_interp_mux_text[] = {
 607         "ZERO", "RX INT0_1 MIX1",
 608 };
 609
 610 static const char * const rx_int1_1_interp_mux_text[] = {
 611         "ZERO", "RX INT1_1 MIX1",
 612 };
 613
 614 static const char * const rx_int2_1_interp_mux_text[] = {
 615         "ZERO", "RX INT2_1 MIX1",
 616 };
 617
 618 static const char * const rx_int3_1_interp_mux_text[] = {
 619         "ZERO", "RX INT3_1 MIX1",
 620 };
 621
 622 static const char * const rx_int4_1_interp_mux_text[] = {
 623         "ZERO", "RX INT4_1 MIX1",
 624 };
 625
 626 static const char * const rx_int7_1_interp_mux_text[] = {
 627         "ZERO", "RX INT7_1 MIX1",
 628 };
 629
 630 static const char * const rx_int8_1_interp_mux_text[] = {
 631         "ZERO", "RX INT8_1 MIX1",
 632 };
 633
 634 static const char * const rx_int0_2_interp_mux_text[] = {
 635         "ZERO", "RX INT0_2 MUX",
 636 };
 637
 638 static const char * const rx_int1_2_interp_mux_text[] = {
 639         "ZERO", "RX INT1_2 MUX",
 640 };
 641
 642 static const char * const rx_int2_2_interp_mux_text[] = {
 643         "ZERO", "RX INT2_2 MUX",
 644 };
 645
 646 static const char * const rx_int3_2_interp_mux_text[] = {
 647         "ZERO", "RX INT3_2 MUX",
 648 };
 649
 650 static const char * const rx_int4_2_interp_mux_text[] = {
 651         "ZERO", "RX INT4_2 MUX",
 652 };
 653
 654 static const char * const rx_int7_2_interp_mux_text[] = {
 655         "ZERO", "RX INT7_2 MUX",
 656 };
 657
 658 static const char * const rx_int8_2_interp_mux_text[] = {
 659         "ZERO", "RX INT8_2 MUX",
 660 };
 661
 662 static const char * const dmic_mux_text[] = {
 663         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
 664 };
 665
 666 static const char * const amic_mux_text[] = {
 667         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
 668 };
 669
 670 static const char * const amic4_5_sel_text[] = {
 671         "AMIC4", "AMIC5"
 672 };
 673
 674 static const char * const adc_mux_text[] = {
 675         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 676 };
 677
 678 static const char * const cdc_if_tx0_mux_text[] = {
 679         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 680 };
 681
 682 static const char * const cdc_if_tx1_mux_text[] = {
 683         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 684 };
 685
 686 static const char * const cdc_if_tx2_mux_text[] = {
 687         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 688 };
 689
 690 static const char * const cdc_if_tx3_mux_text[] = {
 691         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 692 };
 693
 694 static const char * const cdc_if_tx4_mux_text[] = {
 695         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 696 };
 697
 698 static const char * const cdc_if_tx5_mux_text[] = {
 699         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 700 };
 701
 702 static const char * const cdc_if_tx6_mux_text[] = {
 703         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 704 };
 705
 706 static const char * const cdc_if_tx7_mux_text[] = {
 707         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 708 };
 709
 710 static const char * const cdc_if_tx8_mux_text[] = {
 711         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 712 };
 713
 714 static const char * const cdc_if_tx9_mux_text[] = {
 715         "ZERO", "DEC7", "DEC7_192"
 716 };
 717
 718 static const char * const cdc_if_tx10_mux_text[] = {
 719         "ZERO", "DEC6", "DEC6_192"
 720 };
 721
 722 static const char * const cdc_if_tx11_mux_text[] = {
 723         "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
 724 };
 725
 726 static const char * const cdc_if_tx11_inp1_mux_text[] = {
 727         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
 728         "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
 729 };
 730
 731 static const char * const cdc_if_tx13_mux_text[] = {
 732         "CDC_DEC_5", "MAD_BRDCST"
 733 };
 734
 735 static const char * const cdc_if_tx13_inp1_mux_text[] = {
 736         "ZERO", "DEC5", "DEC5_192"
 737 };
 738
 739 static const struct soc_enum cf_dec0_enum =
 740         SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 741
 742 static const struct soc_enum cf_dec1_enum =
 743         SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 744
 745 static const struct soc_enum cf_dec2_enum =
 746         SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 747
 748 static const struct soc_enum cf_dec3_enum =
 749         SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 750
 751 static const struct soc_enum cf_dec4_enum =
 752         SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 753
 754 static const struct soc_enum cf_dec5_enum =
 755         SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 756
 757 static const struct soc_enum cf_dec6_enum =
 758         SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 759
 760 static const struct soc_enum cf_dec7_enum =
 761         SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 762
 763 static const struct soc_enum cf_dec8_enum =
 764         SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 765
 766 static const struct soc_enum cf_int0_1_enum =
 767         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 768
 769 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
 770                      rx_cf_text);
 771
 772 static const struct soc_enum cf_int1_1_enum =
 773         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 774
 775 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
 776                      rx_cf_text);
 777
 778 static const struct soc_enum cf_int2_1_enum =
 779         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 780
 781 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
 782                      rx_cf_text);
 783
 784 static const struct soc_enum cf_int3_1_enum =
 785         SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 786
 787 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
 788                             rx_cf_text);
 789
 790 static const struct soc_enum cf_int4_1_enum =
 791         SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 792
 793 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
 794                             rx_cf_text);
 795
 796 static const struct soc_enum cf_int7_1_enum =
 797         SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 798
 799 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
 800                             rx_cf_text);
 801
 802 static const struct soc_enum cf_int8_1_enum =
 803         SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 804
 805 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
 806                             rx_cf_text);
 807
 808 static const struct soc_enum rx_hph_mode_mux_enum =
 809         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 810                             rx_hph_mode_mux_text);
 811
 812 static const struct soc_enum slim_rx_mux_enum =
 813         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 814
 815 static const struct soc_enum rx_int0_2_mux_chain_enum =
 816         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 817                         rx_int0_7_mix_mux_text);
 818
 819 static const struct soc_enum rx_int1_2_mux_chain_enum =
 820         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 821                         rx_int_mix_mux_text);
 822
 823 static const struct soc_enum rx_int2_2_mux_chain_enum =
 824         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 825                         rx_int_mix_mux_text);
 826
 827 static const struct soc_enum rx_int3_2_mux_chain_enum =
 828         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 829                         rx_int_mix_mux_text);
 830
 831 static const struct soc_enum rx_int4_2_mux_chain_enum =
 832         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 833                         rx_int_mix_mux_text);
 834
 835 static const struct soc_enum rx_int7_2_mux_chain_enum =
 836         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 837                         rx_int0_7_mix_mux_text);
 838
 839 static const struct soc_enum rx_int8_2_mux_chain_enum =
 840         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 841                         rx_int_mix_mux_text);
 842
 843 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 844         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 845                         rx_prim_mix_text);
 846
 847 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 848         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 849                         rx_prim_mix_text);
 850
 851 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 852         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 853                         rx_prim_mix_text);
 854
 855 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 856         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 857                         rx_prim_mix_text);
 858
 859 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 860         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 861                         rx_prim_mix_text);
 862
 863 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 864         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 865                         rx_prim_mix_text);
 866
 867 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 868         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 869                         rx_prim_mix_text);
 870
 871 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 872         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 873                         rx_prim_mix_text);
 874
 875 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 876         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 877                         rx_prim_mix_text);
 878
 879 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 880         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 881                         rx_prim_mix_text);
 882
 883 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 884         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 885                         rx_prim_mix_text);
 886
 887 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 888         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 889                         rx_prim_mix_text);
 890
 891 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 892         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 893                         rx_prim_mix_text);
 894
 895 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 896         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 897                         rx_prim_mix_text);
 898
 899 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 900         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 901                         rx_prim_mix_text);
 902
 903 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 904         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 905                         rx_prim_mix_text);
 906
 907 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 908         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 909                         rx_prim_mix_text);
 910
 911 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 912         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 913                         rx_prim_mix_text);
 914
 915 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 916         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 917                         rx_prim_mix_text);
 918
 919 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 920         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 921                         rx_prim_mix_text);
 922
 923 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 924         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 925                         rx_prim_mix_text);
 926
 927 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
 928         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
 929                         rx_sidetone_mix_text);
 930
 931 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
 932         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
 933                         rx_sidetone_mix_text);
 934
 935 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
 936         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
 937                         rx_sidetone_mix_text);
 938
 939 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
 940         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
 941                         rx_sidetone_mix_text);
 942
 943 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
 944         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
 945                         rx_sidetone_mix_text);
 946
 947 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
 948         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
 949                         rx_sidetone_mix_text);
 950
 951 static const struct soc_enum iir0_inp0_mux_enum =
 952         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
 953                         0, 18, iir_inp_mux_text);
 954
 955 static const struct soc_enum iir0_inp1_mux_enum =
 956         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
 957                         0, 18, iir_inp_mux_text);
 958
 959 static const struct soc_enum iir0_inp2_mux_enum =
 960         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
 961                         0, 18, iir_inp_mux_text);
 962
 963 static const struct soc_enum iir0_inp3_mux_enum =
 964         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
 965                         0, 18, iir_inp_mux_text);
 966
 967 static const struct soc_enum iir1_inp0_mux_enum =
 968         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
 969                         0, 18, iir_inp_mux_text);
 970
 971 static const struct soc_enum iir1_inp1_mux_enum =
 972         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
 973                         0, 18, iir_inp_mux_text);
 974
 975 static const struct soc_enum iir1_inp2_mux_enum =
 976         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
 977                         0, 18, iir_inp_mux_text);
 978
 979 static const struct soc_enum iir1_inp3_mux_enum =
 980         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
 981                         0, 18, iir_inp_mux_text);
 982
 983 static const struct soc_enum rx_int0_dem_inp_mux_enum =
 984         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
 985                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 986                         rx_int_dem_inp_mux_text);
 987
 988 static const struct soc_enum rx_int1_dem_inp_mux_enum =
 989         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
 990                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 991                         rx_int_dem_inp_mux_text);
 992
 993 static const struct soc_enum rx_int2_dem_inp_mux_enum =
 994         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
 995                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 996                         rx_int_dem_inp_mux_text);
 997
 998 static const struct soc_enum tx_adc_mux0_enum =
 999         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1000                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1001 static const struct soc_enum tx_adc_mux1_enum =
1002         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1003                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1004 static const struct soc_enum tx_adc_mux2_enum =
1005         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1006                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1007 static const struct soc_enum tx_adc_mux3_enum =
1008         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1009                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1010 static const struct soc_enum tx_adc_mux4_enum =
1011         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1012                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1013 static const struct soc_enum tx_adc_mux5_enum =
1014         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1015                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1016 static const struct soc_enum tx_adc_mux6_enum =
1017         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1018                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1019 static const struct soc_enum tx_adc_mux7_enum =
1020         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1021                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1022 static const struct soc_enum tx_adc_mux8_enum =
1023         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1024                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1025
1026 static const struct soc_enum rx_int0_1_interp_mux_enum =
1027         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1028                         rx_int0_1_interp_mux_text);
1029
1030 static const struct soc_enum rx_int1_1_interp_mux_enum =
1031         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1032                         rx_int1_1_interp_mux_text);
1033
1034 static const struct soc_enum rx_int2_1_interp_mux_enum =
1035         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1036                         rx_int2_1_interp_mux_text);
1037
1038 static const struct soc_enum rx_int3_1_interp_mux_enum =
1039         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_1_interp_mux_text);
1040
1041 static const struct soc_enum rx_int4_1_interp_mux_enum =
1042         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_1_interp_mux_text);
1043
1044 static const struct soc_enum rx_int7_1_interp_mux_enum =
1045         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_1_interp_mux_text);
1046
1047 static const struct soc_enum rx_int8_1_interp_mux_enum =
1048         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_1_interp_mux_text);
1049
1050 static const struct soc_enum rx_int0_2_interp_mux_enum =
1051         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int0_2_interp_mux_text);
1052
1053 static const struct soc_enum rx_int1_2_interp_mux_enum =
1054         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int1_2_interp_mux_text);
1055
1056 static const struct soc_enum rx_int2_2_interp_mux_enum =
1057         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int2_2_interp_mux_text);
1058
1059 static const struct soc_enum rx_int3_2_interp_mux_enum =
1060         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_2_interp_mux_text);
1061
1062 static const struct soc_enum rx_int4_2_interp_mux_enum =
1063         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_2_interp_mux_text);
1064
1065 static const struct soc_enum rx_int7_2_interp_mux_enum =
1066         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_2_interp_mux_text);
1067
1068 static const struct soc_enum rx_int8_2_interp_mux_enum =
1069         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_2_interp_mux_text);
1070
1071 static const struct soc_enum tx_dmic_mux0_enum =
1072         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1073                         dmic_mux_text);
1074
1075 static const struct soc_enum tx_dmic_mux1_enum =
1076         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1077                         dmic_mux_text);
1078
1079 static const struct soc_enum tx_dmic_mux2_enum =
1080         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1081                         dmic_mux_text);
1082
1083 static const struct soc_enum tx_dmic_mux3_enum =
1084         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1085                         dmic_mux_text);
1086
1087 static const struct soc_enum tx_dmic_mux4_enum =
1088         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1089                         dmic_mux_text);
1090
1091 static const struct soc_enum tx_dmic_mux5_enum =
1092         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1093                         dmic_mux_text);
1094
1095 static const struct soc_enum tx_dmic_mux6_enum =
1096         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1097                         dmic_mux_text);
1098
1099 static const struct soc_enum tx_dmic_mux7_enum =
1100         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1101                         dmic_mux_text);
1102
1103 static const struct soc_enum tx_dmic_mux8_enum =
1104         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1105                         dmic_mux_text);
1106
1107 static const struct soc_enum tx_amic_mux0_enum =
1108         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1109                         amic_mux_text);
1110 static const struct soc_enum tx_amic_mux1_enum =
1111         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1112                         amic_mux_text);
1113 static const struct soc_enum tx_amic_mux2_enum =
1114         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1115                         amic_mux_text);
1116 static const struct soc_enum tx_amic_mux3_enum =
1117         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1118                         amic_mux_text);
1119 static const struct soc_enum tx_amic_mux4_enum =
1120         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1121                         amic_mux_text);
1122 static const struct soc_enum tx_amic_mux5_enum =
1123         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1124                         amic_mux_text);
1125 static const struct soc_enum tx_amic_mux6_enum =
1126         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1127                         amic_mux_text);
1128 static const struct soc_enum tx_amic_mux7_enum =
1129         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1130                         amic_mux_text);
1131 static const struct soc_enum tx_amic_mux8_enum =
1132         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1133                         amic_mux_text);
1134
1135 static const struct soc_enum tx_amic4_5_enum =
1136         SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1137
1138 static const struct soc_enum cdc_if_tx0_mux_enum =
1139         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1140                         ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1141 static const struct soc_enum cdc_if_tx1_mux_enum =
1142         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1143                         ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1144 static const struct soc_enum cdc_if_tx2_mux_enum =
1145         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1146                         ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1147 static const struct soc_enum cdc_if_tx3_mux_enum =
1148         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1149                         ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1150 static const struct soc_enum cdc_if_tx4_mux_enum =
1151         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1152                         ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1153 static const struct soc_enum cdc_if_tx5_mux_enum =
1154         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1155                         ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1156 static const struct soc_enum cdc_if_tx6_mux_enum =
1157         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1158                         ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1159 static const struct soc_enum cdc_if_tx7_mux_enum =
1160         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1161                         ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1162 static const struct soc_enum cdc_if_tx8_mux_enum =
1163         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1164                         ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1165 static const struct soc_enum cdc_if_tx9_mux_enum =
1166         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1167                         ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1168 static const struct soc_enum cdc_if_tx10_mux_enum =
1169         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1170                         ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1171 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1172         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1173                         ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1174                         cdc_if_tx11_inp1_mux_text);
1175 static const struct soc_enum cdc_if_tx11_mux_enum =
1176         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1177                         ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1178 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1179         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1180                         ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1181                         cdc_if_tx13_inp1_mux_text);
1182 static const struct soc_enum cdc_if_tx13_mux_enum =
1183         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1184                         ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1185
1186 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1187 {
1188         if (sido_src == wcd->sido_input_src)
1189                 return 0;
1190
1191         if (sido_src == SIDO_SOURCE_RCO_BG) {
1192                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1193                                    WCD934X_ANA_RCO_BG_EN_MASK,
1194                                    WCD934X_ANA_RCO_BG_ENABLE);
1195                 usleep_range(100, 110);
1196         }
1197         wcd->sido_input_src = sido_src;
1198
1199         return 0;
1200 }
1201
1202 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1203 {
1204         mutex_lock(&wcd->sysclk_mutex);
1205
1206         if (++wcd->sysclk_users != 1) {
1207                 mutex_unlock(&wcd->sysclk_mutex);
1208                 return 0;
1209         }
1210         mutex_unlock(&wcd->sysclk_mutex);
1211
1212         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1213                            WCD934X_ANA_BIAS_EN_MASK,
1214                            WCD934X_ANA_BIAS_EN);
1215         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1216                            WCD934X_ANA_PRECHRG_EN_MASK,
1217                            WCD934X_ANA_PRECHRG_EN);
1218         /*
1219          * 1ms delay is required after pre-charge is enabled
1220          * as per HW requirement
1221          */
1222         usleep_range(1000, 1100);
1223         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1224                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1225         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1226                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1227
1228         /*
1229          * In data clock contrl register is changed
1230          * to CLK_SYS_MCLK_PRG
1231          */
1232
1233         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1234                            WCD934X_EXT_CLK_BUF_EN_MASK,
1235                            WCD934X_EXT_CLK_BUF_EN);
1236         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1237                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
1238                            WCD934X_EXT_CLK_DIV_BY_2);
1239         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1240                            WCD934X_MCLK_SRC_MASK,
1241                            WCD934X_MCLK_SRC_EXT_CLK);
1242         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1243                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1244         regmap_update_bits(wcd->regmap,
1245                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1246                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1247                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1248         regmap_update_bits(wcd->regmap,
1249                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1250                            WCD934X_MCLK_EN_MASK,
1251                            WCD934X_MCLK_EN);
1252         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1253                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1254         /*
1255          * 10us sleep is required after clock is enabled
1256          * as per HW requirement
1257          */
1258         usleep_range(10, 15);
1259
1260         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1261
1262         return 0;
1263 }
1264
1265 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1266 {
1267         mutex_lock(&wcd->sysclk_mutex);
1268         if (--wcd->sysclk_users != 0) {
1269                 mutex_unlock(&wcd->sysclk_mutex);
1270                 return 0;
1271         }
1272         mutex_unlock(&wcd->sysclk_mutex);
1273
1274         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1275                            WCD934X_EXT_CLK_BUF_EN_MASK |
1276                            WCD934X_MCLK_EN_MASK, 0x0);
1277         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1278                            WCD934X_ANA_BIAS_EN_MASK, 0);
1279         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1280                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1281
1282         return 0;
1283 }
1284
1285 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1286 {
1287         int ret = 0;
1288
1289         if (enable) {
1290                 ret = clk_prepare_enable(wcd->extclk);
1291
1292                 if (ret) {
1293                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
1294                                 __func__);
1295                         return ret;
1296                 }
1297                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1298         } else {
1299                 int val;
1300
1301                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1302                             &val);
1303
1304                 /* Don't disable clock if soundwire using it.*/
1305                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1306                         return 0;
1307
1308                 wcd934x_disable_ana_bias_and_syclk(wcd);
1309                 clk_disable_unprepare(wcd->extclk);
1310         }
1311
1312         return ret;
1313 }
1314
1315 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1316                                      struct snd_kcontrol *kc, int event)
1317 {
1318         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1319         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1320
1321         switch (event) {
1322         case SND_SOC_DAPM_PRE_PMU:
1323                 return __wcd934x_cdc_mclk_enable(wcd, true);
1324         case SND_SOC_DAPM_POST_PMD:
1325                 return __wcd934x_cdc_mclk_enable(wcd, false);
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1332 {
1333         int val1, val2, ver, ret;
1334         struct regmap *regmap;
1335         u16 id_minor;
1336         u32 version_mask = 0;
1337
1338         regmap = wcd->regmap;
1339         ver = 0;
1340
1341         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1342                                (u8 *)&id_minor, sizeof(u16));
1343
1344         if (ret)
1345                 return ret;
1346
1347         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1348         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1349
1350         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1351         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1352
1353         switch (version_mask) {
1354         case DSD_DISABLED | SLNQ_DISABLED:
1355                 if (id_minor == 0)
1356                         ver = WCD_VERSION_WCD9340_1_0;
1357                 else if (id_minor == 0x01)
1358                         ver = WCD_VERSION_WCD9340_1_1;
1359                 break;
1360         case SLNQ_DISABLED:
1361                 if (id_minor == 0)
1362                         ver = WCD_VERSION_WCD9341_1_0;
1363                 else if (id_minor == 0x01)
1364                         ver = WCD_VERSION_WCD9341_1_1;
1365                 break;
1366         }
1367
1368         wcd->version = ver;
1369         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1370
1371         return 0;
1372 }
1373
1374 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1375 {
1376         int rc, val;
1377
1378         __wcd934x_cdc_mclk_enable(wcd, true);
1379
1380         regmap_update_bits(wcd->regmap,
1381                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1382                            WCD934X_EFUSE_SENSE_STATE_MASK,
1383                            WCD934X_EFUSE_SENSE_STATE_DEF);
1384         regmap_update_bits(wcd->regmap,
1385                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1386                            WCD934X_EFUSE_SENSE_EN_MASK,
1387                            WCD934X_EFUSE_SENSE_ENABLE);
1388         /*
1389          * 5ms sleep required after enabling efuse control
1390          * before checking the status.
1391          */
1392         usleep_range(5000, 5500);
1393         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1394
1395         rc = regmap_read(wcd->regmap,
1396                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1397         if (rc || (!(val & 0x01)))
1398                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1399                      __func__, val, rc);
1400
1401         __wcd934x_cdc_mclk_enable(wcd, false);
1402 }
1403
1404 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1405 {
1406         if (enable) {
1407                 __wcd934x_cdc_mclk_enable(wcd, true);
1408                 regmap_update_bits(wcd->regmap,
1409                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1410                                    WCD934X_CDC_SWR_CLK_EN_MASK,
1411                                    WCD934X_CDC_SWR_CLK_ENABLE);
1412         } else {
1413                 regmap_update_bits(wcd->regmap,
1414                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1415                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1416                 __wcd934x_cdc_mclk_enable(wcd, false);
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1423                                               u8 rate_val, u32 rate)
1424 {
1425         struct snd_soc_component *comp = dai->component;
1426         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1427         struct wcd934x_slim_ch *ch;
1428         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1429         int inp, j;
1430
1431         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1432                 inp = ch->shift + INTn_1_INP_SEL_RX0;
1433                 /*
1434                  * Loop through all interpolator MUX inputs and find out
1435                  * to which interpolator input, the slim rx port
1436                  * is connected
1437                  */
1438                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1439                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1440                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1441                                 continue;
1442
1443                         cfg0 = snd_soc_component_read(comp,
1444                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1445                         cfg1 = snd_soc_component_read(comp,
1446                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1447
1448                         inp0_sel = cfg0 &
1449                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1450                         inp1_sel = (cfg0 >> 4) &
1451                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1452                         inp2_sel = (cfg1 >> 4) &
1453                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1454
1455                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1456                             (inp2_sel == inp)) {
1457                                 /* rate is in Hz */
1458                                 /*
1459                                  * Ear and speaker primary path does not support
1460                                  * native sample rates
1461                                  */
1462                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1463                                      j == INTERP_SPKR2) && rate == 44100)
1464                                         dev_err(wcd->dev,
1465                                                 "Cannot set 44.1KHz on INT%d\n",
1466                                                 j);
1467                                 else
1468                                         snd_soc_component_update_bits(comp,
1469                                               WCD934X_CDC_RX_PATH_CTL(j),
1470                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1471                                               rate_val);
1472                         }
1473                 }
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1480                                              int rate_val, u32 rate)
1481 {
1482         struct snd_soc_component *component = dai->component;
1483         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1484         struct wcd934x_slim_ch *ch;
1485         int val, j;
1486
1487         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1488                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1489                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1490                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1491                                 continue;
1492                         val = snd_soc_component_read(component,
1493                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1494                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1495
1496                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1497                                 /*
1498                                  * Ear mix path supports only 48, 96, 192,
1499                                  * 384KHz only
1500                                  */
1501                                 if ((j == INTERP_EAR) &&
1502                                     (rate_val < 0x4 ||
1503                                      rate_val > 0x7)) {
1504                                         dev_err(component->dev,
1505                                                 "Invalid rate for AIF_PB DAI(%d)\n",
1506                                                 dai->id);
1507                                         return -EINVAL;
1508                                 }
1509
1510                                 snd_soc_component_update_bits(component,
1511                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
1512                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1513                                               rate_val);
1514                         }
1515                 }
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1522                                          u32 sample_rate)
1523 {
1524         int rate_val = 0;
1525         int i, ret;
1526
1527         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1528                 if (sample_rate == sr_val_tbl[i].sample_rate) {
1529                         rate_val = sr_val_tbl[i].rate_val;
1530                         break;
1531                 }
1532         }
1533         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1534                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1535                 return -EINVAL;
1536         }
1537
1538         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1539                                                  sample_rate);
1540         if (ret)
1541                 return ret;
1542         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1543                                                 sample_rate);
1544         if (ret)
1545                 return ret;
1546
1547         return ret;
1548 }
1549
1550 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1551                                       u8 rate_val, u32 rate)
1552 {
1553         struct snd_soc_component *comp = dai->component;
1554         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1555         u8 shift = 0, shift_val = 0, tx_mux_sel;
1556         struct wcd934x_slim_ch *ch;
1557         int tx_port, tx_port_reg;
1558         int decimator = -1;
1559
1560         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1561                 tx_port = ch->port;
1562                 /* Find the SB TX MUX input - which decimator is connected */
1563                 switch (tx_port) {
1564                 case 0 ...  3:
1565                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1566                         shift = (tx_port << 1);
1567                         shift_val = 0x03;
1568                         break;
1569                 case 4 ... 7:
1570                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1571                         shift = ((tx_port - 4) << 1);
1572                         shift_val = 0x03;
1573                         break;
1574                 case 8 ... 10:
1575                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1576                         shift = ((tx_port - 8) << 1);
1577                         shift_val = 0x03;
1578                         break;
1579                 case 11:
1580                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1581                         shift = 0;
1582                         shift_val = 0x0F;
1583                         break;
1584                 case 13:
1585                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1586                         shift = 4;
1587                         shift_val = 0x03;
1588                         break;
1589                 default:
1590                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1591                                 tx_port, dai->id);
1592                         return -EINVAL;
1593                 }
1594
1595                 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1596                                                       (shift_val << shift);
1597
1598                 tx_mux_sel = tx_mux_sel >> shift;
1599                 switch (tx_port) {
1600                 case 0 ... 8:
1601                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1602                                 decimator = tx_port;
1603                         break;
1604                 case 9 ... 10:
1605                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1606                                 decimator = ((tx_port == 9) ? 7 : 6);
1607                         break;
1608                 case 11:
1609                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1610                                 decimator = tx_mux_sel - 1;
1611                         break;
1612                 case 13:
1613                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1614                                 decimator = 5;
1615                         break;
1616                 default:
1617                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1618                                 tx_port);
1619                         return -EINVAL;
1620                 }
1621
1622                 snd_soc_component_update_bits(comp,
1623                                       WCD934X_CDC_TX_PATH_CTL(decimator),
1624                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1625                                       rate_val);
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1632                                       struct wcd_slim_codec_dai_data *dai_data,
1633                                       int direction)
1634 {
1635         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1636         struct slim_stream_config *cfg = &dai_data->sconfig;
1637         struct wcd934x_slim_ch *ch;
1638         u16 payload = 0;
1639         int ret, i;
1640
1641         cfg->ch_count = 0;
1642         cfg->direction = direction;
1643         cfg->port_mask = 0;
1644
1645         /* Configure slave interface device */
1646         list_for_each_entry(ch, slim_ch_list, list) {
1647                 cfg->ch_count++;
1648                 payload |= 1 << ch->shift;
1649                 cfg->port_mask |= BIT(ch->port);
1650         }
1651
1652         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1653         if (!cfg->chs)
1654                 return -ENOMEM;
1655
1656         i = 0;
1657         list_for_each_entry(ch, slim_ch_list, list) {
1658                 cfg->chs[i++] = ch->ch_num;
1659                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1660                         /* write to interface device */
1661                         ret = regmap_write(wcd->if_regmap,
1662                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1663                            payload);
1664
1665                         if (ret < 0)
1666                                 goto err;
1667
1668                         /* configure the slave port for water mark and enable*/
1669                         ret = regmap_write(wcd->if_regmap,
1670                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1671                                         WCD934X_SLIM_WATER_MARK_VAL);
1672                         if (ret < 0)
1673                                 goto err;
1674                 } else {
1675                         ret = regmap_write(wcd->if_regmap,
1676                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1677                                 payload & 0x00FF);
1678                         if (ret < 0)
1679                                 goto err;
1680
1681                         /* ports 8,9 */
1682                         ret = regmap_write(wcd->if_regmap,
1683                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1684                                 (payload & 0xFF00) >> 8);
1685                         if (ret < 0)
1686                                 goto err;
1687
1688                         /* configure the slave port for water mark and enable*/
1689                         ret = regmap_write(wcd->if_regmap,
1690                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1691                                         WCD934X_SLIM_WATER_MARK_VAL);
1692
1693                         if (ret < 0)
1694                                 goto err;
1695                 }
1696         }
1697
1698         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1699
1700         return 0;
1701
1702 err:
1703         dev_err(wcd->dev, "Error Setting slim hw params\n");
1704         kfree(cfg->chs);
1705         cfg->chs = NULL;
1706
1707         return ret;
1708 }
1709
1710 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1711                              struct snd_pcm_hw_params *params,
1712                              struct snd_soc_dai *dai)
1713 {
1714         struct wcd934x_codec *wcd;
1715         int ret, tx_fs_rate = 0;
1716
1717         wcd = snd_soc_component_get_drvdata(dai->component);
1718
1719         switch (substream->stream) {
1720         case SNDRV_PCM_STREAM_PLAYBACK:
1721                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1722                 if (ret) {
1723                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1724                                 params_rate(params));
1725                         return ret;
1726                 }
1727                 switch (params_width(params)) {
1728                 case 16 ... 24:
1729                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1730                         break;
1731                 default:
1732                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1733                                 params_width(params));
1734                         return -EINVAL;
1735                 }
1736                 break;
1737
1738         case SNDRV_PCM_STREAM_CAPTURE:
1739                 switch (params_rate(params)) {
1740                 case 8000:
1741                         tx_fs_rate = 0;
1742                         break;
1743                 case 16000:
1744                         tx_fs_rate = 1;
1745                         break;
1746                 case 32000:
1747                         tx_fs_rate = 3;
1748                         break;
1749                 case 48000:
1750                         tx_fs_rate = 4;
1751                         break;
1752                 case 96000:
1753                         tx_fs_rate = 5;
1754                         break;
1755                 case 192000:
1756                         tx_fs_rate = 6;
1757                         break;
1758                 case 384000:
1759                         tx_fs_rate = 7;
1760                         break;
1761                 default:
1762                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1763                                 params_rate(params));
1764                         return -EINVAL;
1765
1766                 }
1767
1768                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1769                                                  params_rate(params));
1770                 if (ret < 0) {
1771                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1772                         return ret;
1773                 }
1774                 switch (params_width(params)) {
1775                 case 16 ... 32:
1776                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1777                         break;
1778                 default:
1779                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1780                                 params_width(params));
1781                         return -EINVAL;
1782                 }
1783                 break;
1784         default:
1785                 dev_err(wcd->dev, "Invalid stream type %d\n",
1786                         substream->stream);
1787                 return -EINVAL;
1788         }
1789
1790         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1791
1792         return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1793 }
1794
1795 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1796                            struct snd_soc_dai *dai)
1797 {
1798         struct wcd_slim_codec_dai_data *dai_data;
1799         struct wcd934x_codec *wcd;
1800
1801         wcd = snd_soc_component_get_drvdata(dai->component);
1802
1803         dai_data = &wcd->dai[dai->id];
1804
1805         kfree(dai_data->sconfig.chs);
1806
1807         return 0;
1808 }
1809
1810 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1811                            struct snd_soc_dai *dai)
1812 {
1813         struct wcd_slim_codec_dai_data *dai_data;
1814         struct wcd934x_codec *wcd;
1815         struct slim_stream_config *cfg;
1816
1817         wcd = snd_soc_component_get_drvdata(dai->component);
1818
1819         dai_data = &wcd->dai[dai->id];
1820
1821         switch (cmd) {
1822         case SNDRV_PCM_TRIGGER_START:
1823         case SNDRV_PCM_TRIGGER_RESUME:
1824         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1825                 cfg = &dai_data->sconfig;
1826                 slim_stream_prepare(dai_data->sruntime, cfg);
1827                 slim_stream_enable(dai_data->sruntime);
1828                 break;
1829         case SNDRV_PCM_TRIGGER_STOP:
1830         case SNDRV_PCM_TRIGGER_SUSPEND:
1831         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1832                 slim_stream_disable(dai_data->sruntime);
1833                 slim_stream_unprepare(dai_data->sruntime);
1834                 break;
1835         default:
1836                 break;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1843                                    unsigned int tx_num, unsigned int *tx_slot,
1844                                    unsigned int rx_num, unsigned int *rx_slot)
1845 {
1846         struct wcd934x_codec *wcd;
1847         int i;
1848
1849         wcd = snd_soc_component_get_drvdata(dai->component);
1850
1851         if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1852                 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1853                         tx_num, rx_num);
1854                 return -EINVAL;
1855         }
1856
1857         if (!tx_slot || !rx_slot) {
1858                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1859                         tx_slot, rx_slot);
1860                 return -EINVAL;
1861         }
1862
1863         wcd->num_rx_port = rx_num;
1864         for (i = 0; i < rx_num; i++) {
1865                 wcd->rx_chs[i].ch_num = rx_slot[i];
1866                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1867         }
1868
1869         wcd->num_tx_port = tx_num;
1870         for (i = 0; i < tx_num; i++) {
1871                 wcd->tx_chs[i].ch_num = tx_slot[i];
1872                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1873         }
1874
1875         return 0;
1876 }
1877
1878 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1879                                    unsigned int *tx_num, unsigned int *tx_slot,
1880                                    unsigned int *rx_num, unsigned int *rx_slot)
1881 {
1882         struct wcd934x_slim_ch *ch;
1883         struct wcd934x_codec *wcd;
1884         int i = 0;
1885
1886         wcd = snd_soc_component_get_drvdata(dai->component);
1887
1888         switch (dai->id) {
1889         case AIF1_PB:
1890         case AIF2_PB:
1891         case AIF3_PB:
1892         case AIF4_PB:
1893                 if (!rx_slot || !rx_num) {
1894                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1895                                 rx_slot, rx_num);
1896                         return -EINVAL;
1897                 }
1898
1899                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1900                         rx_slot[i++] = ch->ch_num;
1901
1902                 *rx_num = i;
1903                 break;
1904         case AIF1_CAP:
1905         case AIF2_CAP:
1906         case AIF3_CAP:
1907                 if (!tx_slot || !tx_num) {
1908                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1909                                 tx_slot, tx_num);
1910                         return -EINVAL;
1911                 }
1912
1913                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1914                         tx_slot[i++] = ch->ch_num;
1915
1916                 *tx_num = i;
1917                 break;
1918         default:
1919                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1920                 break;
1921         }
1922
1923         return 0;
1924 }
1925
1926 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1927         .hw_params = wcd934x_hw_params,
1928         .hw_free = wcd934x_hw_free,
1929         .trigger = wcd934x_trigger,
1930         .set_channel_map = wcd934x_set_channel_map,
1931         .get_channel_map = wcd934x_get_channel_map,
1932 };
1933
1934 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1935         [0] = {
1936                 .name = "wcd934x_rx1",
1937                 .id = AIF1_PB,
1938                 .playback = {
1939                         .stream_name = "AIF1 Playback",
1940                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1941                         .formats = WCD934X_FORMATS_S16_S24_LE,
1942                         .rate_max = 192000,
1943                         .rate_min = 8000,
1944                         .channels_min = 1,
1945                         .channels_max = 2,
1946                 },
1947                 .ops = &wcd934x_dai_ops,
1948         },
1949         [1] = {
1950                 .name = "wcd934x_tx1",
1951                 .id = AIF1_CAP,
1952                 .capture = {
1953                         .stream_name = "AIF1 Capture",
1954                         .rates = WCD934X_RATES_MASK,
1955                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1956                         .rate_min = 8000,
1957                         .rate_max = 192000,
1958                         .channels_min = 1,
1959                         .channels_max = 4,
1960                 },
1961                 .ops = &wcd934x_dai_ops,
1962         },
1963         [2] = {
1964                 .name = "wcd934x_rx2",
1965                 .id = AIF2_PB,
1966                 .playback = {
1967                         .stream_name = "AIF2 Playback",
1968                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1969                         .formats = WCD934X_FORMATS_S16_S24_LE,
1970                         .rate_min = 8000,
1971                         .rate_max = 192000,
1972                         .channels_min = 1,
1973                         .channels_max = 2,
1974                 },
1975                 .ops = &wcd934x_dai_ops,
1976         },
1977         [3] = {
1978                 .name = "wcd934x_tx2",
1979                 .id = AIF2_CAP,
1980                 .capture = {
1981                         .stream_name = "AIF2 Capture",
1982                         .rates = WCD934X_RATES_MASK,
1983                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1984                         .rate_min = 8000,
1985                         .rate_max = 192000,
1986                         .channels_min = 1,
1987                         .channels_max = 4,
1988                 },
1989                 .ops = &wcd934x_dai_ops,
1990         },
1991         [4] = {
1992                 .name = "wcd934x_rx3",
1993                 .id = AIF3_PB,
1994                 .playback = {
1995                         .stream_name = "AIF3 Playback",
1996                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1997                         .formats = WCD934X_FORMATS_S16_S24_LE,
1998                         .rate_min = 8000,
1999                         .rate_max = 192000,
2000                         .channels_min = 1,
2001                         .channels_max = 2,
2002                 },
2003                 .ops = &wcd934x_dai_ops,
2004         },
2005         [5] = {
2006                 .name = "wcd934x_tx3",
2007                 .id = AIF3_CAP,
2008                 .capture = {
2009                         .stream_name = "AIF3 Capture",
2010                         .rates = WCD934X_RATES_MASK,
2011                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2012                         .rate_min = 8000,
2013                         .rate_max = 192000,
2014                         .channels_min = 1,
2015                         .channels_max = 4,
2016                 },
2017                 .ops = &wcd934x_dai_ops,
2018         },
2019         [6] = {
2020                 .name = "wcd934x_rx4",
2021                 .id = AIF4_PB,
2022                 .playback = {
2023                         .stream_name = "AIF4 Playback",
2024                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2025                         .formats = WCD934X_FORMATS_S16_S24_LE,
2026                         .rate_min = 8000,
2027                         .rate_max = 192000,
2028                         .channels_min = 1,
2029                         .channels_max = 2,
2030                 },
2031                 .ops = &wcd934x_dai_ops,
2032         },
2033 };
2034
2035 static int swclk_gate_enable(struct clk_hw *hw)
2036 {
2037         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2038 }
2039
2040 static void swclk_gate_disable(struct clk_hw *hw)
2041 {
2042         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2043 }
2044
2045 static int swclk_gate_is_enabled(struct clk_hw *hw)
2046 {
2047         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2048         int ret, val;
2049
2050         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2051         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2052
2053         return ret;
2054 }
2055
2056 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2057                                        unsigned long parent_rate)
2058 {
2059         return parent_rate / 2;
2060 }
2061
2062 static const struct clk_ops swclk_gate_ops = {
2063         .prepare = swclk_gate_enable,
2064         .unprepare = swclk_gate_disable,
2065         .is_enabled = swclk_gate_is_enabled,
2066         .recalc_rate = swclk_recalc_rate,
2067
2068 };
2069
2070 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2071 {
2072         struct clk *parent = wcd->extclk;
2073         struct device *dev = wcd->dev;
2074         struct device_node *np = dev->parent->of_node;
2075         const char *parent_clk_name = NULL;
2076         const char *clk_name = "mclk";
2077         struct clk_hw *hw;
2078         struct clk_init_data init;
2079         int ret;
2080
2081         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2082                 return NULL;
2083
2084         parent_clk_name = __clk_get_name(parent);
2085
2086         of_property_read_string(np, "clock-output-names", &clk_name);
2087
2088         init.name = clk_name;
2089         init.ops = &swclk_gate_ops;
2090         init.flags = 0;
2091         init.parent_names = &parent_clk_name;
2092         init.num_parents = 1;
2093         wcd->hw.init = &init;
2094
2095         hw = &wcd->hw;
2096         ret = clk_hw_register(wcd->dev->parent, hw);
2097         if (ret)
2098                 return ERR_PTR(ret);
2099
2100         of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
2101
2102         return NULL;
2103 }
2104
2105 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
2106 {
2107         int mv;
2108
2109         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2110                 dev_err(dev, "%s value not found, using default\n", micbias);
2111                 mv = WCD934X_DEF_MICBIAS_MV;
2112         } else {
2113                 /* convert it to milli volts */
2114                 mv = mv/1000;
2115         }
2116
2117         if (mv < 1000 || mv > 2850) {
2118                 dev_err(dev, "%s value not in valid range, using default\n",
2119                         micbias);
2120                 mv = WCD934X_DEF_MICBIAS_MV;
2121         }
2122
2123         return (mv - 1000) / 50;
2124 }
2125
2126 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2127 {
2128         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2129         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2130         u32 def_dmic_rate, dmic_clk_drv;
2131
2132         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2133                                              "qcom,micbias1-microvolt");
2134         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2135                                              "qcom,micbias2-microvolt");
2136         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2137                                              "qcom,micbias3-microvolt");
2138         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2139                                              "qcom,micbias4-microvolt");
2140
2141         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2142                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
2143         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2144                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
2145         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2146                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
2147         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2148                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
2149
2150         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2151                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2152         else
2153                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2154
2155         wcd->dmic_sample_rate = def_dmic_rate;
2156
2157         dmic_clk_drv = 0;
2158         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2159                                       0x0C, dmic_clk_drv << 2);
2160
2161         return 0;
2162 }
2163
2164 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2165 {
2166         struct regmap *rm = wcd->regmap;
2167
2168         /* set SPKR rate to FS_2P4_3P072 */
2169         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2170         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2171
2172         /* Take DMICs out of reset */
2173         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2174 }
2175
2176 static int wcd934x_comp_init(struct snd_soc_component *component)
2177 {
2178         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2179
2180         wcd934x_hw_init(wcd);
2181         wcd934x_enable_efuse_sensing(wcd);
2182         wcd934x_get_version(wcd);
2183
2184         return 0;
2185 }
2186
2187 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2188 {
2189         struct wcd934x_codec *wcd = data;
2190         unsigned long status = 0;
2191         int i, j, port_id;
2192         unsigned int val, int_val = 0;
2193         irqreturn_t ret = IRQ_NONE;
2194         bool tx;
2195         unsigned short reg = 0;
2196
2197         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2198              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2199                 regmap_read(wcd->if_regmap, i, &val);
2200                 status |= ((u32)val << (8 * j));
2201         }
2202
2203         for_each_set_bit(j, &status, 32) {
2204                 tx = false;
2205                 port_id = j;
2206
2207                 if (j >= 16) {
2208                         tx = true;
2209                         port_id = j - 16;
2210                 }
2211
2212                 regmap_read(wcd->if_regmap,
2213                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2214                 if (val) {
2215                         if (!tx)
2216                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2217                                         (port_id / 8);
2218                         else
2219                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2220                                         (port_id / 8);
2221                         regmap_read(wcd->if_regmap, reg, &int_val);
2222                 }
2223
2224                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2225                         dev_err_ratelimited(wcd->dev,
2226                                             "overflow error on %s port %d, value %x\n",
2227                                             (tx ? "TX" : "RX"), port_id, val);
2228
2229                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2230                         dev_err_ratelimited(wcd->dev,
2231                                             "underflow error on %s port %d, value %x\n",
2232                                             (tx ? "TX" : "RX"), port_id, val);
2233
2234                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2235                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2236                         if (!tx)
2237                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2238                                         (port_id / 8);
2239                         else
2240                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2241                                         (port_id / 8);
2242                         regmap_read(
2243                                 wcd->if_regmap, reg, &int_val);
2244                         if (int_val & (1 << (port_id % 8))) {
2245                                 int_val = int_val ^ (1 << (port_id % 8));
2246                                 regmap_write(wcd->if_regmap,
2247                                              reg, int_val);
2248                         }
2249                 }
2250
2251                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2252                         dev_err_ratelimited(wcd->dev,
2253                                             "Port Closed %s port %d, value %x\n",
2254                                             (tx ? "TX" : "RX"), port_id, val);
2255
2256                 regmap_write(wcd->if_regmap,
2257                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2258                                 BIT(j % 8));
2259                 ret = IRQ_HANDLED;
2260         }
2261
2262         return ret;
2263 }
2264
2265 static int wcd934x_comp_probe(struct snd_soc_component *component)
2266 {
2267         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2268         int i;
2269
2270         snd_soc_component_init_regmap(component, wcd->regmap);
2271         wcd->component = component;
2272
2273         /* Class-H Init*/
2274         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
2275         if (IS_ERR(wcd->clsh_ctrl))
2276                 return PTR_ERR(wcd->clsh_ctrl);
2277
2278         /* Default HPH Mode to Class-H Low HiFi */
2279         wcd->hph_mode = CLS_H_LOHIFI;
2280
2281         wcd934x_comp_init(component);
2282
2283         for (i = 0; i < NUM_CODEC_DAIS; i++)
2284                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
2285
2286         wcd934x_init_dmic(component);
2287         return 0;
2288 }
2289
2290 static void wcd934x_comp_remove(struct snd_soc_component *comp)
2291 {
2292         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2293
2294         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
2295 }
2296
2297 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
2298                                    int clk_id, int source,
2299                                    unsigned int freq, int dir)
2300 {
2301         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2302         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
2303
2304         wcd->rate = freq;
2305
2306         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
2307                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
2308
2309         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2310                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2311                                       val);
2312
2313         return clk_set_rate(wcd->extclk, freq);
2314 }
2315
2316 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2317                                    int iir_idx, int band_idx, int coeff_idx)
2318 {
2319         u32 value = 0;
2320         int reg, b2_reg;
2321
2322         /* Address does not automatically update if reading */
2323         reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2324         b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2325
2326         snd_soc_component_write(component, reg,
2327                                 ((band_idx * BAND_MAX + coeff_idx) *
2328                                  sizeof(uint32_t)) & 0x7F);
2329
2330         value |= snd_soc_component_read(component, b2_reg);
2331         snd_soc_component_write(component, reg,
2332                                 ((band_idx * BAND_MAX + coeff_idx)
2333                                  * sizeof(uint32_t) + 1) & 0x7F);
2334
2335         value |= (snd_soc_component_read(component, b2_reg) << 8);
2336         snd_soc_component_write(component, reg,
2337                                 ((band_idx * BAND_MAX + coeff_idx)
2338                                  * sizeof(uint32_t) + 2) & 0x7F);
2339
2340         value |= (snd_soc_component_read(component, b2_reg) << 16);
2341         snd_soc_component_write(component, reg,
2342                 ((band_idx * BAND_MAX + coeff_idx)
2343                 * sizeof(uint32_t) + 3) & 0x7F);
2344
2345         /* Mask bits top 2 bits since they are reserved */
2346         value |= (snd_soc_component_read(component, b2_reg) << 24);
2347         return value;
2348 }
2349
2350 static void set_iir_band_coeff(struct snd_soc_component *component,
2351                                int iir_idx, int band_idx, uint32_t value)
2352 {
2353         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2354
2355         snd_soc_component_write(component, reg, (value & 0xFF));
2356         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2357         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2358         /* Mask top 2 bits, 7-8 are reserved */
2359         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2360 }
2361
2362 static int wcd934x_put_iir_band_audio_mixer(
2363                                         struct snd_kcontrol *kcontrol,
2364                                         struct snd_ctl_elem_value *ucontrol)
2365 {
2366         struct snd_soc_component *component =
2367                         snd_soc_kcontrol_component(kcontrol);
2368         struct wcd_iir_filter_ctl *ctl =
2369                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2370         struct soc_bytes_ext *params = &ctl->bytes_ext;
2371         int iir_idx = ctl->iir_idx;
2372         int band_idx = ctl->band_idx;
2373         u32 coeff[BAND_MAX];
2374         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2375
2376         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2377
2378         /* Mask top bit it is reserved */
2379         /* Updates addr automatically for each B2 write */
2380         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2381                                                  sizeof(uint32_t)) & 0x7F);
2382
2383         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2384         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2385         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2386         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2387         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2388
2389         return 0;
2390 }
2391
2392 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2393                                     struct snd_ctl_elem_value *ucontrol)
2394 {
2395         struct snd_soc_component *component =
2396                         snd_soc_kcontrol_component(kcontrol);
2397         struct wcd_iir_filter_ctl *ctl =
2398                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2399         struct soc_bytes_ext *params = &ctl->bytes_ext;
2400         int iir_idx = ctl->iir_idx;
2401         int band_idx = ctl->band_idx;
2402         u32 coeff[BAND_MAX];
2403
2404         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2405         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2406         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2407         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2408         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2409
2410         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2411
2412         return 0;
2413 }
2414
2415 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
2416                                    struct snd_ctl_elem_info *ucontrol)
2417 {
2418         struct wcd_iir_filter_ctl *ctl =
2419                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2420         struct soc_bytes_ext *params = &ctl->bytes_ext;
2421
2422         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2423         ucontrol->count = params->max;
2424
2425         return 0;
2426 }
2427
2428 static int wcd934x_compander_get(struct snd_kcontrol *kc,
2429                                  struct snd_ctl_elem_value *ucontrol)
2430 {
2431         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2432         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2433         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2434
2435         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2436
2437         return 0;
2438 }
2439
2440 static int wcd934x_compander_set(struct snd_kcontrol *kc,
2441                                  struct snd_ctl_elem_value *ucontrol)
2442 {
2443         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2444         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2445         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2446         int value = ucontrol->value.integer.value[0];
2447         int sel;
2448
2449         if (wcd->comp_enabled[comp] == value)
2450                 return 0;
2451
2452         wcd->comp_enabled[comp] = value;
2453         sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
2454                 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
2455
2456         /* Any specific register configuration for compander */
2457         switch (comp) {
2458         case COMPANDER_1:
2459                 /* Set Gain Source Select based on compander enable/disable */
2460                 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
2461                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
2462                                               sel);
2463                 break;
2464         case COMPANDER_2:
2465                 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
2466                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
2467                                               sel);
2468                 break;
2469         case COMPANDER_3:
2470         case COMPANDER_4:
2471         case COMPANDER_7:
2472         case COMPANDER_8:
2473                 break;
2474         default:
2475                 return 0;
2476         }
2477
2478         return 1;
2479 }
2480
2481 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
2482                                    struct snd_ctl_elem_value *ucontrol)
2483 {
2484         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2485         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2486
2487         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2488
2489         return 0;
2490 }
2491
2492 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
2493                                    struct snd_ctl_elem_value *ucontrol)
2494 {
2495         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2496         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2497         u32 mode_val;
2498
2499         mode_val = ucontrol->value.enumerated.item[0];
2500
2501         if (mode_val == wcd->hph_mode)
2502                 return 0;
2503
2504         if (mode_val == 0) {
2505                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2506                 mode_val = CLS_H_LOHIFI;
2507         }
2508         wcd->hph_mode = mode_val;
2509
2510         return 1;
2511 }
2512
2513 static int slim_rx_mux_get(struct snd_kcontrol *kc,
2514                            struct snd_ctl_elem_value *ucontrol)
2515 {
2516         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
2517         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2518         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
2519
2520         ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
2521
2522         return 0;
2523 }
2524
2525 static int slim_rx_mux_to_dai_id(int mux)
2526 {
2527         int aif_id;
2528
2529         switch (mux) {
2530         case 1:
2531                 aif_id = AIF1_PB;
2532                 break;
2533         case 2:
2534                 aif_id = AIF2_PB;
2535                 break;
2536         case 3:
2537                 aif_id = AIF3_PB;
2538                 break;
2539         case 4:
2540                 aif_id = AIF4_PB;
2541                 break;
2542         default:
2543                 aif_id = -1;
2544                 break;
2545         }
2546
2547         return aif_id;
2548 }
2549
2550 static int slim_rx_mux_put(struct snd_kcontrol *kc,
2551                            struct snd_ctl_elem_value *ucontrol)
2552 {
2553         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2554         struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
2555         struct soc_enum *e = (struct soc_enum *)kc->private_value;
2556         struct snd_soc_dapm_update *update = NULL;
2557         struct wcd934x_slim_ch *ch, *c;
2558         u32 port_id = w->shift;
2559         bool found = false;
2560         int mux_idx;
2561         int prev_mux_idx = wcd->rx_port_value[port_id];
2562         int aif_id;
2563
2564         mux_idx = ucontrol->value.enumerated.item[0];
2565
2566         if (mux_idx == prev_mux_idx)
2567                 return 0;
2568
2569         switch(mux_idx) {
2570         case 0:
2571                 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
2572                 if (aif_id < 0)
2573                         return 0;
2574
2575                 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
2576                         if (ch->port == port_id + WCD934X_RX_START) {
2577                                 found = true;
2578                                 list_del_init(&ch->list);
2579                                 break;
2580                         }
2581                 }
2582                 if (!found)
2583                         return 0;
2584
2585                 break;
2586         case 1 ... 4:
2587                 aif_id = slim_rx_mux_to_dai_id(mux_idx);
2588                 if (aif_id < 0)
2589                         return 0;
2590
2591                 if (list_empty(&wcd->rx_chs[port_id].list)) {
2592                         list_add_tail(&wcd->rx_chs[port_id].list,
2593                                       &wcd->dai[aif_id].slim_ch_list);
2594                 } else {
2595                         dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
2596                         return 0;
2597                 }
2598                 break;
2599
2600         default:
2601                 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
2602                 goto err;
2603         }
2604
2605         wcd->rx_port_value[port_id] = mux_idx;
2606         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
2607                                       e, update);
2608
2609         return 1;
2610 err:
2611         return -EINVAL;
2612 }
2613
2614 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
2615                                        struct snd_ctl_elem_value *ucontrol)
2616 {
2617         struct soc_enum *e = (struct soc_enum *)kc->private_value;
2618         struct snd_soc_component *component;
2619         int reg, val, ret;
2620
2621         component = snd_soc_dapm_kcontrol_component(kc);
2622         val = ucontrol->value.enumerated.item[0];
2623         if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
2624                 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
2625         else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
2626                 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
2627         else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
2628                 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
2629         else
2630                 return -EINVAL;
2631
2632         /* Set Look Ahead Delay */
2633         if (val)
2634                 snd_soc_component_update_bits(component, reg,
2635                                               WCD934X_RX_DLY_ZN_EN_MASK,
2636                                               WCD934X_RX_DLY_ZN_ENABLE);
2637         else
2638                 snd_soc_component_update_bits(component, reg,
2639                                               WCD934X_RX_DLY_ZN_EN_MASK,
2640                                               WCD934X_RX_DLY_ZN_DISABLE);
2641
2642         ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
2643
2644         return ret;
2645 }
2646
2647 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
2648                                 struct snd_ctl_elem_value *ucontrol)
2649 {
2650         struct snd_soc_component *comp;
2651         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2652         unsigned int val;
2653         u16 mic_sel_reg = 0;
2654         u8 mic_sel;
2655
2656         comp = snd_soc_dapm_kcontrol_component(kcontrol);
2657
2658         val = ucontrol->value.enumerated.item[0];
2659         if (val > e->items - 1)
2660                 return -EINVAL;
2661
2662         switch (e->reg) {
2663         case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
2664                 if (e->shift_l == 0)
2665                         mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
2666                 else if (e->shift_l == 2)
2667                         mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
2668                 else if (e->shift_l == 4)
2669                         mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
2670                 break;
2671         case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
2672                 if (e->shift_l == 0)
2673                         mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
2674                 else if (e->shift_l == 2)
2675                         mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
2676                 break;
2677         case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
2678                 if (e->shift_l == 0)
2679                         mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
2680                 else if (e->shift_l == 2)
2681                         mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
2682                 break;
2683         case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
2684                 if (e->shift_l == 0)
2685                         mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
2686                 else if (e->shift_l == 2)
2687                         mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
2688                 break;
2689         default:
2690                 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
2691                         __func__, e->reg);
2692                 return -EINVAL;
2693         }
2694
2695         /* ADC: 0, DMIC: 1 */
2696         mic_sel = val ? 0x0 : 0x1;
2697         if (mic_sel_reg)
2698                 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
2699                                               mic_sel << 7);
2700
2701         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2702 }
2703
2704 static const struct snd_kcontrol_new rx_int0_2_mux =
2705         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
2706
2707 static const struct snd_kcontrol_new rx_int1_2_mux =
2708         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
2709
2710 static const struct snd_kcontrol_new rx_int2_2_mux =
2711         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
2712
2713 static const struct snd_kcontrol_new rx_int3_2_mux =
2714         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
2715
2716 static const struct snd_kcontrol_new rx_int4_2_mux =
2717         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
2718
2719 static const struct snd_kcontrol_new rx_int7_2_mux =
2720         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
2721
2722 static const struct snd_kcontrol_new rx_int8_2_mux =
2723         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
2724
2725 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
2726         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
2727
2728 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
2729         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
2730
2731 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
2732         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
2733
2734 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
2735         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
2736
2737 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
2738         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
2739
2740 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
2741         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
2742
2743 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
2744         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
2745
2746 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
2747         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
2748
2749 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
2750         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
2751
2752 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
2753         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
2754
2755 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
2756         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
2757
2758 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
2759         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
2760
2761 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
2762         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
2763
2764 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
2765         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
2766
2767 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
2768         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
2769
2770 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
2771         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
2772
2773 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
2774         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
2775
2776 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
2777         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
2778
2779 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
2780         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
2781
2782 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
2783         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
2784
2785 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
2786         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
2787
2788 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
2789         SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
2790
2791 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
2792         SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
2793
2794 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
2795         SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
2796
2797 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
2798         SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
2799
2800 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
2801         SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
2802
2803 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
2804         SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
2805
2806 static const struct snd_kcontrol_new iir0_inp0_mux =
2807         SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
2808 static const struct snd_kcontrol_new iir0_inp1_mux =
2809         SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
2810 static const struct snd_kcontrol_new iir0_inp2_mux =
2811         SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
2812 static const struct snd_kcontrol_new iir0_inp3_mux =
2813         SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
2814
2815 static const struct snd_kcontrol_new iir1_inp0_mux =
2816         SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2817 static const struct snd_kcontrol_new iir1_inp1_mux =
2818         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2819 static const struct snd_kcontrol_new iir1_inp2_mux =
2820         SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2821 static const struct snd_kcontrol_new iir1_inp3_mux =
2822         SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
2823
2824 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
2825         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2826                           slim_rx_mux_get, slim_rx_mux_put),
2827         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2828                           slim_rx_mux_get, slim_rx_mux_put),
2829         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2830                           slim_rx_mux_get, slim_rx_mux_put),
2831         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2832                           slim_rx_mux_get, slim_rx_mux_put),
2833         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2834                           slim_rx_mux_get, slim_rx_mux_put),
2835         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2836                           slim_rx_mux_get, slim_rx_mux_put),
2837         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2838                           slim_rx_mux_get, slim_rx_mux_put),
2839         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2840                           slim_rx_mux_get, slim_rx_mux_put),
2841 };
2842
2843 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
2844         SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
2845 };
2846
2847 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
2848         SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
2849 };
2850
2851 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
2852         SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
2853 };
2854
2855 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
2856         SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
2857 };
2858
2859 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
2860         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
2861                           snd_soc_dapm_get_enum_double,
2862                           wcd934x_int_dem_inp_mux_put);
2863
2864 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
2865         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
2866                           snd_soc_dapm_get_enum_double,
2867                           wcd934x_int_dem_inp_mux_put);
2868
2869 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
2870         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
2871                           snd_soc_dapm_get_enum_double,
2872                           wcd934x_int_dem_inp_mux_put);
2873
2874 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
2875         SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
2876
2877 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
2878         SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
2879
2880 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
2881         SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
2882
2883 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
2884         SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
2885
2886 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
2887         SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
2888
2889 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
2890         SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
2891
2892 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
2893         SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
2894
2895 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
2896         SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
2897
2898 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
2899         SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
2900
2901 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
2902         SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
2903
2904 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
2905         SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
2906
2907 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
2908         SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
2909
2910 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
2911         SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
2912
2913 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
2914         SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
2915
2916 static const struct snd_kcontrol_new tx_dmic_mux0 =
2917         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
2918
2919 static const struct snd_kcontrol_new tx_dmic_mux1 =
2920         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
2921
2922 static const struct snd_kcontrol_new tx_dmic_mux2 =
2923         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
2924
2925 static const struct snd_kcontrol_new tx_dmic_mux3 =
2926         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
2927
2928 static const struct snd_kcontrol_new tx_dmic_mux4 =
2929         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
2930
2931 static const struct snd_kcontrol_new tx_dmic_mux5 =
2932         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
2933
2934 static const struct snd_kcontrol_new tx_dmic_mux6 =
2935         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
2936
2937 static const struct snd_kcontrol_new tx_dmic_mux7 =
2938         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
2939
2940 static const struct snd_kcontrol_new tx_dmic_mux8 =
2941         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
2942
2943 static const struct snd_kcontrol_new tx_amic_mux0 =
2944         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
2945
2946 static const struct snd_kcontrol_new tx_amic_mux1 =
2947         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
2948
2949 static const struct snd_kcontrol_new tx_amic_mux2 =
2950         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
2951
2952 static const struct snd_kcontrol_new tx_amic_mux3 =
2953         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
2954
2955 static const struct snd_kcontrol_new tx_amic_mux4 =
2956         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
2957
2958 static const struct snd_kcontrol_new tx_amic_mux5 =
2959         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
2960
2961 static const struct snd_kcontrol_new tx_amic_mux6 =
2962         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
2963
2964 static const struct snd_kcontrol_new tx_amic_mux7 =
2965         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
2966
2967 static const struct snd_kcontrol_new tx_amic_mux8 =
2968         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
2969
2970 static const struct snd_kcontrol_new tx_amic4_5 =
2971         SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
2972
2973 static const struct snd_kcontrol_new tx_adc_mux0_mux =
2974         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
2975                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2976 static const struct snd_kcontrol_new tx_adc_mux1_mux =
2977         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
2978                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2979 static const struct snd_kcontrol_new tx_adc_mux2_mux =
2980         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
2981                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2982 static const struct snd_kcontrol_new tx_adc_mux3_mux =
2983         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
2984                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2985 static const struct snd_kcontrol_new tx_adc_mux4_mux =
2986         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
2987                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2988 static const struct snd_kcontrol_new tx_adc_mux5_mux =
2989         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
2990                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2991 static const struct snd_kcontrol_new tx_adc_mux6_mux =
2992         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
2993                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2994 static const struct snd_kcontrol_new tx_adc_mux7_mux =
2995         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
2996                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2997 static const struct snd_kcontrol_new tx_adc_mux8_mux =
2998         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
2999                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3000
3001 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3002         SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3003 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3004         SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3005 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3006         SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3007 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3008         SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3009 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3010         SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3011 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3012         SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3013 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3014         SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3015 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3016         SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3017 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3018         SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3019 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3020         SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3021 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3022         SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3023 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3024         SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3025 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3026         SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3027 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3028         SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3029 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3030         SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3031
3032 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3033                              struct snd_ctl_elem_value *ucontrol)
3034 {
3035         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3036         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3037         struct soc_mixer_control *mixer =
3038                         (struct soc_mixer_control *)kc->private_value;
3039         int port_id = mixer->shift;
3040
3041         ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3042
3043         return 0;
3044 }
3045
3046 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3047                              struct snd_ctl_elem_value *ucontrol)
3048 {
3049         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3050         struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3051         struct snd_soc_dapm_update *update = NULL;
3052         struct soc_mixer_control *mixer =
3053                         (struct soc_mixer_control *)kc->private_value;
3054         int enable = ucontrol->value.integer.value[0];
3055         struct wcd934x_slim_ch *ch, *c;
3056         int dai_id = widget->shift;
3057         int port_id = mixer->shift;
3058
3059         /* only add to the list if value not set */
3060         if (enable == wcd->tx_port_value[port_id])
3061                 return 0;
3062
3063         if (enable) {
3064                 if (list_empty(&wcd->tx_chs[port_id].list)) {
3065                         list_add_tail(&wcd->tx_chs[port_id].list,
3066                                       &wcd->dai[dai_id].slim_ch_list);
3067                 } else {
3068                         dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3069                         return 0;
3070                 }
3071          } else {
3072                 bool found = false;
3073
3074                 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3075                         if (ch->port == port_id) {
3076                                 found = true;
3077                                 list_del_init(&wcd->tx_chs[port_id].list);
3078                                 break;
3079                         }
3080                 }
3081                 if (!found)
3082                         return 0;
3083          }
3084
3085         wcd->tx_port_value[port_id] = enable;
3086         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3087
3088         return 1;
3089 }
3090
3091 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3092         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3093                        slim_tx_mixer_get, slim_tx_mixer_put),
3094         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3095                        slim_tx_mixer_get, slim_tx_mixer_put),
3096         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3097                        slim_tx_mixer_get, slim_tx_mixer_put),
3098         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3099                        slim_tx_mixer_get, slim_tx_mixer_put),
3100         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3101                        slim_tx_mixer_get, slim_tx_mixer_put),
3102         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3103                        slim_tx_mixer_get, slim_tx_mixer_put),
3104         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3105                        slim_tx_mixer_get, slim_tx_mixer_put),
3106         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3107                        slim_tx_mixer_get, slim_tx_mixer_put),
3108         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3109                        slim_tx_mixer_get, slim_tx_mixer_put),
3110         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3111                        slim_tx_mixer_get, slim_tx_mixer_put),
3112         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3113                        slim_tx_mixer_get, slim_tx_mixer_put),
3114         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3115                        slim_tx_mixer_get, slim_tx_mixer_put),
3116         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3117                        slim_tx_mixer_get, slim_tx_mixer_put),
3118 };
3119
3120 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3121         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3122                        slim_tx_mixer_get, slim_tx_mixer_put),
3123         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3124                        slim_tx_mixer_get, slim_tx_mixer_put),
3125         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3126                        slim_tx_mixer_get, slim_tx_mixer_put),
3127         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3128                        slim_tx_mixer_get, slim_tx_mixer_put),
3129         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3130                        slim_tx_mixer_get, slim_tx_mixer_put),
3131         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3132                        slim_tx_mixer_get, slim_tx_mixer_put),
3133         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3134                        slim_tx_mixer_get, slim_tx_mixer_put),
3135         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3136                        slim_tx_mixer_get, slim_tx_mixer_put),
3137         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3138                        slim_tx_mixer_get, slim_tx_mixer_put),
3139         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3140                        slim_tx_mixer_get, slim_tx_mixer_put),
3141         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3142                        slim_tx_mixer_get, slim_tx_mixer_put),
3143         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3144                        slim_tx_mixer_get, slim_tx_mixer_put),
3145         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3146                        slim_tx_mixer_get, slim_tx_mixer_put),
3147 };
3148
3149 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3150         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3151                        slim_tx_mixer_get, slim_tx_mixer_put),
3152         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3153                        slim_tx_mixer_get, slim_tx_mixer_put),
3154         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3155                        slim_tx_mixer_get, slim_tx_mixer_put),
3156         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3157                        slim_tx_mixer_get, slim_tx_mixer_put),
3158         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3159                        slim_tx_mixer_get, slim_tx_mixer_put),
3160         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3161                        slim_tx_mixer_get, slim_tx_mixer_put),
3162         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3163                        slim_tx_mixer_get, slim_tx_mixer_put),
3164         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3165                        slim_tx_mixer_get, slim_tx_mixer_put),
3166         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3167                        slim_tx_mixer_get, slim_tx_mixer_put),
3168         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3169                        slim_tx_mixer_get, slim_tx_mixer_put),
3170         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3171                        slim_tx_mixer_get, slim_tx_mixer_put),
3172         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3173                        slim_tx_mixer_get, slim_tx_mixer_put),
3174         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3175                        slim_tx_mixer_get, slim_tx_mixer_put),
3176 };
3177
3178 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3179         /* Gain Controls */
3180         SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3181         SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3182         SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3183         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3184                        3, 16, 1, line_gain),
3185         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3186                        3, 16, 1, line_gain),
3187
3188         SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3189         SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3190         SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3191         SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3192
3193         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3194                           -84, 40, digital_gain), /* -84dB min - 40dB max */
3195         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3196                           -84, 40, digital_gain),
3197         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3198                           -84, 40, digital_gain),
3199         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3200                           -84, 40, digital_gain),
3201         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3202                           -84, 40, digital_gain),
3203         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3204                           -84, 40, digital_gain),
3205         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3206                           -84, 40, digital_gain),
3207         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3208                           WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3209                           -84, 40, digital_gain),
3210         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3211                           WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3212                           -84, 40, digital_gain),
3213         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3214                           WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3215                           -84, 40, digital_gain),
3216         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3217                           WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3218                           -84, 40, digital_gain),
3219         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3220                           WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3221                           -84, 40, digital_gain),
3222         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3223                           WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3224                           -84, 40, digital_gain),
3225         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
3226                           WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
3227                           -84, 40, digital_gain),
3228
3229         SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
3230                           -84, 40, digital_gain),
3231         SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
3232                           -84, 40, digital_gain),
3233         SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
3234                           -84, 40, digital_gain),
3235         SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
3236                           -84, 40, digital_gain),
3237         SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
3238                           -84, 40, digital_gain),
3239         SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
3240                           -84, 40, digital_gain),
3241         SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
3242                           -84, 40, digital_gain),
3243         SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
3244                           -84, 40, digital_gain),
3245         SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
3246                           -84, 40, digital_gain),
3247
3248         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3249                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3250                           digital_gain),
3251         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3252                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3253                           digital_gain),
3254         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3255                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3256                           digital_gain),
3257         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3258                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3259                           digital_gain),
3260         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3261                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3262                           digital_gain),
3263         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3264                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3265                           digital_gain),
3266         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3267                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3268                           digital_gain),
3269         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3270                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3271                           digital_gain),
3272
3273         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
3274         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
3275         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
3276         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
3277         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
3278         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
3279         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
3280         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
3281         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
3282
3283         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
3284         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
3285         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
3286         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
3287         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
3288         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
3289         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
3290         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
3291         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
3292         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
3293         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
3294         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
3295         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
3296         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
3297
3298         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
3299                      wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
3300
3301         SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3302                    0, 1, 0),
3303         SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3304                    1, 1, 0),
3305         SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3306                    2, 1, 0),
3307         SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3308                    3, 1, 0),
3309         SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3310                    4, 1, 0),
3311         SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3312                    0, 1, 0),
3313         SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3314                    1, 1, 0),
3315         SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3316                    2, 1, 0),
3317         SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3318                    3, 1, 0),
3319         SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3320                    4, 1, 0),
3321         WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3322         WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3323         WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3324         WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3325         WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3326
3327         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3328         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3329         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3330         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3331         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3332
3333         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
3334                        wcd934x_compander_get, wcd934x_compander_set),
3335         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
3336                        wcd934x_compander_get, wcd934x_compander_set),
3337         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
3338                        wcd934x_compander_get, wcd934x_compander_set),
3339         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
3340                        wcd934x_compander_get, wcd934x_compander_set),
3341         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
3342                        wcd934x_compander_get, wcd934x_compander_set),
3343         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
3344                        wcd934x_compander_get, wcd934x_compander_set),
3345 };
3346
3347 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3348                                           struct snd_soc_component *component)
3349 {
3350         int port_num = 0;
3351         unsigned short reg = 0;
3352         unsigned int val = 0;
3353         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3354         struct wcd934x_slim_ch *ch;
3355
3356         list_for_each_entry(ch, &dai->slim_ch_list, list) {
3357                 if (ch->port >= WCD934X_RX_START) {
3358                         port_num = ch->port - WCD934X_RX_START;
3359                         reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3360                 } else {
3361                         port_num = ch->port;
3362                         reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3363                 }
3364
3365                 regmap_read(wcd->if_regmap, reg, &val);
3366                 if (!(val & BIT(port_num % 8)))
3367                         regmap_write(wcd->if_regmap, reg,
3368                                      val | BIT(port_num % 8));
3369         }
3370 }
3371
3372 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
3373                                      struct snd_kcontrol *kc, int event)
3374 {
3375         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3376         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
3377         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3378
3379         switch (event) {
3380         case SND_SOC_DAPM_POST_PMU:
3381                 wcd934x_codec_enable_int_port(dai, comp);
3382                 break;
3383         }
3384
3385         return 0;
3386 }
3387
3388 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
3389                                       u16 interp_idx, int event)
3390 {
3391         u16 hd2_scale_reg;
3392         u16 hd2_enable_reg = 0;
3393
3394         switch (interp_idx) {
3395         case INTERP_HPHL:
3396                 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
3397                 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3398                 break;
3399         case INTERP_HPHR:
3400                 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
3401                 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3402                 break;
3403         default:
3404                 return;
3405         }
3406
3407         if (SND_SOC_DAPM_EVENT_ON(event)) {
3408                 snd_soc_component_update_bits(component, hd2_scale_reg,
3409                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3410                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
3411                 snd_soc_component_update_bits(component, hd2_enable_reg,
3412                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3413                                       WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
3414         }
3415
3416         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3417                 snd_soc_component_update_bits(component, hd2_enable_reg,
3418                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3419                                       WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
3420                 snd_soc_component_update_bits(component, hd2_scale_reg,
3421                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3422                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3423         }
3424 }
3425
3426 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
3427                                              u16 interp_idx, int event)
3428 {
3429         u8 hph_dly_mask;
3430         u16 hph_lut_bypass_reg = 0;
3431
3432         switch (interp_idx) {
3433         case INTERP_HPHL:
3434                 hph_dly_mask = 1;
3435                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
3436                 break;
3437         case INTERP_HPHR:
3438                 hph_dly_mask = 2;
3439                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
3440                 break;
3441         default:
3442                 return;
3443         }
3444
3445         if (SND_SOC_DAPM_EVENT_ON(event)) {
3446                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3447                                               hph_dly_mask, 0x0);
3448                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3449                                               WCD934X_HPH_LUT_BYPASS_MASK,
3450                                               WCD934X_HPH_LUT_BYPASS_ENABLE);
3451         }
3452
3453         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3454                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3455                                               hph_dly_mask, hph_dly_mask);
3456                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3457                                               WCD934X_HPH_LUT_BYPASS_MASK,
3458                                               WCD934X_HPH_LUT_BYPASS_DISABLE);
3459         }
3460 }
3461
3462 static int wcd934x_config_compander(struct snd_soc_component *comp,
3463                                     int interp_n, int event)
3464 {
3465         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3466         int compander;
3467         u16 comp_ctl0_reg, rx_path_cfg0_reg;
3468
3469         /* EAR does not have compander */
3470         if (!interp_n)
3471                 return 0;
3472
3473         compander = interp_n - 1;
3474         if (!wcd->comp_enabled[compander])
3475                 return 0;
3476
3477         comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
3478         rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
3479
3480         switch (event) {
3481         case SND_SOC_DAPM_PRE_PMU:
3482                 /* Enable Compander Clock */
3483                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3484                                               WCD934X_COMP_CLK_EN_MASK,
3485                                               WCD934X_COMP_CLK_ENABLE);
3486                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3487                                               WCD934X_COMP_SOFT_RST_MASK,
3488                                               WCD934X_COMP_SOFT_RST_ENABLE);
3489                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3490                                               WCD934X_COMP_SOFT_RST_MASK,
3491                                               WCD934X_COMP_SOFT_RST_DISABLE);
3492                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3493                                               WCD934X_HPH_CMP_EN_MASK,
3494                                               WCD934X_HPH_CMP_ENABLE);
3495                 break;
3496         case SND_SOC_DAPM_POST_PMD:
3497                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3498                                               WCD934X_HPH_CMP_EN_MASK,
3499                                               WCD934X_HPH_CMP_DISABLE);
3500                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3501                                               WCD934X_COMP_HALT_MASK,
3502                                               WCD934X_COMP_HALT);
3503                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3504                                               WCD934X_COMP_SOFT_RST_MASK,
3505                                               WCD934X_COMP_SOFT_RST_ENABLE);
3506                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3507                                               WCD934X_COMP_SOFT_RST_MASK,
3508                                               WCD934X_COMP_SOFT_RST_DISABLE);
3509                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3510                                               WCD934X_COMP_CLK_EN_MASK, 0x0);
3511                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3512                                               WCD934X_COMP_SOFT_RST_MASK, 0x0);
3513                 break;
3514         }
3515
3516         return 0;
3517 }
3518
3519 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
3520                                          struct snd_kcontrol *kc, int event)
3521 {
3522         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3523         int interp_idx = w->shift;
3524         u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
3525
3526         switch (event) {
3527         case SND_SOC_DAPM_PRE_PMU:
3528                 /* Clk enable */
3529                 snd_soc_component_update_bits(comp, main_reg,
3530                                              WCD934X_RX_CLK_EN_MASK,
3531                                              WCD934X_RX_CLK_ENABLE);
3532                 wcd934x_codec_hd2_control(comp, interp_idx, event);
3533                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3534                 wcd934x_config_compander(comp, interp_idx, event);
3535                 break;
3536         case SND_SOC_DAPM_POST_PMD:
3537                 wcd934x_config_compander(comp, interp_idx, event);
3538                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3539                 wcd934x_codec_hd2_control(comp, interp_idx, event);
3540                 /* Clk Disable */
3541                 snd_soc_component_update_bits(comp, main_reg,
3542                                              WCD934X_RX_CLK_EN_MASK, 0);
3543                 /* Reset enable and disable */
3544                 snd_soc_component_update_bits(comp, main_reg,
3545                                               WCD934X_RX_RESET_MASK,
3546                                               WCD934X_RX_RESET_ENABLE);
3547                 snd_soc_component_update_bits(comp, main_reg,
3548                                               WCD934X_RX_RESET_MASK,
3549                                               WCD934X_RX_RESET_DISABLE);
3550                 /* Reset rate to 48K*/
3551                 snd_soc_component_update_bits(comp, main_reg,
3552                                               WCD934X_RX_PCM_RATE_MASK,
3553                                               WCD934X_RX_PCM_RATE_F_48K);
3554                 break;
3555         }
3556
3557         return 0;
3558 }
3559
3560 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3561                                          struct snd_kcontrol *kc, int event)
3562 {
3563         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3564         int offset_val = 0;
3565         u16 gain_reg, mix_reg;
3566         int val = 0;
3567
3568         gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
3569                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3570         mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
3571                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3572
3573         switch (event) {
3574         case SND_SOC_DAPM_PRE_PMU:
3575                 /* Clk enable */
3576                 snd_soc_component_update_bits(comp, mix_reg,
3577                                               WCD934X_CDC_RX_MIX_CLK_EN_MASK,
3578                                               WCD934X_CDC_RX_MIX_CLK_ENABLE);
3579                 break;
3580
3581         case SND_SOC_DAPM_POST_PMU:
3582                 val = snd_soc_component_read(comp, gain_reg);
3583                 val += offset_val;
3584                 snd_soc_component_write(comp, gain_reg, val);
3585                 break;
3586         }
3587
3588         return 0;
3589 }
3590
3591 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
3592                                       struct snd_kcontrol *kcontrol, int event)
3593 {
3594         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3595         int reg = w->reg;
3596
3597         switch (event) {
3598         case SND_SOC_DAPM_POST_PMU:
3599                 /* B1 GAIN */
3600                 snd_soc_component_write(comp, reg,
3601                                         snd_soc_component_read(comp, reg));
3602                 /* B2 GAIN */
3603                 reg++;
3604                 snd_soc_component_write(comp, reg,
3605                                         snd_soc_component_read(comp, reg));
3606                 /* B3 GAIN */
3607                 reg++;
3608                 snd_soc_component_write(comp, reg,
3609                                         snd_soc_component_read(comp, reg));
3610                 /* B4 GAIN */
3611                 reg++;
3612                 snd_soc_component_write(comp, reg,
3613                                         snd_soc_component_read(comp, reg));
3614                 /* B5 GAIN */
3615                 reg++;
3616                 snd_soc_component_write(comp, reg,
3617                                         snd_soc_component_read(comp, reg));
3618                 break;
3619         default:
3620                 break;
3621         }
3622         return 0;
3623 }
3624
3625 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
3626                                           struct snd_kcontrol *kcontrol,
3627                                           int event)
3628 {
3629         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3630         u16 gain_reg;
3631
3632         gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
3633                                                  WCD934X_RX_PATH_CTL_OFFSET);
3634
3635         switch (event) {
3636         case SND_SOC_DAPM_POST_PMU:
3637                 snd_soc_component_write(comp, gain_reg,
3638                                 snd_soc_component_read(comp, gain_reg));
3639                 break;
3640         }
3641
3642         return 0;
3643 }
3644
3645 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3646                                        struct snd_kcontrol *kc, int event)
3647 {
3648         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3649         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3650
3651         switch (event) {
3652         case SND_SOC_DAPM_PRE_PMU:
3653                 /* Disable AutoChop timer during power up */
3654                 snd_soc_component_update_bits(comp,
3655                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3656                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3657                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3658                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3659
3660                 break;
3661         case SND_SOC_DAPM_POST_PMD:
3662                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3663                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3664                 break;
3665         }
3666
3667         return 0;
3668 }
3669
3670 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3671                                         struct snd_kcontrol *kcontrol,
3672                                         int event)
3673 {
3674         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3675         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3676         int hph_mode = wcd->hph_mode;
3677         u8 dem_inp;
3678
3679         switch (event) {
3680         case SND_SOC_DAPM_PRE_PMU:
3681                 /* Read DEM INP Select */
3682                 dem_inp = snd_soc_component_read(comp,
3683                                    WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
3684
3685                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3686                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3687                         return -EINVAL;
3688                 }
3689                 if (hph_mode != CLS_H_LP)
3690                         /* Ripple freq control enable */
3691                         snd_soc_component_update_bits(comp,
3692                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3693                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3694                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3695                 /* Disable AutoChop timer during power up */
3696                 snd_soc_component_update_bits(comp,
3697                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3698                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3699                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3700                                         WCD_CLSH_STATE_HPHL, hph_mode);
3701
3702                 break;
3703         case SND_SOC_DAPM_POST_PMD:
3704                 /* 1000us required as per HW requirement */
3705                 usleep_range(1000, 1100);
3706                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3707                                         WCD_CLSH_STATE_HPHL, hph_mode);
3708                 if (hph_mode != CLS_H_LP)
3709                         /* Ripple freq control disable */
3710                         snd_soc_component_update_bits(comp,
3711                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3712                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3713
3714                 break;
3715         default:
3716                 break;
3717         }
3718
3719         return 0;
3720 }
3721
3722 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3723                                         struct snd_kcontrol *kcontrol,
3724                                         int event)
3725 {
3726         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3727         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3728         int hph_mode = wcd->hph_mode;
3729         u8 dem_inp;
3730
3731         switch (event) {
3732         case SND_SOC_DAPM_PRE_PMU:
3733                 dem_inp = snd_soc_component_read(comp,
3734                                         WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
3735                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3736                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3737                         return -EINVAL;
3738                 }
3739                 if (hph_mode != CLS_H_LP)
3740                         /* Ripple freq control enable */
3741                         snd_soc_component_update_bits(comp,
3742                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3743                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3744                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3745                 /* Disable AutoChop timer during power up */
3746                 snd_soc_component_update_bits(comp,
3747                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3748                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3749                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3750                                         WCD_CLSH_STATE_HPHR,
3751                              hph_mode);
3752                 break;
3753         case SND_SOC_DAPM_POST_PMD:
3754                 /* 1000us required as per HW requirement */
3755                 usleep_range(1000, 1100);
3756
3757                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3758                                         WCD_CLSH_STATE_HPHR, hph_mode);
3759                 if (hph_mode != CLS_H_LP)
3760                         /* Ripple freq control disable */
3761                         snd_soc_component_update_bits(comp,
3762                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3763                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3764                 break;
3765         default:
3766                 break;
3767         }
3768
3769         return 0;
3770 }
3771
3772 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3773                                            struct snd_kcontrol *kc, int event)
3774 {
3775         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3776         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3777
3778         switch (event) {
3779         case SND_SOC_DAPM_PRE_PMU:
3780                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3781                                         WCD_CLSH_STATE_LO, CLS_AB);
3782                 break;
3783         case SND_SOC_DAPM_POST_PMD:
3784                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3785                                         WCD_CLSH_STATE_LO, CLS_AB);
3786                 break;
3787         }
3788
3789         return 0;
3790 }
3791
3792 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3793                                         struct snd_kcontrol *kcontrol,
3794                                         int event)
3795 {
3796         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3797
3798         switch (event) {
3799         case SND_SOC_DAPM_POST_PMU:
3800                 /*
3801                  * 7ms sleep is required after PA is enabled as per
3802                  * HW requirement. If compander is disabled, then
3803                  * 20ms delay is needed.
3804                  */
3805                 usleep_range(20000, 20100);
3806
3807                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3808                                               WCD934X_HPH_OCP_DET_MASK,
3809                                               WCD934X_HPH_OCP_DET_ENABLE);
3810                 /* Remove Mute on primary path */
3811                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3812                                       WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3813                                       0);
3814                 /* Enable GM3 boost */
3815                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3816                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
3817                                               WCD934X_HPH_GM3_BOOST_ENABLE);
3818                 /* Enable AutoChop timer at the end of power up */
3819                 snd_soc_component_update_bits(comp,
3820                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3821                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3822                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3823                 /* Remove mix path mute */
3824                 snd_soc_component_update_bits(comp,
3825                                 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3826                                 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
3827                 break;
3828         case SND_SOC_DAPM_PRE_PMD:
3829                 /* Enable DSD Mute before PA disable */
3830                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3831                                               WCD934X_HPH_OCP_DET_MASK,
3832                                               WCD934X_HPH_OCP_DET_DISABLE);
3833                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3834                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3835                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3836                 snd_soc_component_update_bits(comp,
3837                                               WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3838                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3839                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3840                 break;
3841         case SND_SOC_DAPM_POST_PMD:
3842                 /*
3843                  * 5ms sleep is required after PA disable. If compander is
3844                  * disabled, then 20ms delay is needed after PA disable.
3845                  */
3846                 usleep_range(20000, 20100);
3847                 break;
3848         }
3849
3850         return 0;
3851 }
3852
3853 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3854                                         struct snd_kcontrol *kcontrol,
3855                                         int event)
3856 {
3857         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3858
3859         switch (event) {
3860         case SND_SOC_DAPM_POST_PMU:
3861                 /*
3862                  * 7ms sleep is required after PA is enabled as per
3863                  * HW requirement. If compander is disabled, then
3864                  * 20ms delay is needed.
3865                  */
3866                 usleep_range(20000, 20100);
3867                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3868                                               WCD934X_HPH_OCP_DET_MASK,
3869                                               WCD934X_HPH_OCP_DET_ENABLE);
3870                 /* Remove mute */
3871                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3872                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3873                                               0);
3874                 /* Enable GM3 boost */
3875                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3876                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
3877                                               WCD934X_HPH_GM3_BOOST_ENABLE);
3878                 /* Enable AutoChop timer at the end of power up */
3879                 snd_soc_component_update_bits(comp,
3880                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3881                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3882                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3883                 /* Remove mix path mute if it is enabled */
3884                 if ((snd_soc_component_read(comp,
3885                                       WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
3886                         snd_soc_component_update_bits(comp,
3887                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3888                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3889                                               WCD934X_CDC_RX_PGA_MUTE_DISABLE);
3890                 break;
3891         case SND_SOC_DAPM_PRE_PMD:
3892                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3893                                               WCD934X_HPH_OCP_DET_MASK,
3894                                               WCD934X_HPH_OCP_DET_DISABLE);
3895                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3896                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3897                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3898                 snd_soc_component_update_bits(comp,
3899                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3900                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3901                                               WCD934X_CDC_RX_PGA_MUTE_ENABLE);
3902                 break;
3903         case SND_SOC_DAPM_POST_PMD:
3904                 /*
3905                  * 5ms sleep is required after PA disable. If compander is
3906                  * disabled, then 20ms delay is needed after PA disable.
3907                  */
3908                 usleep_range(20000, 20100);
3909                 break;
3910         }
3911
3912         return 0;
3913 }
3914
3915 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
3916                                         unsigned int dmic,
3917                                       struct wcd934x_codec *wcd)
3918 {
3919         u8 tx_stream_fs;
3920         u8 adc_mux_index = 0, adc_mux_sel = 0;
3921         bool dec_found = false;
3922         u16 adc_mux_ctl_reg, tx_fs_reg;
3923         u32 dmic_fs;
3924
3925         while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
3926                 if (adc_mux_index < 4) {
3927                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
3928                                                 (adc_mux_index * 2);
3929                 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
3930                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
3931                                                 adc_mux_index - 4;
3932                 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
3933                         ++adc_mux_index;
3934                         continue;
3935                 }
3936                 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
3937                                & 0xF8) >> 3) - 1;
3938
3939                 if (adc_mux_sel == dmic) {
3940                         dec_found = true;
3941                         break;
3942                 }
3943
3944                 ++adc_mux_index;
3945         }
3946
3947         if (dec_found && adc_mux_index <= 8) {
3948                 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
3949                 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
3950                 if (tx_stream_fs <= 4)  {
3951                         if (wcd->dmic_sample_rate <=
3952                                         WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
3953                                 dmic_fs = wcd->dmic_sample_rate;
3954                         else
3955                                 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
3956                 } else
3957                         dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
3958         } else {
3959                 dmic_fs = wcd->dmic_sample_rate;
3960         }
3961
3962         return dmic_fs;
3963 }
3964
3965 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
3966                                    u32 mclk_rate, u32 dmic_clk_rate)
3967 {
3968         u32 div_factor;
3969         u8 dmic_ctl_val;
3970
3971         /* Default value to return in case of error */
3972         if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
3973                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3974         else
3975                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3976
3977         if (dmic_clk_rate == 0) {
3978                 dev_err(comp->dev,
3979                         "%s: dmic_sample_rate cannot be 0\n",
3980                         __func__);
3981                 goto done;
3982         }
3983
3984         div_factor = mclk_rate / dmic_clk_rate;
3985         switch (div_factor) {
3986         case 2:
3987                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3988                 break;
3989         case 3:
3990                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3991                 break;
3992         case 4:
3993                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
3994                 break;
3995         case 6:
3996                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
3997                 break;
3998         case 8:
3999                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4000                 break;
4001         case 16:
4002                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4003                 break;
4004         default:
4005                 dev_err(comp->dev,
4006                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4007                         __func__, div_factor, mclk_rate, dmic_clk_rate);
4008                 break;
4009         }
4010
4011 done:
4012         return dmic_ctl_val;
4013 }
4014
4015 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4016                                      struct snd_kcontrol *kcontrol, int event)
4017 {
4018         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4019         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4020         u8  dmic_clk_en = 0x01;
4021         u16 dmic_clk_reg;
4022         s32 *dmic_clk_cnt;
4023         u8 dmic_rate_val, dmic_rate_shift = 1;
4024         unsigned int dmic;
4025         u32 dmic_sample_rate;
4026         int ret;
4027         char *wname;
4028
4029         wname = strpbrk(w->name, "012345");
4030         if (!wname) {
4031                 dev_err(comp->dev, "%s: widget not found\n", __func__);
4032                 return -EINVAL;
4033         }
4034
4035         ret = kstrtouint(wname, 10, &dmic);
4036         if (ret < 0) {
4037                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4038                         __func__);
4039                 return -EINVAL;
4040         }
4041
4042         switch (dmic) {
4043         case 0:
4044         case 1:
4045                 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4046                 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4047                 break;
4048         case 2:
4049         case 3:
4050                 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4051                 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4052                 break;
4053         case 4:
4054         case 5:
4055                 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4056                 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4057                 break;
4058         default:
4059                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4060                         __func__);
4061                 return -EINVAL;
4062         }
4063
4064         switch (event) {
4065         case SND_SOC_DAPM_PRE_PMU:
4066                 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4067                                                                 wcd);
4068                 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4069                                                          dmic_sample_rate);
4070                 (*dmic_clk_cnt)++;
4071                 if (*dmic_clk_cnt == 1) {
4072                         dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4073                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4074                                                       WCD934X_DMIC_RATE_MASK,
4075                                                       dmic_rate_val);
4076                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4077                                                       dmic_clk_en, dmic_clk_en);
4078                 }
4079
4080                 break;
4081         case SND_SOC_DAPM_POST_PMD:
4082                 (*dmic_clk_cnt)--;
4083                 if (*dmic_clk_cnt == 0)
4084                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4085                                                       dmic_clk_en, 0);
4086                 break;
4087         }
4088
4089         return 0;
4090 }
4091
4092 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4093                                          int adc_mux_n)
4094 {
4095         u16 mask, shift, adc_mux_in_reg;
4096         u16 amic_mux_sel_reg;
4097         bool is_amic;
4098
4099         if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4100             adc_mux_n == WCD934X_INVALID_ADC_MUX)
4101                 return 0;
4102
4103         if (adc_mux_n < 3) {
4104                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4105                                  adc_mux_n;
4106                 mask = 0x03;
4107                 shift = 0;
4108                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4109                                    2 * adc_mux_n;
4110         } else if (adc_mux_n < 4) {
4111                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4112                 mask = 0x03;
4113                 shift = 0;
4114                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4115                                    2 * adc_mux_n;
4116         } else if (adc_mux_n < 7) {
4117                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4118                                  (adc_mux_n - 4);
4119                 mask = 0x0C;
4120                 shift = 2;
4121                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4122                                    adc_mux_n - 4;
4123         } else if (adc_mux_n < 8) {
4124                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4125                 mask = 0x0C;
4126                 shift = 2;
4127                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4128                                    adc_mux_n - 4;
4129         } else if (adc_mux_n < 12) {
4130                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4131                                  ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4132                                   (adc_mux_n - 9));
4133                 mask = 0x30;
4134                 shift = 4;
4135                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4136                                    adc_mux_n - 4;
4137         } else if (adc_mux_n < 13) {
4138                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4139                 mask = 0x30;
4140                 shift = 4;
4141                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4142                                    adc_mux_n - 4;
4143         } else {
4144                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4145                 mask = 0xC0;
4146                 shift = 6;
4147                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4148                                    adc_mux_n - 4;
4149         }
4150
4151         is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4152                      & mask) >> shift) == 1);
4153         if (!is_amic)
4154                 return 0;
4155
4156         return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4157 }
4158
4159 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4160                                             int amic)
4161 {
4162         u16 pwr_level_reg = 0;
4163
4164         switch (amic) {
4165         case 1:
4166         case 2:
4167                 pwr_level_reg = WCD934X_ANA_AMIC1;
4168                 break;
4169
4170         case 3:
4171         case 4:
4172                 pwr_level_reg = WCD934X_ANA_AMIC3;
4173                 break;
4174         default:
4175                 break;
4176         }
4177
4178         return pwr_level_reg;
4179 }
4180
4181 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4182                                     struct snd_kcontrol *kcontrol, int event)
4183 {
4184         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4185         unsigned int decimator;
4186         char *dec_adc_mux_name = NULL;
4187         char *widget_name = NULL;
4188         char *wname;
4189         int ret = 0, amic_n;
4190         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4191         u16 tx_gain_ctl_reg;
4192         char *dec;
4193         u8 hpf_coff_freq;
4194
4195         widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4196         if (!widget_name)
4197                 return -ENOMEM;
4198
4199         wname = widget_name;
4200         dec_adc_mux_name = strsep(&widget_name, " ");
4201         if (!dec_adc_mux_name) {
4202                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4203                         __func__, w->name);
4204                 ret =  -EINVAL;
4205                 goto out;
4206         }
4207         dec_adc_mux_name = widget_name;
4208
4209         dec = strpbrk(dec_adc_mux_name, "012345678");
4210         if (!dec) {
4211                 dev_err(comp->dev, "%s: decimator index not found\n",
4212                         __func__);
4213                 ret =  -EINVAL;
4214                 goto out;
4215         }
4216
4217         ret = kstrtouint(dec, 10, &decimator);
4218         if (ret < 0) {
4219                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4220                         __func__, wname);
4221                 ret =  -EINVAL;
4222                 goto out;
4223         }
4224
4225         tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4226         hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4227         dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
4228         tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
4229
4230         switch (event) {
4231         case SND_SOC_DAPM_PRE_PMU:
4232                 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
4233                 if (amic_n)
4234                         pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
4235                                                                  amic_n);
4236
4237                 if (!pwr_level_reg)
4238                         break;
4239
4240                 switch ((snd_soc_component_read(comp, pwr_level_reg) &
4241                                       WCD934X_AMIC_PWR_LVL_MASK) >>
4242                                       WCD934X_AMIC_PWR_LVL_SHIFT) {
4243                 case WCD934X_AMIC_PWR_LEVEL_LP:
4244                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4245                                         WCD934X_DEC_PWR_LVL_MASK,
4246                                         WCD934X_DEC_PWR_LVL_LP);
4247                         break;
4248                 case WCD934X_AMIC_PWR_LEVEL_HP:
4249                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4250                                         WCD934X_DEC_PWR_LVL_MASK,
4251                                         WCD934X_DEC_PWR_LVL_HP);
4252                         break;
4253                 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
4254                 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
4255                 default:
4256                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4257                                         WCD934X_DEC_PWR_LVL_MASK,
4258                                         WCD934X_DEC_PWR_LVL_DF);
4259                         break;
4260                 }
4261                 break;
4262         case SND_SOC_DAPM_POST_PMU:
4263                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4264                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4265                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4266                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4267                                                       TX_HPF_CUT_OFF_FREQ_MASK,
4268                                                       CF_MIN_3DB_150HZ << 5);
4269                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4270                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4271                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4272                         /*
4273                          * Minimum 1 clk cycle delay is required as per
4274                          * HW spec.
4275                          */
4276                         usleep_range(1000, 1010);
4277                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4278                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4279                                       0);
4280                 }
4281                 /* apply gain after decimator is enabled */
4282                 snd_soc_component_write(comp, tx_gain_ctl_reg,
4283                                         snd_soc_component_read(comp,
4284                                                          tx_gain_ctl_reg));
4285                 break;
4286         case SND_SOC_DAPM_PRE_PMD:
4287                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
4288                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4289
4290                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4291                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4292                                                       TX_HPF_CUT_OFF_FREQ_MASK,
4293                                                       hpf_coff_freq << 5);
4294                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4295                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4296                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4297                                 /*
4298                                  * Minimum 1 clk cycle delay is required as per
4299                                  * HW spec.
4300                                  */
4301                         usleep_range(1000, 1010);
4302                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4303                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4304                                       0);
4305                 }
4306                 break;
4307         case SND_SOC_DAPM_POST_PMD:
4308                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
4309                                               0x10, 0x00);
4310                 snd_soc_component_update_bits(comp, dec_cfg_reg,
4311                                               WCD934X_DEC_PWR_LVL_MASK,
4312                                               WCD934X_DEC_PWR_LVL_DF);
4313                 break;
4314         }
4315 out:
4316         kfree(wname);
4317         return ret;
4318 }
4319
4320 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
4321                                       u16 amic_reg, bool set)
4322 {
4323         u8 mask = 0x20;
4324         u8 val;
4325
4326         if (amic_reg == WCD934X_ANA_AMIC1 ||
4327             amic_reg == WCD934X_ANA_AMIC3)
4328                 mask = 0x40;
4329
4330         val = set ? mask : 0x00;
4331
4332         switch (amic_reg) {
4333         case WCD934X_ANA_AMIC1:
4334         case WCD934X_ANA_AMIC2:
4335                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
4336                                               mask, val);
4337                 break;
4338         case WCD934X_ANA_AMIC3:
4339         case WCD934X_ANA_AMIC4:
4340                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
4341                                               mask, val);
4342                 break;
4343         default:
4344                 break;
4345         }
4346 }
4347
4348 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
4349                                     struct snd_kcontrol *kcontrol, int event)
4350 {
4351         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4352
4353         switch (event) {
4354         case SND_SOC_DAPM_PRE_PMU:
4355                 wcd934x_codec_set_tx_hold(comp, w->reg, true);
4356                 break;
4357         default:
4358                 break;
4359         }
4360
4361         return 0;
4362 }
4363
4364 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
4365         /* Analog Outputs */
4366         SND_SOC_DAPM_OUTPUT("EAR"),
4367         SND_SOC_DAPM_OUTPUT("HPHL"),
4368         SND_SOC_DAPM_OUTPUT("HPHR"),
4369         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4370         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4371         SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
4372         SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
4373         SND_SOC_DAPM_OUTPUT("ANC EAR"),
4374         SND_SOC_DAPM_OUTPUT("ANC HPHL"),
4375         SND_SOC_DAPM_OUTPUT("ANC HPHR"),
4376         SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
4377         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
4378         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
4379         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4380                               AIF1_PB, 0, wcd934x_codec_enable_slim,
4381                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4382         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4383                               AIF2_PB, 0, wcd934x_codec_enable_slim,
4384                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4385         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4386                               AIF3_PB, 0, wcd934x_codec_enable_slim,
4387                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4388         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4389                               AIF4_PB, 0, wcd934x_codec_enable_slim,
4390                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4391
4392         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
4393                          &slim_rx_mux[WCD934X_RX0]),
4394         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
4395                          &slim_rx_mux[WCD934X_RX1]),
4396         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
4397                          &slim_rx_mux[WCD934X_RX2]),
4398         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
4399                          &slim_rx_mux[WCD934X_RX3]),
4400         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
4401                          &slim_rx_mux[WCD934X_RX4]),
4402         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
4403                          &slim_rx_mux[WCD934X_RX5]),
4404         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
4405                          &slim_rx_mux[WCD934X_RX6]),
4406         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
4407                          &slim_rx_mux[WCD934X_RX7]),
4408
4409         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4410         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4411         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4412         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4413         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4414         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4415         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4416         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4417
4418         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
4419                            &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
4420                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4421                            SND_SOC_DAPM_POST_PMD),
4422         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
4423                            &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
4424                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4425                            SND_SOC_DAPM_POST_PMD),
4426         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
4427                            &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
4428                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4429                            SND_SOC_DAPM_POST_PMD),
4430         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
4431                            &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
4432                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4433                            SND_SOC_DAPM_POST_PMD),
4434         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
4435                            &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
4436                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4437                            SND_SOC_DAPM_POST_PMD),
4438         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
4439                            &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
4440                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4441                            SND_SOC_DAPM_POST_PMD),
4442         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
4443                            &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
4444                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4445                            SND_SOC_DAPM_POST_PMD),
4446
4447         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4448                          &rx_int0_1_mix_inp0_mux),
4449         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4450                          &rx_int0_1_mix_inp1_mux),
4451         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4452                          &rx_int0_1_mix_inp2_mux),
4453         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4454                          &rx_int1_1_mix_inp0_mux),
4455         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4456                          &rx_int1_1_mix_inp1_mux),
4457         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4458                          &rx_int1_1_mix_inp2_mux),
4459         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4460                          &rx_int2_1_mix_inp0_mux),
4461         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4462                          &rx_int2_1_mix_inp1_mux),
4463         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4464                          &rx_int2_1_mix_inp2_mux),
4465         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4466                          &rx_int3_1_mix_inp0_mux),
4467         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4468                          &rx_int3_1_mix_inp1_mux),
4469         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4470                          &rx_int3_1_mix_inp2_mux),
4471         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4472                          &rx_int4_1_mix_inp0_mux),
4473         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4474                          &rx_int4_1_mix_inp1_mux),
4475         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4476                          &rx_int4_1_mix_inp2_mux),
4477         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4478                            &rx_int7_1_mix_inp0_mux),
4479         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4480                            &rx_int7_1_mix_inp1_mux),
4481         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4482                            &rx_int7_1_mix_inp2_mux),
4483         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4484                            &rx_int8_1_mix_inp0_mux),
4485         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4486                            &rx_int8_1_mix_inp1_mux),
4487         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4488                            &rx_int8_1_mix_inp2_mux),
4489         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4490         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4491         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4492         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
4493                            rx_int1_asrc_switch,
4494                            ARRAY_SIZE(rx_int1_asrc_switch)),
4495         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4496         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
4497                            rx_int2_asrc_switch,
4498                            ARRAY_SIZE(rx_int2_asrc_switch)),
4499         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4500         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
4501                            rx_int3_asrc_switch,
4502                            ARRAY_SIZE(rx_int3_asrc_switch)),
4503         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4504         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
4505                            rx_int4_asrc_switch,
4506                            ARRAY_SIZE(rx_int4_asrc_switch)),
4507         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4508         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4509         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4510         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4511         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4512         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4513         SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4514         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4515         SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4516         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4517         SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4518         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4519         SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4520
4521         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4522         SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
4523                              NULL, 0, NULL, 0),
4524         SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
4525                              NULL, 0, NULL, 0),
4526         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
4527                            0,  &rx_int0_mix2_inp_mux, NULL,
4528                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4529         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
4530                            0, &rx_int1_mix2_inp_mux,  NULL,
4531                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4532         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
4533                            0, &rx_int2_mix2_inp_mux, NULL,
4534                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4535         SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
4536                            0, &rx_int3_mix2_inp_mux, NULL,
4537                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4538         SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
4539                            0, &rx_int4_mix2_inp_mux, NULL,
4540                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4541         SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
4542                            0, &rx_int7_mix2_inp_mux, NULL,
4543                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4544
4545         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
4546         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
4547         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
4548         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
4549         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4550         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4551         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4552         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4553
4554         SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
4555                            0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4556                            SND_SOC_DAPM_POST_PMU),
4557         SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4558                            1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4559                            SND_SOC_DAPM_POST_PMU),
4560         SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4561                            4, 0, NULL, 0),
4562         SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4563                            4, 0, NULL, 0),
4564         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4565                          &rx_int0_dem_inp_mux),
4566         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4567                          &rx_int1_dem_inp_mux),
4568         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4569                          &rx_int2_dem_inp_mux),
4570
4571         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
4572                            &rx_int0_1_interp_mux,
4573                            wcd934x_codec_enable_main_path,
4574                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4575                            SND_SOC_DAPM_POST_PMD),
4576         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
4577                            &rx_int1_1_interp_mux,
4578                            wcd934x_codec_enable_main_path,
4579                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4580                            SND_SOC_DAPM_POST_PMD),
4581         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
4582                            &rx_int2_1_interp_mux,
4583                            wcd934x_codec_enable_main_path,
4584                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4585                            SND_SOC_DAPM_POST_PMD),
4586         SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
4587                            &rx_int3_1_interp_mux,
4588                            wcd934x_codec_enable_main_path,
4589                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4590                            SND_SOC_DAPM_POST_PMD),
4591         SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
4592                            &rx_int4_1_interp_mux,
4593                            wcd934x_codec_enable_main_path,
4594                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4595                            SND_SOC_DAPM_POST_PMD),
4596         SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
4597                            &rx_int7_1_interp_mux,
4598                            wcd934x_codec_enable_main_path,
4599                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4600                            SND_SOC_DAPM_POST_PMD),
4601         SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
4602                            &rx_int8_1_interp_mux,
4603                            wcd934x_codec_enable_main_path,
4604                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4605                            SND_SOC_DAPM_POST_PMD),
4606
4607         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
4608                          &rx_int0_2_interp_mux),
4609         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
4610                          &rx_int1_2_interp_mux),
4611         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
4612                          &rx_int2_2_interp_mux),
4613         SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
4614                          &rx_int3_2_interp_mux),
4615         SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
4616                          &rx_int4_2_interp_mux),
4617         SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
4618                          &rx_int7_2_interp_mux),
4619         SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
4620                          &rx_int8_2_interp_mux),
4621         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4622                            0, 0, wcd934x_codec_ear_dac_event,
4623                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4624                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4625         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
4626                            5, 0, wcd934x_codec_hphl_dac_event,
4627                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4628                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4629         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4630                            4, 0, wcd934x_codec_hphr_dac_event,
4631                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4632                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4633         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4634                            0, 0, wcd934x_codec_lineout_dac_event,
4635                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4636         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4637                            0, 0, wcd934x_codec_lineout_dac_event,
4638                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4639         SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
4640         SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
4641                            wcd934x_codec_enable_hphl_pa,
4642                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4643                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4644         SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
4645                            wcd934x_codec_enable_hphr_pa,
4646                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4647                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4648         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
4649                            NULL, 0),
4650         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
4651                            NULL, 0),
4652         SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
4653                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4654         SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
4655                          0, 0, NULL, 0),
4656         SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
4657                             0, 0, NULL, 0),
4658         SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
4659                          0, 0, NULL, 0),
4660         SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
4661                             0, 0, NULL, 0),
4662         SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
4663                             wcd934x_codec_enable_interp_clk,
4664                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4665         SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
4666                             wcd934x_codec_enable_interp_clk,
4667                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4668         SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
4669                             wcd934x_codec_enable_interp_clk,
4670                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4671         SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
4672                             wcd934x_codec_enable_interp_clk,
4673                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4674         SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
4675                             wcd934x_codec_enable_interp_clk,
4676                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4677         SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
4678                             wcd934x_codec_enable_interp_clk,
4679                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4680         SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
4681                             wcd934x_codec_enable_interp_clk,
4682                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4683         SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
4684                             0, 0, NULL, 0),
4685         SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
4686                             0, 0, NULL, 0),
4687         SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
4688                             0, 0, NULL, 0),
4689         SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
4690                             0, 0, NULL, 0),
4691         SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
4692                             0, 0, NULL, 0),
4693         SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
4694                             0, 0, NULL, 0),
4695         SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
4696                             0, 0, NULL, 0),
4697         SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4698                             wcd934x_codec_enable_mclk,
4699                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4700
4701         /* TX */
4702         SND_SOC_DAPM_INPUT("AMIC1"),
4703         SND_SOC_DAPM_INPUT("AMIC2"),
4704         SND_SOC_DAPM_INPUT("AMIC3"),
4705         SND_SOC_DAPM_INPUT("AMIC4"),
4706         SND_SOC_DAPM_INPUT("AMIC5"),
4707         SND_SOC_DAPM_INPUT("DMIC0 Pin"),
4708         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
4709         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
4710         SND_SOC_DAPM_INPUT("DMIC3 Pin"),
4711         SND_SOC_DAPM_INPUT("DMIC4 Pin"),
4712         SND_SOC_DAPM_INPUT("DMIC5 Pin"),
4713
4714         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4715                                AIF1_CAP, 0, wcd934x_codec_enable_slim,
4716                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4717         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4718                                AIF2_CAP, 0, wcd934x_codec_enable_slim,
4719                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4720         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4721                                AIF3_CAP, 0, wcd934x_codec_enable_slim,
4722                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4723
4724         SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4725         SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4726         SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4727         SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4728         SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4729         SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4730         SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4731         SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4732         SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
4733         SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
4734         SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
4735         SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
4736         SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
4737
4738         /* Digital Mic Inputs */
4739         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4740                            wcd934x_codec_enable_dmic,
4741                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4742         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4743                            wcd934x_codec_enable_dmic,
4744                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4745         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4746                            wcd934x_codec_enable_dmic,
4747                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4748         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4749                            wcd934x_codec_enable_dmic,
4750                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4751         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4752                            wcd934x_codec_enable_dmic,
4753                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4754         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4755                            wcd934x_codec_enable_dmic,
4756                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4757         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
4758         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
4759         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
4760         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
4761         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
4762         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
4763         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
4764         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
4765         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
4766         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
4767         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
4768         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
4769         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
4770         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
4771         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
4772         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
4773         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
4774         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
4775         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
4776                            &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
4777                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4778                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4779         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
4780                            &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
4781                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4782                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4783         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
4784                            &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
4785                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4786                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4787         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
4788                            &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
4789                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4790                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4791         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
4792                            &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
4793                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4794                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4795         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
4796                            &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
4797                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4798                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4799         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
4800                            &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
4801                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4802                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4803         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
4804                            &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
4805                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4806                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4807         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
4808                            &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
4809                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4810                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4811         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
4812                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4813         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
4814                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4815         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
4816                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4817         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
4818                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4819         SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
4820                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4821         SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
4822                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4823         SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
4824                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4825         SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
4826                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4827
4828         SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
4829         SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
4830                          &cdc_if_tx0_mux),
4831         SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
4832                          &cdc_if_tx1_mux),
4833         SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
4834                          &cdc_if_tx2_mux),
4835         SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
4836                          &cdc_if_tx3_mux),
4837         SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
4838                          &cdc_if_tx4_mux),
4839         SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
4840                          &cdc_if_tx5_mux),
4841         SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
4842                          &cdc_if_tx6_mux),
4843         SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
4844                          &cdc_if_tx7_mux),
4845         SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
4846                          &cdc_if_tx8_mux),
4847         SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
4848                          &cdc_if_tx9_mux),
4849         SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
4850                          &cdc_if_tx10_mux),
4851         SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4852                          &cdc_if_tx11_mux),
4853         SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4854                          &cdc_if_tx11_inp1_mux),
4855         SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4856                          &cdc_if_tx13_mux),
4857         SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4858                          &cdc_if_tx13_inp1_mux),
4859         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4860                            aif1_slim_cap_mixer,
4861                            ARRAY_SIZE(aif1_slim_cap_mixer)),
4862         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4863                            aif2_slim_cap_mixer,
4864                            ARRAY_SIZE(aif2_slim_cap_mixer)),
4865         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4866                            aif3_slim_cap_mixer,
4867                            ARRAY_SIZE(aif3_slim_cap_mixer)),
4868 };
4869
4870 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4871         /* RX0-RX7 */
4872         WCD934X_SLIM_RX_AIF_PATH(0),
4873         WCD934X_SLIM_RX_AIF_PATH(1),
4874         WCD934X_SLIM_RX_AIF_PATH(2),
4875         WCD934X_SLIM_RX_AIF_PATH(3),
4876         WCD934X_SLIM_RX_AIF_PATH(4),
4877         WCD934X_SLIM_RX_AIF_PATH(5),
4878         WCD934X_SLIM_RX_AIF_PATH(6),
4879         WCD934X_SLIM_RX_AIF_PATH(7),
4880
4881         /* RX0 Ear out */
4882         WCD934X_INTERPOLATOR_PATH(0),
4883         WCD934X_INTERPOLATOR_MIX2(0),
4884         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4885         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4886         {"RX INT0 DAC", NULL, "RX_BIAS"},
4887         {"EAR PA", NULL, "RX INT0 DAC"},
4888         {"EAR", NULL, "EAR PA"},
4889
4890         /* RX1 Headphone left */
4891         WCD934X_INTERPOLATOR_PATH(1),
4892         WCD934X_INTERPOLATOR_MIX2(1),
4893         {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4894         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4895         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4896         {"RX INT1 DAC", NULL, "RX_BIAS"},
4897         {"HPHL PA", NULL, "RX INT1 DAC"},
4898         {"HPHL", NULL, "HPHL PA"},
4899
4900         /* RX2 Headphone right */
4901         WCD934X_INTERPOLATOR_PATH(2),
4902         WCD934X_INTERPOLATOR_MIX2(2),
4903         {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4904         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4905         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4906         {"RX INT2 DAC", NULL, "RX_BIAS"},
4907         {"HPHR PA", NULL, "RX INT2 DAC"},
4908         {"HPHR", NULL, "HPHR PA"},
4909
4910         /* RX3 HIFi LineOut1 */
4911         WCD934X_INTERPOLATOR_PATH(3),
4912         WCD934X_INTERPOLATOR_MIX2(3),
4913         {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4914         {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4915         {"RX INT3 DAC", NULL, "RX_BIAS"},
4916         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4917         {"LINEOUT1", NULL, "LINEOUT1 PA"},
4918
4919         /* RX4 HIFi LineOut2 */
4920         WCD934X_INTERPOLATOR_PATH(4),
4921         WCD934X_INTERPOLATOR_MIX2(4),
4922         {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4923         {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4924         {"RX INT4 DAC", NULL, "RX_BIAS"},
4925         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4926         {"LINEOUT2", NULL, "LINEOUT2 PA"},
4927
4928         /* RX7 Speaker Left Out PA */
4929         WCD934X_INTERPOLATOR_PATH(7),
4930         WCD934X_INTERPOLATOR_MIX2(7),
4931         {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4932         {"RX INT7 CHAIN", NULL, "RX_BIAS"},
4933         {"RX INT7 CHAIN", NULL, "SBOOST0"},
4934         {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4935         {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4936
4937         /* RX8 Speaker Right Out PA */
4938         WCD934X_INTERPOLATOR_PATH(8),
4939         {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4940         {"RX INT8 CHAIN", NULL, "RX_BIAS"},
4941         {"RX INT8 CHAIN", NULL, "SBOOST1"},
4942         {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4943         {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4944
4945         /* Tx */
4946         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4947         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4948         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4949
4950         WCD934X_SLIM_TX_AIF_PATH(0),
4951         WCD934X_SLIM_TX_AIF_PATH(1),
4952         WCD934X_SLIM_TX_AIF_PATH(2),
4953         WCD934X_SLIM_TX_AIF_PATH(3),
4954         WCD934X_SLIM_TX_AIF_PATH(4),
4955         WCD934X_SLIM_TX_AIF_PATH(5),
4956         WCD934X_SLIM_TX_AIF_PATH(6),
4957         WCD934X_SLIM_TX_AIF_PATH(7),
4958         WCD934X_SLIM_TX_AIF_PATH(8),
4959
4960         WCD934X_ADC_MUX(0),
4961         WCD934X_ADC_MUX(1),
4962         WCD934X_ADC_MUX(2),
4963         WCD934X_ADC_MUX(3),
4964         WCD934X_ADC_MUX(4),
4965         WCD934X_ADC_MUX(5),
4966         WCD934X_ADC_MUX(6),
4967         WCD934X_ADC_MUX(7),
4968         WCD934X_ADC_MUX(8),
4969
4970         {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4971         {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4972         {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4973         {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4974         {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4975         {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4976         {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4977         {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4978         {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
4979
4980         {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
4981         {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
4982
4983         { "DMIC0", NULL, "DMIC0 Pin" },
4984         { "DMIC1", NULL, "DMIC1 Pin" },
4985         { "DMIC2", NULL, "DMIC2 Pin" },
4986         { "DMIC3", NULL, "DMIC3 Pin" },
4987         { "DMIC4", NULL, "DMIC4 Pin" },
4988         { "DMIC5", NULL, "DMIC5 Pin" },
4989
4990         {"ADC1", NULL, "AMIC1"},
4991         {"ADC2", NULL, "AMIC2"},
4992         {"ADC3", NULL, "AMIC3"},
4993         {"ADC4", NULL, "AMIC4_5 SEL"},
4994
4995         WCD934X_IIR_INP_MUX(0),
4996         WCD934X_IIR_INP_MUX(1),
4997
4998         {"SRC0", NULL, "IIR0"},
4999         {"SRC1", NULL, "IIR1"},
5000 };
5001
5002 static const struct snd_soc_component_driver wcd934x_component_drv = {
5003         .probe = wcd934x_comp_probe,
5004         .remove = wcd934x_comp_remove,
5005         .set_sysclk = wcd934x_comp_set_sysclk,
5006         .controls = wcd934x_snd_controls,
5007         .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5008         .dapm_widgets = wcd934x_dapm_widgets,
5009         .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5010         .dapm_routes = wcd934x_audio_map,
5011         .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5012 };
5013
5014 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5015 {
5016         struct device *dev = &wcd->sdev->dev;
5017         struct device_node *ifc_dev_np;
5018
5019         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5020         if (!ifc_dev_np) {
5021                 dev_err(dev, "No Interface device found\n");
5022                 return -EINVAL;
5023         }
5024
5025         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5026         of_node_put(ifc_dev_np);
5027         if (!wcd->sidev) {
5028                 dev_err(dev, "Unable to get SLIM Interface device\n");
5029                 return -EINVAL;
5030         }
5031
5032         slim_get_logical_addr(wcd->sidev);
5033         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5034                                   &wcd934x_ifc_regmap_config);
5035         if (IS_ERR(wcd->if_regmap)) {
5036                 dev_err(dev, "Failed to allocate ifc register map\n");
5037                 return PTR_ERR(wcd->if_regmap);
5038         }
5039
5040         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5041                              &wcd->dmic_sample_rate);
5042
5043         return 0;
5044 }
5045
5046 static int wcd934x_codec_probe(struct platform_device *pdev)
5047 {
5048         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5049         struct wcd934x_codec *wcd;
5050         struct device *dev = &pdev->dev;
5051         int ret, irq;
5052
5053         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5054         if (!wcd)
5055                 return -ENOMEM;
5056
5057         wcd->dev = dev;
5058         wcd->regmap = data->regmap;
5059         wcd->extclk = data->extclk;
5060         wcd->sdev = to_slim_device(data->dev);
5061         mutex_init(&wcd->sysclk_mutex);
5062
5063         ret = wcd934x_codec_parse_data(wcd);
5064         if (ret) {
5065                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5066                 return ret;
5067         }
5068
5069         /* set default rate 9P6MHz */
5070         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5071                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5072                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5073         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5074         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5075
5076         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5077         if (irq < 0) {
5078                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5079                 return irq;
5080         }
5081
5082         ret = devm_request_threaded_irq(dev, irq, NULL,
5083                                         wcd934x_slim_irq_handler,
5084                                         IRQF_TRIGGER_RISING,
5085                                         "slim", wcd);
5086         if (ret) {
5087                 dev_err(dev, "Failed to request slimbus irq\n");
5088                 return ret;
5089         }
5090
5091         wcd934x_register_mclk_output(wcd);
5092         platform_set_drvdata(pdev, wcd);
5093
5094         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5095                                                wcd934x_slim_dais,
5096                                                ARRAY_SIZE(wcd934x_slim_dais));
5097 }
5098
5099 static const struct platform_device_id wcd934x_driver_id[] = {
5100         {
5101                 .name = "wcd934x-codec",
5102         },
5103         {},
5104 };
5105 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5106
5107 static struct platform_driver wcd934x_codec_driver = {
5108         .probe  = &wcd934x_codec_probe,
5109         .id_table = wcd934x_driver_id,
5110         .driver = {
5111                 .name   = "wcd934x-codec",
5112         }
5113 };
5114
5115 MODULE_ALIAS("platform:wcd934x-codec");
5116 module_platform_driver(wcd934x_codec_driver);
5117 MODULE_DESCRIPTION("WCD934x codec driver");
5118 MODULE_LICENSE("GPL v2");