sound/soc/codecs/wcd9335.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   3 // Copyright (c) 2017-2018, Linaro Limited
   4
   5 #include <linux/module.h>
   6 #include <linux/init.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/device.h>
   9 #include <linux/wait.h>
  10 #include <linux/bitops.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slimbus.h>
  16 #include <sound/soc.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc-dapm.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <sound/tlv.h>
  23 #include <sound/info.h>
  24 #include "wcd9335.h"
  25 #include "wcd-clsh-v2.h"
  26
  27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  28                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  29                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  30 /* Fractional Rates */
  31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
  32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  33                                   SNDRV_PCM_FMTBIT_S24_LE)
  34
  35 /* slave port water mark level
  36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  37  */
  38 #define SLAVE_PORT_WATER_MARK_6BYTES  0
  39 #define SLAVE_PORT_WATER_MARK_9BYTES  1
  40 #define SLAVE_PORT_WATER_MARK_12BYTES 2
  41 #define SLAVE_PORT_WATER_MARK_15BYTES 3
  42 #define SLAVE_PORT_WATER_MARK_SHIFT 1
  43 #define SLAVE_PORT_ENABLE           1
  44 #define SLAVE_PORT_DISABLE          0
  45 #define WCD9335_SLIM_WATER_MARK_VAL \
  46         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  47          (SLAVE_PORT_ENABLE))
  48
  49 #define WCD9335_SLIM_NUM_PORT_REG 3
  50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
  51
  52 #define WCD9335_MCLK_CLK_12P288MHZ      12288000
  53 #define WCD9335_MCLK_CLK_9P6MHZ         9600000
  54
  55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
  56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
  57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
  58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
  59
  60 #define WCD9335_NUM_INTERPOLATORS 9
  61 #define WCD9335_RX_START        16
  62 #define WCD9335_SLIM_CH_START 128
  63 #define WCD9335_MAX_MICBIAS 4
  64 #define WCD9335_MAX_VALID_ADC_MUX  13
  65 #define WCD9335_INVALID_ADC_MUX 9
  66
  67 #define  TX_HPF_CUT_OFF_FREQ_MASK       0x60
  68 #define  CF_MIN_3DB_4HZ                 0x0
  69 #define  CF_MIN_3DB_75HZ                0x1
  70 #define  CF_MIN_3DB_150HZ               0x2
  71 #define WCD9335_DMIC_CLK_DIV_2  0x0
  72 #define WCD9335_DMIC_CLK_DIV_3  0x1
  73 #define WCD9335_DMIC_CLK_DIV_4  0x2
  74 #define WCD9335_DMIC_CLK_DIV_6  0x3
  75 #define WCD9335_DMIC_CLK_DIV_8  0x4
  76 #define WCD9335_DMIC_CLK_DIV_16  0x5
  77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
  78 #define WCD9335_AMIC_PWR_LEVEL_LP 0
  79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
  80 #define WCD9335_AMIC_PWR_LEVEL_HP 2
  81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
  82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
  83
  84 #define WCD9335_DEC_PWR_LVL_MASK 0x06
  85 #define WCD9335_DEC_PWR_LVL_LP 0x02
  86 #define WCD9335_DEC_PWR_LVL_HP 0x04
  87 #define WCD9335_DEC_PWR_LVL_DF 0x00
  88
  89 #define WCD9335_SLIM_RX_CH(p) \
  90         {.port = p + WCD9335_RX_START, .shift = p,}
  91
  92 #define WCD9335_SLIM_TX_CH(p) \
  93         {.port = p, .shift = p,}
  94
  95 /* vout step value */
  96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
  97
  98 #define WCD9335_INTERPOLATOR_PATH(id)                   \
  99         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 100         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 101         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 102         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 103         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 104         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 105         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 106         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 107         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 108         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 109         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 110         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 111         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 112         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 113         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 114         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 115         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 116         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 117         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 118         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 119         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 120         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 121         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 122         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 123         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 124         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 125         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 126         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 127         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 128         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 129         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 130         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 131         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"},    \
 132         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"},    \
 133         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"},    \
 134         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"},         \
 135         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"},        \
 136         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"},          \
 137         {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
 138
 139 #define WCD9335_ADC_MUX_PATH(id)                        \
 140         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 141         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 142         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 143         {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
 144         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id},        \
 145         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id},        \
 146         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 147         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 148         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 149         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 150         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 151         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 152         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 153         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 154         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 155         {"AMIC MUX" #id, "ADC4", "ADC4"},               \
 156         {"AMIC MUX" #id, "ADC5", "ADC5"},               \
 157         {"AMIC MUX" #id, "ADC6", "ADC6"}
 158
 159 enum {
 160         WCD9335_RX0 = 0,
 161         WCD9335_RX1,
 162         WCD9335_RX2,
 163         WCD9335_RX3,
 164         WCD9335_RX4,
 165         WCD9335_RX5,
 166         WCD9335_RX6,
 167         WCD9335_RX7,
 168         WCD9335_RX8,
 169         WCD9335_RX9,
 170         WCD9335_RX10,
 171         WCD9335_RX11,
 172         WCD9335_RX12,
 173         WCD9335_RX_MAX,
 174 };
 175
 176 enum {
 177         WCD9335_TX0 = 0,
 178         WCD9335_TX1,
 179         WCD9335_TX2,
 180         WCD9335_TX3,
 181         WCD9335_TX4,
 182         WCD9335_TX5,
 183         WCD9335_TX6,
 184         WCD9335_TX7,
 185         WCD9335_TX8,
 186         WCD9335_TX9,
 187         WCD9335_TX10,
 188         WCD9335_TX11,
 189         WCD9335_TX12,
 190         WCD9335_TX13,
 191         WCD9335_TX14,
 192         WCD9335_TX15,
 193         WCD9335_TX_MAX,
 194 };
 195
 196 enum {
 197         SIDO_SOURCE_INTERNAL = 0,
 198         SIDO_SOURCE_RCO_BG,
 199 };
 200
 201 enum wcd9335_sido_voltage {
 202         SIDO_VOLTAGE_SVS_MV = 950,
 203         SIDO_VOLTAGE_NOMINAL_MV = 1100,
 204 };
 205
 206 enum {
 207         AIF1_PB = 0,
 208         AIF1_CAP,
 209         AIF2_PB,
 210         AIF2_CAP,
 211         AIF3_PB,
 212         AIF3_CAP,
 213         AIF4_PB,
 214         NUM_CODEC_DAIS,
 215 };
 216
 217 enum {
 218         COMPANDER_1, /* HPH_L */
 219         COMPANDER_2, /* HPH_R */
 220         COMPANDER_3, /* LO1_DIFF */
 221         COMPANDER_4, /* LO2_DIFF */
 222         COMPANDER_5, /* LO3_SE */
 223         COMPANDER_6, /* LO4_SE */
 224         COMPANDER_7, /* SWR SPK CH1 */
 225         COMPANDER_8, /* SWR SPK CH2 */
 226         COMPANDER_MAX,
 227 };
 228
 229 enum {
 230         INTn_2_INP_SEL_ZERO = 0,
 231         INTn_2_INP_SEL_RX0,
 232         INTn_2_INP_SEL_RX1,
 233         INTn_2_INP_SEL_RX2,
 234         INTn_2_INP_SEL_RX3,
 235         INTn_2_INP_SEL_RX4,
 236         INTn_2_INP_SEL_RX5,
 237         INTn_2_INP_SEL_RX6,
 238         INTn_2_INP_SEL_RX7,
 239         INTn_2_INP_SEL_PROXIMITY,
 240 };
 241
 242 enum {
 243         INTn_1_MIX_INP_SEL_ZERO = 0,
 244         INTn_1_MIX_INP_SEL_DEC0,
 245         INTn_1_MIX_INP_SEL_DEC1,
 246         INTn_1_MIX_INP_SEL_IIR0,
 247         INTn_1_MIX_INP_SEL_IIR1,
 248         INTn_1_MIX_INP_SEL_RX0,
 249         INTn_1_MIX_INP_SEL_RX1,
 250         INTn_1_MIX_INP_SEL_RX2,
 251         INTn_1_MIX_INP_SEL_RX3,
 252         INTn_1_MIX_INP_SEL_RX4,
 253         INTn_1_MIX_INP_SEL_RX5,
 254         INTn_1_MIX_INP_SEL_RX6,
 255         INTn_1_MIX_INP_SEL_RX7,
 256
 257 };
 258
 259 enum {
 260         INTERP_EAR = 0,
 261         INTERP_HPHL,
 262         INTERP_HPHR,
 263         INTERP_LO1,
 264         INTERP_LO2,
 265         INTERP_LO3,
 266         INTERP_LO4,
 267         INTERP_SPKR1,
 268         INTERP_SPKR2,
 269 };
 270
 271 enum wcd_clock_type {
 272         WCD_CLK_OFF,
 273         WCD_CLK_RCO,
 274         WCD_CLK_MCLK,
 275 };
 276
 277 enum {
 278         MIC_BIAS_1 = 1,
 279         MIC_BIAS_2,
 280         MIC_BIAS_3,
 281         MIC_BIAS_4
 282 };
 283
 284 enum {
 285         MICB_PULLUP_ENABLE,
 286         MICB_PULLUP_DISABLE,
 287         MICB_ENABLE,
 288         MICB_DISABLE,
 289 };
 290
 291 struct wcd9335_slim_ch {
 292         u32 ch_num;
 293         u16 port;
 294         u16 shift;
 295         struct list_head list;
 296 };
 297
 298 struct wcd_slim_codec_dai_data {
 299         struct list_head slim_ch_list;
 300         struct slim_stream_config sconfig;
 301         struct slim_stream_runtime *sruntime;
 302 };
 303
 304 struct wcd9335_codec {
 305         struct device *dev;
 306         struct clk *mclk;
 307         struct clk *native_clk;
 308         u32 mclk_rate;
 309         u8 version;
 310
 311         struct slim_device *slim;
 312         struct slim_device *slim_ifc_dev;
 313         struct regmap *regmap;
 314         struct regmap *if_regmap;
 315         struct regmap_irq_chip_data *irq_data;
 316
 317         struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
 318         struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
 319         u32 num_rx_port;
 320         u32 num_tx_port;
 321
 322         int sido_input_src;
 323         enum wcd9335_sido_voltage sido_voltage;
 324
 325         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 326         struct snd_soc_component *component;
 327
 328         int master_bias_users;
 329         int clk_mclk_users;
 330         int clk_rco_users;
 331         int sido_ccl_cnt;
 332         enum wcd_clock_type clk_type;
 333
 334         struct wcd_clsh_ctrl *clsh_ctrl;
 335         u32 hph_mode;
 336         int prim_int_users[WCD9335_NUM_INTERPOLATORS];
 337
 338         int comp_enabled[COMPANDER_MAX];
 339
 340         int intr1;
 341         int reset_gpio;
 342         struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
 343
 344         unsigned int rx_port_value;
 345         unsigned int tx_port_value;
 346         int hph_l_gain;
 347         int hph_r_gain;
 348         u32 rx_bias_count;
 349
 350         /*TX*/
 351         int micb_ref[WCD9335_MAX_MICBIAS];
 352         int pullup_ref[WCD9335_MAX_MICBIAS];
 353
 354         int dmic_0_1_clk_cnt;
 355         int dmic_2_3_clk_cnt;
 356         int dmic_4_5_clk_cnt;
 357         int dmic_sample_rate;
 358         int mad_dmic_sample_rate;
 359
 360         int native_clk_users;
 361 };
 362
 363 struct wcd9335_irq {
 364         int irq;
 365         irqreturn_t (*handler)(int irq, void *data);
 366         char *name;
 367 };
 368
 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
 370         WCD9335_SLIM_TX_CH(0),
 371         WCD9335_SLIM_TX_CH(1),
 372         WCD9335_SLIM_TX_CH(2),
 373         WCD9335_SLIM_TX_CH(3),
 374         WCD9335_SLIM_TX_CH(4),
 375         WCD9335_SLIM_TX_CH(5),
 376         WCD9335_SLIM_TX_CH(6),
 377         WCD9335_SLIM_TX_CH(7),
 378         WCD9335_SLIM_TX_CH(8),
 379         WCD9335_SLIM_TX_CH(9),
 380         WCD9335_SLIM_TX_CH(10),
 381         WCD9335_SLIM_TX_CH(11),
 382         WCD9335_SLIM_TX_CH(12),
 383         WCD9335_SLIM_TX_CH(13),
 384         WCD9335_SLIM_TX_CH(14),
 385         WCD9335_SLIM_TX_CH(15),
 386 };
 387
 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
 389         WCD9335_SLIM_RX_CH(0),   /* 16 */
 390         WCD9335_SLIM_RX_CH(1),   /* 17 */
 391         WCD9335_SLIM_RX_CH(2),
 392         WCD9335_SLIM_RX_CH(3),
 393         WCD9335_SLIM_RX_CH(4),
 394         WCD9335_SLIM_RX_CH(5),
 395         WCD9335_SLIM_RX_CH(6),
 396         WCD9335_SLIM_RX_CH(7),
 397         WCD9335_SLIM_RX_CH(8),
 398         WCD9335_SLIM_RX_CH(9),
 399         WCD9335_SLIM_RX_CH(10),
 400         WCD9335_SLIM_RX_CH(11),
 401         WCD9335_SLIM_RX_CH(12),
 402 };
 403
 404 struct interp_sample_rate {
 405         int rate;
 406         int rate_val;
 407 };
 408
 409 static struct interp_sample_rate int_mix_rate_val[] = {
 410         {48000, 0x4},   /* 48K */
 411         {96000, 0x5},   /* 96K */
 412         {192000, 0x6},  /* 192K */
 413 };
 414
 415 static struct interp_sample_rate int_prim_rate_val[] = {
 416         {8000, 0x0},    /* 8K */
 417         {16000, 0x1},   /* 16K */
 418         {24000, -EINVAL},/* 24K */
 419         {32000, 0x3},   /* 32K */
 420         {48000, 0x4},   /* 48K */
 421         {96000, 0x5},   /* 96K */
 422         {192000, 0x6},  /* 192K */
 423         {384000, 0x7},  /* 384K */
 424         {44100, 0x8}, /* 44.1K */
 425 };
 426
 427 struct wcd9335_reg_mask_val {
 428         u16 reg;
 429         u8 mask;
 430         u8 val;
 431 };
 432
 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
 434         /* Rbuckfly/R_EAR(32) */
 435         {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
 436         {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
 437         {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
 438         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
 439         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
 440         {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
 441         {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
 442         {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
 443         {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
 444         {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
 445         {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
 446         {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
 447         {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
 448         {WCD9335_EAR_CMBUFF, 0x08, 0x00},
 449         {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 450         {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 451         {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 452         {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 453         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
 454         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
 455         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
 456         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
 457         {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
 458         {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
 459         {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
 460         {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
 461         {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
 462         {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
 463         {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
 464         {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
 465         {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
 466         {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
 467         {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
 468         {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
 469         {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
 470         {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
 471         {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
 472         {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
 473         {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
 474         {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
 475         {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
 476         {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
 477         {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
 478         {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
 479         {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
 480         {WCD9335_HPH_L_TEST, 0x01, 0x01},
 481         {WCD9335_HPH_R_TEST, 0x01, 0x01},
 482         {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
 483         {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
 484         {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
 485         {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
 486         {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
 487         {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
 488         {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
 489         {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
 490         {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
 491         {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
 492 };
 493
 494 /* Cutoff frequency for high pass filter */
 495 static const char * const cf_text[] = {
 496         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 497 };
 498
 499 static const char * const rx_cf_text[] = {
 500         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 501         "CF_NEG_3DB_0P48HZ"
 502 };
 503
 504 static const char * const rx_int0_7_mix_mux_text[] = {
 505         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 506         "RX6", "RX7", "PROXIMITY"
 507 };
 508
 509 static const char * const rx_int_mix_mux_text[] = {
 510         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 511         "RX6", "RX7"
 512 };
 513
 514 static const char * const rx_prim_mix_text[] = {
 515         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 516         "RX3", "RX4", "RX5", "RX6", "RX7"
 517 };
 518
 519 static const char * const rx_int_dem_inp_mux_text[] = {
 520         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 521 };
 522
 523 static const char * const rx_int0_interp_mux_text[] = {
 524         "ZERO", "RX INT0 MIX2",
 525 };
 526
 527 static const char * const rx_int1_interp_mux_text[] = {
 528         "ZERO", "RX INT1 MIX2",
 529 };
 530
 531 static const char * const rx_int2_interp_mux_text[] = {
 532         "ZERO", "RX INT2 MIX2",
 533 };
 534
 535 static const char * const rx_int3_interp_mux_text[] = {
 536         "ZERO", "RX INT3 MIX2",
 537 };
 538
 539 static const char * const rx_int4_interp_mux_text[] = {
 540         "ZERO", "RX INT4 MIX2",
 541 };
 542
 543 static const char * const rx_int5_interp_mux_text[] = {
 544         "ZERO", "RX INT5 MIX2",
 545 };
 546
 547 static const char * const rx_int6_interp_mux_text[] = {
 548         "ZERO", "RX INT6 MIX2",
 549 };
 550
 551 static const char * const rx_int7_interp_mux_text[] = {
 552         "ZERO", "RX INT7 MIX2",
 553 };
 554
 555 static const char * const rx_int8_interp_mux_text[] = {
 556         "ZERO", "RX INT8 SEC MIX"
 557 };
 558
 559 static const char * const rx_hph_mode_mux_text[] = {
 560         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 561         "Class-H Hi-Fi Low Power"
 562 };
 563
 564 static const char *const slim_rx_mux_text[] = {
 565         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 566 };
 567
 568 static const char * const adc_mux_text[] = {
 569         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 570 };
 571
 572 static const char * const dmic_mux_text[] = {
 573         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 574         "SMIC0", "SMIC1", "SMIC2", "SMIC3"
 575 };
 576
 577 static const char * const dmic_mux_alt_text[] = {
 578         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 579 };
 580
 581 static const char * const amic_mux_text[] = {
 582         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
 583 };
 584
 585 static const char * const sb_tx0_mux_text[] = {
 586         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 587 };
 588
 589 static const char * const sb_tx1_mux_text[] = {
 590         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 591 };
 592
 593 static const char * const sb_tx2_mux_text[] = {
 594         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 595 };
 596
 597 static const char * const sb_tx3_mux_text[] = {
 598         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 599 };
 600
 601 static const char * const sb_tx4_mux_text[] = {
 602         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 603 };
 604
 605 static const char * const sb_tx5_mux_text[] = {
 606         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 607 };
 608
 609 static const char * const sb_tx6_mux_text[] = {
 610         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 611 };
 612
 613 static const char * const sb_tx7_mux_text[] = {
 614         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 615 };
 616
 617 static const char * const sb_tx8_mux_text[] = {
 618         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 619 };
 620
 621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 625
 626 static const struct soc_enum cf_dec0_enum =
 627         SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 628
 629 static const struct soc_enum cf_dec1_enum =
 630         SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 631
 632 static const struct soc_enum cf_dec2_enum =
 633         SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 634
 635 static const struct soc_enum cf_dec3_enum =
 636         SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 637
 638 static const struct soc_enum cf_dec4_enum =
 639         SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 640
 641 static const struct soc_enum cf_dec5_enum =
 642         SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 643
 644 static const struct soc_enum cf_dec6_enum =
 645         SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 646
 647 static const struct soc_enum cf_dec7_enum =
 648         SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 649
 650 static const struct soc_enum cf_dec8_enum =
 651         SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 652
 653 static const struct soc_enum cf_int0_1_enum =
 654         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 655
 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
 657                      rx_cf_text);
 658
 659 static const struct soc_enum cf_int1_1_enum =
 660         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 661
 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
 663                      rx_cf_text);
 664
 665 static const struct soc_enum cf_int2_1_enum =
 666         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 667
 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
 669                      rx_cf_text);
 670
 671 static const struct soc_enum cf_int3_1_enum =
 672         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 673
 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
 675                      rx_cf_text);
 676
 677 static const struct soc_enum cf_int4_1_enum =
 678         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 679
 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
 681                      rx_cf_text);
 682
 683 static const struct soc_enum cf_int5_1_enum =
 684         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
 685
 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
 687                      rx_cf_text);
 688
 689 static const struct soc_enum cf_int6_1_enum =
 690         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
 691
 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
 693                      rx_cf_text);
 694
 695 static const struct soc_enum cf_int7_1_enum =
 696         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 697
 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
 699                      rx_cf_text);
 700
 701 static const struct soc_enum cf_int8_1_enum =
 702         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 703
 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
 705                      rx_cf_text);
 706
 707 static const struct soc_enum rx_hph_mode_mux_enum =
 708         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 709                             rx_hph_mode_mux_text);
 710
 711 static const struct soc_enum slim_rx_mux_enum =
 712         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 713
 714 static const struct soc_enum rx_int0_2_mux_chain_enum =
 715         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 716                         rx_int0_7_mix_mux_text);
 717
 718 static const struct soc_enum rx_int1_2_mux_chain_enum =
 719         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 720                         rx_int_mix_mux_text);
 721
 722 static const struct soc_enum rx_int2_2_mux_chain_enum =
 723         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 724                         rx_int_mix_mux_text);
 725
 726 static const struct soc_enum rx_int3_2_mux_chain_enum =
 727         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 728                         rx_int_mix_mux_text);
 729
 730 static const struct soc_enum rx_int4_2_mux_chain_enum =
 731         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 732                         rx_int_mix_mux_text);
 733
 734 static const struct soc_enum rx_int5_2_mux_chain_enum =
 735         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
 736                         rx_int_mix_mux_text);
 737
 738 static const struct soc_enum rx_int6_2_mux_chain_enum =
 739         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
 740                         rx_int_mix_mux_text);
 741
 742 static const struct soc_enum rx_int7_2_mux_chain_enum =
 743         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 744                         rx_int0_7_mix_mux_text);
 745
 746 static const struct soc_enum rx_int8_2_mux_chain_enum =
 747         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 748                         rx_int_mix_mux_text);
 749
 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 751         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 752                         rx_prim_mix_text);
 753
 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 755         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 756                         rx_prim_mix_text);
 757
 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 759         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 760                         rx_prim_mix_text);
 761
 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 763         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 764                         rx_prim_mix_text);
 765
 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 767         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 768                         rx_prim_mix_text);
 769
 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 771         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 772                         rx_prim_mix_text);
 773
 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 775         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 776                         rx_prim_mix_text);
 777
 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 779         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 780                         rx_prim_mix_text);
 781
 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 783         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 784                         rx_prim_mix_text);
 785
 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 787         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 788                         rx_prim_mix_text);
 789
 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 791         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 792                         rx_prim_mix_text);
 793
 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 795         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 796                         rx_prim_mix_text);
 797
 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 799         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 800                         rx_prim_mix_text);
 801
 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 803         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 804                         rx_prim_mix_text);
 805
 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 807         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 808                         rx_prim_mix_text);
 809
 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
 811         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
 812                         rx_prim_mix_text);
 813
 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
 815         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
 816                         rx_prim_mix_text);
 817
 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
 819         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
 820                         rx_prim_mix_text);
 821
 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
 823         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
 824                         rx_prim_mix_text);
 825
 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
 827         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
 828                         rx_prim_mix_text);
 829
 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
 831         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
 832                         rx_prim_mix_text);
 833
 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 835         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 836                         rx_prim_mix_text);
 837
 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 839         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 840                         rx_prim_mix_text);
 841
 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 843         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 844                         rx_prim_mix_text);
 845
 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 847         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 848                         rx_prim_mix_text);
 849
 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 851         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 852                         rx_prim_mix_text);
 853
 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 855         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 856                         rx_prim_mix_text);
 857
 858 static const struct soc_enum rx_int0_dem_inp_mux_enum =
 859         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
 860                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 861                         rx_int_dem_inp_mux_text);
 862
 863 static const struct soc_enum rx_int1_dem_inp_mux_enum =
 864         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
 865                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 866                         rx_int_dem_inp_mux_text);
 867
 868 static const struct soc_enum rx_int2_dem_inp_mux_enum =
 869         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
 870                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 871                         rx_int_dem_inp_mux_text);
 872
 873 static const struct soc_enum rx_int0_interp_mux_enum =
 874         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
 875                         rx_int0_interp_mux_text);
 876
 877 static const struct soc_enum rx_int1_interp_mux_enum =
 878         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
 879                         rx_int1_interp_mux_text);
 880
 881 static const struct soc_enum rx_int2_interp_mux_enum =
 882         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
 883                         rx_int2_interp_mux_text);
 884
 885 static const struct soc_enum rx_int3_interp_mux_enum =
 886         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
 887                         rx_int3_interp_mux_text);
 888
 889 static const struct soc_enum rx_int4_interp_mux_enum =
 890         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
 891                         rx_int4_interp_mux_text);
 892
 893 static const struct soc_enum rx_int5_interp_mux_enum =
 894         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
 895                         rx_int5_interp_mux_text);
 896
 897 static const struct soc_enum rx_int6_interp_mux_enum =
 898         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
 899                         rx_int6_interp_mux_text);
 900
 901 static const struct soc_enum rx_int7_interp_mux_enum =
 902         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
 903                         rx_int7_interp_mux_text);
 904
 905 static const struct soc_enum rx_int8_interp_mux_enum =
 906         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
 907                         rx_int8_interp_mux_text);
 908
 909 static const struct soc_enum tx_adc_mux0_chain_enum =
 910         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
 911                         adc_mux_text);
 912
 913 static const struct soc_enum tx_adc_mux1_chain_enum =
 914         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
 915                         adc_mux_text);
 916
 917 static const struct soc_enum tx_adc_mux2_chain_enum =
 918         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
 919                         adc_mux_text);
 920
 921 static const struct soc_enum tx_adc_mux3_chain_enum =
 922         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
 923                         adc_mux_text);
 924
 925 static const struct soc_enum tx_adc_mux4_chain_enum =
 926         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
 927                         adc_mux_text);
 928
 929 static const struct soc_enum tx_adc_mux5_chain_enum =
 930         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
 931                         adc_mux_text);
 932
 933 static const struct soc_enum tx_adc_mux6_chain_enum =
 934         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
 935                         adc_mux_text);
 936
 937 static const struct soc_enum tx_adc_mux7_chain_enum =
 938         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
 939                         adc_mux_text);
 940
 941 static const struct soc_enum tx_adc_mux8_chain_enum =
 942         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
 943                         adc_mux_text);
 944
 945 static const struct soc_enum tx_dmic_mux0_enum =
 946         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
 947                         dmic_mux_text);
 948
 949 static const struct soc_enum tx_dmic_mux1_enum =
 950         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
 951                         dmic_mux_text);
 952
 953 static const struct soc_enum tx_dmic_mux2_enum =
 954         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
 955                         dmic_mux_text);
 956
 957 static const struct soc_enum tx_dmic_mux3_enum =
 958         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
 959                         dmic_mux_text);
 960
 961 static const struct soc_enum tx_dmic_mux4_enum =
 962         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
 963                         dmic_mux_alt_text);
 964
 965 static const struct soc_enum tx_dmic_mux5_enum =
 966         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
 967                         dmic_mux_alt_text);
 968
 969 static const struct soc_enum tx_dmic_mux6_enum =
 970         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
 971                         dmic_mux_alt_text);
 972
 973 static const struct soc_enum tx_dmic_mux7_enum =
 974         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
 975                         dmic_mux_alt_text);
 976
 977 static const struct soc_enum tx_dmic_mux8_enum =
 978         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
 979                         dmic_mux_alt_text);
 980
 981 static const struct soc_enum tx_amic_mux0_enum =
 982         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
 983                         amic_mux_text);
 984
 985 static const struct soc_enum tx_amic_mux1_enum =
 986         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
 987                         amic_mux_text);
 988
 989 static const struct soc_enum tx_amic_mux2_enum =
 990         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
 991                         amic_mux_text);
 992
 993 static const struct soc_enum tx_amic_mux3_enum =
 994         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
 995                         amic_mux_text);
 996
 997 static const struct soc_enum tx_amic_mux4_enum =
 998         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
 999                         amic_mux_text);
1000
1001 static const struct soc_enum tx_amic_mux5_enum =
1002         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
1003                         amic_mux_text);
1004
1005 static const struct soc_enum tx_amic_mux6_enum =
1006         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
1007                         amic_mux_text);
1008
1009 static const struct soc_enum tx_amic_mux7_enum =
1010         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1011                         amic_mux_text);
1012
1013 static const struct soc_enum tx_amic_mux8_enum =
1014         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1015                         amic_mux_text);
1016
1017 static const struct soc_enum sb_tx0_mux_enum =
1018         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1019                         sb_tx0_mux_text);
1020
1021 static const struct soc_enum sb_tx1_mux_enum =
1022         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1023                         sb_tx1_mux_text);
1024
1025 static const struct soc_enum sb_tx2_mux_enum =
1026         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1027                         sb_tx2_mux_text);
1028
1029 static const struct soc_enum sb_tx3_mux_enum =
1030         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1031                         sb_tx3_mux_text);
1032
1033 static const struct soc_enum sb_tx4_mux_enum =
1034         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1035                         sb_tx4_mux_text);
1036
1037 static const struct soc_enum sb_tx5_mux_enum =
1038         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1039                         sb_tx5_mux_text);
1040
1041 static const struct soc_enum sb_tx6_mux_enum =
1042         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1043                         sb_tx6_mux_text);
1044
1045 static const struct soc_enum sb_tx7_mux_enum =
1046         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1047                         sb_tx7_mux_text);
1048
1049 static const struct soc_enum sb_tx8_mux_enum =
1050         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1051                         sb_tx8_mux_text);
1052
1053 static const struct snd_kcontrol_new rx_int0_2_mux =
1054         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int1_2_mux =
1057         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int2_2_mux =
1060         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int3_2_mux =
1063         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int4_2_mux =
1066         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int5_2_mux =
1069         SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int6_2_mux =
1072         SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int7_2_mux =
1075         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int8_2_mux =
1078         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1081         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1084         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1087         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1090         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1093         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1096         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1099         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1102         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1105         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1108         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1111         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1114         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1117         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1120         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1123         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1126         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1129         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1132         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1135         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1138         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1141         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1144         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1147         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1150         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1153         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1154
1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1156         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1157
1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1159         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1160
1161 static const struct snd_kcontrol_new rx_int0_interp_mux =
1162         SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int1_interp_mux =
1165         SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int2_interp_mux =
1168         SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int3_interp_mux =
1171         SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int4_interp_mux =
1174         SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int5_interp_mux =
1177         SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new rx_int6_interp_mux =
1180         SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1181
1182 static const struct snd_kcontrol_new rx_int7_interp_mux =
1183         SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1184
1185 static const struct snd_kcontrol_new rx_int8_interp_mux =
1186         SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux0 =
1189         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux1 =
1192         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux2 =
1195         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux3 =
1198         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux4 =
1201         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux5 =
1204         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1205
1206 static const struct snd_kcontrol_new tx_dmic_mux6 =
1207         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1208
1209 static const struct snd_kcontrol_new tx_dmic_mux7 =
1210         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1211
1212 static const struct snd_kcontrol_new tx_dmic_mux8 =
1213         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux0 =
1216         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux1 =
1219         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux2 =
1222         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux3 =
1225         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux4 =
1228         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux5 =
1231         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1232
1233 static const struct snd_kcontrol_new tx_amic_mux6 =
1234         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1235
1236 static const struct snd_kcontrol_new tx_amic_mux7 =
1237         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1238
1239 static const struct snd_kcontrol_new tx_amic_mux8 =
1240         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx0_mux =
1243         SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx1_mux =
1246         SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx2_mux =
1249         SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx3_mux =
1252         SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx4_mux =
1255         SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx5_mux =
1258         SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1259
1260 static const struct snd_kcontrol_new sb_tx6_mux =
1261         SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1262
1263 static const struct snd_kcontrol_new sb_tx7_mux =
1264         SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1265
1266 static const struct snd_kcontrol_new sb_tx8_mux =
1267         SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1268
1269 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1270                            struct snd_ctl_elem_value *ucontrol)
1271 {
1272         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1273         struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1274
1275         ucontrol->value.enumerated.item[0] = wcd->rx_port_value;
1276
1277         return 0;
1278 }
1279
1280 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1281                            struct snd_ctl_elem_value *ucontrol)
1282 {
1283         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1284         struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1285         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1286         struct snd_soc_dapm_update *update = NULL;
1287         u32 port_id = w->shift;
1288
1289         wcd->rx_port_value = ucontrol->value.enumerated.item[0];
1290
1291         switch (wcd->rx_port_value) {
1292         case 0:
1293                 list_del_init(&wcd->rx_chs[port_id].list);
1294                 break;
1295         case 1:
1296                 list_add_tail(&wcd->rx_chs[port_id].list,
1297                               &wcd->dai[AIF1_PB].slim_ch_list);
1298                 break;
1299         case 2:
1300                 list_add_tail(&wcd->rx_chs[port_id].list,
1301                               &wcd->dai[AIF2_PB].slim_ch_list);
1302                 break;
1303         case 3:
1304                 list_add_tail(&wcd->rx_chs[port_id].list,
1305                               &wcd->dai[AIF3_PB].slim_ch_list);
1306                 break;
1307         case 4:
1308                 list_add_tail(&wcd->rx_chs[port_id].list,
1309                               &wcd->dai[AIF4_PB].slim_ch_list);
1310                 break;
1311         default:
1312                 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value);
1313                 goto err;
1314         }
1315
1316         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value,
1317                                       e, update);
1318
1319         return 0;
1320 err:
1321         return -EINVAL;
1322 }
1323
1324 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1325                              struct snd_ctl_elem_value *ucontrol)
1326 {
1327
1328         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1329         struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1330
1331         ucontrol->value.integer.value[0] = wcd->tx_port_value;
1332
1333         return 0;
1334 }
1335
1336 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1337                              struct snd_ctl_elem_value *ucontrol)
1338 {
1339
1340         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1341         struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1342         struct snd_soc_dapm_update *update = NULL;
1343         struct soc_mixer_control *mixer =
1344                         (struct soc_mixer_control *)kc->private_value;
1345         int enable = ucontrol->value.integer.value[0];
1346         int dai_id = widget->shift;
1347         int port_id = mixer->shift;
1348
1349         switch (dai_id) {
1350         case AIF1_CAP:
1351         case AIF2_CAP:
1352         case AIF3_CAP:
1353                 /* only add to the list if value not set */
1354                 if (enable && !(wcd->tx_port_value & BIT(port_id))) {
1355                         wcd->tx_port_value |= BIT(port_id);
1356                         list_add_tail(&wcd->tx_chs[port_id].list,
1357                                         &wcd->dai[dai_id].slim_ch_list);
1358                 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) {
1359                         wcd->tx_port_value &= ~BIT(port_id);
1360                         list_del_init(&wcd->tx_chs[port_id].list);
1361                 }
1362                 break;
1363         default:
1364                 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1365                 return -EINVAL;
1366         }
1367
1368         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1369
1370         return 0;
1371 }
1372
1373 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1374         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1375                           slim_rx_mux_get, slim_rx_mux_put),
1376         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1377                           slim_rx_mux_get, slim_rx_mux_put),
1378         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1379                           slim_rx_mux_get, slim_rx_mux_put),
1380         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1381                           slim_rx_mux_get, slim_rx_mux_put),
1382         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1383                           slim_rx_mux_get, slim_rx_mux_put),
1384         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1385                           slim_rx_mux_get, slim_rx_mux_put),
1386         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1387                           slim_rx_mux_get, slim_rx_mux_put),
1388         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1389                           slim_rx_mux_get, slim_rx_mux_put),
1390 };
1391
1392 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1393         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1394                         slim_tx_mixer_get, slim_tx_mixer_put),
1395         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1396                         slim_tx_mixer_get, slim_tx_mixer_put),
1397         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1398                         slim_tx_mixer_get, slim_tx_mixer_put),
1399         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1400                         slim_tx_mixer_get, slim_tx_mixer_put),
1401         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1402                         slim_tx_mixer_get, slim_tx_mixer_put),
1403         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1404                         slim_tx_mixer_get, slim_tx_mixer_put),
1405         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1406                         slim_tx_mixer_get, slim_tx_mixer_put),
1407         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1408                         slim_tx_mixer_get, slim_tx_mixer_put),
1409         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1410                         slim_tx_mixer_get, slim_tx_mixer_put),
1411         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1412                         slim_tx_mixer_get, slim_tx_mixer_put),
1413         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1414                         slim_tx_mixer_get, slim_tx_mixer_put),
1415         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1416                         slim_tx_mixer_get, slim_tx_mixer_put),
1417         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1418                         slim_tx_mixer_get, slim_tx_mixer_put),
1419 };
1420
1421 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1422         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1423                         slim_tx_mixer_get, slim_tx_mixer_put),
1424         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1425                         slim_tx_mixer_get, slim_tx_mixer_put),
1426         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1427                         slim_tx_mixer_get, slim_tx_mixer_put),
1428         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1429                         slim_tx_mixer_get, slim_tx_mixer_put),
1430         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1431                         slim_tx_mixer_get, slim_tx_mixer_put),
1432         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1433                         slim_tx_mixer_get, slim_tx_mixer_put),
1434         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1435                         slim_tx_mixer_get, slim_tx_mixer_put),
1436         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1437                         slim_tx_mixer_get, slim_tx_mixer_put),
1438         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1439                         slim_tx_mixer_get, slim_tx_mixer_put),
1440         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1441                         slim_tx_mixer_get, slim_tx_mixer_put),
1442         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1443                         slim_tx_mixer_get, slim_tx_mixer_put),
1444         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1445                         slim_tx_mixer_get, slim_tx_mixer_put),
1446         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1447                         slim_tx_mixer_get, slim_tx_mixer_put),
1448 };
1449
1450 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1451         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1452                         slim_tx_mixer_get, slim_tx_mixer_put),
1453         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1454                         slim_tx_mixer_get, slim_tx_mixer_put),
1455         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1456                         slim_tx_mixer_get, slim_tx_mixer_put),
1457         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1458                         slim_tx_mixer_get, slim_tx_mixer_put),
1459         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1460                         slim_tx_mixer_get, slim_tx_mixer_put),
1461         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1462                         slim_tx_mixer_get, slim_tx_mixer_put),
1463         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1464                         slim_tx_mixer_get, slim_tx_mixer_put),
1465         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1466                         slim_tx_mixer_get, slim_tx_mixer_put),
1467         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1468                         slim_tx_mixer_get, slim_tx_mixer_put),
1469 };
1470
1471 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1472                                 struct snd_ctl_elem_value *ucontrol)
1473 {
1474         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1475         struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1476         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1477         unsigned int val, reg, sel;
1478
1479         val = ucontrol->value.enumerated.item[0];
1480
1481         switch (e->reg) {
1482         case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1483                 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1484                 break;
1485         case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1486                 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1487                 break;
1488         case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1489                 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1490                 break;
1491         case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1492                 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1493                 break;
1494         case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1495                 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1496                 break;
1497         case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1498                 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1499                 break;
1500         case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1501                 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1502                 break;
1503         case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1504                 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1505                 break;
1506         case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1507                 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1508                 break;
1509         default:
1510                 return -EINVAL;
1511         }
1512
1513         /* AMIC: 0, DMIC: 1 */
1514         sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1515         snd_soc_component_update_bits(component, reg,
1516                                       WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1517                                       sel);
1518
1519         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1520 }
1521
1522 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1523                                  struct snd_ctl_elem_value *ucontrol)
1524 {
1525         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1526         struct snd_soc_component *component;
1527         int reg, val;
1528
1529         component = snd_soc_dapm_kcontrol_component(kc);
1530         val = ucontrol->value.enumerated.item[0];
1531
1532         if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1533                 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1534         else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1535                 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1536         else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1537                 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1538         else
1539                 return -EINVAL;
1540
1541         /* Set Look Ahead Delay */
1542         snd_soc_component_update_bits(component, reg,
1543                                 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1544                                 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1545         /* Set DEM INP Select */
1546         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1547 }
1548
1549 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1550         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1551                           snd_soc_dapm_get_enum_double,
1552                           wcd9335_int_dem_inp_mux_put);
1553
1554 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1555         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1556                           snd_soc_dapm_get_enum_double,
1557                           wcd9335_int_dem_inp_mux_put);
1558
1559 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1560         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1561                           snd_soc_dapm_get_enum_double,
1562                           wcd9335_int_dem_inp_mux_put);
1563
1564 static const struct snd_kcontrol_new tx_adc_mux0 =
1565         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1566                           snd_soc_dapm_get_enum_double,
1567                           wcd9335_put_dec_enum);
1568
1569 static const struct snd_kcontrol_new tx_adc_mux1 =
1570         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1571                           snd_soc_dapm_get_enum_double,
1572                           wcd9335_put_dec_enum);
1573
1574 static const struct snd_kcontrol_new tx_adc_mux2 =
1575         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1576                           snd_soc_dapm_get_enum_double,
1577                           wcd9335_put_dec_enum);
1578
1579 static const struct snd_kcontrol_new tx_adc_mux3 =
1580         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1581                           snd_soc_dapm_get_enum_double,
1582                           wcd9335_put_dec_enum);
1583
1584 static const struct snd_kcontrol_new tx_adc_mux4 =
1585         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1586                           snd_soc_dapm_get_enum_double,
1587                           wcd9335_put_dec_enum);
1588
1589 static const struct snd_kcontrol_new tx_adc_mux5 =
1590         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1591                           snd_soc_dapm_get_enum_double,
1592                           wcd9335_put_dec_enum);
1593
1594 static const struct snd_kcontrol_new tx_adc_mux6 =
1595         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1596                           snd_soc_dapm_get_enum_double,
1597                           wcd9335_put_dec_enum);
1598
1599 static const struct snd_kcontrol_new tx_adc_mux7 =
1600         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1601                           snd_soc_dapm_get_enum_double,
1602                           wcd9335_put_dec_enum);
1603
1604 static const struct snd_kcontrol_new tx_adc_mux8 =
1605         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1606                           snd_soc_dapm_get_enum_double,
1607                           wcd9335_put_dec_enum);
1608
1609 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1610                                              int rate_val,
1611                                              u32 rate)
1612 {
1613         struct snd_soc_component *component = dai->component;
1614         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1615         struct wcd9335_slim_ch *ch;
1616         int val, j;
1617
1618         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1619                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1620                         val = snd_soc_component_read(component,
1621                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1622                                         WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1623
1624                         if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1625                                 snd_soc_component_update_bits(component,
1626                                                 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1627                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1628                                                 rate_val);
1629                 }
1630         }
1631
1632         return 0;
1633 }
1634
1635 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1636                                               u8 rate_val,
1637                                               u32 rate)
1638 {
1639         struct snd_soc_component *comp = dai->component;
1640         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1641         struct wcd9335_slim_ch *ch;
1642         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1643         int inp, j;
1644
1645         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1646                 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1647                 /*
1648                  * Loop through all interpolator MUX inputs and find out
1649                  * to which interpolator input, the slim rx port
1650                  * is connected
1651                  */
1652                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1653                         cfg0 = snd_soc_component_read(comp,
1654                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1655                         cfg1 = snd_soc_component_read(comp,
1656                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1657
1658                         inp0_sel = cfg0 &
1659                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1660                         inp1_sel = (cfg0 >> 4) &
1661                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1662                         inp2_sel = (cfg1 >> 4) &
1663                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1664
1665                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1666                             (inp2_sel == inp)) {
1667                                 /* rate is in Hz */
1668                                 if ((j == 0) && (rate == 44100))
1669                                         dev_info(wcd->dev,
1670                                                 "Cannot set 44.1KHz on INT0\n");
1671                                 else
1672                                         snd_soc_component_update_bits(comp,
1673                                                 WCD9335_CDC_RX_PATH_CTL(j),
1674                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1675                                                 rate_val);
1676                         }
1677                 }
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1684 {
1685         int i;
1686
1687         /* set mixing path rate */
1688         for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1689                 if (rate == int_mix_rate_val[i].rate) {
1690                         wcd9335_set_mix_interpolator_rate(dai,
1691                                         int_mix_rate_val[i].rate_val, rate);
1692                         break;
1693                 }
1694         }
1695
1696         /* set primary path sample rate */
1697         for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1698                 if (rate == int_prim_rate_val[i].rate) {
1699                         wcd9335_set_prim_interpolator_rate(dai,
1700                                         int_prim_rate_val[i].rate_val, rate);
1701                         break;
1702                 }
1703         }
1704
1705         return 0;
1706 }
1707
1708 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1709                                  struct wcd_slim_codec_dai_data *dai_data,
1710                                  int direction)
1711 {
1712         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1713         struct slim_stream_config *cfg = &dai_data->sconfig;
1714         struct wcd9335_slim_ch *ch;
1715         u16 payload = 0;
1716         int ret, i;
1717
1718         cfg->ch_count = 0;
1719         cfg->direction = direction;
1720         cfg->port_mask = 0;
1721
1722         /* Configure slave interface device */
1723         list_for_each_entry(ch, slim_ch_list, list) {
1724                 cfg->ch_count++;
1725                 payload |= 1 << ch->shift;
1726                 cfg->port_mask |= BIT(ch->port);
1727         }
1728
1729         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1730         if (!cfg->chs)
1731                 return -ENOMEM;
1732
1733         i = 0;
1734         list_for_each_entry(ch, slim_ch_list, list) {
1735                 cfg->chs[i++] = ch->ch_num;
1736                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1737                         /* write to interface device */
1738                         ret = regmap_write(wcd->if_regmap,
1739                                 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1740                                 payload);
1741
1742                         if (ret < 0)
1743                                 goto err;
1744
1745                         /* configure the slave port for water mark and enable*/
1746                         ret = regmap_write(wcd->if_regmap,
1747                                         WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1748                                         WCD9335_SLIM_WATER_MARK_VAL);
1749                         if (ret < 0)
1750                                 goto err;
1751                 } else {
1752                         ret = regmap_write(wcd->if_regmap,
1753                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1754                                 payload & 0x00FF);
1755                         if (ret < 0)
1756                                 goto err;
1757
1758                         /* ports 8,9 */
1759                         ret = regmap_write(wcd->if_regmap,
1760                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1761                                 (payload & 0xFF00)>>8);
1762                         if (ret < 0)
1763                                 goto err;
1764
1765                         /* configure the slave port for water mark and enable*/
1766                         ret = regmap_write(wcd->if_regmap,
1767                                         WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1768                                         WCD9335_SLIM_WATER_MARK_VAL);
1769
1770                         if (ret < 0)
1771                                 goto err;
1772                 }
1773         }
1774
1775         dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1776
1777         return 0;
1778
1779 err:
1780         dev_err(wcd->dev, "Error Setting slim hw params\n");
1781         kfree(cfg->chs);
1782         cfg->chs = NULL;
1783
1784         return ret;
1785 }
1786
1787 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1788                                       u8 rate_val, u32 rate)
1789 {
1790         struct snd_soc_component *comp = dai->component;
1791         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1792         u8 shift = 0, shift_val = 0, tx_mux_sel;
1793         struct wcd9335_slim_ch *ch;
1794         int tx_port, tx_port_reg;
1795         int decimator = -1;
1796
1797         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1798                 tx_port = ch->port;
1799                 if ((tx_port == 12) || (tx_port >= 14)) {
1800                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1801                                 tx_port, dai->id);
1802                         return -EINVAL;
1803                 }
1804                 /* Find the SB TX MUX input - which decimator is connected */
1805                 if (tx_port < 4) {
1806                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1807                         shift = (tx_port << 1);
1808                         shift_val = 0x03;
1809                 } else if ((tx_port >= 4) && (tx_port < 8)) {
1810                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1811                         shift = ((tx_port - 4) << 1);
1812                         shift_val = 0x03;
1813                 } else if ((tx_port >= 8) && (tx_port < 11)) {
1814                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1815                         shift = ((tx_port - 8) << 1);
1816                         shift_val = 0x03;
1817                 } else if (tx_port == 11) {
1818                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1819                         shift = 0;
1820                         shift_val = 0x0F;
1821                 } else if (tx_port == 13) {
1822                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1823                         shift = 4;
1824                         shift_val = 0x03;
1825                 } else {
1826                         return -EINVAL;
1827                 }
1828
1829                 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1830                                                       (shift_val << shift);
1831
1832                 tx_mux_sel = tx_mux_sel >> shift;
1833                 if (tx_port <= 8) {
1834                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1835                                 decimator = tx_port;
1836                 } else if (tx_port <= 10) {
1837                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1838                                 decimator = ((tx_port == 9) ? 7 : 6);
1839                 } else if (tx_port == 11) {
1840                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1841                                 decimator = tx_mux_sel - 1;
1842                 } else if (tx_port == 13) {
1843                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1844                                 decimator = 5;
1845                 }
1846
1847                 if (decimator >= 0) {
1848                         snd_soc_component_update_bits(comp,
1849                                         WCD9335_CDC_TX_PATH_CTL(decimator),
1850                                         WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1851                                         rate_val);
1852                 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1853                         /* Check if the TX Mux input is RX MIX TXn */
1854                         dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1855                                 tx_port, tx_port);
1856                 } else {
1857                         dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1858                                 decimator);
1859                         return -EINVAL;
1860                 }
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1867                            struct snd_pcm_hw_params *params,
1868                            struct snd_soc_dai *dai)
1869 {
1870         struct wcd9335_codec *wcd;
1871         int ret, tx_fs_rate = 0;
1872
1873         wcd = snd_soc_component_get_drvdata(dai->component);
1874
1875         switch (substream->stream) {
1876         case SNDRV_PCM_STREAM_PLAYBACK:
1877                 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1878                 if (ret) {
1879                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1880                                 params_rate(params));
1881                         return ret;
1882                 }
1883                 switch (params_width(params)) {
1884                 case 16 ... 24:
1885                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1886                         break;
1887                 default:
1888                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1889                                 __func__, params_width(params));
1890                         return -EINVAL;
1891                 }
1892                 break;
1893
1894         case SNDRV_PCM_STREAM_CAPTURE:
1895                 switch (params_rate(params)) {
1896                 case 8000:
1897                         tx_fs_rate = 0;
1898                         break;
1899                 case 16000:
1900                         tx_fs_rate = 1;
1901                         break;
1902                 case 32000:
1903                         tx_fs_rate = 3;
1904                         break;
1905                 case 48000:
1906                         tx_fs_rate = 4;
1907                         break;
1908                 case 96000:
1909                         tx_fs_rate = 5;
1910                         break;
1911                 case 192000:
1912                         tx_fs_rate = 6;
1913                         break;
1914                 case 384000:
1915                         tx_fs_rate = 7;
1916                         break;
1917                 default:
1918                         dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1919                                 __func__, params_rate(params));
1920                         return -EINVAL;
1921
1922                 }
1923
1924                 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1925                                                 params_rate(params));
1926                 if (ret < 0) {
1927                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1928                         return ret;
1929                 }
1930                 switch (params_width(params)) {
1931                 case 16 ... 32:
1932                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1933                         break;
1934                 default:
1935                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1936                                 __func__, params_width(params));
1937                         return -EINVAL;
1938                 }
1939                 break;
1940         default:
1941                 dev_err(wcd->dev, "Invalid stream type %d\n",
1942                         substream->stream);
1943                 return -EINVAL;
1944         }
1945
1946         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1947         wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1948
1949         return 0;
1950 }
1951
1952 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1953                            struct snd_soc_dai *dai)
1954 {
1955         struct wcd_slim_codec_dai_data *dai_data;
1956         struct wcd9335_codec *wcd;
1957         struct slim_stream_config *cfg;
1958
1959         wcd = snd_soc_component_get_drvdata(dai->component);
1960
1961         dai_data = &wcd->dai[dai->id];
1962
1963         switch (cmd) {
1964         case SNDRV_PCM_TRIGGER_START:
1965         case SNDRV_PCM_TRIGGER_RESUME:
1966         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967                 cfg = &dai_data->sconfig;
1968                 slim_stream_prepare(dai_data->sruntime, cfg);
1969                 slim_stream_enable(dai_data->sruntime);
1970                 break;
1971         case SNDRV_PCM_TRIGGER_STOP:
1972         case SNDRV_PCM_TRIGGER_SUSPEND:
1973         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1974                 slim_stream_disable(dai_data->sruntime);
1975                 slim_stream_unprepare(dai_data->sruntime);
1976                 break;
1977         default:
1978                 break;
1979         }
1980
1981         return 0;
1982 }
1983
1984 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1985                                    unsigned int tx_num, unsigned int *tx_slot,
1986                                    unsigned int rx_num, unsigned int *rx_slot)
1987 {
1988         struct wcd9335_codec *wcd;
1989         int i;
1990
1991         wcd = snd_soc_component_get_drvdata(dai->component);
1992
1993         if (!tx_slot || !rx_slot) {
1994                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1995                         tx_slot, rx_slot);
1996                 return -EINVAL;
1997         }
1998
1999         wcd->num_rx_port = rx_num;
2000         for (i = 0; i < rx_num; i++) {
2001                 wcd->rx_chs[i].ch_num = rx_slot[i];
2002                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2003         }
2004
2005         wcd->num_tx_port = tx_num;
2006         for (i = 0; i < tx_num; i++) {
2007                 wcd->tx_chs[i].ch_num = tx_slot[i];
2008                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2009         }
2010
2011         return 0;
2012 }
2013
2014 static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
2015                                    unsigned int *tx_num, unsigned int *tx_slot,
2016                                    unsigned int *rx_num, unsigned int *rx_slot)
2017 {
2018         struct wcd9335_slim_ch *ch;
2019         struct wcd9335_codec *wcd;
2020         int i = 0;
2021
2022         wcd = snd_soc_component_get_drvdata(dai->component);
2023
2024         switch (dai->id) {
2025         case AIF1_PB:
2026         case AIF2_PB:
2027         case AIF3_PB:
2028         case AIF4_PB:
2029                 if (!rx_slot || !rx_num) {
2030                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2031                                 rx_slot, rx_num);
2032                         return -EINVAL;
2033                 }
2034
2035                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2036                         rx_slot[i++] = ch->ch_num;
2037
2038                 *rx_num = i;
2039                 break;
2040         case AIF1_CAP:
2041         case AIF2_CAP:
2042         case AIF3_CAP:
2043                 if (!tx_slot || !tx_num) {
2044                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2045                                 tx_slot, tx_num);
2046                         return -EINVAL;
2047                 }
2048                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2049                         tx_slot[i++] = ch->ch_num;
2050
2051                 *tx_num = i;
2052                 break;
2053         default:
2054                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2055                 break;
2056         }
2057
2058         return 0;
2059 }
2060
2061 static struct snd_soc_dai_ops wcd9335_dai_ops = {
2062         .hw_params = wcd9335_hw_params,
2063         .trigger = wcd9335_trigger,
2064         .set_channel_map = wcd9335_set_channel_map,
2065         .get_channel_map = wcd9335_get_channel_map,
2066 };
2067
2068 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2069         [0] = {
2070                 .name = "wcd9335_rx1",
2071                 .id = AIF1_PB,
2072                 .playback = {
2073                         .stream_name = "AIF1 Playback",
2074                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2075                                  SNDRV_PCM_RATE_384000,
2076                         .formats = WCD9335_FORMATS_S16_S24_LE,
2077                         .rate_max = 384000,
2078                         .rate_min = 8000,
2079                         .channels_min = 1,
2080                         .channels_max = 2,
2081                 },
2082                 .ops = &wcd9335_dai_ops,
2083         },
2084         [1] = {
2085                 .name = "wcd9335_tx1",
2086                 .id = AIF1_CAP,
2087                 .capture = {
2088                         .stream_name = "AIF1 Capture",
2089                         .rates = WCD9335_RATES_MASK,
2090                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2091                         .rate_min = 8000,
2092                         .rate_max = 192000,
2093                         .channels_min = 1,
2094                         .channels_max = 4,
2095                 },
2096                 .ops = &wcd9335_dai_ops,
2097         },
2098         [2] = {
2099                 .name = "wcd9335_rx2",
2100                 .id = AIF2_PB,
2101                 .playback = {
2102                         .stream_name = "AIF2 Playback",
2103                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2104                                  SNDRV_PCM_RATE_384000,
2105                         .formats = WCD9335_FORMATS_S16_S24_LE,
2106                         .rate_min = 8000,
2107                         .rate_max = 384000,
2108                         .channels_min = 1,
2109                         .channels_max = 2,
2110                 },
2111                 .ops = &wcd9335_dai_ops,
2112         },
2113         [3] = {
2114                 .name = "wcd9335_tx2",
2115                 .id = AIF2_CAP,
2116                 .capture = {
2117                         .stream_name = "AIF2 Capture",
2118                         .rates = WCD9335_RATES_MASK,
2119                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2120                         .rate_min = 8000,
2121                         .rate_max = 192000,
2122                         .channels_min = 1,
2123                         .channels_max = 4,
2124                 },
2125                 .ops = &wcd9335_dai_ops,
2126         },
2127         [4] = {
2128                 .name = "wcd9335_rx3",
2129                 .id = AIF3_PB,
2130                 .playback = {
2131                         .stream_name = "AIF3 Playback",
2132                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2133                                  SNDRV_PCM_RATE_384000,
2134                         .formats = WCD9335_FORMATS_S16_S24_LE,
2135                         .rate_min = 8000,
2136                         .rate_max = 384000,
2137                         .channels_min = 1,
2138                         .channels_max = 2,
2139                 },
2140                 .ops = &wcd9335_dai_ops,
2141         },
2142         [5] = {
2143                 .name = "wcd9335_tx3",
2144                 .id = AIF3_CAP,
2145                 .capture = {
2146                         .stream_name = "AIF3 Capture",
2147                         .rates = WCD9335_RATES_MASK,
2148                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2149                         .rate_min = 8000,
2150                         .rate_max = 192000,
2151                         .channels_min = 1,
2152                         .channels_max = 4,
2153                 },
2154                 .ops = &wcd9335_dai_ops,
2155         },
2156         [6] = {
2157                 .name = "wcd9335_rx4",
2158                 .id = AIF4_PB,
2159                 .playback = {
2160                         .stream_name = "AIF4 Playback",
2161                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2162                                  SNDRV_PCM_RATE_384000,
2163                         .formats = WCD9335_FORMATS_S16_S24_LE,
2164                         .rate_min = 8000,
2165                         .rate_max = 384000,
2166                         .channels_min = 1,
2167                         .channels_max = 2,
2168                 },
2169                 .ops = &wcd9335_dai_ops,
2170         },
2171 };
2172
2173 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2174                                struct snd_ctl_elem_value *ucontrol)
2175 {
2176
2177         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2178         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2179         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2180
2181         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2182         return 0;
2183 }
2184
2185 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2186                                  struct snd_ctl_elem_value *ucontrol)
2187 {
2188         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2189         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2190         int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2191         int value = ucontrol->value.integer.value[0];
2192         int sel;
2193
2194         wcd->comp_enabled[comp] = value;
2195         sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2196                 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2197
2198         /* Any specific register configuration for compander */
2199         switch (comp) {
2200         case COMPANDER_1:
2201                 /* Set Gain Source Select based on compander enable/disable */
2202                 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2203                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2204                 break;
2205         case COMPANDER_2:
2206                 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2207                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2208                 break;
2209         case COMPANDER_5:
2210                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2211                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2212                 break;
2213         case COMPANDER_6:
2214                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2215                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2216                 break;
2217         default:
2218                 break;
2219         }
2220
2221         return 0;
2222 }
2223
2224 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2225                                  struct snd_ctl_elem_value *ucontrol)
2226 {
2227         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2228         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2229
2230         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2231
2232         return 0;
2233 }
2234
2235 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2236                                  struct snd_ctl_elem_value *ucontrol)
2237 {
2238         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2239         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2240         u32 mode_val;
2241
2242         mode_val = ucontrol->value.enumerated.item[0];
2243
2244         if (mode_val == 0) {
2245                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2246                 mode_val = CLS_H_HIFI;
2247         }
2248         wcd->hph_mode = mode_val;
2249
2250         return 0;
2251 }
2252
2253 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2254         /* -84dB min - 40dB max */
2255         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2256                         -84, 40, digital_gain),
2257         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2258                         -84, 40, digital_gain),
2259         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2260                         -84, 40, digital_gain),
2261         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2262                         -84, 40, digital_gain),
2263         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2264                         -84, 40, digital_gain),
2265         SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2266                         -84, 40, digital_gain),
2267         SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2268                         -84, 40, digital_gain),
2269         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2270                         -84, 40, digital_gain),
2271         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2272                         -84, 40, digital_gain),
2273         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2274                         -84, 40, digital_gain),
2275         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2276                         -84, 40, digital_gain),
2277         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2278                         -84, 40, digital_gain),
2279         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2280                         -84, 40, digital_gain),
2281         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2282                         -84, 40, digital_gain),
2283         SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2284                         -84, 40, digital_gain),
2285         SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2286                         -84, 40, digital_gain),
2287         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2288                         -84, 40, digital_gain),
2289         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2290                         -84, 40, digital_gain),
2291         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2292         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2293         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2294         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2295         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2296         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2297         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2298         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2299         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2300         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2301         SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2302         SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2303         SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2304         SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2305         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2306         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2307         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2308         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2309         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2310                        wcd9335_get_compander, wcd9335_set_compander),
2311         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2312                        wcd9335_get_compander, wcd9335_set_compander),
2313         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2314                        wcd9335_get_compander, wcd9335_set_compander),
2315         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2316                        wcd9335_get_compander, wcd9335_set_compander),
2317         SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2318                        wcd9335_get_compander, wcd9335_set_compander),
2319         SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2320                        wcd9335_get_compander, wcd9335_set_compander),
2321         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2322                        wcd9335_get_compander, wcd9335_set_compander),
2323         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2324                        wcd9335_get_compander, wcd9335_set_compander),
2325         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2326                        wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2327
2328         /* Gain Controls */
2329         SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2330                 ear_pa_gain),
2331         SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2332                 line_gain),
2333         SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2334                 line_gain),
2335         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2336                         3, 16, 1, line_gain),
2337         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2338                         3, 16, 1, line_gain),
2339         SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2340                         line_gain),
2341         SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2342                         line_gain),
2343
2344         SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2345                         analog_gain),
2346         SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2347                         analog_gain),
2348         SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2349                         analog_gain),
2350         SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2351                         analog_gain),
2352         SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2353                         analog_gain),
2354         SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2355                         analog_gain),
2356
2357         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2358         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2359         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2360         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2361         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2362         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2363         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2364         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2365         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2366 };
2367
2368 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2369         {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2370         {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2371         {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2372         {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2373         {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2374         {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2375         {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2376         {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2377
2378         {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2379         {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2380         {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2381         {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2382         {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2383         {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2384         {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2385         {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2386
2387         {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2388         {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2389         {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2390         {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2391         {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2392         {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2393         {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2394         {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2395
2396         {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2397         {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2398         {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2399         {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2400         {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2401         {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2402         {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2403         {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2404
2405         {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2406         {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2407         {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2408         {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2409         {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2410         {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2411         {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2412         {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2413
2414         WCD9335_INTERPOLATOR_PATH(0),
2415         WCD9335_INTERPOLATOR_PATH(1),
2416         WCD9335_INTERPOLATOR_PATH(2),
2417         WCD9335_INTERPOLATOR_PATH(3),
2418         WCD9335_INTERPOLATOR_PATH(4),
2419         WCD9335_INTERPOLATOR_PATH(5),
2420         WCD9335_INTERPOLATOR_PATH(6),
2421         WCD9335_INTERPOLATOR_PATH(7),
2422         WCD9335_INTERPOLATOR_PATH(8),
2423
2424         /* EAR PA */
2425         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2426         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2427         {"RX INT0 DAC", NULL, "RX_BIAS"},
2428         {"EAR PA", NULL, "RX INT0 DAC"},
2429         {"EAR", NULL, "EAR PA"},
2430
2431         /* HPHL */
2432         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2433         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2434         {"RX INT1 DAC", NULL, "RX_BIAS"},
2435         {"HPHL PA", NULL, "RX INT1 DAC"},
2436         {"HPHL", NULL, "HPHL PA"},
2437
2438         /* HPHR */
2439         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2440         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2441         {"RX INT2 DAC", NULL, "RX_BIAS"},
2442         {"HPHR PA", NULL, "RX INT2 DAC"},
2443         {"HPHR", NULL, "HPHR PA"},
2444
2445         /* LINEOUT1 */
2446         {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2447         {"RX INT3 DAC", NULL, "RX_BIAS"},
2448         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2449         {"LINEOUT1", NULL, "LINEOUT1 PA"},
2450
2451         /* LINEOUT2 */
2452         {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2453         {"RX INT4 DAC", NULL, "RX_BIAS"},
2454         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2455         {"LINEOUT2", NULL, "LINEOUT2 PA"},
2456
2457         /* LINEOUT3 */
2458         {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2459         {"RX INT5 DAC", NULL, "RX_BIAS"},
2460         {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2461         {"LINEOUT3", NULL, "LINEOUT3 PA"},
2462
2463         /* LINEOUT4 */
2464         {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2465         {"RX INT6 DAC", NULL, "RX_BIAS"},
2466         {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2467         {"LINEOUT4", NULL, "LINEOUT4 PA"},
2468
2469         /* SLIMBUS Connections */
2470         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2471         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2472         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2473
2474         /* ADC Mux */
2475         WCD9335_ADC_MUX_PATH(0),
2476         WCD9335_ADC_MUX_PATH(1),
2477         WCD9335_ADC_MUX_PATH(2),
2478         WCD9335_ADC_MUX_PATH(3),
2479         WCD9335_ADC_MUX_PATH(4),
2480         WCD9335_ADC_MUX_PATH(5),
2481         WCD9335_ADC_MUX_PATH(6),
2482         WCD9335_ADC_MUX_PATH(7),
2483         WCD9335_ADC_MUX_PATH(8),
2484
2485         /* ADC Connections */
2486         {"ADC1", NULL, "AMIC1"},
2487         {"ADC2", NULL, "AMIC2"},
2488         {"ADC3", NULL, "AMIC3"},
2489         {"ADC4", NULL, "AMIC4"},
2490         {"ADC5", NULL, "AMIC5"},
2491         {"ADC6", NULL, "AMIC6"},
2492 };
2493
2494 static int wcd9335_micbias_control(struct snd_soc_component *component,
2495                                    int micb_num, int req, bool is_dapm)
2496 {
2497         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2498         int micb_index = micb_num - 1;
2499         u16 micb_reg;
2500
2501         if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2502                 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2503                         micb_index);
2504                 return -EINVAL;
2505         }
2506
2507         switch (micb_num) {
2508         case MIC_BIAS_1:
2509                 micb_reg = WCD9335_ANA_MICB1;
2510                 break;
2511         case MIC_BIAS_2:
2512                 micb_reg = WCD9335_ANA_MICB2;
2513                 break;
2514         case MIC_BIAS_3:
2515                 micb_reg = WCD9335_ANA_MICB3;
2516                 break;
2517         case MIC_BIAS_4:
2518                 micb_reg = WCD9335_ANA_MICB4;
2519                 break;
2520         default:
2521                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2522                         __func__, micb_num);
2523                 return -EINVAL;
2524         }
2525
2526         switch (req) {
2527         case MICB_PULLUP_ENABLE:
2528                 wcd->pullup_ref[micb_index]++;
2529                 if ((wcd->pullup_ref[micb_index] == 1) &&
2530                     (wcd->micb_ref[micb_index] == 0))
2531                         snd_soc_component_update_bits(component, micb_reg,
2532                                                         0xC0, 0x80);
2533                 break;
2534         case MICB_PULLUP_DISABLE:
2535                 wcd->pullup_ref[micb_index]--;
2536                 if ((wcd->pullup_ref[micb_index] == 0) &&
2537                     (wcd->micb_ref[micb_index] == 0))
2538                         snd_soc_component_update_bits(component, micb_reg,
2539                                                         0xC0, 0x00);
2540                 break;
2541         case MICB_ENABLE:
2542                 wcd->micb_ref[micb_index]++;
2543                 if (wcd->micb_ref[micb_index] == 1)
2544                         snd_soc_component_update_bits(component, micb_reg,
2545                                                         0xC0, 0x40);
2546                 break;
2547         case MICB_DISABLE:
2548                 wcd->micb_ref[micb_index]--;
2549                 if ((wcd->micb_ref[micb_index] == 0) &&
2550                     (wcd->pullup_ref[micb_index] > 0))
2551                         snd_soc_component_update_bits(component, micb_reg,
2552                                                         0xC0, 0x80);
2553                 else if ((wcd->micb_ref[micb_index] == 0) &&
2554                          (wcd->pullup_ref[micb_index] == 0)) {
2555                         snd_soc_component_update_bits(component, micb_reg,
2556                                                         0xC0, 0x00);
2557                 }
2558                 break;
2559         }
2560
2561         return 0;
2562 }
2563
2564 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2565                                         int event)
2566 {
2567         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2568         int micb_num;
2569
2570         if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2571                 micb_num = MIC_BIAS_1;
2572         else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2573                 micb_num = MIC_BIAS_2;
2574         else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2575                 micb_num = MIC_BIAS_3;
2576         else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2577                 micb_num = MIC_BIAS_4;
2578         else
2579                 return -EINVAL;
2580
2581         switch (event) {
2582         case SND_SOC_DAPM_PRE_PMU:
2583                 /*
2584                  * MIC BIAS can also be requested by MBHC,
2585                  * so use ref count to handle micbias pullup
2586                  * and enable requests
2587                  */
2588                 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2589                 break;
2590         case SND_SOC_DAPM_POST_PMU:
2591                 /* wait for cnp time */
2592                 usleep_range(1000, 1100);
2593                 break;
2594         case SND_SOC_DAPM_POST_PMD:
2595                 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2596                 break;
2597         }
2598
2599         return 0;
2600 }
2601
2602 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2603                 struct snd_kcontrol *kc, int event)
2604 {
2605         return __wcd9335_codec_enable_micbias(w, event);
2606 }
2607
2608 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2609                                       u16 amic_reg, bool set)
2610 {
2611         u8 mask = 0x20;
2612         u8 val;
2613
2614         if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2615             amic_reg == WCD9335_ANA_AMIC5)
2616                 mask = 0x40;
2617
2618         val = set ? mask : 0x00;
2619
2620         switch (amic_reg) {
2621         case WCD9335_ANA_AMIC1:
2622         case WCD9335_ANA_AMIC2:
2623                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2624                                                 val);
2625                 break;
2626         case WCD9335_ANA_AMIC3:
2627         case WCD9335_ANA_AMIC4:
2628                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2629                                                 val);
2630                 break;
2631         case WCD9335_ANA_AMIC5:
2632         case WCD9335_ANA_AMIC6:
2633                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2634                                                 val);
2635                 break;
2636         default:
2637                 dev_err(comp->dev, "%s: invalid amic: %d\n",
2638                         __func__, amic_reg);
2639                 break;
2640         }
2641 }
2642
2643 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2644                 struct snd_kcontrol *kc, int event)
2645 {
2646         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2647
2648         switch (event) {
2649         case SND_SOC_DAPM_PRE_PMU:
2650                 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2651                 break;
2652         default:
2653                 break;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2660                                          int adc_mux_n)
2661 {
2662         int mux_sel, reg, mreg;
2663
2664         if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2665             adc_mux_n == WCD9335_INVALID_ADC_MUX)
2666                 return 0;
2667
2668         /* Check whether adc mux input is AMIC or DMIC */
2669         if (adc_mux_n < 4) {
2670                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2671                 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2672                 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2673         } else {
2674                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2675                 mreg = reg;
2676                 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2677         }
2678
2679         if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2680                 return 0;
2681
2682         return snd_soc_component_read(comp, mreg) & 0x07;
2683 }
2684
2685 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2686                                             int amic)
2687 {
2688         u16 pwr_level_reg = 0;
2689
2690         switch (amic) {
2691         case 1:
2692         case 2:
2693                 pwr_level_reg = WCD9335_ANA_AMIC1;
2694                 break;
2695
2696         case 3:
2697         case 4:
2698                 pwr_level_reg = WCD9335_ANA_AMIC3;
2699                 break;
2700
2701         case 5:
2702         case 6:
2703                 pwr_level_reg = WCD9335_ANA_AMIC5;
2704                 break;
2705         default:
2706                 dev_err(comp->dev, "invalid amic: %d\n", amic);
2707                 break;
2708         }
2709
2710         return pwr_level_reg;
2711 }
2712
2713 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2714         struct snd_kcontrol *kc, int event)
2715 {
2716         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2717         unsigned int decimator;
2718         char *dec_adc_mux_name = NULL;
2719         char *widget_name = NULL;
2720         char *wname;
2721         int ret = 0, amic_n;
2722         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2723         u16 tx_gain_ctl_reg;
2724         char *dec;
2725         u8 hpf_coff_freq;
2726
2727         widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
2728         if (!widget_name)
2729                 return -ENOMEM;
2730
2731         wname = widget_name;
2732         dec_adc_mux_name = strsep(&widget_name, " ");
2733         if (!dec_adc_mux_name) {
2734                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2735                         __func__, w->name);
2736                 ret =  -EINVAL;
2737                 goto out;
2738         }
2739         dec_adc_mux_name = widget_name;
2740
2741         dec = strpbrk(dec_adc_mux_name, "012345678");
2742         if (!dec) {
2743                 dev_err(comp->dev, "%s: decimator index not found\n",
2744                         __func__);
2745                 ret =  -EINVAL;
2746                 goto out;
2747         }
2748
2749         ret = kstrtouint(dec, 10, &decimator);
2750         if (ret < 0) {
2751                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2752                         __func__, wname);
2753                 ret =  -EINVAL;
2754                 goto out;
2755         }
2756
2757         tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2758         hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2759         dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2760         tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2761
2762         switch (event) {
2763         case SND_SOC_DAPM_PRE_PMU:
2764                 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2765                 if (amic_n)
2766                         pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2767                                                                        amic_n);
2768
2769                 if (pwr_level_reg) {
2770                         switch ((snd_soc_component_read(comp, pwr_level_reg) &
2771                                               WCD9335_AMIC_PWR_LVL_MASK) >>
2772                                               WCD9335_AMIC_PWR_LVL_SHIFT) {
2773                         case WCD9335_AMIC_PWR_LEVEL_LP:
2774                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2775                                                     WCD9335_DEC_PWR_LVL_MASK,
2776                                                     WCD9335_DEC_PWR_LVL_LP);
2777                                 break;
2778
2779                         case WCD9335_AMIC_PWR_LEVEL_HP:
2780                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2781                                                     WCD9335_DEC_PWR_LVL_MASK,
2782                                                     WCD9335_DEC_PWR_LVL_HP);
2783                                 break;
2784                         case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2785                         default:
2786                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2787                                                     WCD9335_DEC_PWR_LVL_MASK,
2788                                                     WCD9335_DEC_PWR_LVL_DF);
2789                                 break;
2790                         }
2791                 }
2792                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2793                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2794
2795                 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2796                         snd_soc_component_update_bits(comp, dec_cfg_reg,
2797                                             TX_HPF_CUT_OFF_FREQ_MASK,
2798                                             CF_MIN_3DB_150HZ << 5);
2799                 /* Enable TX PGA Mute */
2800                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2801                                                 0x10, 0x10);
2802                 /* Enable APC */
2803                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2804                 break;
2805         case SND_SOC_DAPM_POST_PMU:
2806                 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2807
2808                 if (decimator == 0) {
2809                         snd_soc_component_write(comp,
2810                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2811                         snd_soc_component_write(comp,
2812                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2813                         snd_soc_component_write(comp,
2814                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2815                         snd_soc_component_write(comp,
2816                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2817                 }
2818
2819                 snd_soc_component_update_bits(comp, hpf_gate_reg,
2820                                                 0x01, 0x01);
2821                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2822                                                 0x10, 0x00);
2823                 snd_soc_component_write(comp, tx_gain_ctl_reg,
2824                               snd_soc_component_read(comp, tx_gain_ctl_reg));
2825                 break;
2826         case SND_SOC_DAPM_PRE_PMD:
2827                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2828                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2829                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2830                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2831                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2832                         snd_soc_component_update_bits(comp, dec_cfg_reg,
2833                                                       TX_HPF_CUT_OFF_FREQ_MASK,
2834                                                       hpf_coff_freq << 5);
2835                 }
2836                 break;
2837         case SND_SOC_DAPM_POST_PMD:
2838                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2839                 break;
2840         }
2841 out:
2842         kfree(wname);
2843         return ret;
2844 }
2845
2846 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2847                                  u32 mclk_rate, u32 dmic_clk_rate)
2848 {
2849         u32 div_factor;
2850         u8 dmic_ctl_val;
2851
2852         dev_err(component->dev,
2853                 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
2854                 __func__, mclk_rate, dmic_clk_rate);
2855
2856         /* Default value to return in case of error */
2857         if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2858                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2859         else
2860                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2861
2862         if (dmic_clk_rate == 0) {
2863                 dev_err(component->dev,
2864                         "%s: dmic_sample_rate cannot be 0\n",
2865                         __func__);
2866                 goto done;
2867         }
2868
2869         div_factor = mclk_rate / dmic_clk_rate;
2870         switch (div_factor) {
2871         case 2:
2872                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2873                 break;
2874         case 3:
2875                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2876                 break;
2877         case 4:
2878                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
2879                 break;
2880         case 6:
2881                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
2882                 break;
2883         case 8:
2884                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
2885                 break;
2886         case 16:
2887                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
2888                 break;
2889         default:
2890                 dev_err(component->dev,
2891                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
2892                         __func__, div_factor, mclk_rate, dmic_clk_rate);
2893                 break;
2894         }
2895
2896 done:
2897         return dmic_ctl_val;
2898 }
2899
2900 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2901                 struct snd_kcontrol *kc, int event)
2902 {
2903         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2904         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2905         u8  dmic_clk_en = 0x01;
2906         u16 dmic_clk_reg;
2907         s32 *dmic_clk_cnt;
2908         u8 dmic_rate_val, dmic_rate_shift = 1;
2909         unsigned int dmic;
2910         int ret;
2911         char *wname;
2912
2913         wname = strpbrk(w->name, "012345");
2914         if (!wname) {
2915                 dev_err(comp->dev, "%s: widget not found\n", __func__);
2916                 return -EINVAL;
2917         }
2918
2919         ret = kstrtouint(wname, 10, &dmic);
2920         if (ret < 0) {
2921                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2922                         __func__);
2923                 return -EINVAL;
2924         }
2925
2926         switch (dmic) {
2927         case 0:
2928         case 1:
2929                 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2930                 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2931                 break;
2932         case 2:
2933         case 3:
2934                 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2935                 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2936                 break;
2937         case 4:
2938         case 5:
2939                 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2940                 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2941                 break;
2942         default:
2943                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2944                         __func__);
2945                 return -EINVAL;
2946         }
2947
2948         switch (event) {
2949         case SND_SOC_DAPM_PRE_PMU:
2950                 dmic_rate_val =
2951                         wcd9335_get_dmic_clk_val(comp,
2952                                         wcd->mclk_rate,
2953                                         wcd->dmic_sample_rate);
2954
2955                 (*dmic_clk_cnt)++;
2956                 if (*dmic_clk_cnt == 1) {
2957                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2958                                 0x07 << dmic_rate_shift,
2959                                 dmic_rate_val << dmic_rate_shift);
2960                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2961                                         dmic_clk_en, dmic_clk_en);
2962                 }
2963
2964                 break;
2965         case SND_SOC_DAPM_POST_PMD:
2966                 dmic_rate_val =
2967                         wcd9335_get_dmic_clk_val(comp,
2968                                         wcd->mclk_rate,
2969                                         wcd->mad_dmic_sample_rate);
2970                 (*dmic_clk_cnt)--;
2971                 if (*dmic_clk_cnt  == 0) {
2972                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2973                                         dmic_clk_en, 0);
2974                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2975                                 0x07 << dmic_rate_shift,
2976                                 dmic_rate_val << dmic_rate_shift);
2977                 }
2978                 break;
2979         }
2980
2981         return 0;
2982 }
2983
2984 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2985                                         struct snd_soc_component *component)
2986 {
2987         int port_num = 0;
2988         unsigned short reg = 0;
2989         unsigned int val = 0;
2990         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2991         struct wcd9335_slim_ch *ch;
2992
2993         list_for_each_entry(ch, &dai->slim_ch_list, list) {
2994                 if (ch->port >= WCD9335_RX_START) {
2995                         port_num = ch->port - WCD9335_RX_START;
2996                         reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
2997                 } else {
2998                         port_num = ch->port;
2999                         reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3000                 }
3001
3002                 regmap_read(wcd->if_regmap, reg, &val);
3003                 if (!(val & BIT(port_num % 8)))
3004                         regmap_write(wcd->if_regmap, reg,
3005                                         val | BIT(port_num % 8));
3006         }
3007 }
3008
3009 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
3010                                        struct snd_kcontrol *kc,
3011                                        int event)
3012 {
3013         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3014         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
3015         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3016
3017         switch (event) {
3018         case SND_SOC_DAPM_POST_PMU:
3019                 wcd9335_codec_enable_int_port(dai, comp);
3020                 break;
3021         case SND_SOC_DAPM_POST_PMD:
3022                 kfree(dai->sconfig.chs);
3023
3024                 break;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3031                 struct snd_kcontrol *kc, int event)
3032 {
3033         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3034         u16 gain_reg;
3035         int offset_val = 0;
3036         int val = 0;
3037
3038         switch (w->reg) {
3039         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3040                 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
3041                 break;
3042         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3043                 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
3044                 break;
3045         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3046                 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
3047                 break;
3048         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3049                 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3050                 break;
3051         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3052                 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3053                 break;
3054         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3055                 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3056                 break;
3057         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3058                 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3059                 break;
3060         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3061                 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3062                 break;
3063         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3064                 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3065                 break;
3066         default:
3067                 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3068                         __func__, w->name);
3069                 return 0;
3070         }
3071
3072         switch (event) {
3073         case SND_SOC_DAPM_POST_PMU:
3074                 val = snd_soc_component_read(comp, gain_reg);
3075                 val += offset_val;
3076                 snd_soc_component_write(comp, gain_reg, val);
3077                 break;
3078         case SND_SOC_DAPM_POST_PMD:
3079                 break;
3080         }
3081
3082         return 0;
3083 }
3084
3085 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3086 {
3087         u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3088
3089         switch (reg) {
3090         case WCD9335_CDC_RX0_RX_PATH_CTL:
3091         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3092                 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3093                 *ind = 0;
3094                 break;
3095         case WCD9335_CDC_RX1_RX_PATH_CTL:
3096         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3097                 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3098                 *ind = 1;
3099                 break;
3100         case WCD9335_CDC_RX2_RX_PATH_CTL:
3101         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3102                 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3103                 *ind = 2;
3104                 break;
3105         case WCD9335_CDC_RX3_RX_PATH_CTL:
3106         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3107                 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3108                 *ind = 3;
3109                 break;
3110         case WCD9335_CDC_RX4_RX_PATH_CTL:
3111         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3112                 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3113                 *ind = 4;
3114                 break;
3115         case WCD9335_CDC_RX5_RX_PATH_CTL:
3116         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3117                 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3118                 *ind = 5;
3119                 break;
3120         case WCD9335_CDC_RX6_RX_PATH_CTL:
3121         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3122                 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3123                 *ind = 6;
3124                 break;
3125         case WCD9335_CDC_RX7_RX_PATH_CTL:
3126         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3127                 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3128                 *ind = 7;
3129                 break;
3130         case WCD9335_CDC_RX8_RX_PATH_CTL:
3131         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3132                 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3133                 *ind = 8;
3134                 break;
3135         }
3136
3137         return prim_int_reg;
3138 }
3139
3140 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3141                                     u16 prim_int_reg, int event)
3142 {
3143         u16 hd2_scale_reg;
3144         u16 hd2_enable_reg = 0;
3145
3146         if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3147                 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3148                 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3149         }
3150         if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3151                 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3152                 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3153         }
3154
3155         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3156                 snd_soc_component_update_bits(component, hd2_scale_reg,
3157                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3158                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3159                 snd_soc_component_update_bits(component, hd2_scale_reg,
3160                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3161                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3162                 snd_soc_component_update_bits(component, hd2_enable_reg,
3163                                 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3164                                 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3165         }
3166
3167         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3168                 snd_soc_component_update_bits(component, hd2_enable_reg,
3169                                         WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3170                                         WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3171                 snd_soc_component_update_bits(component, hd2_scale_reg,
3172                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3173                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3174                 snd_soc_component_update_bits(component, hd2_scale_reg,
3175                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3176                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3177         }
3178 }
3179
3180 static int wcd9335_codec_enable_prim_interpolator(
3181                                                 struct snd_soc_component *comp,
3182                                                 u16 reg, int event)
3183 {
3184         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3185         u16 ind = 0;
3186         int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3187
3188         switch (event) {
3189         case SND_SOC_DAPM_PRE_PMU:
3190                 wcd->prim_int_users[ind]++;
3191                 if (wcd->prim_int_users[ind] == 1) {
3192                         snd_soc_component_update_bits(comp, prim_int_reg,
3193                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3194                                         WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3195                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3196                         snd_soc_component_update_bits(comp, prim_int_reg,
3197                                         WCD9335_CDC_RX_CLK_EN_MASK,
3198                                         WCD9335_CDC_RX_CLK_ENABLE);
3199                 }
3200
3201                 if ((reg != prim_int_reg) &&
3202                         ((snd_soc_component_read(comp, prim_int_reg)) &
3203                          WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3204                         snd_soc_component_update_bits(comp, reg,
3205                                                 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3206                                                 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3207                 break;
3208         case SND_SOC_DAPM_POST_PMD:
3209                 wcd->prim_int_users[ind]--;
3210                 if (wcd->prim_int_users[ind] == 0) {
3211                         snd_soc_component_update_bits(comp, prim_int_reg,
3212                                         WCD9335_CDC_RX_CLK_EN_MASK,
3213                                         WCD9335_CDC_RX_CLK_DISABLE);
3214                         snd_soc_component_update_bits(comp, prim_int_reg,
3215                                         WCD9335_CDC_RX_RESET_MASK,
3216                                         WCD9335_CDC_RX_RESET_ENABLE);
3217                         snd_soc_component_update_bits(comp, prim_int_reg,
3218                                         WCD9335_CDC_RX_RESET_MASK,
3219                                         WCD9335_CDC_RX_RESET_DISABLE);
3220                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3221                 }
3222                 break;
3223         }
3224
3225         return 0;
3226 }
3227
3228 static int wcd9335_config_compander(struct snd_soc_component *component,
3229                                     int interp_n, int event)
3230 {
3231         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3232         int comp;
3233         u16 comp_ctl0_reg, rx_path_cfg0_reg;
3234
3235         /* EAR does not have compander */
3236         if (!interp_n)
3237                 return 0;
3238
3239         comp = interp_n - 1;
3240         if (!wcd->comp_enabled[comp])
3241                 return 0;
3242
3243         comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3244         rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3245
3246         if (SND_SOC_DAPM_EVENT_ON(event)) {
3247                 /* Enable Compander Clock */
3248                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3249                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3250                                         WCD9335_CDC_COMPANDER_CLK_ENABLE);
3251                 /* Reset comander */
3252                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3253                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3254                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3255                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3256                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3257                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3258                 /* Enables DRE in this path */
3259                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3260                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3261                                         WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3262         }
3263
3264         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3265                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3266                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3267                                         WCD9335_CDC_COMPANDER_HALT);
3268                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3269                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3270                                         WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3271
3272                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3273                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3274                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3275                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3276                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3277                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3278                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3279                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3280                                         WCD9335_CDC_COMPANDER_CLK_DISABLE);
3281                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3282                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3283                                         WCD9335_CDC_COMPANDER_NOHALT);
3284         }
3285
3286         return 0;
3287 }
3288
3289 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3290                 struct snd_kcontrol *kc, int event)
3291 {
3292         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3293         u16 gain_reg;
3294         u16 reg;
3295         int val;
3296         int offset_val = 0;
3297
3298         if (!(strcmp(w->name, "RX INT0 INTERP"))) {
3299                 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3300                 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3301         } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
3302                 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3303                 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3304         } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
3305                 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3306                 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3307         } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
3308                 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3309                 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3310         } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
3311                 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3312                 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3313         } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
3314                 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3315                 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3316         } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
3317                 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3318                 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3319         } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
3320                 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3321                 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3322         } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
3323                 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3324                 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3325         } else {
3326                 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3327                         __func__);
3328                 return -EINVAL;
3329         }
3330
3331         switch (event) {
3332         case SND_SOC_DAPM_PRE_PMU:
3333                 /* Reset if needed */
3334                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3335                 break;
3336         case SND_SOC_DAPM_POST_PMU:
3337                 wcd9335_config_compander(comp, w->shift, event);
3338                 val = snd_soc_component_read(comp, gain_reg);
3339                 val += offset_val;
3340                 snd_soc_component_write(comp, gain_reg, val);
3341                 break;
3342         case SND_SOC_DAPM_POST_PMD:
3343                 wcd9335_config_compander(comp, w->shift, event);
3344                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3345                 break;
3346         }
3347
3348         return 0;
3349 }
3350
3351 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3352                                             u8 gain)
3353 {
3354         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3355         u8 hph_l_en, hph_r_en;
3356         u8 l_val, r_val;
3357         u8 hph_pa_status;
3358         bool is_hphl_pa, is_hphr_pa;
3359
3360         hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3361         is_hphl_pa = hph_pa_status >> 7;
3362         is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3363
3364         hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3365         hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3366
3367         l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3368         r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3369
3370         /*
3371          * Set HPH_L & HPH_R gain source selection to REGISTER
3372          * for better click and pop only if corresponding PAs are
3373          * not enabled. Also cache the values of the HPHL/R
3374          * PA gains to be applied after PAs are enabled
3375          */
3376         if ((l_val != hph_l_en) && !is_hphl_pa) {
3377                 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3378                 wcd->hph_l_gain = hph_l_en & 0x1F;
3379         }
3380
3381         if ((r_val != hph_r_en) && !is_hphr_pa) {
3382                 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3383                 wcd->hph_r_gain = hph_r_en & 0x1F;
3384         }
3385 }
3386
3387 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3388                                           int event)
3389 {
3390         if (SND_SOC_DAPM_EVENT_ON(event)) {
3391                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3392                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3393                                         0x06);
3394                 snd_soc_component_update_bits(comp,
3395                                         WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3396                                         0xF0, 0x40);
3397                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3398                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3399                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3400                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3401                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3402                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3403                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3404                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3405                                 0x0C);
3406                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3407         }
3408
3409         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3410                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3411                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3412                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3413                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3414                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3415                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3416                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3417                                         0x8A);
3418                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3419                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3420                                         0x0A);
3421         }
3422 }
3423
3424 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3425                                       int event)
3426 {
3427         if (SND_SOC_DAPM_EVENT_ON(event)) {
3428                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3429                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3430                                 0x0C);
3431                 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3432                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3433                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3434                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3435                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3436                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3437                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3438                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3439                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3440                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3441                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3442                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3443                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3444                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3445                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3446                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3447                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3448                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3449                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3450                 snd_soc_component_update_bits(comp,
3451                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3452                 snd_soc_component_update_bits(comp,
3453                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3454         }
3455
3456         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3457                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3458                                         0x88);
3459                 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3460                                         0x33);
3461                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3462                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3463                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3464                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3465                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3466                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3467                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3468                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3469                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3470                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3471                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3472                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3473                 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3474                                 WCD9335_HPH_CONST_SEL_L_MASK,
3475                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3476                 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3477                                 WCD9335_HPH_CONST_SEL_L_MASK,
3478                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3479         }
3480 }
3481
3482 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3483                                         int event)
3484 {
3485         if (SND_SOC_DAPM_EVENT_ON(event)) {
3486                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3487                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3488                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3489                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3490                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3491                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3492                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3493                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3494                                 0x0C);
3495                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3496         }
3497
3498         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3499                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3500                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3501                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3502                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3503                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3504                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3505         }
3506 }
3507
3508 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3509                                           int event, int mode)
3510 {
3511         switch (mode) {
3512         case CLS_H_LP:
3513                 wcd9335_codec_hph_lp_config(component, event);
3514                 break;
3515         case CLS_H_LOHIFI:
3516                 wcd9335_codec_hph_lohifi_config(component, event);
3517                 break;
3518         case CLS_H_HIFI:
3519                 wcd9335_codec_hph_hifi_config(component, event);
3520                 break;
3521         }
3522 }
3523
3524 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3525                                         struct snd_kcontrol *kc,
3526                                         int event)
3527 {
3528         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3529         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3530         int hph_mode = wcd->hph_mode;
3531         u8 dem_inp;
3532
3533         switch (event) {
3534         case SND_SOC_DAPM_PRE_PMU:
3535                 /* Read DEM INP Select */
3536                 dem_inp = snd_soc_component_read(comp,
3537                                 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3538                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3539                                 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3540                         dev_err(comp->dev, "Incorrect DEM Input\n");
3541                         return -EINVAL;
3542                 }
3543                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3544                                         WCD_CLSH_STATE_HPHL,
3545                                         ((hph_mode == CLS_H_LOHIFI) ?
3546                                          CLS_H_HIFI : hph_mode));
3547
3548                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3549
3550                 break;
3551         case SND_SOC_DAPM_POST_PMU:
3552                 usleep_range(1000, 1100);
3553                 break;
3554         case SND_SOC_DAPM_PRE_PMD:
3555                 break;
3556         case SND_SOC_DAPM_POST_PMD:
3557                 /* 1000us required as per HW requirement */
3558                 usleep_range(1000, 1100);
3559
3560                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3561                                 WCD_CLSH_STATE_HPHR))
3562                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3563
3564                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3565                                 WCD_CLSH_STATE_HPHL,
3566                                 ((hph_mode == CLS_H_LOHIFI) ?
3567                                  CLS_H_HIFI : hph_mode));
3568                 break;
3569         }
3570
3571         return 0;
3572 }
3573
3574 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3575                                            struct snd_kcontrol *kc, int event)
3576 {
3577         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3578         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3579
3580         switch (event) {
3581         case SND_SOC_DAPM_PRE_PMU:
3582                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3583                                         WCD_CLSH_STATE_LO, CLS_AB);
3584                 break;
3585         case SND_SOC_DAPM_POST_PMD:
3586                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3587                                         WCD_CLSH_STATE_LO, CLS_AB);
3588                 break;
3589         }
3590
3591         return 0;
3592 }
3593
3594 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3595                                        struct snd_kcontrol *kc, int event)
3596 {
3597         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3598         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3599
3600         switch (event) {
3601         case SND_SOC_DAPM_PRE_PMU:
3602                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3603                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3604
3605                 break;
3606         case SND_SOC_DAPM_POST_PMD:
3607                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3608                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3609                 break;
3610         }
3611
3612         return 0;
3613 }
3614
3615 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3616                                              int mode, int event)
3617 {
3618         u8 scale_val = 0;
3619
3620         switch (event) {
3621         case SND_SOC_DAPM_POST_PMU:
3622                 switch (mode) {
3623                 case CLS_H_HIFI:
3624                         scale_val = 0x3;
3625                         break;
3626                 case CLS_H_LOHIFI:
3627                         scale_val = 0x1;
3628                         break;
3629                 }
3630                 break;
3631         case SND_SOC_DAPM_PRE_PMD:
3632                 scale_val = 0x6;
3633                 break;
3634         }
3635
3636         if (scale_val)
3637                 snd_soc_component_update_bits(wcd->component,
3638                                         WCD9335_HPH_PA_CTL1,
3639                                         WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3640                                         scale_val << 1);
3641         if (SND_SOC_DAPM_EVENT_ON(event)) {
3642                 if (wcd->comp_enabled[COMPANDER_1] ||
3643                     wcd->comp_enabled[COMPANDER_2]) {
3644                         /* GAIN Source Selection */
3645                         snd_soc_component_update_bits(wcd->component,
3646                                         WCD9335_HPH_L_EN,
3647                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3648                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3649                         snd_soc_component_update_bits(wcd->component,
3650                                         WCD9335_HPH_R_EN,
3651                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3652                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3653                         snd_soc_component_update_bits(wcd->component,
3654                                         WCD9335_HPH_AUTO_CHOP,
3655                                         WCD9335_HPH_AUTO_CHOP_MASK,
3656                                         WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3657                 }
3658                 snd_soc_component_update_bits(wcd->component,
3659                                                 WCD9335_HPH_L_EN,
3660                                                 WCD9335_HPH_PA_GAIN_MASK,
3661                                                 wcd->hph_l_gain);
3662                 snd_soc_component_update_bits(wcd->component,
3663                                                 WCD9335_HPH_R_EN,
3664                                                 WCD9335_HPH_PA_GAIN_MASK,
3665                                                 wcd->hph_r_gain);
3666         }
3667
3668         if (SND_SOC_DAPM_EVENT_OFF(event))
3669                 snd_soc_component_update_bits(wcd->component,
3670                                 WCD9335_HPH_AUTO_CHOP,
3671                                 WCD9335_HPH_AUTO_CHOP_MASK,
3672                                 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3673 }
3674
3675 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3676                                       struct snd_kcontrol *kc,
3677                                       int event)
3678 {
3679         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3680         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3681         int hph_mode = wcd->hph_mode;
3682         u8 dem_inp;
3683
3684         switch (event) {
3685         case SND_SOC_DAPM_PRE_PMU:
3686
3687                 /* Read DEM INP Select */
3688                 dem_inp = snd_soc_component_read(comp,
3689                                 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3690                                 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3691                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3692                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3693                         dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3694                                 hph_mode);
3695                         return -EINVAL;
3696                 }
3697
3698                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3699                              WCD_CLSH_EVENT_PRE_DAC,
3700                              WCD_CLSH_STATE_HPHR,
3701                              ((hph_mode == CLS_H_LOHIFI) ?
3702                                CLS_H_HIFI : hph_mode));
3703
3704                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3705
3706                 break;
3707         case SND_SOC_DAPM_POST_PMD:
3708                 /* 1000us required as per HW requirement */
3709                 usleep_range(1000, 1100);
3710
3711                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3712                                         WCD_CLSH_STATE_HPHL))
3713                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3714
3715                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3716                              WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3717                                                 CLS_H_HIFI : hph_mode));
3718                 break;
3719         }
3720
3721         return 0;
3722 }
3723
3724 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3725                                       struct snd_kcontrol *kc,
3726                                       int event)
3727 {
3728         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3729         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3730         int hph_mode = wcd->hph_mode;
3731
3732         switch (event) {
3733         case SND_SOC_DAPM_PRE_PMU:
3734                 break;
3735         case SND_SOC_DAPM_POST_PMU:
3736                 /*
3737                  * 7ms sleep is required after PA is enabled as per
3738                  * HW requirement
3739                  */
3740                 usleep_range(7000, 7100);
3741
3742                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3743                 snd_soc_component_update_bits(comp,
3744                                         WCD9335_CDC_RX1_RX_PATH_CTL,
3745                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3746                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3747
3748                 /* Remove mix path mute if it is enabled */
3749                 if ((snd_soc_component_read(comp,
3750                                         WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3751                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3752                         snd_soc_component_update_bits(comp,
3753                                             WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3754                                             WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3755                                             WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3756
3757                 break;
3758         case SND_SOC_DAPM_PRE_PMD:
3759                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3760                 break;
3761         case SND_SOC_DAPM_POST_PMD:
3762                 /* 5ms sleep is required after PA is disabled as per
3763                  * HW requirement
3764                  */
3765                 usleep_range(5000, 5500);
3766                 break;
3767         }
3768
3769         return 0;
3770 }
3771
3772 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3773                                          struct snd_kcontrol *kc,
3774                                          int event)
3775 {
3776         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3777         int vol_reg = 0, mix_vol_reg = 0;
3778
3779         if (w->reg == WCD9335_ANA_LO_1_2) {
3780                 if (w->shift == 7) {
3781                         vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3782                         mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3783                 } else if (w->shift == 6) {
3784                         vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3785                         mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3786                 }
3787         } else if (w->reg == WCD9335_ANA_LO_3_4) {
3788                 if (w->shift == 7) {
3789                         vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3790                         mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3791                 } else if (w->shift == 6) {
3792                         vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3793                         mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3794                 }
3795         } else {
3796                 dev_err(comp->dev, "Error enabling lineout PA\n");
3797                 return -EINVAL;
3798         }
3799
3800         switch (event) {
3801         case SND_SOC_DAPM_POST_PMU:
3802                 /* 5ms sleep is required after PA is enabled as per
3803                  * HW requirement
3804                  */
3805                 usleep_range(5000, 5500);
3806                 snd_soc_component_update_bits(comp, vol_reg,
3807                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3808                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3809
3810                 /* Remove mix path mute if it is enabled */
3811                 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3812                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3813                         snd_soc_component_update_bits(comp,  mix_vol_reg,
3814                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3815                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3816                 break;
3817         case SND_SOC_DAPM_POST_PMD:
3818                 /* 5ms sleep is required after PA is disabled as per
3819                  * HW requirement
3820                  */
3821                 usleep_range(5000, 5500);
3822                 break;
3823         }
3824
3825         return 0;
3826 }
3827
3828 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3829 {
3830         snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3831                                         WCD9335_HPH_CONST_SEL_L_MASK,
3832                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3833         snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3834                                         WCD9335_HPH_CONST_SEL_L_MASK,
3835                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3836         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3837                                         WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3838                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3839         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3840                                         WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3841                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3842 }
3843
3844 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3845                 struct snd_kcontrol *kc, int event)
3846 {
3847         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3848         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3849
3850         switch (event) {
3851         case SND_SOC_DAPM_PRE_PMU:
3852                 wcd->rx_bias_count++;
3853                 if (wcd->rx_bias_count == 1) {
3854                         wcd9335_codec_init_flyback(comp);
3855                         snd_soc_component_update_bits(comp,
3856                                                 WCD9335_ANA_RX_SUPPLIES,
3857                                                 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3858                                                 WCD9335_ANA_RX_BIAS_ENABLE);
3859                 }
3860                 break;
3861         case SND_SOC_DAPM_POST_PMD:
3862                 wcd->rx_bias_count--;
3863                 if (!wcd->rx_bias_count)
3864                         snd_soc_component_update_bits(comp,
3865                                         WCD9335_ANA_RX_SUPPLIES,
3866                                         WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3867                                         WCD9335_ANA_RX_BIAS_DISABLE);
3868                 break;
3869         }
3870
3871         return 0;
3872 }
3873
3874 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3875                                         struct snd_kcontrol *kc, int event)
3876 {
3877         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3878         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3879         int hph_mode = wcd->hph_mode;
3880
3881         switch (event) {
3882         case SND_SOC_DAPM_PRE_PMU:
3883                 break;
3884         case SND_SOC_DAPM_POST_PMU:
3885                 /*
3886                  * 7ms sleep is required after PA is enabled as per
3887                  * HW requirement
3888                  */
3889                 usleep_range(7000, 7100);
3890                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3891                 snd_soc_component_update_bits(comp,
3892                                         WCD9335_CDC_RX2_RX_PATH_CTL,
3893                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3894                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3895                 /* Remove mix path mute if it is enabled */
3896                 if ((snd_soc_component_read(comp,
3897                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3898                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3899                         snd_soc_component_update_bits(comp,
3900                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3901                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3902                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3903
3904                 break;
3905
3906         case SND_SOC_DAPM_PRE_PMD:
3907                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3908                 break;
3909         case SND_SOC_DAPM_POST_PMD:
3910                 /* 5ms sleep is required after PA is disabled as per
3911                  * HW requirement
3912                  */
3913                 usleep_range(5000, 5500);
3914                 break;
3915         }
3916
3917         return 0;
3918 }
3919
3920 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3921                                        struct snd_kcontrol *kc, int event)
3922 {
3923         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3924
3925         switch (event) {
3926         case SND_SOC_DAPM_POST_PMU:
3927                 /* 5ms sleep is required after PA is enabled as per
3928                  * HW requirement
3929                  */
3930                 usleep_range(5000, 5500);
3931                 snd_soc_component_update_bits(comp,
3932                                         WCD9335_CDC_RX0_RX_PATH_CTL,
3933                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3934                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3935                 /* Remove mix path mute if it is enabled */
3936                 if ((snd_soc_component_read(comp,
3937                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3938                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3939                         snd_soc_component_update_bits(comp,
3940                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3941                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3942                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3943                 break;
3944         case SND_SOC_DAPM_POST_PMD:
3945                 /* 5ms sleep is required after PA is disabled as per
3946                  * HW requirement
3947                  */
3948                 usleep_range(5000, 5500);
3949
3950                 break;
3951         }
3952
3953         return 0;
3954 }
3955
3956 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3957 {
3958         struct wcd9335_codec *wcd = data;
3959         unsigned long status = 0;
3960         int i, j, port_id;
3961         unsigned int val, int_val = 0;
3962         irqreturn_t ret = IRQ_NONE;
3963         bool tx;
3964         unsigned short reg = 0;
3965
3966         for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3967              i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3968                 regmap_read(wcd->if_regmap, i, &val);
3969                 status |= ((u32)val << (8 * j));
3970         }
3971
3972         for_each_set_bit(j, &status, 32) {
3973                 tx = (j >= 16 ? true : false);
3974                 port_id = (tx ? j - 16 : j);
3975                 regmap_read(wcd->if_regmap,
3976                                 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3977                 if (val) {
3978                         if (!tx)
3979                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3980                                         (port_id / 8);
3981                         else
3982                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3983                                         (port_id / 8);
3984                         regmap_read(
3985                                 wcd->if_regmap, reg, &int_val);
3986                         /*
3987                          * Ignore interrupts for ports for which the
3988                          * interrupts are not specifically enabled.
3989                          */
3990                         if (!(int_val & (1 << (port_id % 8))))
3991                                 continue;
3992                 }
3993
3994                 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3995                         dev_err_ratelimited(wcd->dev,
3996                            "%s: overflow error on %s port %d, value %x\n",
3997                            __func__, (tx ? "TX" : "RX"), port_id, val);
3998
3999                 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
4000                         dev_err_ratelimited(wcd->dev,
4001                            "%s: underflow error on %s port %d, value %x\n",
4002                            __func__, (tx ? "TX" : "RX"), port_id, val);
4003
4004                 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
4005                         (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
4006                         if (!tx)
4007                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
4008                                         (port_id / 8);
4009                         else
4010                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
4011                                         (port_id / 8);
4012                         regmap_read(
4013                                 wcd->if_regmap, reg, &int_val);
4014                         if (int_val & (1 << (port_id % 8))) {
4015                                 int_val = int_val ^ (1 << (port_id % 8));
4016                                 regmap_write(wcd->if_regmap,
4017                                         reg, int_val);
4018                         }
4019                 }
4020
4021                 regmap_write(wcd->if_regmap,
4022                                 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
4023                                 BIT(j % 8));
4024                 ret = IRQ_HANDLED;
4025         }
4026
4027         return ret;
4028 }
4029
4030 static struct wcd9335_irq wcd9335_irqs[] = {
4031         {
4032                 .irq = WCD9335_IRQ_SLIMBUS,
4033                 .handler = wcd9335_slimbus_irq,
4034                 .name = "SLIM Slave",
4035         },
4036 };
4037
4038 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
4039 {
4040         int irq, ret, i;
4041
4042         for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
4043                 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
4044                 if (irq < 0) {
4045                         dev_err(wcd->dev, "Failed to get %s\n",
4046                                         wcd9335_irqs[i].name);
4047                         return irq;
4048                 }
4049
4050                 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
4051                                                 wcd9335_irqs[i].handler,
4052                                                 IRQF_TRIGGER_RISING |
4053                                                 IRQF_ONESHOT,
4054                                                 wcd9335_irqs[i].name, wcd);
4055                 if (ret) {
4056                         dev_err(wcd->dev, "Failed to request %s\n",
4057                                         wcd9335_irqs[i].name);
4058                         return ret;
4059                 }
4060         }
4061
4062         /* enable interrupts on all slave ports */
4063         for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4064                 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4065                              0xFF);
4066
4067         return ret;
4068 }
4069
4070 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4071 {
4072         int i;
4073
4074         /* disable interrupts on all slave ports */
4075         for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4076                 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4077                              0x00);
4078 }
4079
4080 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4081                                         bool ccl_flag)
4082 {
4083         struct snd_soc_component *comp = wcd->component;
4084
4085         if (ccl_flag) {
4086                 if (++wcd->sido_ccl_cnt == 1)
4087                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4088                                         WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4089         } else {
4090                 if (wcd->sido_ccl_cnt == 0) {
4091                         dev_err(wcd->dev, "sido_ccl already disabled\n");
4092                         return;
4093                 }
4094                 if (--wcd->sido_ccl_cnt == 0)
4095                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4096                                 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4097         }
4098 }
4099
4100 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4101 {
4102         wcd->master_bias_users++;
4103         if (wcd->master_bias_users == 1) {
4104                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4105                                         WCD9335_ANA_BIAS_EN_MASK,
4106                                         WCD9335_ANA_BIAS_ENABLE);
4107                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4108                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4109                                         WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4110                 /*
4111                  * 1ms delay is required after pre-charge is enabled
4112                  * as per HW requirement
4113                  */
4114                 usleep_range(1000, 1100);
4115                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4116                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4117                                         WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4118                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4119                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4120                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4121         }
4122
4123         return 0;
4124 }
4125
4126 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4127 {
4128         /* Enable mclk requires master bias to be enabled first */
4129         if (wcd->master_bias_users <= 0)
4130                 return -EINVAL;
4131
4132         if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4133             ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4134                 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4135                         wcd->clk_type);
4136                 return -EINVAL;
4137         }
4138
4139         if (++wcd->clk_mclk_users == 1) {
4140                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4141                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4142                                         WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4143                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4144                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4145                                         WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4146                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4147                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4148                                         WCD9335_ANA_CLK_MCLK_ENABLE);
4149                 regmap_update_bits(wcd->regmap,
4150                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4151                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4152                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4153                 regmap_update_bits(wcd->regmap,
4154                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4155                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4156                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4157                 /*
4158                  * 10us sleep is required after clock is enabled
4159                  * as per HW requirement
4160                  */
4161                 usleep_range(10, 15);
4162         }
4163
4164         wcd->clk_type = WCD_CLK_MCLK;
4165
4166         return 0;
4167 }
4168
4169 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4170 {
4171         if (wcd->clk_mclk_users <= 0)
4172                 return -EINVAL;
4173
4174         if (--wcd->clk_mclk_users == 0) {
4175                 if (wcd->clk_rco_users > 0) {
4176                         /* MCLK to RCO switch */
4177                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4178                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4179                                         WCD9335_ANA_CLK_MCLK_SRC_RCO);
4180                         wcd->clk_type = WCD_CLK_RCO;
4181                 } else {
4182                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4183                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4184                                         WCD9335_ANA_CLK_MCLK_DISABLE);
4185                         wcd->clk_type = WCD_CLK_OFF;
4186                 }
4187
4188                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4189                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4190                                         WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4191         }
4192
4193         return 0;
4194 }
4195
4196 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4197 {
4198         if (wcd->master_bias_users <= 0)
4199                 return -EINVAL;
4200
4201         wcd->master_bias_users--;
4202         if (wcd->master_bias_users == 0) {
4203                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4204                                 WCD9335_ANA_BIAS_EN_MASK,
4205                                 WCD9335_ANA_BIAS_DISABLE);
4206                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4207                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4208                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4209         }
4210         return 0;
4211 }
4212
4213 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4214                                      bool enable)
4215 {
4216         int ret = 0;
4217
4218         if (enable) {
4219                 wcd9335_cdc_sido_ccl_enable(wcd, true);
4220                 ret = clk_prepare_enable(wcd->mclk);
4221                 if (ret) {
4222                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
4223                                 __func__);
4224                         goto err;
4225                 }
4226                 /* get BG */
4227                 wcd9335_enable_master_bias(wcd);
4228                 /* get MCLK */
4229                 wcd9335_enable_mclk(wcd);
4230
4231         } else {
4232                 /* put MCLK */
4233                 wcd9335_disable_mclk(wcd);
4234                 /* put BG */
4235                 wcd9335_disable_master_bias(wcd);
4236                 clk_disable_unprepare(wcd->mclk);
4237                 wcd9335_cdc_sido_ccl_enable(wcd, false);
4238         }
4239 err:
4240         return ret;
4241 }
4242
4243 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4244                                              enum wcd9335_sido_voltage req_mv)
4245 {
4246         struct snd_soc_component *comp = wcd->component;
4247         int vout_d_val;
4248
4249         if (req_mv == wcd->sido_voltage)
4250                 return;
4251
4252         /* compute the vout_d step value */
4253         vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4254                         WCD9335_ANA_BUCK_VOUT_MASK;
4255         snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4256         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4257                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4258                                 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4259
4260         /* 1 msec sleep required after SIDO Vout_D voltage change */
4261         usleep_range(1000, 1100);
4262         wcd->sido_voltage = req_mv;
4263         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4264                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4265                                 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4266 }
4267
4268 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4269                                              enum wcd9335_sido_voltage req_mv)
4270 {
4271         int ret = 0;
4272
4273         /* enable mclk before setting SIDO voltage */
4274         ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4275         if (ret) {
4276                 dev_err(wcd->dev, "Ext clk enable failed\n");
4277                 goto err;
4278         }
4279
4280         wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4281         wcd9335_cdc_req_mclk_enable(wcd, false);
4282
4283 err:
4284         return ret;
4285 }
4286
4287 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4288                                       int enable)
4289 {
4290         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4291         int ret;
4292
4293         if (enable) {
4294                 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4295                 if (ret)
4296                         return ret;
4297
4298                 wcd9335_codec_apply_sido_voltage(wcd,
4299                                 SIDO_VOLTAGE_NOMINAL_MV);
4300         } else {
4301                 wcd9335_codec_update_sido_voltage(wcd,
4302                                         wcd->sido_voltage);
4303                 wcd9335_cdc_req_mclk_enable(wcd, false);
4304         }
4305
4306         return 0;
4307 }
4308
4309 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4310                                      struct snd_kcontrol *kc, int event)
4311 {
4312         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4313
4314         switch (event) {
4315         case SND_SOC_DAPM_PRE_PMU:
4316                 return _wcd9335_codec_enable_mclk(comp, true);
4317         case SND_SOC_DAPM_POST_PMD:
4318                 return _wcd9335_codec_enable_mclk(comp, false);
4319         }
4320
4321         return 0;
4322 }
4323
4324 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4325         /* TODO SPK1 & SPK2 OUT*/
4326         SND_SOC_DAPM_OUTPUT("EAR"),
4327         SND_SOC_DAPM_OUTPUT("HPHL"),
4328         SND_SOC_DAPM_OUTPUT("HPHR"),
4329         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4330         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4331         SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4332         SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4333         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4334                                 AIF1_PB, 0, wcd9335_codec_enable_slim,
4335                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4336         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4337                                 AIF2_PB, 0, wcd9335_codec_enable_slim,
4338                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4339         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4340                                 AIF3_PB, 0, wcd9335_codec_enable_slim,
4341                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4342         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4343                                 AIF4_PB, 0, wcd9335_codec_enable_slim,
4344                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4345         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4346                                 &slim_rx_mux[WCD9335_RX0]),
4347         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4348                                 &slim_rx_mux[WCD9335_RX1]),
4349         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4350                                 &slim_rx_mux[WCD9335_RX2]),
4351         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4352                                 &slim_rx_mux[WCD9335_RX3]),
4353         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4354                                 &slim_rx_mux[WCD9335_RX4]),
4355         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4356                                 &slim_rx_mux[WCD9335_RX5]),
4357         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4358                                 &slim_rx_mux[WCD9335_RX6]),
4359         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4360                                 &slim_rx_mux[WCD9335_RX7]),
4361         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4362         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4363         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4364         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4365         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4366         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4367         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4368         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4369         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4370                         5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4371                         SND_SOC_DAPM_POST_PMU),
4372         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4373                         5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4374                         SND_SOC_DAPM_POST_PMU),
4375         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4376                         5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4377                         SND_SOC_DAPM_POST_PMU),
4378         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4379                         5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4380                         SND_SOC_DAPM_POST_PMU),
4381         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4382                         5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4383                         SND_SOC_DAPM_POST_PMU),
4384         SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4385                         5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4386                         SND_SOC_DAPM_POST_PMU),
4387         SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4388                         5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4389                         SND_SOC_DAPM_POST_PMU),
4390         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4391                         5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4392                         SND_SOC_DAPM_POST_PMU),
4393         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4394                         5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4395                         SND_SOC_DAPM_POST_PMU),
4396         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4397                 &rx_int0_1_mix_inp0_mux),
4398         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4399                 &rx_int0_1_mix_inp1_mux),
4400         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4401                 &rx_int0_1_mix_inp2_mux),
4402         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4403                 &rx_int1_1_mix_inp0_mux),
4404         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4405                 &rx_int1_1_mix_inp1_mux),
4406         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4407                 &rx_int1_1_mix_inp2_mux),
4408         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4409                 &rx_int2_1_mix_inp0_mux),
4410         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4411                 &rx_int2_1_mix_inp1_mux),
4412         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4413                 &rx_int2_1_mix_inp2_mux),
4414         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4415                 &rx_int3_1_mix_inp0_mux),
4416         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4417                 &rx_int3_1_mix_inp1_mux),
4418         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4419                 &rx_int3_1_mix_inp2_mux),
4420         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4421                 &rx_int4_1_mix_inp0_mux),
4422         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4423                 &rx_int4_1_mix_inp1_mux),
4424         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4425                 &rx_int4_1_mix_inp2_mux),
4426         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4427                 &rx_int5_1_mix_inp0_mux),
4428         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4429                 &rx_int5_1_mix_inp1_mux),
4430         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4431                 &rx_int5_1_mix_inp2_mux),
4432         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4433                 &rx_int6_1_mix_inp0_mux),
4434         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4435                 &rx_int6_1_mix_inp1_mux),
4436         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4437                 &rx_int6_1_mix_inp2_mux),
4438         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4439                 &rx_int7_1_mix_inp0_mux),
4440         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4441                 &rx_int7_1_mix_inp1_mux),
4442         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4443                 &rx_int7_1_mix_inp2_mux),
4444         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4445                 &rx_int8_1_mix_inp0_mux),
4446         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4447                 &rx_int8_1_mix_inp1_mux),
4448         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4449                 &rx_int8_1_mix_inp2_mux),
4450
4451         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4452         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4453         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4454         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4455         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4456         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4457         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4458         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4459         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4460         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4461         SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4462         SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4463         SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4464         SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4465         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4467         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4468         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4469
4470         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4471         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4472         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4473         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4474         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4475         SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4476         SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4477         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4478         SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4479
4480         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4481                 &rx_int0_dem_inp_mux),
4482         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4483                 &rx_int1_dem_inp_mux),
4484         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4485                 &rx_int2_dem_inp_mux),
4486
4487         SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4488                 INTERP_EAR, 0, &rx_int0_interp_mux,
4489                 wcd9335_codec_enable_interpolator,
4490                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4491                 SND_SOC_DAPM_POST_PMD),
4492         SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4493                 INTERP_HPHL, 0, &rx_int1_interp_mux,
4494                 wcd9335_codec_enable_interpolator,
4495                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4496                 SND_SOC_DAPM_POST_PMD),
4497         SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4498                 INTERP_HPHR, 0, &rx_int2_interp_mux,
4499                 wcd9335_codec_enable_interpolator,
4500                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4501                 SND_SOC_DAPM_POST_PMD),
4502         SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4503                 INTERP_LO1, 0, &rx_int3_interp_mux,
4504                 wcd9335_codec_enable_interpolator,
4505                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4506                 SND_SOC_DAPM_POST_PMD),
4507         SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4508                 INTERP_LO2, 0, &rx_int4_interp_mux,
4509                 wcd9335_codec_enable_interpolator,
4510                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4511                 SND_SOC_DAPM_POST_PMD),
4512         SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4513                 INTERP_LO3, 0, &rx_int5_interp_mux,
4514                 wcd9335_codec_enable_interpolator,
4515                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4516                 SND_SOC_DAPM_POST_PMD),
4517         SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4518                 INTERP_LO4, 0, &rx_int6_interp_mux,
4519                 wcd9335_codec_enable_interpolator,
4520                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4521                 SND_SOC_DAPM_POST_PMD),
4522         SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4523                 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4524                 wcd9335_codec_enable_interpolator,
4525                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4526                 SND_SOC_DAPM_POST_PMD),
4527         SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4528                 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4529                 wcd9335_codec_enable_interpolator,
4530                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4531                 SND_SOC_DAPM_POST_PMD),
4532
4533         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4534                 0, 0, wcd9335_codec_ear_dac_event,
4535                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4536                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4537         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4538                 5, 0, wcd9335_codec_hphl_dac_event,
4539                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4540                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4541         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4542                 4, 0, wcd9335_codec_hphr_dac_event,
4543                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4544                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4545         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4546                 0, 0, wcd9335_codec_lineout_dac_event,
4547                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4548         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4549                 0, 0, wcd9335_codec_lineout_dac_event,
4550                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4551         SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4552                 0, 0, wcd9335_codec_lineout_dac_event,
4553                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4554         SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4555                 0, 0, wcd9335_codec_lineout_dac_event,
4556                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4557         SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4558                            wcd9335_codec_enable_hphl_pa,
4559                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4560                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4561         SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4562                            wcd9335_codec_enable_hphr_pa,
4563                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4564                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4565         SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4566                            wcd9335_codec_enable_ear_pa,
4567                            SND_SOC_DAPM_POST_PMU |
4568                            SND_SOC_DAPM_POST_PMD),
4569         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4570                            wcd9335_codec_enable_lineout_pa,
4571                            SND_SOC_DAPM_POST_PMU |
4572                            SND_SOC_DAPM_POST_PMD),
4573         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4574                            wcd9335_codec_enable_lineout_pa,
4575                            SND_SOC_DAPM_POST_PMU |
4576                            SND_SOC_DAPM_POST_PMD),
4577         SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4578                            wcd9335_codec_enable_lineout_pa,
4579                            SND_SOC_DAPM_POST_PMU |
4580                            SND_SOC_DAPM_POST_PMD),
4581         SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4582                            wcd9335_codec_enable_lineout_pa,
4583                            SND_SOC_DAPM_POST_PMU |
4584                            SND_SOC_DAPM_POST_PMD),
4585         SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4586                 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4587                 SND_SOC_DAPM_POST_PMD),
4588         SND_SOC_DAPM_SUPPLY("MCLK",  SND_SOC_NOPM, 0, 0,
4589                 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4590                 SND_SOC_DAPM_POST_PMD),
4591
4592         /* TX */
4593         SND_SOC_DAPM_INPUT("AMIC1"),
4594         SND_SOC_DAPM_INPUT("AMIC2"),
4595         SND_SOC_DAPM_INPUT("AMIC3"),
4596         SND_SOC_DAPM_INPUT("AMIC4"),
4597         SND_SOC_DAPM_INPUT("AMIC5"),
4598         SND_SOC_DAPM_INPUT("AMIC6"),
4599
4600         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4601                 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4602                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4603
4604         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4605                 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4606                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4607
4608         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4609                 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4610                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4611
4612         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4613                                wcd9335_codec_enable_micbias,
4614                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4615                                SND_SOC_DAPM_POST_PMD),
4616         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4617                                wcd9335_codec_enable_micbias,
4618                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4619                                SND_SOC_DAPM_POST_PMD),
4620         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4621                                wcd9335_codec_enable_micbias,
4622                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4623                                SND_SOC_DAPM_POST_PMD),
4624         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4625                                wcd9335_codec_enable_micbias,
4626                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4627                                SND_SOC_DAPM_POST_PMD),
4628
4629         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4630                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4631         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4632                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4633         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4634                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4635         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4636                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4637         SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4638                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4639         SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4640                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4641
4642         /* Digital Mic Inputs */
4643         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4644                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4645                 SND_SOC_DAPM_POST_PMD),
4646
4647         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4648                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4649                 SND_SOC_DAPM_POST_PMD),
4650
4651         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4652                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4653                 SND_SOC_DAPM_POST_PMD),
4654
4655         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4656                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4657                 SND_SOC_DAPM_POST_PMD),
4658
4659         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4660                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4661                 SND_SOC_DAPM_POST_PMD),
4662
4663         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4664                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4665                 SND_SOC_DAPM_POST_PMD),
4666
4667         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4668                 &tx_dmic_mux0),
4669         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4670                 &tx_dmic_mux1),
4671         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4672                 &tx_dmic_mux2),
4673         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4674                 &tx_dmic_mux3),
4675         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4676                 &tx_dmic_mux4),
4677         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4678                 &tx_dmic_mux5),
4679         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4680                 &tx_dmic_mux6),
4681         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4682                 &tx_dmic_mux7),
4683         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4684                 &tx_dmic_mux8),
4685
4686         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4687                 &tx_amic_mux0),
4688         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4689                 &tx_amic_mux1),
4690         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4691                 &tx_amic_mux2),
4692         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4693                 &tx_amic_mux3),
4694         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4695                 &tx_amic_mux4),
4696         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4697                 &tx_amic_mux5),
4698         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4699                 &tx_amic_mux6),
4700         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4701                 &tx_amic_mux7),
4702         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4703                 &tx_amic_mux8),
4704
4705         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4706                 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4707
4708         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4709                 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4710
4711         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4712                 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4713
4714         SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4715                 &sb_tx0_mux),
4716         SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4717                 &sb_tx1_mux),
4718         SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4719                 &sb_tx2_mux),
4720         SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4721                 &sb_tx3_mux),
4722         SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4723                 &sb_tx4_mux),
4724         SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4725                 &sb_tx5_mux),
4726         SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4727                 &sb_tx6_mux),
4728         SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4729                 &sb_tx7_mux),
4730         SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4731                 &sb_tx8_mux),
4732
4733         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4734                            &tx_adc_mux0, wcd9335_codec_enable_dec,
4735                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4736                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4737
4738         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4739                            &tx_adc_mux1, wcd9335_codec_enable_dec,
4740                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4741                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4742
4743         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4744                            &tx_adc_mux2, wcd9335_codec_enable_dec,
4745                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4746                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4747
4748         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4749                            &tx_adc_mux3, wcd9335_codec_enable_dec,
4750                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4751                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4752
4753         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4754                            &tx_adc_mux4, wcd9335_codec_enable_dec,
4755                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4756                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4757
4758         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4759                            &tx_adc_mux5, wcd9335_codec_enable_dec,
4760                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4761                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4762
4763         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4764                            &tx_adc_mux6, wcd9335_codec_enable_dec,
4765                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4766                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4767
4768         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4769                            &tx_adc_mux7, wcd9335_codec_enable_dec,
4770                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4771                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4772
4773         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4774                            &tx_adc_mux8, wcd9335_codec_enable_dec,
4775                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4776                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4777 };
4778
4779 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4780 {
4781         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4782
4783         snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4784                                         WCD9335_ANA_RCO_BG_EN_MASK,
4785                                         WCD9335_ANA_RCO_BG_ENABLE);
4786         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4787                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4788                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4789         /* 100us sleep needed after IREF settings */
4790         usleep_range(100, 110);
4791         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4792                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4793                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4794         /* 100us sleep needed after VREF settings */
4795         usleep_range(100, 110);
4796         wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4797 }
4798
4799 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4800 {
4801         _wcd9335_codec_enable_mclk(comp, true);
4802         snd_soc_component_update_bits(comp,
4803                                 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4804                                 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4805                                 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4806         /*
4807          * 5ms sleep required after enabling efuse control
4808          * before checking the status.
4809          */
4810         usleep_range(5000, 5500);
4811
4812         if (!(snd_soc_component_read(comp,
4813                                         WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4814                                         WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4815                 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4816
4817         wcd9335_enable_sido_buck(comp);
4818         _wcd9335_codec_enable_mclk(comp, false);
4819
4820         return 0;
4821 }
4822
4823 static void wcd9335_codec_init(struct snd_soc_component *component)
4824 {
4825         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4826         int i;
4827
4828         /* ungate MCLK and set clk rate */
4829         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4830                                 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4831
4832         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4833                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4834                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4835
4836         for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4837                 snd_soc_component_update_bits(component,
4838                                         wcd9335_codec_reg_init[i].reg,
4839                                         wcd9335_codec_reg_init[i].mask,
4840                                         wcd9335_codec_reg_init[i].val);
4841
4842         wcd9335_enable_efuse_sensing(component);
4843 }
4844
4845 static int wcd9335_codec_probe(struct snd_soc_component *component)
4846 {
4847         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4848         int ret;
4849         int i;
4850
4851         snd_soc_component_init_regmap(component, wcd->regmap);
4852         /* Class-H Init*/
4853         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
4854         if (IS_ERR(wcd->clsh_ctrl))
4855                 return PTR_ERR(wcd->clsh_ctrl);
4856
4857         /* Default HPH Mode to Class-H HiFi */
4858         wcd->hph_mode = CLS_H_HIFI;
4859         wcd->component = component;
4860
4861         wcd9335_codec_init(component);
4862
4863         for (i = 0; i < NUM_CODEC_DAIS; i++)
4864                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4865
4866         ret = wcd9335_setup_irqs(wcd);
4867         if (ret)
4868                 goto free_clsh_ctrl;
4869
4870         return 0;
4871
4872 free_clsh_ctrl:
4873         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4874         return ret;
4875 }
4876
4877 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4878 {
4879         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4880
4881         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4882         wcd9335_teardown_irqs(wcd);
4883 }
4884
4885 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4886                                     int clk_id, int source,
4887                                     unsigned int freq, int dir)
4888 {
4889         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4890
4891         wcd->mclk_rate = freq;
4892
4893         if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4894                 snd_soc_component_update_bits(comp,
4895                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4896                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4897                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4898         else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4899                 snd_soc_component_update_bits(comp,
4900                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4901                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4902                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4903
4904         return clk_set_rate(wcd->mclk, freq);
4905 }
4906
4907 static const struct snd_soc_component_driver wcd9335_component_drv = {
4908         .probe = wcd9335_codec_probe,
4909         .remove = wcd9335_codec_remove,
4910         .set_sysclk = wcd9335_codec_set_sysclk,
4911         .controls = wcd9335_snd_controls,
4912         .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4913         .dapm_widgets = wcd9335_dapm_widgets,
4914         .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4915         .dapm_routes = wcd9335_audio_map,
4916         .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4917 };
4918
4919 static int wcd9335_probe(struct wcd9335_codec *wcd)
4920 {
4921         struct device *dev = wcd->dev;
4922
4923         memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4924         memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4925
4926         wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4927         wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4928
4929         return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4930                                                wcd9335_slim_dais,
4931                                                ARRAY_SIZE(wcd9335_slim_dais));
4932 }
4933
4934 static const struct regmap_range_cfg wcd9335_ranges[] = {
4935         {
4936                 .name = "WCD9335",
4937                 .range_min =  0x0,
4938                 .range_max =  WCD9335_MAX_REGISTER,
4939                 .selector_reg = WCD9335_SEL_REGISTER,
4940                 .selector_mask = 0xff,
4941                 .selector_shift = 0,
4942                 .window_start = 0x800,
4943                 .window_len = 0x100,
4944         },
4945 };
4946
4947 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4948 {
4949         switch (reg) {
4950         case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4951         case WCD9335_ANA_MBHC_RESULT_3:
4952         case WCD9335_ANA_MBHC_RESULT_2:
4953         case WCD9335_ANA_MBHC_RESULT_1:
4954         case WCD9335_ANA_MBHC_MECH:
4955         case WCD9335_ANA_MBHC_ELECT:
4956         case WCD9335_ANA_MBHC_ZDET:
4957         case WCD9335_ANA_MICB2:
4958         case WCD9335_ANA_RCO:
4959         case WCD9335_ANA_BIAS:
4960                 return true;
4961         default:
4962                 return false;
4963         }
4964 }
4965
4966 static struct regmap_config wcd9335_regmap_config = {
4967         .reg_bits = 16,
4968         .val_bits = 8,
4969         .cache_type = REGCACHE_RBTREE,
4970         .max_register = WCD9335_MAX_REGISTER,
4971         .can_multi_write = true,
4972         .ranges = wcd9335_ranges,
4973         .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4974         .volatile_reg = wcd9335_is_volatile_register,
4975 };
4976
4977 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4978         {
4979                 .name = "WCD9335-IFC-DEV",
4980                 .range_min =  0x0,
4981                 .range_max = WCD9335_MAX_REGISTER,
4982                 .selector_reg = WCD9335_SEL_REGISTER,
4983                 .selector_mask = 0xfff,
4984                 .selector_shift = 0,
4985                 .window_start = 0x800,
4986                 .window_len = 0x400,
4987         },
4988 };
4989
4990 static struct regmap_config wcd9335_ifc_regmap_config = {
4991         .reg_bits = 16,
4992         .val_bits = 8,
4993         .can_multi_write = true,
4994         .max_register = WCD9335_MAX_REGISTER,
4995         .ranges = wcd9335_ifc_ranges,
4996         .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4997 };
4998
4999 static const struct regmap_irq wcd9335_codec_irqs[] = {
5000         /* INTR_REG 0 */
5001         [WCD9335_IRQ_SLIMBUS] = {
5002                 .reg_offset = 0,
5003                 .mask = BIT(0),
5004                 .type = {
5005                         .type_reg_offset = 0,
5006                         .types_supported = IRQ_TYPE_EDGE_BOTH,
5007                         .type_reg_mask  = BIT(0),
5008                 },
5009         },
5010 };
5011
5012 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
5013         .name = "wcd9335_pin1_irq",
5014         .status_base = WCD9335_INTR_PIN1_STATUS0,
5015         .mask_base = WCD9335_INTR_PIN1_MASK0,
5016         .ack_base = WCD9335_INTR_PIN1_CLEAR0,
5017         .type_base = WCD9335_INTR_LEVEL0,
5018         .num_type_reg = 4,
5019         .num_regs = 4,
5020         .irqs = wcd9335_codec_irqs,
5021         .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
5022 };
5023
5024 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
5025 {
5026         struct device *dev = wcd->dev;
5027         struct device_node *np = dev->of_node;
5028         int ret;
5029
5030         wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
5031         if (wcd->reset_gpio < 0) {
5032                 dev_err(dev, "Reset GPIO missing from DT\n");
5033                 return wcd->reset_gpio;
5034         }
5035
5036         wcd->mclk = devm_clk_get(dev, "mclk");
5037         if (IS_ERR(wcd->mclk)) {
5038                 dev_err(dev, "mclk not found\n");
5039                 return PTR_ERR(wcd->mclk);
5040         }
5041
5042         wcd->native_clk = devm_clk_get(dev, "slimbus");
5043         if (IS_ERR(wcd->native_clk)) {
5044                 dev_err(dev, "slimbus clock not found\n");
5045                 return PTR_ERR(wcd->native_clk);
5046         }
5047
5048         wcd->supplies[0].supply = "vdd-buck";
5049         wcd->supplies[1].supply = "vdd-buck-sido";
5050         wcd->supplies[2].supply = "vdd-tx";
5051         wcd->supplies[3].supply = "vdd-rx";
5052         wcd->supplies[4].supply = "vdd-io";
5053
5054         ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
5055         if (ret) {
5056                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5057                 return ret;
5058         }
5059
5060         return 0;
5061 }
5062
5063 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5064 {
5065         struct device *dev = wcd->dev;
5066         int ret;
5067
5068         ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
5069         if (ret) {
5070                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5071                 return ret;
5072         }
5073
5074         /*
5075          * For WCD9335, it takes about 600us for the Vout_A and
5076          * Vout_D to be ready after BUCK_SIDO is powered up.
5077          * SYS_RST_N shouldn't be pulled high during this time
5078          * Toggle the reset line to make sure the reset pulse is
5079          * correctly applied
5080          */
5081         usleep_range(600, 650);
5082
5083         gpio_direction_output(wcd->reset_gpio, 0);
5084         msleep(20);
5085         gpio_set_value(wcd->reset_gpio, 1);
5086         msleep(20);
5087
5088         return 0;
5089 }
5090
5091 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5092 {
5093         struct regmap *rm = wcd->regmap;
5094         int val, byte0;
5095
5096         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5097         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5098
5099         if ((val < 0) || (byte0 < 0)) {
5100                 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5101                 return -EINVAL;
5102         }
5103
5104         if (byte0 == 0x1) {
5105                 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5106                 wcd->version = WCD9335_VERSION_2_0;
5107                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5108                 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5109                 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5110                 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5111                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5112                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5113                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5114                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5115         } else {
5116                 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5117                 return -EINVAL;
5118         }
5119
5120         return 0;
5121 }
5122
5123 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5124 {
5125         int ret;
5126
5127         /*
5128          * INTR1 consists of all possible interrupt sources Ear OCP,
5129          * HPH OCP, MBHC, MAD, VBAT, and SVA
5130          * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5131          */
5132         wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5133         if (wcd->intr1 < 0) {
5134                 if (wcd->intr1 != -EPROBE_DEFER)
5135                         dev_err(wcd->dev, "Unable to configure IRQ\n");
5136
5137                 return wcd->intr1;
5138         }
5139
5140         ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5141                                  IRQF_TRIGGER_HIGH, 0,
5142                                  &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5143         if (ret)
5144                 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret);
5145
5146         return ret;
5147 }
5148
5149 static int wcd9335_slim_probe(struct slim_device *slim)
5150 {
5151         struct device *dev = &slim->dev;
5152         struct wcd9335_codec *wcd;
5153         int ret;
5154
5155         wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5156         if (!wcd)
5157                 return  -ENOMEM;
5158
5159         wcd->dev = dev;
5160         ret = wcd9335_parse_dt(wcd);
5161         if (ret) {
5162                 dev_err(dev, "Error parsing DT: %d\n", ret);
5163                 return ret;
5164         }
5165
5166         ret = wcd9335_power_on_reset(wcd);
5167         if (ret)
5168                 return ret;
5169
5170         dev_set_drvdata(dev, wcd);
5171
5172         return 0;
5173 }
5174
5175 static int wcd9335_slim_status(struct slim_device *sdev,
5176                                enum slim_device_status status)
5177 {
5178         struct device *dev = &sdev->dev;
5179         struct device_node *ifc_dev_np;
5180         struct wcd9335_codec *wcd;
5181         int ret;
5182
5183         wcd = dev_get_drvdata(dev);
5184
5185         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5186         if (!ifc_dev_np) {
5187                 dev_err(dev, "No Interface device found\n");
5188                 return -EINVAL;
5189         }
5190
5191         wcd->slim = sdev;
5192         wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5193         of_node_put(ifc_dev_np);
5194         if (!wcd->slim_ifc_dev) {
5195                 dev_err(dev, "Unable to get SLIM Interface device\n");
5196                 return -EINVAL;
5197         }
5198
5199         slim_get_logical_addr(wcd->slim_ifc_dev);
5200
5201         wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5202         if (IS_ERR(wcd->regmap)) {
5203                 dev_err(dev, "Failed to allocate slim register map\n");
5204                 return PTR_ERR(wcd->regmap);
5205         }
5206
5207         wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5208                                                   &wcd9335_ifc_regmap_config);
5209         if (IS_ERR(wcd->if_regmap)) {
5210                 dev_err(dev, "Failed to allocate ifc register map\n");
5211                 return PTR_ERR(wcd->if_regmap);
5212         }
5213
5214         ret = wcd9335_bring_up(wcd);
5215         if (ret) {
5216                 dev_err(dev, "Failed to bringup WCD9335\n");
5217                 return ret;
5218         }
5219
5220         ret = wcd9335_irq_init(wcd);
5221         if (ret)
5222                 return ret;
5223
5224         wcd9335_probe(wcd);
5225
5226         return ret;
5227 }
5228
5229 static const struct slim_device_id wcd9335_slim_id[] = {
5230         {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5231         {}
5232 };
5233 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5234
5235 static struct slim_driver wcd9335_slim_driver = {
5236         .driver = {
5237                 .name = "wcd9335-slim",
5238         },
5239         .probe = wcd9335_slim_probe,
5240         .device_status = wcd9335_slim_status,
5241         .id_table = wcd9335_slim_id,
5242 };
5243
5244 module_slim_driver(wcd9335_slim_driver);
5245 MODULE_DESCRIPTION("WCD9335 slim driver");
5246 MODULE_LICENSE("GPL v2");
5247 MODULE_ALIAS("slim:217:1a0:*");