sound/soc/codecs/src4xxx.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // src4xxx.h  --  SRC4XXX ALSA SoC audio driver
   4 //
   5 // Copyright 2021-2022 Deqx Pty Ltd
   6 // Author: Matt R Flax <flatmax@flatmax.com>
   7
   8 #ifndef __SRC4XXX_H__
   9 #define __SRC4XXX_H__
  10
  11 #define SRC4XXX_RES_00 0x00
  12 #define SRC4XXX_PWR_RST_01 0x01
  13 #define SRC4XXX_RESET 0x80
  14 #define SRC4XXX_POWER_DOWN 0x00
  15 #define SRC4XXX_POWER_ENABLE 0x20
  16 #define SRC4XXX_ENABLE_SRC 0x1
  17 #define SRC4XXX_ENABLE_SRC_SHIFT 0
  18 #define SRC4XXX_ENABLE_DIR 0x2
  19 #define SRC4XXX_ENABLE_DIR_SHIFT 1
  20 #define SRC4XXX_ENABLE_DIT 0x4
  21 #define SRC4XXX_ENABLE_DIT_SHIFT 2
  22 #define SRC4XXX_ENABLE_PORT_B 0x8
  23 #define SRC4XXX_ENABLE_PORT_B_SHIFT 3
  24 #define SRC4XXX_ENABLE_PORT_A 0x10
  25 #define SRC4XXX_ENABLE_PORT_A_SHIFT 4
  26
  27 #define SRC4XXX_PORTA_CTL_03 0x03
  28 #define SRC4XXX_BUS_MASTER 0x8
  29 #define SRC4XXX_BUS_LEFT_J 0x0
  30 #define SRC4XXX_BUS_I2S 0x1
  31 #define SRC4XXX_BUS_RIGHT_J_16 0x4
  32 #define SRC4XXX_BUS_RIGHT_J_18 0x5
  33 #define SRC4XXX_BUS_RIGHT_J_20 0x6
  34 #define SRC4XXX_BUS_RIGHT_J_24 0x7
  35 #define SRC4XXX_BUS_FMT_MS_MASK 0xf
  36
  37 #define SRC4XXX_PORTA_CTL_04 0x04
  38 #define SRC4XXX_MCLK_DIV_MASK 0x3
  39
  40 #define SRC4XXX_BUS_FMT(id) (SRC4XXX_PORTA_CTL_03+2*id)
  41 #define SRC4XXX_BUS_CLK(id) (SRC4XXX_PORTA_CTL_04+2*id)
  42
  43 #define SRC4XXX_PORTB_CTL_05 0x05
  44 #define SRC4XXX_PORTB_CTL_06 0x06
  45
  46 #define SRC4XXX_TX_CTL_07 0x07
  47 #define SRC4XXX_TX_MCLK_DIV_MASK 0x60
  48 #define SRC4XXX_TX_MCLK_DIV_SHIFT 5
  49
  50 #define SRC4XXX_TX_CTL_08 0x08
  51 #define SRC4XXX_TX_CTL_09 0x09
  52 #define SRC4XXX_SRC_DIT_IRQ_MSK_0B 0x0B
  53 #define SRC4XXX_SRC_BTI_EN 0x01
  54 #define SRC4XXX_SRC_TSLIP_EN 0x02
  55 #define SRC4XXX_SRC_DIT_IRQ_MODE_0C 0x0C
  56 #define SRC4XXX_RCV_CTL_0D 0x0D
  57 #define SRC4XXX_RXCLK_RXCKI 0x0
  58 #define SRC4XXX_RXCLK_MCLK 0x8
  59 #define SRC4XXX_RCV_CTL_0E 0x0E
  60 #define SRC4XXX_REC_MCLK_EN 0x1
  61 #define SRC4XXX_PLL2_DIV_0 (0x0<<1)
  62 #define SRC4XXX_PLL2_DIV_2 (0x1<<1)
  63 #define SRC4XXX_PLL2_DIV_4 (0x2<<1)
  64 #define SRC4XXX_PLL2_DIV_8 (0x3<<1)
  65 #define SRC4XXX_PLL2_LOL 0x8
  66 #define SRC4XXX_RCV_PLL_0F 0x0F
  67 #define SRC4XXX_RCV_PLL_10 0x10
  68 #define SRC4XXX_RCV_PLL_11 0x11
  69 #define SRC4XXX_RVC_IRQ_MSK_16 0x16
  70 #define SRC4XXX_RVC_IRQ_MSK_17 0x17
  71 #define SRC4XXX_RVC_IRQ_MODE_18 0x18
  72 #define SRC4XXX_RVC_IRQ_MODE_19 0x19
  73 #define SRC4XXX_RVC_IRQ_MODE_1A 0x1A
  74 #define SRC4XXX_GPIO_1_1B 0x1B
  75 #define SRC4XXX_GPIO_2_1C 0x1C
  76 #define SRC4XXX_GPIO_3_1D 0x1D
  77 #define SRC4XXX_GPIO_4_1E 0x1E
  78 #define SRC4XXX_SCR_CTL_2D 0x2D
  79 #define SRC4XXX_SCR_CTL_2E 0x2E
  80 #define SRC4XXX_SCR_CTL_2F 0x2F
  81 #define SRC4XXX_SCR_CTL_30 0x30
  82 #define SRC4XXX_SCR_CTL_31 0x31
  83 #define SRC4XXX_PAGE_SEL_7F 0x7F
  84
  85 // read only registers
  86 #define SRC4XXX_GLOBAL_ITR_STS_02 0x02
  87 #define SRC4XXX_SRC_DIT_STS_0A 0x0A
  88 #define SRC4XXX_NON_AUDIO_D_12 0x12
  89 #define SRC4XXX_RVC_STS_13 0x13
  90 #define SRC4XXX_RVC_STS_14 0x14
  91 #define SRC4XXX_RVC_STS_15 0x15
  92 #define SRC4XXX_SUB_CODE_1F 0x1F
  93 #define SRC4XXX_SUB_CODE_20 0x20
  94 #define SRC4XXX_SUB_CODE_21 0x21
  95 #define SRC4XXX_SUB_CODE_22 0x22
  96 #define SRC4XXX_SUB_CODE_23 0x23
  97 #define SRC4XXX_SUB_CODE_24 0x24
  98 #define SRC4XXX_SUB_CODE_25 0x25
  99 #define SRC4XXX_SUB_CODE_26 0x26
 100 #define SRC4XXX_SUB_CODE_27 0x27
 101 #define SRC4XXX_SUB_CODE_28 0x28
 102 #define SRC4XXX_PC_PREAMBLE_HI_29 0x29
 103 #define SRC4XXX_PC_PREAMBLE_LO_2A 0x2A
 104 #define SRC4XXX_PD_PREAMBLE_HI_2B 0x2B
 105 #define SRC4XXX_PC_PREAMBLE_LO_2C 0x2C
 106 #define SRC4XXX_IO_RATIO_32 0x32
 107 #define SRC4XXX_IO_RATIO_33 0x33
 108
 109 int src4xxx_probe(struct device *dev, struct regmap *regmap,
 110                 void (*switch_mode)(struct device *dev));
 111 extern const struct regmap_config src4xxx_regmap_config;
 112
 113 #endif /* __SRC4XXX_H__ */