2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* Delay for the VAG ramp up */
39 #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
40 /* Delay for the VAG ramp down */
41 #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
43 #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
45 /* default value of sgtl5000 registers */
46 static const struct reg_default sgtl5000_reg_defaults[] = {
47 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
48 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
49 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
50 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
51 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
52 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
53 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
54 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
55 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
56 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
57 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
58 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
59 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
60 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
61 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
62 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
63 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
64 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
65 { SGTL5000_DAP_CTRL, 0x0000 },
66 { SGTL5000_DAP_PEQ, 0x0000 },
67 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
68 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
69 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
70 { SGTL5000_DAP_SURROUND, 0x0040 },
71 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
72 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
73 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
74 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
75 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
76 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
77 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
78 { SGTL5000_DAP_AVC_CTRL, 0x5100 },
79 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
80 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
81 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
84 /* AVC: Threshold dB -> register: pre-calculated values */
85 static const u16 avc_thr_db2reg[97] = {
86 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
87 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
88 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
89 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
90 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
91 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
92 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
93 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
94 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
95 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
98 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
99 enum sgtl5000_regulator_supplies {
106 /* vddd is optional supply */
107 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
113 #define LDO_VOLTAGE 1200000
114 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
116 enum sgtl5000_micbias_resistor {
117 SGTL5000_MICBIAS_OFF = 0,
118 SGTL5000_MICBIAS_2K = 2,
119 SGTL5000_MICBIAS_4K = 4,
120 SGTL5000_MICBIAS_8K = 8,
124 I2S_LRCLK_STRENGTH_DISABLE,
125 I2S_LRCLK_STRENGTH_LOW,
126 I2S_LRCLK_STRENGTH_MEDIUM,
127 I2S_LRCLK_STRENGTH_HIGH,
134 LAST_POWER_EVENT = ADC_POWER_EVENT
137 /* sgtl5000 private structure in codec */
138 struct sgtl5000_priv {
139 int sysclk; /* sysclk rate */
140 int master; /* i2s master or not */
141 int fmt; /* i2s data format */
142 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
144 struct regmap *regmap;
150 u16 mute_state[LAST_POWER_EVENT + 1];
153 static inline int hp_sel_input(struct snd_soc_component *component)
155 unsigned int ana_reg = 0;
157 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &ana_reg);
159 return (ana_reg & SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
162 static inline u16 mute_output(struct snd_soc_component *component,
165 unsigned int mute_reg = 0;
167 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &mute_reg);
169 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
170 mute_mask, mute_mask);
174 static inline void restore_output(struct snd_soc_component *component,
175 u16 mute_mask, u16 mute_reg)
177 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
178 mute_mask, mute_reg);
181 static void vag_power_on(struct snd_soc_component *component, u32 source)
183 unsigned int ana_reg = 0;
185 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_reg);
187 if (ana_reg & SGTL5000_VAG_POWERUP)
190 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
191 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
193 /* When VAG powering on to get local loop from Line-In, the sleep
194 * is required to avoid loud pop.
196 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
197 source == HP_POWER_EVENT)
198 msleep(SGTL5000_VAG_POWERUP_DELAY);
201 static int vag_power_consumers(struct snd_soc_component *component,
202 u16 ana_pwr_reg, u32 source)
206 /* count dac/adc consumers unconditional */
207 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
209 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
213 * If the event comes from HP and Line-In is selected,
214 * current action is 'DAC to be powered down'.
215 * As HP_POWERUP is not set when HP muxed to line-in,
216 * we need to keep VAG power ON.
218 if (source == HP_POWER_EVENT) {
219 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
222 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
229 static void vag_power_off(struct snd_soc_component *component, u32 source)
231 unsigned int ana_pwr = SGTL5000_VAG_POWERUP;
233 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_pwr);
235 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
239 * This function calls when any of VAG power consumers is disappearing.
240 * Thus, if there is more than one consumer at the moment, as minimum
241 * one consumer will definitely stay after the end of the current
243 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
244 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
247 * (the current consumer is disappearing right now)
249 if (vag_power_consumers(component, ana_pwr, source) >= 2)
252 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
253 SGTL5000_VAG_POWERUP, 0);
254 /* In power down case, we need wait 400-1000 ms
255 * when VAG fully ramped down.
256 * As longer we wait, as smaller pop we've got.
258 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
262 * mic_bias power on/off share the same register bits with
263 * output impedance of mic bias, when power on mic bias, we
264 * need reclaim it to impedance value.
270 static int mic_bias_event(struct snd_soc_dapm_widget *w,
271 struct snd_kcontrol *kcontrol, int event)
273 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
274 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
277 case SND_SOC_DAPM_POST_PMU:
278 /* change mic bias resistor */
279 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
280 SGTL5000_BIAS_R_MASK,
281 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
284 case SND_SOC_DAPM_PRE_PMD:
285 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
286 SGTL5000_BIAS_R_MASK, 0);
292 static int vag_and_mute_control(struct snd_soc_component *component,
293 int event, int event_source)
295 static const u16 mute_mask[] = {
297 * Mask for HP_POWER_EVENT.
298 * Muxing Headphones have to be wrapped with mute/unmute
303 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
304 * Muxing DAC or ADC block have to be wrapped with mute/unmute
305 * both headphones and line-out.
307 SGTL5000_OUTPUTS_MUTE,
308 SGTL5000_OUTPUTS_MUTE
311 struct sgtl5000_priv *sgtl5000 =
312 snd_soc_component_get_drvdata(component);
315 case SND_SOC_DAPM_PRE_PMU:
316 sgtl5000->mute_state[event_source] =
317 mute_output(component, mute_mask[event_source]);
319 case SND_SOC_DAPM_POST_PMU:
320 vag_power_on(component, event_source);
321 restore_output(component, mute_mask[event_source],
322 sgtl5000->mute_state[event_source]);
324 case SND_SOC_DAPM_PRE_PMD:
325 sgtl5000->mute_state[event_source] =
326 mute_output(component, mute_mask[event_source]);
327 vag_power_off(component, event_source);
329 case SND_SOC_DAPM_POST_PMD:
330 restore_output(component, mute_mask[event_source],
331 sgtl5000->mute_state[event_source]);
341 * Mute Headphone when power it up/down.
342 * Control VAG power on HP power path.
344 static int headphone_pga_event(struct snd_soc_dapm_widget *w,
345 struct snd_kcontrol *kcontrol, int event)
347 struct snd_soc_component *component =
348 snd_soc_dapm_to_component(w->dapm);
350 return vag_and_mute_control(component, event, HP_POWER_EVENT);
353 /* As manual describes, ADC/DAC powering up/down requires
354 * to mute outputs to avoid pops.
355 * Control VAG power on ADC/DAC power path.
357 static int adc_updown_depop(struct snd_soc_dapm_widget *w,
358 struct snd_kcontrol *kcontrol, int event)
360 struct snd_soc_component *component =
361 snd_soc_dapm_to_component(w->dapm);
363 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
366 static int dac_updown_depop(struct snd_soc_dapm_widget *w,
367 struct snd_kcontrol *kcontrol, int event)
369 struct snd_soc_component *component =
370 snd_soc_dapm_to_component(w->dapm);
372 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
375 /* input sources for ADC */
376 static const char *adc_mux_text[] = {
380 static SOC_ENUM_SINGLE_DECL(adc_enum,
381 SGTL5000_CHIP_ANA_CTRL, 2,
384 static const struct snd_kcontrol_new adc_mux =
385 SOC_DAPM_ENUM("Capture Mux", adc_enum);
387 /* input sources for DAC */
388 static const char *dac_mux_text[] = {
392 static SOC_ENUM_SINGLE_DECL(dac_enum,
393 SGTL5000_CHIP_ANA_CTRL, 6,
396 static const struct snd_kcontrol_new dac_mux =
397 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
399 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
400 SND_SOC_DAPM_INPUT("LINE_IN"),
401 SND_SOC_DAPM_INPUT("MIC_IN"),
403 SND_SOC_DAPM_OUTPUT("HP_OUT"),
404 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
406 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
408 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
410 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
412 SND_SOC_DAPM_PRE_POST_PMU |
413 SND_SOC_DAPM_PRE_POST_PMD),
414 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
416 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
417 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
419 /* aif for i2s input */
420 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
421 0, SGTL5000_CHIP_DIG_POWER,
424 /* aif for i2s output */
425 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
426 0, SGTL5000_CHIP_DIG_POWER,
429 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
430 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
431 SND_SOC_DAPM_PRE_POST_PMD),
432 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
433 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
434 SND_SOC_DAPM_PRE_POST_PMD),
437 /* routes for sgtl5000 */
438 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
439 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
440 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
442 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
443 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
445 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
446 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
447 {"LO", NULL, "DAC"}, /* dac --> line_out */
449 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
450 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
452 {"LINE_OUT", NULL, "LO"},
453 {"HP_OUT", NULL, "HP"},
456 /* custom function to fetch info of PCM playback volume */
457 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
458 struct snd_ctl_elem_info *uinfo)
460 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
462 uinfo->value.integer.min = 0;
463 uinfo->value.integer.max = 0xfc - 0x3c;
468 * custom function to get of PCM playback volume
470 * dac volume register
471 * 15-------------8-7--------------0
472 * | R channel vol | L channel vol |
473 * -------------------------------
475 * PCM volume with 0.5017 dB steps from 0 to -90 dB
477 * register values map to dB
478 * 0x3B and less = Reserved
482 * 0xFC and greater = Muted
484 * register value map to userspace value
486 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
487 * ------------------------------
488 * userspace value 0xc0 0
490 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
491 struct snd_ctl_elem_value *ucontrol)
493 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
498 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
500 /* get left channel volume */
501 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
503 /* get right channel volume */
504 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
506 /* make sure value fall in (0x3c,0xfc) */
507 l = clamp(l, 0x3c, 0xfc);
508 r = clamp(r, 0x3c, 0xfc);
510 /* invert it and map to userspace value */
514 ucontrol->value.integer.value[0] = l;
515 ucontrol->value.integer.value[1] = r;
521 * custom function to put of PCM playback volume
523 * dac volume register
524 * 15-------------8-7--------------0
525 * | R channel vol | L channel vol |
526 * -------------------------------
528 * PCM volume with 0.5017 dB steps from 0 to -90 dB
530 * register values map to dB
531 * 0x3B and less = Reserved
535 * 0xFC and greater = Muted
537 * userspace value map to register value
539 * userspace value 0xc0 0
540 * ------------------------------
541 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
543 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_value *ucontrol)
546 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
551 l = ucontrol->value.integer.value[0];
552 r = ucontrol->value.integer.value[1];
554 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
555 l = clamp(l, 0, 0xfc - 0x3c);
556 r = clamp(r, 0, 0xfc - 0x3c);
558 /* invert it, get the value can be set to register */
562 /* shift to get the register value */
563 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
564 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
566 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
572 * custom function to get AVC threshold
574 * The threshold dB is calculated by rearranging the calculation from the
575 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
576 * dB = ( fls(register_value) - 14.347 ) * 6.02
578 * As this calculation is expensive and the threshold dB values may not exeed
579 * 0 to 96 we use pre-calculated values.
581 static int avc_get_threshold(struct snd_kcontrol *kcontrol,
582 struct snd_ctl_elem_value *ucontrol)
584 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
586 u16 reg = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD);
588 /* register value 0 => -96dB */
590 ucontrol->value.integer.value[0] = 96;
591 ucontrol->value.integer.value[1] = 96;
595 /* get dB from register value (rounded down) */
596 for (i = 0; avc_thr_db2reg[i] > reg; i++)
600 ucontrol->value.integer.value[0] = db;
601 ucontrol->value.integer.value[1] = db;
607 * custom function to put AVC threshold
609 * The register value is calculated by following formula:
610 * register_value = 10^(dB/20) * 0.636 * 2^15
611 * As this calculation is expensive and the threshold dB values may not exeed
612 * 0 to 96 we use pre-calculated values.
614 static int avc_put_threshold(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
617 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
621 db = (int)ucontrol->value.integer.value[0];
622 if (db < 0 || db > 96)
624 reg = avc_thr_db2reg[db];
625 snd_soc_write(codec, SGTL5000_DAP_AVC_THRESHOLD, reg);
630 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
632 /* tlv for mic gain, 0db 20db 30db 40db */
633 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
634 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
635 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
638 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
639 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
641 /* tlv for lineout volume, 31 steps of .5db each */
642 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
644 /* tlv for dap avc max gain, 0db, 6db, 12db */
645 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
647 /* tlv for dap avc threshold, */
648 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
650 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
651 /* SOC_DOUBLE_S8_TLV with invert */
653 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
654 .name = "PCM Playback Volume",
655 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
656 SNDRV_CTL_ELEM_ACCESS_READWRITE,
657 .info = dac_info_volsw,
658 .get = dac_get_volsw,
659 .put = dac_put_volsw,
662 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
663 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
664 SGTL5000_CHIP_ANA_ADC_CTRL,
665 8, 1, 0, capture_6db_attenuate),
666 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
668 SOC_DOUBLE_TLV("Headphone Playback Volume",
669 SGTL5000_CHIP_ANA_HP_CTRL,
673 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
675 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
678 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
679 0, 3, 0, mic_gain_tlv),
681 SOC_DOUBLE_TLV("Lineout Playback Volume",
682 SGTL5000_CHIP_LINE_OUT_VOL,
683 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
684 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
687 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
689 /* Automatic Volume Control (DAP AVC) */
690 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
691 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
692 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
694 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
695 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
696 0, 96, 0, avc_get_threshold, avc_put_threshold,
700 /* mute the codec used by alsa core */
701 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
703 struct snd_soc_codec *codec = codec_dai->codec;
704 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
706 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
707 adcdac_ctrl, mute ? adcdac_ctrl : 0);
712 /* set codec format */
713 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
715 struct snd_soc_codec *codec = codec_dai->codec;
716 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
719 sgtl5000->master = 0;
721 * i2s clock and frame master setting.
723 * - clock and frame slave,
724 * - clock and frame master
726 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
727 case SND_SOC_DAIFMT_CBS_CFS:
729 case SND_SOC_DAIFMT_CBM_CFM:
730 i2sctl |= SGTL5000_I2S_MASTER;
731 sgtl5000->master = 1;
737 /* setting i2s data format */
738 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
739 case SND_SOC_DAIFMT_DSP_A:
740 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
742 case SND_SOC_DAIFMT_DSP_B:
743 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
744 i2sctl |= SGTL5000_I2S_LRALIGN;
746 case SND_SOC_DAIFMT_I2S:
747 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
749 case SND_SOC_DAIFMT_RIGHT_J:
750 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
751 i2sctl |= SGTL5000_I2S_LRPOL;
753 case SND_SOC_DAIFMT_LEFT_J:
754 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
755 i2sctl |= SGTL5000_I2S_LRALIGN;
761 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
763 /* Clock inversion */
764 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
765 case SND_SOC_DAIFMT_NB_NF:
767 case SND_SOC_DAIFMT_IB_NF:
768 i2sctl |= SGTL5000_I2S_SCLK_INV;
774 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
779 /* set codec sysclk */
780 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
781 int clk_id, unsigned int freq, int dir)
783 struct snd_soc_codec *codec = codec_dai->codec;
784 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
787 case SGTL5000_SYSCLK:
788 sgtl5000->sysclk = freq;
798 * set clock according to i2s frame clock,
799 * sgtl5000 provides 2 clock sources:
800 * 1. sys_mclk: sample freq can only be configured to
801 * 1/256, 1/384, 1/512 of sys_mclk.
802 * 2. pll: can derive any audio clocks.
804 * clock setting rules:
805 * 1. in slave mode, only sys_mclk can be used
806 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
808 * 3. usage of sys_mclk is preferred over pll to save power.
810 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
812 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
814 int sys_fs; /* sample freq */
817 * sample freq should be divided by frame clock,
818 * if frame clock is lower than 44.1 kHz, sample freq should be set to
819 * 32 kHz or 44.1 kHz.
821 switch (frame_rate) {
835 /* set divided factor of frame clock */
836 switch (sys_fs / frame_rate) {
838 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
841 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
844 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
850 /* set the sys_fs according to frame rate */
853 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
856 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
859 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
862 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
865 dev_err(codec->dev, "frame rate %d not supported\n",
871 * calculate the divider of mclk/sample_freq,
872 * factor of freq = 96 kHz can only be 256, since mclk is in the range
875 switch (sgtl5000->sysclk / frame_rate) {
877 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
878 SGTL5000_MCLK_FREQ_SHIFT;
881 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
882 SGTL5000_MCLK_FREQ_SHIFT;
885 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
886 SGTL5000_MCLK_FREQ_SHIFT;
889 /* if mclk does not satisfy the divider, use pll */
890 if (sgtl5000->master) {
891 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
892 SGTL5000_MCLK_FREQ_SHIFT;
895 "PLL not supported in slave mode\n");
896 dev_err(codec->dev, "%d ratio is not supported. "
897 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
898 sgtl5000->sysclk / frame_rate);
903 /* if using pll, please check manual 6.4.2 for detail */
904 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
908 unsigned int in, int_div, frac_div;
910 if (sgtl5000->sysclk > 17000000) {
912 in = sgtl5000->sysclk / 2;
915 in = sgtl5000->sysclk;
926 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
927 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
929 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
931 snd_soc_update_bits(codec,
932 SGTL5000_CHIP_CLK_TOP_CTRL,
933 SGTL5000_INPUT_FREQ_DIV2,
934 SGTL5000_INPUT_FREQ_DIV2);
936 snd_soc_update_bits(codec,
937 SGTL5000_CHIP_CLK_TOP_CTRL,
938 SGTL5000_INPUT_FREQ_DIV2,
942 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
943 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
944 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
946 /* if using pll, clk_ctrl must be set after pll power up */
947 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
949 /* otherwise, clk_ctrl must be set before pll power down */
950 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
953 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
954 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
962 * Set PCM DAI bit size and sample rate.
963 * input: params_rate, params_fmt
965 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
966 struct snd_pcm_hw_params *params,
967 struct snd_soc_dai *dai)
969 struct snd_soc_codec *codec = dai->codec;
970 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
971 int channels = params_channels(params);
976 /* sysclk should already set */
977 if (!sgtl5000->sysclk) {
978 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
982 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
983 stereo = SGTL5000_DAC_STEREO;
985 stereo = SGTL5000_ADC_STEREO;
987 /* set mono to save power */
988 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
989 channels == 1 ? 0 : stereo);
991 /* set codec clock base on lrclk */
992 ret = sgtl5000_set_clock(codec, params_rate(params));
996 /* set i2s data format */
997 switch (params_width(params)) {
999 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1001 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
1002 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
1003 SGTL5000_I2S_SCLKFREQ_SHIFT;
1006 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
1007 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1008 SGTL5000_I2S_SCLKFREQ_SHIFT;
1011 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
1012 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1013 SGTL5000_I2S_SCLKFREQ_SHIFT;
1016 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1018 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
1019 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1020 SGTL5000_I2S_SCLKFREQ_SHIFT;
1026 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
1027 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
1035 * common state changes:
1037 * off --> standby --> prepare --> on
1038 * standby --> prepare --> on
1041 * on --> prepare --> standby
1043 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
1044 enum snd_soc_bias_level level)
1046 struct sgtl5000_priv *sgtl = snd_soc_codec_get_drvdata(codec);
1050 case SND_SOC_BIAS_ON:
1051 case SND_SOC_BIAS_PREPARE:
1052 case SND_SOC_BIAS_STANDBY:
1053 regcache_cache_only(sgtl->regmap, false);
1054 ret = regcache_sync(sgtl->regmap);
1056 regcache_cache_only(sgtl->regmap, true);
1060 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1061 SGTL5000_REFTOP_POWERUP,
1062 SGTL5000_REFTOP_POWERUP);
1064 case SND_SOC_BIAS_OFF:
1065 regcache_cache_only(sgtl->regmap, true);
1066 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1067 SGTL5000_REFTOP_POWERUP, 0);
1074 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1075 SNDRV_PCM_FMTBIT_S20_3LE |\
1076 SNDRV_PCM_FMTBIT_S24_LE |\
1077 SNDRV_PCM_FMTBIT_S32_LE)
1079 static const struct snd_soc_dai_ops sgtl5000_ops = {
1080 .hw_params = sgtl5000_pcm_hw_params,
1081 .digital_mute = sgtl5000_digital_mute,
1082 .set_fmt = sgtl5000_set_dai_fmt,
1083 .set_sysclk = sgtl5000_set_dai_sysclk,
1086 static struct snd_soc_dai_driver sgtl5000_dai = {
1089 .stream_name = "Playback",
1093 * only support 8~48K + 96K,
1094 * TODO modify hw_param to support more
1096 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1097 .formats = SGTL5000_FORMATS,
1100 .stream_name = "Capture",
1103 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1104 .formats = SGTL5000_FORMATS,
1106 .ops = &sgtl5000_ops,
1107 .symmetric_rates = 1,
1110 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1113 case SGTL5000_CHIP_ID:
1114 case SGTL5000_CHIP_ADCDAC_CTRL:
1115 case SGTL5000_CHIP_ANA_STATUS:
1122 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1125 case SGTL5000_CHIP_ID:
1126 case SGTL5000_CHIP_DIG_POWER:
1127 case SGTL5000_CHIP_CLK_CTRL:
1128 case SGTL5000_CHIP_I2S_CTRL:
1129 case SGTL5000_CHIP_SSS_CTRL:
1130 case SGTL5000_CHIP_ADCDAC_CTRL:
1131 case SGTL5000_CHIP_DAC_VOL:
1132 case SGTL5000_CHIP_PAD_STRENGTH:
1133 case SGTL5000_CHIP_ANA_ADC_CTRL:
1134 case SGTL5000_CHIP_ANA_HP_CTRL:
1135 case SGTL5000_CHIP_ANA_CTRL:
1136 case SGTL5000_CHIP_LINREG_CTRL:
1137 case SGTL5000_CHIP_REF_CTRL:
1138 case SGTL5000_CHIP_MIC_CTRL:
1139 case SGTL5000_CHIP_LINE_OUT_CTRL:
1140 case SGTL5000_CHIP_LINE_OUT_VOL:
1141 case SGTL5000_CHIP_ANA_POWER:
1142 case SGTL5000_CHIP_PLL_CTRL:
1143 case SGTL5000_CHIP_CLK_TOP_CTRL:
1144 case SGTL5000_CHIP_ANA_STATUS:
1145 case SGTL5000_CHIP_SHORT_CTRL:
1146 case SGTL5000_CHIP_ANA_TEST2:
1147 case SGTL5000_DAP_CTRL:
1148 case SGTL5000_DAP_PEQ:
1149 case SGTL5000_DAP_BASS_ENHANCE:
1150 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1151 case SGTL5000_DAP_AUDIO_EQ:
1152 case SGTL5000_DAP_SURROUND:
1153 case SGTL5000_DAP_FLT_COEF_ACCESS:
1154 case SGTL5000_DAP_COEF_WR_B0_MSB:
1155 case SGTL5000_DAP_COEF_WR_B0_LSB:
1156 case SGTL5000_DAP_EQ_BASS_BAND0:
1157 case SGTL5000_DAP_EQ_BASS_BAND1:
1158 case SGTL5000_DAP_EQ_BASS_BAND2:
1159 case SGTL5000_DAP_EQ_BASS_BAND3:
1160 case SGTL5000_DAP_EQ_BASS_BAND4:
1161 case SGTL5000_DAP_MAIN_CHAN:
1162 case SGTL5000_DAP_MIX_CHAN:
1163 case SGTL5000_DAP_AVC_CTRL:
1164 case SGTL5000_DAP_AVC_THRESHOLD:
1165 case SGTL5000_DAP_AVC_ATTACK:
1166 case SGTL5000_DAP_AVC_DECAY:
1167 case SGTL5000_DAP_COEF_WR_B1_MSB:
1168 case SGTL5000_DAP_COEF_WR_B1_LSB:
1169 case SGTL5000_DAP_COEF_WR_B2_MSB:
1170 case SGTL5000_DAP_COEF_WR_B2_LSB:
1171 case SGTL5000_DAP_COEF_WR_A1_MSB:
1172 case SGTL5000_DAP_COEF_WR_A1_LSB:
1173 case SGTL5000_DAP_COEF_WR_A2_MSB:
1174 case SGTL5000_DAP_COEF_WR_A2_LSB:
1183 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1184 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1185 * The calculatation was done for all possible register values which
1186 * is the array index and the following formula: 10^((idx−15)/40) * 100
1188 static const u8 vol_quot_table[] = {
1189 42, 45, 47, 50, 53, 56, 60, 63,
1190 67, 71, 75, 79, 84, 89, 94, 100,
1191 106, 112, 119, 126, 133, 141, 150, 158,
1192 168, 178, 188, 200, 211, 224, 237, 251
1196 * sgtl5000 has 3 internal power supplies:
1197 * 1. VAG, normally set to vdda/2
1198 * 2. charge pump, set to different value
1199 * according to voltage of vdda and vddio
1200 * 3. line out VAG, normally set to vddio/2
1202 * and should be set according to:
1203 * 1. vddd provided by external or not
1204 * 2. vdda and vddio voltage value. > 3.1v or not
1206 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1218 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1220 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1221 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1222 vddd = (sgtl5000->num_supplies > VDDD)
1223 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1227 vddio = vddio / 1000;
1230 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1231 dev_err(codec->dev, "regulator voltage not set correctly\n");
1236 /* according to datasheet, maximum voltage of supplies */
1237 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1239 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1246 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1247 ana_pwr |= SGTL5000_DAC_STEREO |
1248 SGTL5000_ADC_STEREO |
1249 SGTL5000_REFTOP_POWERUP;
1250 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1252 if (vddio < 3100 && vdda < 3100) {
1253 /* enable internal oscillator used for charge pump */
1254 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1255 SGTL5000_INT_OSC_EN,
1256 SGTL5000_INT_OSC_EN);
1257 /* Enable VDDC charge pump */
1258 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1260 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1262 * if vddio == vdda the source of charge pump should be
1263 * assigned manually to VDDIO
1265 if (vddio == vdda) {
1266 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1267 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1268 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1272 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1274 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1277 * set ADC/DAC VAG to vdda / 2,
1278 * should stay in range (0.8v, 1.575v)
1281 if (vag <= SGTL5000_ANA_GND_BASE)
1283 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1284 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1285 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1287 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1289 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1290 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1292 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1294 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1296 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1297 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1298 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1300 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1301 SGTL5000_LINE_OUT_GND_STP;
1303 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1304 SGTL5000_LINE_OUT_CURRENT_MASK |
1305 SGTL5000_LINE_OUT_GND_MASK,
1306 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1307 SGTL5000_LINE_OUT_CURRENT_360u <<
1308 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1311 * Set lineout output level in range (0..31)
1312 * the same value is used for right and left channel
1314 * Searching for a suitable index solving this formula:
1315 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1317 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1319 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1320 if (vol_quot >= vol_quot_table[i])
1326 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1327 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1328 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1329 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1330 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1335 static int sgtl5000_enable_regulators(struct i2c_client *client)
1339 int external_vddd = 0;
1340 struct regulator *vddd;
1341 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1343 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1344 sgtl5000->supplies[i].supply = supply_names[i];
1346 vddd = regulator_get_optional(&client->dev, "VDDD");
1348 /* See if it's just not registered yet */
1349 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1350 return -EPROBE_DEFER;
1353 regulator_put(vddd);
1356 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1357 - 1 + external_vddd;
1358 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1359 sgtl5000->supplies);
1363 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1364 sgtl5000->supplies);
1366 usleep_range(10, 20);
1368 regulator_bulk_free(sgtl5000->num_supplies,
1369 sgtl5000->supplies);
1374 static int sgtl5000_probe(struct snd_soc_codec *codec)
1378 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1380 /* power up sgtl5000 */
1381 ret = sgtl5000_set_power_regs(codec);
1385 /* enable small pop, introduce 400ms delay in turning off */
1386 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1387 SGTL5000_SMALL_POP, 1);
1389 /* disable short cut detector */
1390 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1393 * set i2s as default input of sound switch
1394 * TODO: add sound switch to control and dapm widge.
1396 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1397 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1398 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1399 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1401 /* enable dac volume ramp by default */
1402 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1403 SGTL5000_DAC_VOL_RAMP_EN |
1404 SGTL5000_DAC_MUTE_RIGHT |
1405 SGTL5000_DAC_MUTE_LEFT);
1407 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
1408 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg);
1410 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1411 SGTL5000_HP_ZCD_EN |
1412 SGTL5000_ADC_ZCD_EN);
1414 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1415 SGTL5000_BIAS_R_MASK,
1416 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1418 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1419 SGTL5000_BIAS_VOLT_MASK,
1420 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1424 * Enable DAP in kcontrol and dapm.
1426 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1434 static int sgtl5000_remove(struct snd_soc_codec *codec)
1439 static const struct snd_soc_codec_driver sgtl5000_driver = {
1440 .probe = sgtl5000_probe,
1441 .remove = sgtl5000_remove,
1442 .set_bias_level = sgtl5000_set_bias_level,
1443 .suspend_bias_off = true,
1444 .component_driver = {
1445 .controls = sgtl5000_snd_controls,
1446 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1447 .dapm_widgets = sgtl5000_dapm_widgets,
1448 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1449 .dapm_routes = sgtl5000_dapm_routes,
1450 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1454 static const struct regmap_config sgtl5000_regmap = {
1459 .max_register = SGTL5000_MAX_REG_OFFSET,
1460 .volatile_reg = sgtl5000_volatile,
1461 .readable_reg = sgtl5000_readable,
1463 .cache_type = REGCACHE_RBTREE,
1464 .reg_defaults = sgtl5000_reg_defaults,
1465 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1469 * Write all the default values from sgtl5000_reg_defaults[] array into the
1470 * sgtl5000 registers, to make sure we always start with the sane registers
1471 * values as stated in the datasheet.
1473 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1474 * we follow this approach to guarantee we always start from the default values
1475 * and avoid problems like, not being able to probe after an audio playback
1476 * followed by a system reset or a 'reboot' command in Linux
1478 static void sgtl5000_fill_defaults(struct i2c_client *client)
1480 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1481 int i, ret, val, index;
1483 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1484 val = sgtl5000_reg_defaults[i].def;
1485 index = sgtl5000_reg_defaults[i].reg;
1486 ret = regmap_write(sgtl5000->regmap, index, val);
1488 dev_err(&client->dev,
1489 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1490 __func__, ret, index, val);
1494 static int sgtl5000_i2c_probe(struct i2c_client *client,
1495 const struct i2c_device_id *id)
1497 struct sgtl5000_priv *sgtl5000;
1499 struct device_node *np = client->dev.of_node;
1503 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1507 i2c_set_clientdata(client, sgtl5000);
1509 ret = sgtl5000_enable_regulators(client);
1513 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1514 if (IS_ERR(sgtl5000->regmap)) {
1515 ret = PTR_ERR(sgtl5000->regmap);
1516 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1520 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1521 if (IS_ERR(sgtl5000->mclk)) {
1522 ret = PTR_ERR(sgtl5000->mclk);
1523 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1524 /* Defer the probe to see if the clk will be provided later */
1526 ret = -EPROBE_DEFER;
1530 ret = clk_prepare_enable(sgtl5000->mclk);
1532 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1536 /* Need 8 clocks before I2C accesses */
1539 /* read chip information */
1540 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1542 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1546 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1547 SGTL5000_PARTID_PART_ID) {
1548 dev_err(&client->dev,
1549 "Device with ID register %x is not a sgtl5000\n", reg);
1554 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1555 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1556 sgtl5000->revision = rev;
1558 /* reconfigure the clocks in case we're using the PLL */
1559 ret = regmap_write(sgtl5000->regmap,
1560 SGTL5000_CHIP_CLK_CTRL,
1561 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1563 dev_err(&client->dev,
1564 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1566 /* Mute everything to avoid pop from the following power-up */
1567 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
1568 SGTL5000_CHIP_ANA_CTRL_DEFAULT);
1570 dev_err(&client->dev,
1571 "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
1576 * If VAG is powered-on (e.g. from previous boot), it would be disabled
1577 * by the write to ANA_POWER in later steps of the probe code. This
1578 * may create a loud pop even with all outputs muted. The proper way
1579 * to circumvent this is disabling the bit first and waiting the proper
1582 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
1584 dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
1587 if (value & SGTL5000_VAG_POWERUP) {
1588 ret = regmap_update_bits(sgtl5000->regmap,
1589 SGTL5000_CHIP_ANA_POWER,
1590 SGTL5000_VAG_POWERUP,
1593 dev_err(&client->dev, "Error %d disabling VAG\n", ret);
1597 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
1600 /* Follow section 2.2.1.1 of AN3663 */
1601 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1602 if (sgtl5000->num_supplies <= VDDD) {
1603 /* internal VDDD at 1.2V */
1604 ret = regmap_update_bits(sgtl5000->regmap,
1605 SGTL5000_CHIP_LINREG_CTRL,
1606 SGTL5000_LINREG_VDDD_MASK,
1609 dev_err(&client->dev,
1610 "Error %d setting LINREG_VDDD\n", ret);
1612 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1613 dev_info(&client->dev,
1614 "Using internal LDO instead of VDDD: check ER1\n");
1616 /* using external LDO for VDDD
1617 * Clear startup powerup and simple powerup
1618 * bits to save power
1620 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1621 | SGTL5000_LINREG_SIMPLE_POWERUP);
1622 dev_dbg(&client->dev, "Using external VDDD\n");
1624 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1626 dev_err(&client->dev,
1627 "Error %d setting CHIP_ANA_POWER to %04x\n",
1631 if (!of_property_read_u32(np,
1632 "micbias-resistor-k-ohms", &value)) {
1634 case SGTL5000_MICBIAS_OFF:
1635 sgtl5000->micbias_resistor = 0;
1637 case SGTL5000_MICBIAS_2K:
1638 sgtl5000->micbias_resistor = 1;
1640 case SGTL5000_MICBIAS_4K:
1641 sgtl5000->micbias_resistor = 2;
1643 case SGTL5000_MICBIAS_8K:
1644 sgtl5000->micbias_resistor = 3;
1647 sgtl5000->micbias_resistor = 2;
1648 dev_err(&client->dev,
1649 "Unsuitable MicBias resistor\n");
1652 /* default is 4Kohms */
1653 sgtl5000->micbias_resistor = 2;
1655 if (!of_property_read_u32(np,
1656 "micbias-voltage-m-volts", &value)) {
1658 /* steps of 250mV */
1659 if ((value >= 1250) && (value <= 3000))
1660 sgtl5000->micbias_voltage = (value / 250) - 5;
1662 sgtl5000->micbias_voltage = 0;
1663 dev_err(&client->dev,
1664 "Unsuitable MicBias voltage\n");
1667 sgtl5000->micbias_voltage = 0;
1671 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1672 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1673 if (value > I2S_LRCLK_STRENGTH_HIGH)
1674 value = I2S_LRCLK_STRENGTH_LOW;
1675 sgtl5000->lrclk_strength = value;
1678 /* Ensure sgtl5000 will start with sane register values */
1679 sgtl5000_fill_defaults(client);
1681 ret = snd_soc_register_codec(&client->dev,
1682 &sgtl5000_driver, &sgtl5000_dai, 1);
1689 clk_disable_unprepare(sgtl5000->mclk);
1692 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1693 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1698 static int sgtl5000_i2c_remove(struct i2c_client *client)
1700 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1702 snd_soc_unregister_codec(&client->dev);
1703 clk_disable_unprepare(sgtl5000->mclk);
1704 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1705 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1710 static const struct i2c_device_id sgtl5000_id[] = {
1715 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1717 static const struct of_device_id sgtl5000_dt_ids[] = {
1718 { .compatible = "fsl,sgtl5000", },
1721 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1723 static struct i2c_driver sgtl5000_i2c_driver = {
1726 .of_match_table = sgtl5000_dt_ids,
1728 .probe = sgtl5000_i2c_probe,
1729 .remove = sgtl5000_i2c_remove,
1730 .id_table = sgtl5000_id,
1733 module_i2c_driver(sgtl5000_i2c_driver);
1735 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1736 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1737 MODULE_LICENSE("GPL");