2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* Delay for the VAG ramp up */
39 #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
40 /* Delay for the VAG ramp down */
41 #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
43 #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
45 /* default value of sgtl5000 registers */
46 static const struct reg_default sgtl5000_reg_defaults[] = {
47 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
48 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
49 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
50 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
51 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
52 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
53 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
54 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
55 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
56 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
57 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
58 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
59 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
60 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
61 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
62 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
63 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
64 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
65 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
66 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
67 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
68 { SGTL5000_DAP_CTRL, 0x0000 },
69 { SGTL5000_DAP_PEQ, 0x0000 },
70 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
71 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
72 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
73 { SGTL5000_DAP_SURROUND, 0x0040 },
74 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
75 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
76 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
77 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
78 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
79 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
80 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
81 { SGTL5000_DAP_AVC_CTRL, 0x5100 },
82 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
83 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
84 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
87 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
88 enum sgtl5000_regulator_supplies {
95 /* vddd is optional supply */
96 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
102 #define LDO_CONSUMER_NAME "VDDD_LDO"
103 #define LDO_VOLTAGE 1200000
105 static struct regulator_consumer_supply ldo_consumer[] = {
106 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
109 static struct regulator_init_data ldo_init_data = {
113 .valid_modes_mask = REGULATOR_MODE_NORMAL,
114 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
116 .num_consumer_supplies = 1,
117 .consumer_supplies = &ldo_consumer[0],
121 * sgtl5000 internal ldo regulator,
122 * enabled when VDDD not provided
124 struct ldo_regulator {
125 struct regulator_desc desc;
126 struct regulator_dev *dev;
132 enum sgtl5000_micbias_resistor {
133 SGTL5000_MICBIAS_OFF = 0,
134 SGTL5000_MICBIAS_2K = 2,
135 SGTL5000_MICBIAS_4K = 4,
136 SGTL5000_MICBIAS_8K = 8,
143 LAST_POWER_EVENT = ADC_POWER_EVENT
146 /* sgtl5000 private structure in codec */
147 struct sgtl5000_priv {
148 int sysclk; /* sysclk rate */
149 int master; /* i2s master or not */
150 int fmt; /* i2s data format */
151 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
152 struct ldo_regulator *ldo;
153 struct regmap *regmap;
158 u16 mute_state[LAST_POWER_EVENT + 1];
161 static inline int hp_sel_input(struct snd_soc_component *component)
163 unsigned int ana_reg = 0;
165 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &ana_reg);
167 return (ana_reg & SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
170 static inline u16 mute_output(struct snd_soc_component *component,
173 unsigned int mute_reg = 0;
175 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &mute_reg);
177 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
178 mute_mask, mute_mask);
182 static inline void restore_output(struct snd_soc_component *component,
183 u16 mute_mask, u16 mute_reg)
185 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
186 mute_mask, mute_reg);
189 static void vag_power_on(struct snd_soc_component *component, u32 source)
191 unsigned int ana_reg = 0;
193 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_reg);
195 if (ana_reg & SGTL5000_VAG_POWERUP)
198 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
199 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
201 /* When VAG powering on to get local loop from Line-In, the sleep
202 * is required to avoid loud pop.
204 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
205 source == HP_POWER_EVENT)
206 msleep(SGTL5000_VAG_POWERUP_DELAY);
209 static int vag_power_consumers(struct snd_soc_component *component,
210 u16 ana_pwr_reg, u32 source)
214 /* count dac/adc consumers unconditional */
215 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
217 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
221 * If the event comes from HP and Line-In is selected,
222 * current action is 'DAC to be powered down'.
223 * As HP_POWERUP is not set when HP muxed to line-in,
224 * we need to keep VAG power ON.
226 if (source == HP_POWER_EVENT) {
227 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
230 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
237 static void vag_power_off(struct snd_soc_component *component, u32 source)
239 unsigned int ana_pwr = SGTL5000_VAG_POWERUP;
241 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_pwr);
243 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
247 * This function calls when any of VAG power consumers is disappearing.
248 * Thus, if there is more than one consumer at the moment, as minimum
249 * one consumer will definitely stay after the end of the current
251 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
252 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
255 * (the current consumer is disappearing right now)
257 if (vag_power_consumers(component, ana_pwr, source) >= 2)
260 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
261 SGTL5000_VAG_POWERUP, 0);
262 /* In power down case, we need wait 400-1000 ms
263 * when VAG fully ramped down.
264 * As longer we wait, as smaller pop we've got.
266 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
270 * mic_bias power on/off share the same register bits with
271 * output impedance of mic bias, when power on mic bias, we
272 * need reclaim it to impedance value.
278 static int mic_bias_event(struct snd_soc_dapm_widget *w,
279 struct snd_kcontrol *kcontrol, int event)
281 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
282 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
285 case SND_SOC_DAPM_POST_PMU:
286 /* change mic bias resistor */
287 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
288 SGTL5000_BIAS_R_MASK,
289 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
292 case SND_SOC_DAPM_PRE_PMD:
293 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
294 SGTL5000_BIAS_R_MASK, 0);
300 static int vag_and_mute_control(struct snd_soc_component *component,
301 int event, int event_source)
303 static const u16 mute_mask[] = {
305 * Mask for HP_POWER_EVENT.
306 * Muxing Headphones have to be wrapped with mute/unmute
311 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
312 * Muxing DAC or ADC block have to be wrapped with mute/unmute
313 * both headphones and line-out.
315 SGTL5000_OUTPUTS_MUTE,
316 SGTL5000_OUTPUTS_MUTE
319 struct sgtl5000_priv *sgtl5000 =
320 snd_soc_component_get_drvdata(component);
323 case SND_SOC_DAPM_PRE_PMU:
324 sgtl5000->mute_state[event_source] =
325 mute_output(component, mute_mask[event_source]);
327 case SND_SOC_DAPM_POST_PMU:
328 vag_power_on(component, event_source);
329 restore_output(component, mute_mask[event_source],
330 sgtl5000->mute_state[event_source]);
332 case SND_SOC_DAPM_PRE_PMD:
333 sgtl5000->mute_state[event_source] =
334 mute_output(component, mute_mask[event_source]);
335 vag_power_off(component, event_source);
337 case SND_SOC_DAPM_POST_PMD:
338 restore_output(component, mute_mask[event_source],
339 sgtl5000->mute_state[event_source]);
349 * Mute Headphone when power it up/down.
350 * Control VAG power on HP power path.
352 static int headphone_pga_event(struct snd_soc_dapm_widget *w,
353 struct snd_kcontrol *kcontrol, int event)
355 struct snd_soc_component *component =
356 snd_soc_dapm_to_component(w->dapm);
358 return vag_and_mute_control(component, event, HP_POWER_EVENT);
361 /* As manual describes, ADC/DAC powering up/down requires
362 * to mute outputs to avoid pops.
363 * Control VAG power on ADC/DAC power path.
365 static int adc_updown_depop(struct snd_soc_dapm_widget *w,
366 struct snd_kcontrol *kcontrol, int event)
368 struct snd_soc_component *component =
369 snd_soc_dapm_to_component(w->dapm);
371 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
374 static int dac_updown_depop(struct snd_soc_dapm_widget *w,
375 struct snd_kcontrol *kcontrol, int event)
377 struct snd_soc_component *component =
378 snd_soc_dapm_to_component(w->dapm);
380 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
383 /* input sources for ADC */
384 static const char *adc_mux_text[] = {
388 static SOC_ENUM_SINGLE_DECL(adc_enum,
389 SGTL5000_CHIP_ANA_CTRL, 2,
392 static const struct snd_kcontrol_new adc_mux =
393 SOC_DAPM_ENUM("Capture Mux", adc_enum);
395 /* input sources for DAC */
396 static const char *dac_mux_text[] = {
400 static SOC_ENUM_SINGLE_DECL(dac_enum,
401 SGTL5000_CHIP_ANA_CTRL, 6,
404 static const struct snd_kcontrol_new dac_mux =
405 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
407 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
408 SND_SOC_DAPM_INPUT("LINE_IN"),
409 SND_SOC_DAPM_INPUT("MIC_IN"),
411 SND_SOC_DAPM_OUTPUT("HP_OUT"),
412 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
414 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
416 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
418 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
420 SND_SOC_DAPM_PRE_POST_PMU |
421 SND_SOC_DAPM_PRE_POST_PMD),
422 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
424 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
425 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
427 /* aif for i2s input */
428 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
429 0, SGTL5000_CHIP_DIG_POWER,
432 /* aif for i2s output */
433 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
434 0, SGTL5000_CHIP_DIG_POWER,
437 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
438 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
439 SND_SOC_DAPM_PRE_POST_PMD),
440 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
441 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
442 SND_SOC_DAPM_PRE_POST_PMD),
445 /* routes for sgtl5000 */
446 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
447 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
448 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
450 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
451 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
453 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
454 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
455 {"LO", NULL, "DAC"}, /* dac --> line_out */
457 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
458 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
460 {"LINE_OUT", NULL, "LO"},
461 {"HP_OUT", NULL, "HP"},
464 /* custom function to fetch info of PCM playback volume */
465 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
466 struct snd_ctl_elem_info *uinfo)
468 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
470 uinfo->value.integer.min = 0;
471 uinfo->value.integer.max = 0xfc - 0x3c;
476 * custom function to get of PCM playback volume
478 * dac volume register
479 * 15-------------8-7--------------0
480 * | R channel vol | L channel vol |
481 * -------------------------------
483 * PCM volume with 0.5017 dB steps from 0 to -90 dB
485 * register values map to dB
486 * 0x3B and less = Reserved
490 * 0xFC and greater = Muted
492 * register value map to userspace value
494 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
495 * ------------------------------
496 * userspace value 0xc0 0
498 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
499 struct snd_ctl_elem_value *ucontrol)
501 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
506 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
508 /* get left channel volume */
509 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
511 /* get right channel volume */
512 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
514 /* make sure value fall in (0x3c,0xfc) */
515 l = clamp(l, 0x3c, 0xfc);
516 r = clamp(r, 0x3c, 0xfc);
518 /* invert it and map to userspace value */
522 ucontrol->value.integer.value[0] = l;
523 ucontrol->value.integer.value[1] = r;
529 * custom function to put of PCM playback volume
531 * dac volume register
532 * 15-------------8-7--------------0
533 * | R channel vol | L channel vol |
534 * -------------------------------
536 * PCM volume with 0.5017 dB steps from 0 to -90 dB
538 * register values map to dB
539 * 0x3B and less = Reserved
543 * 0xFC and greater = Muted
545 * userspace value map to register value
547 * userspace value 0xc0 0
548 * ------------------------------
549 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
551 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
552 struct snd_ctl_elem_value *ucontrol)
554 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
559 l = ucontrol->value.integer.value[0];
560 r = ucontrol->value.integer.value[1];
562 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
563 l = clamp(l, 0, 0xfc - 0x3c);
564 r = clamp(r, 0, 0xfc - 0x3c);
566 /* invert it, get the value can be set to register */
570 /* shift to get the register value */
571 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
572 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
574 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
579 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
581 /* tlv for mic gain, 0db 20db 30db 40db */
582 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
583 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
584 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
587 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
588 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
590 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
591 /* SOC_DOUBLE_S8_TLV with invert */
593 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
594 .name = "PCM Playback Volume",
595 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
596 SNDRV_CTL_ELEM_ACCESS_READWRITE,
597 .info = dac_info_volsw,
598 .get = dac_get_volsw,
599 .put = dac_put_volsw,
602 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
603 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
604 SGTL5000_CHIP_ANA_ADC_CTRL,
605 8, 1, 0, capture_6db_attenuate),
606 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
608 SOC_DOUBLE_TLV("Headphone Playback Volume",
609 SGTL5000_CHIP_ANA_HP_CTRL,
613 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
616 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
617 0, 3, 0, mic_gain_tlv),
620 /* mute the codec used by alsa core */
621 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
623 struct snd_soc_codec *codec = codec_dai->codec;
624 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
626 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
627 adcdac_ctrl, mute ? adcdac_ctrl : 0);
632 /* set codec format */
633 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
635 struct snd_soc_codec *codec = codec_dai->codec;
636 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
639 sgtl5000->master = 0;
641 * i2s clock and frame master setting.
643 * - clock and frame slave,
644 * - clock and frame master
646 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
647 case SND_SOC_DAIFMT_CBS_CFS:
649 case SND_SOC_DAIFMT_CBM_CFM:
650 i2sctl |= SGTL5000_I2S_MASTER;
651 sgtl5000->master = 1;
657 /* setting i2s data format */
658 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
659 case SND_SOC_DAIFMT_DSP_A:
660 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
662 case SND_SOC_DAIFMT_DSP_B:
663 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
664 i2sctl |= SGTL5000_I2S_LRALIGN;
666 case SND_SOC_DAIFMT_I2S:
667 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
669 case SND_SOC_DAIFMT_RIGHT_J:
670 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
671 i2sctl |= SGTL5000_I2S_LRPOL;
673 case SND_SOC_DAIFMT_LEFT_J:
674 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
675 i2sctl |= SGTL5000_I2S_LRALIGN;
681 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
683 /* Clock inversion */
684 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
685 case SND_SOC_DAIFMT_NB_NF:
687 case SND_SOC_DAIFMT_IB_NF:
688 i2sctl |= SGTL5000_I2S_SCLK_INV;
694 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
699 /* set codec sysclk */
700 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
701 int clk_id, unsigned int freq, int dir)
703 struct snd_soc_codec *codec = codec_dai->codec;
704 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
707 case SGTL5000_SYSCLK:
708 sgtl5000->sysclk = freq;
718 * set clock according to i2s frame clock,
719 * sgtl5000 provides 2 clock sources:
720 * 1. sys_mclk: sample freq can only be configured to
721 * 1/256, 1/384, 1/512 of sys_mclk.
722 * 2. pll: can derive any audio clocks.
724 * clock setting rules:
725 * 1. in slave mode, only sys_mclk can be used
726 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
728 * 3. usage of sys_mclk is preferred over pll to save power.
730 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
732 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
734 int sys_fs; /* sample freq */
737 * sample freq should be divided by frame clock,
738 * if frame clock is lower than 44.1 kHz, sample freq should be set to
739 * 32 kHz or 44.1 kHz.
741 switch (frame_rate) {
755 /* set divided factor of frame clock */
756 switch (sys_fs / frame_rate) {
758 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
761 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
764 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
770 /* set the sys_fs according to frame rate */
773 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
776 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
779 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
782 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
785 dev_err(codec->dev, "frame rate %d not supported\n",
791 * calculate the divider of mclk/sample_freq,
792 * factor of freq = 96 kHz can only be 256, since mclk is in the range
795 switch (sgtl5000->sysclk / frame_rate) {
797 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
798 SGTL5000_MCLK_FREQ_SHIFT;
801 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
802 SGTL5000_MCLK_FREQ_SHIFT;
805 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
806 SGTL5000_MCLK_FREQ_SHIFT;
809 /* if mclk does not satisfy the divider, use pll */
810 if (sgtl5000->master) {
811 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
812 SGTL5000_MCLK_FREQ_SHIFT;
815 "PLL not supported in slave mode\n");
816 dev_err(codec->dev, "%d ratio is not supported. "
817 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
818 sgtl5000->sysclk / frame_rate);
823 /* if using pll, please check manual 6.4.2 for detail */
824 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
828 unsigned int in, int_div, frac_div;
830 if (sgtl5000->sysclk > 17000000) {
832 in = sgtl5000->sysclk / 2;
835 in = sgtl5000->sysclk;
846 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
847 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
849 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
851 snd_soc_update_bits(codec,
852 SGTL5000_CHIP_CLK_TOP_CTRL,
853 SGTL5000_INPUT_FREQ_DIV2,
854 SGTL5000_INPUT_FREQ_DIV2);
856 snd_soc_update_bits(codec,
857 SGTL5000_CHIP_CLK_TOP_CTRL,
858 SGTL5000_INPUT_FREQ_DIV2,
862 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
863 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
864 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
866 /* if using pll, clk_ctrl must be set after pll power up */
867 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
869 /* otherwise, clk_ctrl must be set before pll power down */
870 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
873 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
874 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
882 * Set PCM DAI bit size and sample rate.
883 * input: params_rate, params_fmt
885 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
886 struct snd_pcm_hw_params *params,
887 struct snd_soc_dai *dai)
889 struct snd_soc_codec *codec = dai->codec;
890 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
891 int channels = params_channels(params);
896 /* sysclk should already set */
897 if (!sgtl5000->sysclk) {
898 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
902 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
903 stereo = SGTL5000_DAC_STEREO;
905 stereo = SGTL5000_ADC_STEREO;
907 /* set mono to save power */
908 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
909 channels == 1 ? 0 : stereo);
911 /* set codec clock base on lrclk */
912 ret = sgtl5000_set_clock(codec, params_rate(params));
916 /* set i2s data format */
917 switch (params_width(params)) {
919 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
921 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
922 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
923 SGTL5000_I2S_SCLKFREQ_SHIFT;
926 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
927 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
928 SGTL5000_I2S_SCLKFREQ_SHIFT;
931 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
932 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
933 SGTL5000_I2S_SCLKFREQ_SHIFT;
936 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
938 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
939 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
940 SGTL5000_I2S_SCLKFREQ_SHIFT;
946 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
947 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
953 #ifdef CONFIG_REGULATOR
954 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
956 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
961 static int ldo_regulator_enable(struct regulator_dev *dev)
963 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
964 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
967 if (ldo_regulator_is_enabled(dev))
970 /* set regulator value firstly */
971 reg = (1600 - ldo->voltage / 1000) / 50;
972 reg = clamp(reg, 0x0, 0xf);
974 /* amend the voltage value, unit: uV */
975 ldo->voltage = (1600 - reg * 50) * 1000;
977 /* set voltage to register */
978 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
979 SGTL5000_LINREG_VDDD_MASK, reg);
981 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
982 SGTL5000_LINEREG_D_POWERUP,
983 SGTL5000_LINEREG_D_POWERUP);
985 /* when internal ldo is enabled, simple digital power can be disabled */
986 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
987 SGTL5000_LINREG_SIMPLE_POWERUP,
994 static int ldo_regulator_disable(struct regulator_dev *dev)
996 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
997 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
999 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1000 SGTL5000_LINEREG_D_POWERUP,
1003 /* clear voltage info */
1004 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1005 SGTL5000_LINREG_VDDD_MASK, 0);
1012 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
1014 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
1016 return ldo->voltage;
1019 static struct regulator_ops ldo_regulator_ops = {
1020 .is_enabled = ldo_regulator_is_enabled,
1021 .enable = ldo_regulator_enable,
1022 .disable = ldo_regulator_disable,
1023 .get_voltage = ldo_regulator_get_voltage,
1026 static int ldo_regulator_register(struct snd_soc_codec *codec,
1027 struct regulator_init_data *init_data,
1030 struct ldo_regulator *ldo;
1031 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1032 struct regulator_config config = { };
1034 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
1039 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
1040 if (!ldo->desc.name) {
1042 dev_err(codec->dev, "failed to allocate decs name memory\n");
1046 ldo->desc.type = REGULATOR_VOLTAGE;
1047 ldo->desc.owner = THIS_MODULE;
1048 ldo->desc.ops = &ldo_regulator_ops;
1049 ldo->desc.n_voltages = 1;
1051 ldo->codec_data = codec;
1052 ldo->voltage = voltage;
1054 config.dev = codec->dev;
1055 config.driver_data = ldo;
1056 config.init_data = init_data;
1058 ldo->dev = regulator_register(&ldo->desc, &config);
1059 if (IS_ERR(ldo->dev)) {
1060 int ret = PTR_ERR(ldo->dev);
1062 dev_err(codec->dev, "failed to register regulator\n");
1063 kfree(ldo->desc.name);
1068 sgtl5000->ldo = ldo;
1073 static int ldo_regulator_remove(struct snd_soc_codec *codec)
1075 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1076 struct ldo_regulator *ldo = sgtl5000->ldo;
1081 regulator_unregister(ldo->dev);
1082 kfree(ldo->desc.name);
1088 static int ldo_regulator_register(struct snd_soc_codec *codec,
1089 struct regulator_init_data *init_data,
1092 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
1096 static int ldo_regulator_remove(struct snd_soc_codec *codec)
1104 * common state changes:
1106 * off --> standby --> prepare --> on
1107 * standby --> prepare --> on
1110 * on --> prepare --> standby
1112 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
1113 enum snd_soc_bias_level level)
1116 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1119 case SND_SOC_BIAS_ON:
1120 case SND_SOC_BIAS_PREPARE:
1122 case SND_SOC_BIAS_STANDBY:
1123 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1124 ret = regulator_bulk_enable(
1125 ARRAY_SIZE(sgtl5000->supplies),
1126 sgtl5000->supplies);
1131 regcache_cache_only(sgtl5000->regmap, false);
1133 ret = regcache_sync(sgtl5000->regmap);
1136 "Failed to restore cache: %d\n", ret);
1138 regcache_cache_only(sgtl5000->regmap, true);
1139 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1140 sgtl5000->supplies);
1147 case SND_SOC_BIAS_OFF:
1148 regcache_cache_only(sgtl5000->regmap, true);
1149 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1150 sgtl5000->supplies);
1157 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1158 SNDRV_PCM_FMTBIT_S20_3LE |\
1159 SNDRV_PCM_FMTBIT_S24_LE |\
1160 SNDRV_PCM_FMTBIT_S32_LE)
1162 static const struct snd_soc_dai_ops sgtl5000_ops = {
1163 .hw_params = sgtl5000_pcm_hw_params,
1164 .digital_mute = sgtl5000_digital_mute,
1165 .set_fmt = sgtl5000_set_dai_fmt,
1166 .set_sysclk = sgtl5000_set_dai_sysclk,
1169 static struct snd_soc_dai_driver sgtl5000_dai = {
1172 .stream_name = "Playback",
1176 * only support 8~48K + 96K,
1177 * TODO modify hw_param to support more
1179 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1180 .formats = SGTL5000_FORMATS,
1183 .stream_name = "Capture",
1186 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1187 .formats = SGTL5000_FORMATS,
1189 .ops = &sgtl5000_ops,
1190 .symmetric_rates = 1,
1193 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1196 case SGTL5000_CHIP_ID:
1197 case SGTL5000_CHIP_ADCDAC_CTRL:
1198 case SGTL5000_CHIP_ANA_STATUS:
1205 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1208 case SGTL5000_CHIP_ID:
1209 case SGTL5000_CHIP_DIG_POWER:
1210 case SGTL5000_CHIP_CLK_CTRL:
1211 case SGTL5000_CHIP_I2S_CTRL:
1212 case SGTL5000_CHIP_SSS_CTRL:
1213 case SGTL5000_CHIP_ADCDAC_CTRL:
1214 case SGTL5000_CHIP_DAC_VOL:
1215 case SGTL5000_CHIP_PAD_STRENGTH:
1216 case SGTL5000_CHIP_ANA_ADC_CTRL:
1217 case SGTL5000_CHIP_ANA_HP_CTRL:
1218 case SGTL5000_CHIP_ANA_CTRL:
1219 case SGTL5000_CHIP_LINREG_CTRL:
1220 case SGTL5000_CHIP_REF_CTRL:
1221 case SGTL5000_CHIP_MIC_CTRL:
1222 case SGTL5000_CHIP_LINE_OUT_CTRL:
1223 case SGTL5000_CHIP_LINE_OUT_VOL:
1224 case SGTL5000_CHIP_ANA_POWER:
1225 case SGTL5000_CHIP_PLL_CTRL:
1226 case SGTL5000_CHIP_CLK_TOP_CTRL:
1227 case SGTL5000_CHIP_ANA_STATUS:
1228 case SGTL5000_CHIP_SHORT_CTRL:
1229 case SGTL5000_CHIP_ANA_TEST2:
1230 case SGTL5000_DAP_CTRL:
1231 case SGTL5000_DAP_PEQ:
1232 case SGTL5000_DAP_BASS_ENHANCE:
1233 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1234 case SGTL5000_DAP_AUDIO_EQ:
1235 case SGTL5000_DAP_SURROUND:
1236 case SGTL5000_DAP_FLT_COEF_ACCESS:
1237 case SGTL5000_DAP_COEF_WR_B0_MSB:
1238 case SGTL5000_DAP_COEF_WR_B0_LSB:
1239 case SGTL5000_DAP_EQ_BASS_BAND0:
1240 case SGTL5000_DAP_EQ_BASS_BAND1:
1241 case SGTL5000_DAP_EQ_BASS_BAND2:
1242 case SGTL5000_DAP_EQ_BASS_BAND3:
1243 case SGTL5000_DAP_EQ_BASS_BAND4:
1244 case SGTL5000_DAP_MAIN_CHAN:
1245 case SGTL5000_DAP_MIX_CHAN:
1246 case SGTL5000_DAP_AVC_CTRL:
1247 case SGTL5000_DAP_AVC_THRESHOLD:
1248 case SGTL5000_DAP_AVC_ATTACK:
1249 case SGTL5000_DAP_AVC_DECAY:
1250 case SGTL5000_DAP_COEF_WR_B1_MSB:
1251 case SGTL5000_DAP_COEF_WR_B1_LSB:
1252 case SGTL5000_DAP_COEF_WR_B2_MSB:
1253 case SGTL5000_DAP_COEF_WR_B2_LSB:
1254 case SGTL5000_DAP_COEF_WR_A1_MSB:
1255 case SGTL5000_DAP_COEF_WR_A1_LSB:
1256 case SGTL5000_DAP_COEF_WR_A2_MSB:
1257 case SGTL5000_DAP_COEF_WR_A2_LSB:
1266 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1267 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1268 * The calculatation was done for all possible register values which
1269 * is the array index and the following formula: 10^((idx−15)/40) * 100
1271 static const u8 vol_quot_table[] = {
1272 42, 45, 47, 50, 53, 56, 60, 63,
1273 67, 71, 75, 79, 84, 89, 94, 100,
1274 106, 112, 119, 126, 133, 141, 150, 158,
1275 168, 178, 188, 200, 211, 224, 237, 251
1279 * sgtl5000 has 3 internal power supplies:
1280 * 1. VAG, normally set to vdda/2
1281 * 2. charge pump, set to different value
1282 * according to voltage of vdda and vddio
1283 * 3. line out VAG, normally set to vddio/2
1285 * and should be set according to:
1286 * 1. vddd provided by external or not
1287 * 2. vdda and vddio voltage value. > 3.1v or not
1288 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1290 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1302 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1304 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1305 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1306 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1309 vddio = vddio / 1000;
1312 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1313 dev_err(codec->dev, "regulator voltage not set correctly\n");
1318 /* according to datasheet, maximum voltage of supplies */
1319 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1321 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1328 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1329 ana_pwr |= SGTL5000_DAC_STEREO |
1330 SGTL5000_ADC_STEREO |
1331 SGTL5000_REFTOP_POWERUP;
1332 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1334 if (vddio < 3100 && vdda < 3100) {
1335 /* enable internal oscillator used for charge pump */
1336 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1337 SGTL5000_INT_OSC_EN,
1338 SGTL5000_INT_OSC_EN);
1339 /* Enable VDDC charge pump */
1340 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1342 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1344 * if vddio == vdda the source of charge pump should be
1345 * assigned manually to VDDIO
1347 if (vddio == vdda) {
1348 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1349 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1350 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1354 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1356 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1358 /* set voltage to register */
1359 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1360 SGTL5000_LINREG_VDDD_MASK, 0x8);
1363 * if vddd linear reg has been enabled,
1364 * simple digital supply should be clear to get
1365 * proper VDDD voltage.
1367 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1368 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1369 SGTL5000_LINREG_SIMPLE_POWERUP,
1372 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1373 SGTL5000_LINREG_SIMPLE_POWERUP |
1374 SGTL5000_STARTUP_POWERUP,
1378 * set ADC/DAC VAG to vdda / 2,
1379 * should stay in range (0.8v, 1.575v)
1382 if (vag <= SGTL5000_ANA_GND_BASE)
1384 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1385 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1386 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1388 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1390 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1391 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1393 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1395 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1397 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1398 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1399 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1401 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1402 SGTL5000_LINE_OUT_GND_STP;
1404 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1405 SGTL5000_LINE_OUT_CURRENT_MASK |
1406 SGTL5000_LINE_OUT_GND_MASK,
1407 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1408 SGTL5000_LINE_OUT_CURRENT_360u <<
1409 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1412 * Set lineout output level in range (0..31)
1413 * the same value is used for right and left channel
1415 * Searching for a suitable index solving this formula:
1416 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1418 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1420 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1421 if (vol_quot >= vol_quot_table[i])
1427 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1428 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1429 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1430 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1431 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1436 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1438 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1441 /* set internal ldo to 1.2v */
1442 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1445 "Failed to register vddd internal supplies: %d\n", ret);
1449 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1451 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1455 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1459 int external_vddd = 0;
1460 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1461 struct regulator *vddd;
1463 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1464 sgtl5000->supplies[i].supply = supply_names[i];
1466 /* External VDDD only works before revision 0x11 */
1467 if (sgtl5000->revision < 0x11) {
1468 vddd = regulator_get_optional(codec->dev, "VDDD");
1470 /* See if it's just not registered yet */
1471 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1472 return -EPROBE_DEFER;
1475 regulator_put(vddd);
1479 if (!external_vddd) {
1480 ret = sgtl5000_replace_vddd_with_ldo(codec);
1485 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1486 sgtl5000->supplies);
1488 goto err_ldo_remove;
1490 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1491 sgtl5000->supplies);
1493 goto err_regulator_free;
1495 /* wait for all power rails bring up */
1501 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1502 sgtl5000->supplies);
1505 ldo_regulator_remove(codec);
1510 static int sgtl5000_probe(struct snd_soc_codec *codec)
1513 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1515 ret = sgtl5000_enable_regulators(codec);
1519 /* power up sgtl5000 */
1520 ret = sgtl5000_set_power_regs(codec);
1524 /* enable small pop, introduce 400ms delay in turning off */
1525 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1526 SGTL5000_SMALL_POP, 1);
1528 /* disable short cut detector */
1529 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1532 * set i2s as default input of sound switch
1533 * TODO: add sound switch to control and dapm widge.
1535 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1536 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1537 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1538 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1540 /* enable dac volume ramp by default */
1541 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1542 SGTL5000_DAC_VOL_RAMP_EN |
1543 SGTL5000_DAC_MUTE_RIGHT |
1544 SGTL5000_DAC_MUTE_LEFT);
1546 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1548 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1549 SGTL5000_HP_ZCD_EN |
1550 SGTL5000_ADC_ZCD_EN);
1552 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1553 SGTL5000_BIAS_R_MASK,
1554 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1556 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1557 SGTL5000_BIAS_VOLT_MASK,
1558 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1562 * Enable DAP in kcontrol and dapm.
1564 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1569 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1570 sgtl5000->supplies);
1571 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1572 sgtl5000->supplies);
1573 ldo_regulator_remove(codec);
1578 static int sgtl5000_remove(struct snd_soc_codec *codec)
1580 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1582 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1583 sgtl5000->supplies);
1584 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1585 sgtl5000->supplies);
1586 ldo_regulator_remove(codec);
1591 static struct snd_soc_codec_driver sgtl5000_driver = {
1592 .probe = sgtl5000_probe,
1593 .remove = sgtl5000_remove,
1594 .set_bias_level = sgtl5000_set_bias_level,
1595 .suspend_bias_off = true,
1596 .controls = sgtl5000_snd_controls,
1597 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1598 .dapm_widgets = sgtl5000_dapm_widgets,
1599 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1600 .dapm_routes = sgtl5000_dapm_routes,
1601 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1604 static const struct regmap_config sgtl5000_regmap = {
1609 .max_register = SGTL5000_MAX_REG_OFFSET,
1610 .volatile_reg = sgtl5000_volatile,
1611 .readable_reg = sgtl5000_readable,
1613 .cache_type = REGCACHE_RBTREE,
1614 .reg_defaults = sgtl5000_reg_defaults,
1615 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1619 * Write all the default values from sgtl5000_reg_defaults[] array into the
1620 * sgtl5000 registers, to make sure we always start with the sane registers
1621 * values as stated in the datasheet.
1623 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1624 * we follow this approach to guarantee we always start from the default values
1625 * and avoid problems like, not being able to probe after an audio playback
1626 * followed by a system reset or a 'reboot' command in Linux
1628 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1630 int i, ret, val, index;
1632 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1633 val = sgtl5000_reg_defaults[i].def;
1634 index = sgtl5000_reg_defaults[i].reg;
1635 ret = regmap_write(sgtl5000->regmap, index, val);
1643 static int sgtl5000_i2c_probe(struct i2c_client *client,
1644 const struct i2c_device_id *id)
1646 struct sgtl5000_priv *sgtl5000;
1648 struct device_node *np = client->dev.of_node;
1651 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1655 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1656 if (IS_ERR(sgtl5000->regmap)) {
1657 ret = PTR_ERR(sgtl5000->regmap);
1658 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1662 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1663 if (IS_ERR(sgtl5000->mclk)) {
1664 ret = PTR_ERR(sgtl5000->mclk);
1665 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1666 /* Defer the probe to see if the clk will be provided later */
1668 return -EPROBE_DEFER;
1672 ret = clk_prepare_enable(sgtl5000->mclk);
1676 /* Need 8 clocks before I2C accesses */
1679 /* read chip information */
1680 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1684 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1685 SGTL5000_PARTID_PART_ID) {
1686 dev_err(&client->dev,
1687 "Device with ID register %x is not a sgtl5000\n", reg);
1692 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1693 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1694 sgtl5000->revision = rev;
1697 if (!of_property_read_u32(np,
1698 "micbias-resistor-k-ohms", &value)) {
1700 case SGTL5000_MICBIAS_OFF:
1701 sgtl5000->micbias_resistor = 0;
1703 case SGTL5000_MICBIAS_2K:
1704 sgtl5000->micbias_resistor = 1;
1706 case SGTL5000_MICBIAS_4K:
1707 sgtl5000->micbias_resistor = 2;
1709 case SGTL5000_MICBIAS_8K:
1710 sgtl5000->micbias_resistor = 3;
1713 sgtl5000->micbias_resistor = 2;
1714 dev_err(&client->dev,
1715 "Unsuitable MicBias resistor\n");
1718 /* default is 4Kohms */
1719 sgtl5000->micbias_resistor = 2;
1721 if (!of_property_read_u32(np,
1722 "micbias-voltage-m-volts", &value)) {
1724 /* steps of 250mV */
1725 if ((value >= 1250) && (value <= 3000))
1726 sgtl5000->micbias_voltage = (value / 250) - 5;
1728 sgtl5000->micbias_voltage = 0;
1729 dev_err(&client->dev,
1730 "Unsuitable MicBias voltage\n");
1733 sgtl5000->micbias_voltage = 0;
1737 i2c_set_clientdata(client, sgtl5000);
1739 /* Ensure sgtl5000 will start with sane register values */
1740 ret = sgtl5000_fill_defaults(sgtl5000);
1744 ret = snd_soc_register_codec(&client->dev,
1745 &sgtl5000_driver, &sgtl5000_dai, 1);
1752 clk_disable_unprepare(sgtl5000->mclk);
1756 static int sgtl5000_i2c_remove(struct i2c_client *client)
1758 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1760 snd_soc_unregister_codec(&client->dev);
1761 clk_disable_unprepare(sgtl5000->mclk);
1765 static const struct i2c_device_id sgtl5000_id[] = {
1770 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1772 static const struct of_device_id sgtl5000_dt_ids[] = {
1773 { .compatible = "fsl,sgtl5000", },
1776 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1778 static struct i2c_driver sgtl5000_i2c_driver = {
1781 .of_match_table = sgtl5000_dt_ids,
1783 .probe = sgtl5000_i2c_probe,
1784 .remove = sgtl5000_i2c_remove,
1785 .id_table = sgtl5000_id,
1788 module_i2c_driver(sgtl5000_i2c_driver);
1790 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1791 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1792 MODULE_LICENSE("GPL");