2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* Delay for the VAG ramp up */
39 #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
40 /* Delay for the VAG ramp down */
41 #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
43 #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
45 /* default value of sgtl5000 registers */
46 static const struct reg_default sgtl5000_reg_defaults[] = {
47 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
48 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
49 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
50 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
51 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
52 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
53 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
54 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
55 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
56 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
57 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
58 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
59 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
60 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
61 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
62 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
63 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
64 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
65 { SGTL5000_DAP_CTRL, 0x0000 },
66 { SGTL5000_DAP_PEQ, 0x0000 },
67 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
68 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
69 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
70 { SGTL5000_DAP_SURROUND, 0x0040 },
71 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
72 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
73 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
74 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
75 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
76 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
77 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
78 { SGTL5000_DAP_AVC_CTRL, 0x5100 },
79 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
80 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
81 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
84 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
85 enum sgtl5000_regulator_supplies {
92 /* vddd is optional supply */
93 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
99 #define LDO_VOLTAGE 1200000
100 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
102 enum sgtl5000_micbias_resistor {
103 SGTL5000_MICBIAS_OFF = 0,
104 SGTL5000_MICBIAS_2K = 2,
105 SGTL5000_MICBIAS_4K = 4,
106 SGTL5000_MICBIAS_8K = 8,
113 LAST_POWER_EVENT = ADC_POWER_EVENT
116 /* sgtl5000 private structure in codec */
117 struct sgtl5000_priv {
118 int sysclk; /* sysclk rate */
119 int master; /* i2s master or not */
120 int fmt; /* i2s data format */
121 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
123 struct regmap *regmap;
128 u16 mute_state[LAST_POWER_EVENT + 1];
131 static inline int hp_sel_input(struct snd_soc_component *component)
133 unsigned int ana_reg = 0;
135 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &ana_reg);
137 return (ana_reg & SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
140 static inline u16 mute_output(struct snd_soc_component *component,
143 unsigned int mute_reg = 0;
145 snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL, &mute_reg);
147 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
148 mute_mask, mute_mask);
152 static inline void restore_output(struct snd_soc_component *component,
153 u16 mute_mask, u16 mute_reg)
155 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
156 mute_mask, mute_reg);
159 static void vag_power_on(struct snd_soc_component *component, u32 source)
161 unsigned int ana_reg = 0;
163 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_reg);
165 if (ana_reg & SGTL5000_VAG_POWERUP)
168 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
169 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
171 /* When VAG powering on to get local loop from Line-In, the sleep
172 * is required to avoid loud pop.
174 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
175 source == HP_POWER_EVENT)
176 msleep(SGTL5000_VAG_POWERUP_DELAY);
179 static int vag_power_consumers(struct snd_soc_component *component,
180 u16 ana_pwr_reg, u32 source)
184 /* count dac/adc consumers unconditional */
185 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
187 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
191 * If the event comes from HP and Line-In is selected,
192 * current action is 'DAC to be powered down'.
193 * As HP_POWERUP is not set when HP muxed to line-in,
194 * we need to keep VAG power ON.
196 if (source == HP_POWER_EVENT) {
197 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
200 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
207 static void vag_power_off(struct snd_soc_component *component, u32 source)
209 unsigned int ana_pwr = SGTL5000_VAG_POWERUP;
211 snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER, &ana_pwr);
213 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
217 * This function calls when any of VAG power consumers is disappearing.
218 * Thus, if there is more than one consumer at the moment, as minimum
219 * one consumer will definitely stay after the end of the current
221 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
222 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
225 * (the current consumer is disappearing right now)
227 if (vag_power_consumers(component, ana_pwr, source) >= 2)
230 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
231 SGTL5000_VAG_POWERUP, 0);
232 /* In power down case, we need wait 400-1000 ms
233 * when VAG fully ramped down.
234 * As longer we wait, as smaller pop we've got.
236 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
240 * mic_bias power on/off share the same register bits with
241 * output impedance of mic bias, when power on mic bias, we
242 * need reclaim it to impedance value.
248 static int mic_bias_event(struct snd_soc_dapm_widget *w,
249 struct snd_kcontrol *kcontrol, int event)
251 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
252 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
255 case SND_SOC_DAPM_POST_PMU:
256 /* change mic bias resistor */
257 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
258 SGTL5000_BIAS_R_MASK,
259 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
262 case SND_SOC_DAPM_PRE_PMD:
263 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
264 SGTL5000_BIAS_R_MASK, 0);
270 static int vag_and_mute_control(struct snd_soc_component *component,
271 int event, int event_source)
273 static const u16 mute_mask[] = {
275 * Mask for HP_POWER_EVENT.
276 * Muxing Headphones have to be wrapped with mute/unmute
281 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
282 * Muxing DAC or ADC block have to be wrapped with mute/unmute
283 * both headphones and line-out.
285 SGTL5000_OUTPUTS_MUTE,
286 SGTL5000_OUTPUTS_MUTE
289 struct sgtl5000_priv *sgtl5000 =
290 snd_soc_component_get_drvdata(component);
293 case SND_SOC_DAPM_PRE_PMU:
294 sgtl5000->mute_state[event_source] =
295 mute_output(component, mute_mask[event_source]);
297 case SND_SOC_DAPM_POST_PMU:
298 vag_power_on(component, event_source);
299 restore_output(component, mute_mask[event_source],
300 sgtl5000->mute_state[event_source]);
302 case SND_SOC_DAPM_PRE_PMD:
303 sgtl5000->mute_state[event_source] =
304 mute_output(component, mute_mask[event_source]);
305 vag_power_off(component, event_source);
307 case SND_SOC_DAPM_POST_PMD:
308 restore_output(component, mute_mask[event_source],
309 sgtl5000->mute_state[event_source]);
319 * Mute Headphone when power it up/down.
320 * Control VAG power on HP power path.
322 static int headphone_pga_event(struct snd_soc_dapm_widget *w,
323 struct snd_kcontrol *kcontrol, int event)
325 struct snd_soc_component *component =
326 snd_soc_dapm_to_component(w->dapm);
328 return vag_and_mute_control(component, event, HP_POWER_EVENT);
331 /* As manual describes, ADC/DAC powering up/down requires
332 * to mute outputs to avoid pops.
333 * Control VAG power on ADC/DAC power path.
335 static int adc_updown_depop(struct snd_soc_dapm_widget *w,
336 struct snd_kcontrol *kcontrol, int event)
338 struct snd_soc_component *component =
339 snd_soc_dapm_to_component(w->dapm);
341 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
344 static int dac_updown_depop(struct snd_soc_dapm_widget *w,
345 struct snd_kcontrol *kcontrol, int event)
347 struct snd_soc_component *component =
348 snd_soc_dapm_to_component(w->dapm);
350 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
353 /* input sources for ADC */
354 static const char *adc_mux_text[] = {
358 static SOC_ENUM_SINGLE_DECL(adc_enum,
359 SGTL5000_CHIP_ANA_CTRL, 2,
362 static const struct snd_kcontrol_new adc_mux =
363 SOC_DAPM_ENUM("Capture Mux", adc_enum);
365 /* input sources for DAC */
366 static const char *dac_mux_text[] = {
370 static SOC_ENUM_SINGLE_DECL(dac_enum,
371 SGTL5000_CHIP_ANA_CTRL, 6,
374 static const struct snd_kcontrol_new dac_mux =
375 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
377 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
378 SND_SOC_DAPM_INPUT("LINE_IN"),
379 SND_SOC_DAPM_INPUT("MIC_IN"),
381 SND_SOC_DAPM_OUTPUT("HP_OUT"),
382 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
384 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
386 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
388 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
390 SND_SOC_DAPM_PRE_POST_PMU |
391 SND_SOC_DAPM_PRE_POST_PMD),
392 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
394 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
395 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
397 /* aif for i2s input */
398 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
399 0, SGTL5000_CHIP_DIG_POWER,
402 /* aif for i2s output */
403 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
404 0, SGTL5000_CHIP_DIG_POWER,
407 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
408 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
409 SND_SOC_DAPM_PRE_POST_PMD),
410 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
411 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
412 SND_SOC_DAPM_PRE_POST_PMD),
415 /* routes for sgtl5000 */
416 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
417 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
418 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
420 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
421 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
423 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
424 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
425 {"LO", NULL, "DAC"}, /* dac --> line_out */
427 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
428 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
430 {"LINE_OUT", NULL, "LO"},
431 {"HP_OUT", NULL, "HP"},
434 /* custom function to fetch info of PCM playback volume */
435 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_info *uinfo)
438 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
440 uinfo->value.integer.min = 0;
441 uinfo->value.integer.max = 0xfc - 0x3c;
446 * custom function to get of PCM playback volume
448 * dac volume register
449 * 15-------------8-7--------------0
450 * | R channel vol | L channel vol |
451 * -------------------------------
453 * PCM volume with 0.5017 dB steps from 0 to -90 dB
455 * register values map to dB
456 * 0x3B and less = Reserved
460 * 0xFC and greater = Muted
462 * register value map to userspace value
464 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
465 * ------------------------------
466 * userspace value 0xc0 0
468 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
469 struct snd_ctl_elem_value *ucontrol)
471 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
476 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
478 /* get left channel volume */
479 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
481 /* get right channel volume */
482 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
484 /* make sure value fall in (0x3c,0xfc) */
485 l = clamp(l, 0x3c, 0xfc);
486 r = clamp(r, 0x3c, 0xfc);
488 /* invert it and map to userspace value */
492 ucontrol->value.integer.value[0] = l;
493 ucontrol->value.integer.value[1] = r;
499 * custom function to put of PCM playback volume
501 * dac volume register
502 * 15-------------8-7--------------0
503 * | R channel vol | L channel vol |
504 * -------------------------------
506 * PCM volume with 0.5017 dB steps from 0 to -90 dB
508 * register values map to dB
509 * 0x3B and less = Reserved
513 * 0xFC and greater = Muted
515 * userspace value map to register value
517 * userspace value 0xc0 0
518 * ------------------------------
519 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
521 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
522 struct snd_ctl_elem_value *ucontrol)
524 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
529 l = ucontrol->value.integer.value[0];
530 r = ucontrol->value.integer.value[1];
532 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
533 l = clamp(l, 0, 0xfc - 0x3c);
534 r = clamp(r, 0, 0xfc - 0x3c);
536 /* invert it, get the value can be set to register */
540 /* shift to get the register value */
541 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
542 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
544 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
549 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
551 /* tlv for mic gain, 0db 20db 30db 40db */
552 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
553 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
554 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
557 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
558 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
560 /* tlv for lineout volume, 31 steps of .5db each */
561 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
563 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
564 /* SOC_DOUBLE_S8_TLV with invert */
566 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
567 .name = "PCM Playback Volume",
568 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
569 SNDRV_CTL_ELEM_ACCESS_READWRITE,
570 .info = dac_info_volsw,
571 .get = dac_get_volsw,
572 .put = dac_put_volsw,
575 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
576 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
577 SGTL5000_CHIP_ANA_ADC_CTRL,
578 8, 1, 0, capture_6db_attenuate),
579 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
581 SOC_DOUBLE_TLV("Headphone Playback Volume",
582 SGTL5000_CHIP_ANA_HP_CTRL,
586 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
588 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
591 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
592 0, 3, 0, mic_gain_tlv),
594 SOC_DOUBLE_TLV("Lineout Playback Volume",
595 SGTL5000_CHIP_LINE_OUT_VOL,
596 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
597 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
600 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
603 /* mute the codec used by alsa core */
604 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
606 struct snd_soc_codec *codec = codec_dai->codec;
607 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
609 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
610 adcdac_ctrl, mute ? adcdac_ctrl : 0);
615 /* set codec format */
616 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
618 struct snd_soc_codec *codec = codec_dai->codec;
619 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
622 sgtl5000->master = 0;
624 * i2s clock and frame master setting.
626 * - clock and frame slave,
627 * - clock and frame master
629 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
630 case SND_SOC_DAIFMT_CBS_CFS:
632 case SND_SOC_DAIFMT_CBM_CFM:
633 i2sctl |= SGTL5000_I2S_MASTER;
634 sgtl5000->master = 1;
640 /* setting i2s data format */
641 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
642 case SND_SOC_DAIFMT_DSP_A:
643 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
645 case SND_SOC_DAIFMT_DSP_B:
646 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
647 i2sctl |= SGTL5000_I2S_LRALIGN;
649 case SND_SOC_DAIFMT_I2S:
650 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
652 case SND_SOC_DAIFMT_RIGHT_J:
653 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
654 i2sctl |= SGTL5000_I2S_LRPOL;
656 case SND_SOC_DAIFMT_LEFT_J:
657 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
658 i2sctl |= SGTL5000_I2S_LRALIGN;
664 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
666 /* Clock inversion */
667 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
668 case SND_SOC_DAIFMT_NB_NF:
670 case SND_SOC_DAIFMT_IB_NF:
671 i2sctl |= SGTL5000_I2S_SCLK_INV;
677 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
682 /* set codec sysclk */
683 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
684 int clk_id, unsigned int freq, int dir)
686 struct snd_soc_codec *codec = codec_dai->codec;
687 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
690 case SGTL5000_SYSCLK:
691 sgtl5000->sysclk = freq;
701 * set clock according to i2s frame clock,
702 * sgtl5000 provides 2 clock sources:
703 * 1. sys_mclk: sample freq can only be configured to
704 * 1/256, 1/384, 1/512 of sys_mclk.
705 * 2. pll: can derive any audio clocks.
707 * clock setting rules:
708 * 1. in slave mode, only sys_mclk can be used
709 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
711 * 3. usage of sys_mclk is preferred over pll to save power.
713 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
715 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
717 int sys_fs; /* sample freq */
720 * sample freq should be divided by frame clock,
721 * if frame clock is lower than 44.1 kHz, sample freq should be set to
722 * 32 kHz or 44.1 kHz.
724 switch (frame_rate) {
738 /* set divided factor of frame clock */
739 switch (sys_fs / frame_rate) {
741 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
744 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
747 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
753 /* set the sys_fs according to frame rate */
756 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
759 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
762 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
765 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
768 dev_err(codec->dev, "frame rate %d not supported\n",
774 * calculate the divider of mclk/sample_freq,
775 * factor of freq = 96 kHz can only be 256, since mclk is in the range
778 switch (sgtl5000->sysclk / frame_rate) {
780 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
781 SGTL5000_MCLK_FREQ_SHIFT;
784 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
785 SGTL5000_MCLK_FREQ_SHIFT;
788 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
789 SGTL5000_MCLK_FREQ_SHIFT;
792 /* if mclk does not satisfy the divider, use pll */
793 if (sgtl5000->master) {
794 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
795 SGTL5000_MCLK_FREQ_SHIFT;
798 "PLL not supported in slave mode\n");
799 dev_err(codec->dev, "%d ratio is not supported. "
800 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
801 sgtl5000->sysclk / frame_rate);
806 /* if using pll, please check manual 6.4.2 for detail */
807 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
811 unsigned int in, int_div, frac_div;
813 if (sgtl5000->sysclk > 17000000) {
815 in = sgtl5000->sysclk / 2;
818 in = sgtl5000->sysclk;
829 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
830 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
832 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
834 snd_soc_update_bits(codec,
835 SGTL5000_CHIP_CLK_TOP_CTRL,
836 SGTL5000_INPUT_FREQ_DIV2,
837 SGTL5000_INPUT_FREQ_DIV2);
839 snd_soc_update_bits(codec,
840 SGTL5000_CHIP_CLK_TOP_CTRL,
841 SGTL5000_INPUT_FREQ_DIV2,
845 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
846 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
847 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
849 /* if using pll, clk_ctrl must be set after pll power up */
850 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
852 /* otherwise, clk_ctrl must be set before pll power down */
853 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
856 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
857 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
865 * Set PCM DAI bit size and sample rate.
866 * input: params_rate, params_fmt
868 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
869 struct snd_pcm_hw_params *params,
870 struct snd_soc_dai *dai)
872 struct snd_soc_codec *codec = dai->codec;
873 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
874 int channels = params_channels(params);
879 /* sysclk should already set */
880 if (!sgtl5000->sysclk) {
881 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
885 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
886 stereo = SGTL5000_DAC_STEREO;
888 stereo = SGTL5000_ADC_STEREO;
890 /* set mono to save power */
891 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
892 channels == 1 ? 0 : stereo);
894 /* set codec clock base on lrclk */
895 ret = sgtl5000_set_clock(codec, params_rate(params));
899 /* set i2s data format */
900 switch (params_width(params)) {
902 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
904 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
905 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
906 SGTL5000_I2S_SCLKFREQ_SHIFT;
909 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
910 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
911 SGTL5000_I2S_SCLKFREQ_SHIFT;
914 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
915 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
916 SGTL5000_I2S_SCLKFREQ_SHIFT;
919 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
921 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
922 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
923 SGTL5000_I2S_SCLKFREQ_SHIFT;
929 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
930 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
938 * common state changes:
940 * off --> standby --> prepare --> on
941 * standby --> prepare --> on
944 * on --> prepare --> standby
946 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
947 enum snd_soc_bias_level level)
949 struct sgtl5000_priv *sgtl = snd_soc_codec_get_drvdata(codec);
953 case SND_SOC_BIAS_ON:
954 case SND_SOC_BIAS_PREPARE:
955 case SND_SOC_BIAS_STANDBY:
956 regcache_cache_only(sgtl->regmap, false);
957 ret = regcache_sync(sgtl->regmap);
959 regcache_cache_only(sgtl->regmap, true);
963 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
964 SGTL5000_REFTOP_POWERUP,
965 SGTL5000_REFTOP_POWERUP);
967 case SND_SOC_BIAS_OFF:
968 regcache_cache_only(sgtl->regmap, true);
969 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
970 SGTL5000_REFTOP_POWERUP, 0);
977 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
978 SNDRV_PCM_FMTBIT_S20_3LE |\
979 SNDRV_PCM_FMTBIT_S24_LE |\
980 SNDRV_PCM_FMTBIT_S32_LE)
982 static const struct snd_soc_dai_ops sgtl5000_ops = {
983 .hw_params = sgtl5000_pcm_hw_params,
984 .digital_mute = sgtl5000_digital_mute,
985 .set_fmt = sgtl5000_set_dai_fmt,
986 .set_sysclk = sgtl5000_set_dai_sysclk,
989 static struct snd_soc_dai_driver sgtl5000_dai = {
992 .stream_name = "Playback",
996 * only support 8~48K + 96K,
997 * TODO modify hw_param to support more
999 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1000 .formats = SGTL5000_FORMATS,
1003 .stream_name = "Capture",
1006 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1007 .formats = SGTL5000_FORMATS,
1009 .ops = &sgtl5000_ops,
1010 .symmetric_rates = 1,
1013 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1016 case SGTL5000_CHIP_ID:
1017 case SGTL5000_CHIP_ADCDAC_CTRL:
1018 case SGTL5000_CHIP_ANA_STATUS:
1025 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1028 case SGTL5000_CHIP_ID:
1029 case SGTL5000_CHIP_DIG_POWER:
1030 case SGTL5000_CHIP_CLK_CTRL:
1031 case SGTL5000_CHIP_I2S_CTRL:
1032 case SGTL5000_CHIP_SSS_CTRL:
1033 case SGTL5000_CHIP_ADCDAC_CTRL:
1034 case SGTL5000_CHIP_DAC_VOL:
1035 case SGTL5000_CHIP_PAD_STRENGTH:
1036 case SGTL5000_CHIP_ANA_ADC_CTRL:
1037 case SGTL5000_CHIP_ANA_HP_CTRL:
1038 case SGTL5000_CHIP_ANA_CTRL:
1039 case SGTL5000_CHIP_LINREG_CTRL:
1040 case SGTL5000_CHIP_REF_CTRL:
1041 case SGTL5000_CHIP_MIC_CTRL:
1042 case SGTL5000_CHIP_LINE_OUT_CTRL:
1043 case SGTL5000_CHIP_LINE_OUT_VOL:
1044 case SGTL5000_CHIP_ANA_POWER:
1045 case SGTL5000_CHIP_PLL_CTRL:
1046 case SGTL5000_CHIP_CLK_TOP_CTRL:
1047 case SGTL5000_CHIP_ANA_STATUS:
1048 case SGTL5000_CHIP_SHORT_CTRL:
1049 case SGTL5000_CHIP_ANA_TEST2:
1050 case SGTL5000_DAP_CTRL:
1051 case SGTL5000_DAP_PEQ:
1052 case SGTL5000_DAP_BASS_ENHANCE:
1053 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1054 case SGTL5000_DAP_AUDIO_EQ:
1055 case SGTL5000_DAP_SURROUND:
1056 case SGTL5000_DAP_FLT_COEF_ACCESS:
1057 case SGTL5000_DAP_COEF_WR_B0_MSB:
1058 case SGTL5000_DAP_COEF_WR_B0_LSB:
1059 case SGTL5000_DAP_EQ_BASS_BAND0:
1060 case SGTL5000_DAP_EQ_BASS_BAND1:
1061 case SGTL5000_DAP_EQ_BASS_BAND2:
1062 case SGTL5000_DAP_EQ_BASS_BAND3:
1063 case SGTL5000_DAP_EQ_BASS_BAND4:
1064 case SGTL5000_DAP_MAIN_CHAN:
1065 case SGTL5000_DAP_MIX_CHAN:
1066 case SGTL5000_DAP_AVC_CTRL:
1067 case SGTL5000_DAP_AVC_THRESHOLD:
1068 case SGTL5000_DAP_AVC_ATTACK:
1069 case SGTL5000_DAP_AVC_DECAY:
1070 case SGTL5000_DAP_COEF_WR_B1_MSB:
1071 case SGTL5000_DAP_COEF_WR_B1_LSB:
1072 case SGTL5000_DAP_COEF_WR_B2_MSB:
1073 case SGTL5000_DAP_COEF_WR_B2_LSB:
1074 case SGTL5000_DAP_COEF_WR_A1_MSB:
1075 case SGTL5000_DAP_COEF_WR_A1_LSB:
1076 case SGTL5000_DAP_COEF_WR_A2_MSB:
1077 case SGTL5000_DAP_COEF_WR_A2_LSB:
1086 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1087 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1088 * The calculatation was done for all possible register values which
1089 * is the array index and the following formula: 10^((idx−15)/40) * 100
1091 static const u8 vol_quot_table[] = {
1092 42, 45, 47, 50, 53, 56, 60, 63,
1093 67, 71, 75, 79, 84, 89, 94, 100,
1094 106, 112, 119, 126, 133, 141, 150, 158,
1095 168, 178, 188, 200, 211, 224, 237, 251
1099 * sgtl5000 has 3 internal power supplies:
1100 * 1. VAG, normally set to vdda/2
1101 * 2. charge pump, set to different value
1102 * according to voltage of vdda and vddio
1103 * 3. line out VAG, normally set to vddio/2
1105 * and should be set according to:
1106 * 1. vddd provided by external or not
1107 * 2. vdda and vddio voltage value. > 3.1v or not
1109 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1121 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1123 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1124 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1125 vddd = (sgtl5000->num_supplies > VDDD)
1126 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1130 vddio = vddio / 1000;
1133 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1134 dev_err(codec->dev, "regulator voltage not set correctly\n");
1139 /* according to datasheet, maximum voltage of supplies */
1140 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1142 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1149 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1150 ana_pwr |= SGTL5000_DAC_STEREO |
1151 SGTL5000_ADC_STEREO |
1152 SGTL5000_REFTOP_POWERUP;
1153 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1155 if (vddio < 3100 && vdda < 3100) {
1156 /* enable internal oscillator used for charge pump */
1157 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1158 SGTL5000_INT_OSC_EN,
1159 SGTL5000_INT_OSC_EN);
1160 /* Enable VDDC charge pump */
1161 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1163 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1165 * if vddio == vdda the source of charge pump should be
1166 * assigned manually to VDDIO
1168 if (vddio == vdda) {
1169 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1170 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1171 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1175 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1177 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1180 * set ADC/DAC VAG to vdda / 2,
1181 * should stay in range (0.8v, 1.575v)
1184 if (vag <= SGTL5000_ANA_GND_BASE)
1186 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1187 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1188 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1190 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1192 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1193 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1195 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1197 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1199 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1200 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1201 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1203 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1204 SGTL5000_LINE_OUT_GND_STP;
1206 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1207 SGTL5000_LINE_OUT_CURRENT_MASK |
1208 SGTL5000_LINE_OUT_GND_MASK,
1209 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1210 SGTL5000_LINE_OUT_CURRENT_360u <<
1211 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1214 * Set lineout output level in range (0..31)
1215 * the same value is used for right and left channel
1217 * Searching for a suitable index solving this formula:
1218 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1220 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1222 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1223 if (vol_quot >= vol_quot_table[i])
1229 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1230 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1231 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1232 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1233 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1238 static int sgtl5000_enable_regulators(struct i2c_client *client)
1242 int external_vddd = 0;
1243 struct regulator *vddd;
1244 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1246 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1247 sgtl5000->supplies[i].supply = supply_names[i];
1249 vddd = regulator_get_optional(&client->dev, "VDDD");
1251 /* See if it's just not registered yet */
1252 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1253 return -EPROBE_DEFER;
1256 regulator_put(vddd);
1259 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1260 - 1 + external_vddd;
1261 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1262 sgtl5000->supplies);
1266 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1267 sgtl5000->supplies);
1269 usleep_range(10, 20);
1271 regulator_bulk_free(sgtl5000->num_supplies,
1272 sgtl5000->supplies);
1277 static int sgtl5000_probe(struct snd_soc_codec *codec)
1280 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1282 /* power up sgtl5000 */
1283 ret = sgtl5000_set_power_regs(codec);
1287 /* enable small pop, introduce 400ms delay in turning off */
1288 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1289 SGTL5000_SMALL_POP, 1);
1291 /* disable short cut detector */
1292 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1295 * set i2s as default input of sound switch
1296 * TODO: add sound switch to control and dapm widge.
1298 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1299 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1300 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1301 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1303 /* enable dac volume ramp by default */
1304 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1305 SGTL5000_DAC_VOL_RAMP_EN |
1306 SGTL5000_DAC_MUTE_RIGHT |
1307 SGTL5000_DAC_MUTE_LEFT);
1309 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1311 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1312 SGTL5000_HP_ZCD_EN |
1313 SGTL5000_ADC_ZCD_EN);
1315 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1316 SGTL5000_BIAS_R_MASK,
1317 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1319 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1320 SGTL5000_BIAS_VOLT_MASK,
1321 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1325 * Enable DAP in kcontrol and dapm.
1327 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1335 static int sgtl5000_remove(struct snd_soc_codec *codec)
1340 static struct snd_soc_codec_driver sgtl5000_driver = {
1341 .probe = sgtl5000_probe,
1342 .remove = sgtl5000_remove,
1343 .set_bias_level = sgtl5000_set_bias_level,
1344 .suspend_bias_off = true,
1345 .component_driver = {
1346 .controls = sgtl5000_snd_controls,
1347 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1348 .dapm_widgets = sgtl5000_dapm_widgets,
1349 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1350 .dapm_routes = sgtl5000_dapm_routes,
1351 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1355 static const struct regmap_config sgtl5000_regmap = {
1360 .max_register = SGTL5000_MAX_REG_OFFSET,
1361 .volatile_reg = sgtl5000_volatile,
1362 .readable_reg = sgtl5000_readable,
1364 .cache_type = REGCACHE_RBTREE,
1365 .reg_defaults = sgtl5000_reg_defaults,
1366 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1370 * Write all the default values from sgtl5000_reg_defaults[] array into the
1371 * sgtl5000 registers, to make sure we always start with the sane registers
1372 * values as stated in the datasheet.
1374 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1375 * we follow this approach to guarantee we always start from the default values
1376 * and avoid problems like, not being able to probe after an audio playback
1377 * followed by a system reset or a 'reboot' command in Linux
1379 static void sgtl5000_fill_defaults(struct i2c_client *client)
1381 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1382 int i, ret, val, index;
1384 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1385 val = sgtl5000_reg_defaults[i].def;
1386 index = sgtl5000_reg_defaults[i].reg;
1387 ret = regmap_write(sgtl5000->regmap, index, val);
1389 dev_err(&client->dev,
1390 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1391 __func__, ret, index, val);
1395 static int sgtl5000_i2c_probe(struct i2c_client *client,
1396 const struct i2c_device_id *id)
1398 struct sgtl5000_priv *sgtl5000;
1400 struct device_node *np = client->dev.of_node;
1404 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1408 i2c_set_clientdata(client, sgtl5000);
1410 ret = sgtl5000_enable_regulators(client);
1414 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1415 if (IS_ERR(sgtl5000->regmap)) {
1416 ret = PTR_ERR(sgtl5000->regmap);
1417 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1421 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1422 if (IS_ERR(sgtl5000->mclk)) {
1423 ret = PTR_ERR(sgtl5000->mclk);
1424 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1425 /* Defer the probe to see if the clk will be provided later */
1427 ret = -EPROBE_DEFER;
1431 ret = clk_prepare_enable(sgtl5000->mclk);
1433 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1437 /* Need 8 clocks before I2C accesses */
1440 /* read chip information */
1441 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1443 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1447 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1448 SGTL5000_PARTID_PART_ID) {
1449 dev_err(&client->dev,
1450 "Device with ID register %x is not a sgtl5000\n", reg);
1455 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1456 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1457 sgtl5000->revision = rev;
1459 /* reconfigure the clocks in case we're using the PLL */
1460 ret = regmap_write(sgtl5000->regmap,
1461 SGTL5000_CHIP_CLK_CTRL,
1462 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1464 dev_err(&client->dev,
1465 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1467 /* Mute everything to avoid pop from the following power-up */
1468 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
1469 SGTL5000_CHIP_ANA_CTRL_DEFAULT);
1471 dev_err(&client->dev,
1472 "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
1477 * If VAG is powered-on (e.g. from previous boot), it would be disabled
1478 * by the write to ANA_POWER in later steps of the probe code. This
1479 * may create a loud pop even with all outputs muted. The proper way
1480 * to circumvent this is disabling the bit first and waiting the proper
1483 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
1485 dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
1488 if (value & SGTL5000_VAG_POWERUP) {
1489 ret = regmap_update_bits(sgtl5000->regmap,
1490 SGTL5000_CHIP_ANA_POWER,
1491 SGTL5000_VAG_POWERUP,
1494 dev_err(&client->dev, "Error %d disabling VAG\n", ret);
1498 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
1501 /* Follow section 2.2.1.1 of AN3663 */
1502 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1503 if (sgtl5000->num_supplies <= VDDD) {
1504 /* internal VDDD at 1.2V */
1505 ret = regmap_update_bits(sgtl5000->regmap,
1506 SGTL5000_CHIP_LINREG_CTRL,
1507 SGTL5000_LINREG_VDDD_MASK,
1510 dev_err(&client->dev,
1511 "Error %d setting LINREG_VDDD\n", ret);
1513 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1514 dev_info(&client->dev,
1515 "Using internal LDO instead of VDDD: check ER1\n");
1517 /* using external LDO for VDDD
1518 * Clear startup powerup and simple powerup
1519 * bits to save power
1521 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1522 | SGTL5000_LINREG_SIMPLE_POWERUP);
1523 dev_dbg(&client->dev, "Using external VDDD\n");
1525 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1527 dev_err(&client->dev,
1528 "Error %d setting CHIP_ANA_POWER to %04x\n",
1532 if (!of_property_read_u32(np,
1533 "micbias-resistor-k-ohms", &value)) {
1535 case SGTL5000_MICBIAS_OFF:
1536 sgtl5000->micbias_resistor = 0;
1538 case SGTL5000_MICBIAS_2K:
1539 sgtl5000->micbias_resistor = 1;
1541 case SGTL5000_MICBIAS_4K:
1542 sgtl5000->micbias_resistor = 2;
1544 case SGTL5000_MICBIAS_8K:
1545 sgtl5000->micbias_resistor = 3;
1548 sgtl5000->micbias_resistor = 2;
1549 dev_err(&client->dev,
1550 "Unsuitable MicBias resistor\n");
1553 /* default is 4Kohms */
1554 sgtl5000->micbias_resistor = 2;
1556 if (!of_property_read_u32(np,
1557 "micbias-voltage-m-volts", &value)) {
1559 /* steps of 250mV */
1560 if ((value >= 1250) && (value <= 3000))
1561 sgtl5000->micbias_voltage = (value / 250) - 5;
1563 sgtl5000->micbias_voltage = 0;
1564 dev_err(&client->dev,
1565 "Unsuitable MicBias voltage\n");
1568 sgtl5000->micbias_voltage = 0;
1572 /* Ensure sgtl5000 will start with sane register values */
1573 sgtl5000_fill_defaults(client);
1575 ret = snd_soc_register_codec(&client->dev,
1576 &sgtl5000_driver, &sgtl5000_dai, 1);
1583 clk_disable_unprepare(sgtl5000->mclk);
1586 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1587 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1592 static int sgtl5000_i2c_remove(struct i2c_client *client)
1594 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1596 snd_soc_unregister_codec(&client->dev);
1597 clk_disable_unprepare(sgtl5000->mclk);
1598 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1599 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1604 static const struct i2c_device_id sgtl5000_id[] = {
1609 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1611 static const struct of_device_id sgtl5000_dt_ids[] = {
1612 { .compatible = "fsl,sgtl5000", },
1615 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1617 static struct i2c_driver sgtl5000_i2c_driver = {
1620 .of_match_table = sgtl5000_dt_ids,
1622 .probe = sgtl5000_i2c_probe,
1623 .remove = sgtl5000_i2c_remove,
1624 .id_table = sgtl5000_id,
1627 module_i2c_driver(sgtl5000_i2c_driver);
1629 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1630 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1631 MODULE_LICENSE("GPL");