1 // SPDX-License-Identifier: GPL-2.0
3 // sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
5 // Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/module.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/slab.h>
13 #include <linux/i2c.h>
14 #include <linux/clk.h>
15 #include <linux/log2.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/of_device.h>
21 #include <sound/core.h>
22 #include <sound/tlv.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
31 #define SGTL5000_DAP_REG_OFFSET 0x0100
32 #define SGTL5000_MAX_REG_OFFSET 0x013A
34 /* Delay for the VAG ramp up */
35 #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
36 /* Delay for the VAG ramp down */
37 #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
39 #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
41 /* default value of sgtl5000 registers */
42 static const struct reg_default sgtl5000_reg_defaults[] = {
43 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
44 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
45 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
46 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
47 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
48 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
49 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
50 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
51 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
52 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
53 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
54 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
55 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
74 { SGTL5000_DAP_AVC_CTRL, 0x5100 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
80 /* AVC: Threshold dB -> register: pre-calculated values */
81 static const u16 avc_thr_db2reg[97] = {
82 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
83 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
84 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
85 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
86 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
87 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
88 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
89 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
90 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
91 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
94 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
95 enum sgtl5000_regulator_supplies {
102 /* vddd is optional supply */
103 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
109 #define LDO_VOLTAGE 1200000
110 #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
112 enum sgtl5000_micbias_resistor {
113 SGTL5000_MICBIAS_OFF = 0,
114 SGTL5000_MICBIAS_2K = 2,
115 SGTL5000_MICBIAS_4K = 4,
116 SGTL5000_MICBIAS_8K = 8,
120 I2S_LRCLK_STRENGTH_DISABLE,
121 I2S_LRCLK_STRENGTH_LOW,
122 I2S_LRCLK_STRENGTH_MEDIUM,
123 I2S_LRCLK_STRENGTH_HIGH,
130 LAST_POWER_EVENT = ADC_POWER_EVENT
133 /* sgtl5000 private structure in codec */
134 struct sgtl5000_priv {
135 int sysclk; /* sysclk rate */
136 int master; /* i2s master or not */
137 int fmt; /* i2s data format */
138 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
140 struct regmap *regmap;
146 u16 mute_state[LAST_POWER_EVENT + 1];
149 static inline int hp_sel_input(struct snd_soc_component *component)
151 return (snd_soc_component_read32(component, SGTL5000_CHIP_ANA_CTRL) &
152 SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
155 static inline u16 mute_output(struct snd_soc_component *component,
158 u16 mute_reg = snd_soc_component_read32(component,
159 SGTL5000_CHIP_ANA_CTRL);
161 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
162 mute_mask, mute_mask);
166 static inline void restore_output(struct snd_soc_component *component,
167 u16 mute_mask, u16 mute_reg)
169 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
170 mute_mask, mute_reg);
173 static void vag_power_on(struct snd_soc_component *component, u32 source)
175 if (snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER) &
176 SGTL5000_VAG_POWERUP)
179 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
180 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
182 /* When VAG powering on to get local loop from Line-In, the sleep
183 * is required to avoid loud pop.
185 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
186 source == HP_POWER_EVENT)
187 msleep(SGTL5000_VAG_POWERUP_DELAY);
190 static int vag_power_consumers(struct snd_soc_component *component,
191 u16 ana_pwr_reg, u32 source)
195 /* count dac/adc consumers unconditional */
196 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
198 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
202 * If the event comes from HP and Line-In is selected,
203 * current action is 'DAC to be powered down'.
204 * As HP_POWERUP is not set when HP muxed to line-in,
205 * we need to keep VAG power ON.
207 if (source == HP_POWER_EVENT) {
208 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
211 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
218 static void vag_power_off(struct snd_soc_component *component, u32 source)
220 u16 ana_pwr = snd_soc_component_read32(component,
221 SGTL5000_CHIP_ANA_POWER);
223 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
227 * This function calls when any of VAG power consumers is disappearing.
228 * Thus, if there is more than one consumer at the moment, as minimum
229 * one consumer will definitely stay after the end of the current
231 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
232 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
235 * (the current consumer is disappearing right now)
237 if (vag_power_consumers(component, ana_pwr, source) >= 2)
240 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
241 SGTL5000_VAG_POWERUP, 0);
242 /* In power down case, we need wait 400-1000 ms
243 * when VAG fully ramped down.
244 * As longer we wait, as smaller pop we've got.
246 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
250 * mic_bias power on/off share the same register bits with
251 * output impedance of mic bias, when power on mic bias, we
252 * need reclaim it to impedance value.
258 static int mic_bias_event(struct snd_soc_dapm_widget *w,
259 struct snd_kcontrol *kcontrol, int event)
261 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
262 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
265 case SND_SOC_DAPM_POST_PMU:
266 /* change mic bias resistor */
267 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
268 SGTL5000_BIAS_R_MASK,
269 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
272 case SND_SOC_DAPM_PRE_PMD:
273 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
274 SGTL5000_BIAS_R_MASK, 0);
280 static int vag_and_mute_control(struct snd_soc_component *component,
281 int event, int event_source)
283 static const u16 mute_mask[] = {
285 * Mask for HP_POWER_EVENT.
286 * Muxing Headphones have to be wrapped with mute/unmute
291 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
292 * Muxing DAC or ADC block have to wrapped with mute/unmute
293 * both headphones and line-out.
295 SGTL5000_OUTPUTS_MUTE,
296 SGTL5000_OUTPUTS_MUTE
299 struct sgtl5000_priv *sgtl5000 =
300 snd_soc_component_get_drvdata(component);
303 case SND_SOC_DAPM_PRE_PMU:
304 sgtl5000->mute_state[event_source] =
305 mute_output(component, mute_mask[event_source]);
307 case SND_SOC_DAPM_POST_PMU:
308 vag_power_on(component, event_source);
309 restore_output(component, mute_mask[event_source],
310 sgtl5000->mute_state[event_source]);
312 case SND_SOC_DAPM_PRE_PMD:
313 sgtl5000->mute_state[event_source] =
314 mute_output(component, mute_mask[event_source]);
315 vag_power_off(component, event_source);
317 case SND_SOC_DAPM_POST_PMD:
318 restore_output(component, mute_mask[event_source],
319 sgtl5000->mute_state[event_source]);
329 * Mute Headphone when power it up/down.
330 * Control VAG power on HP power path.
332 static int headphone_pga_event(struct snd_soc_dapm_widget *w,
333 struct snd_kcontrol *kcontrol, int event)
335 struct snd_soc_component *component =
336 snd_soc_dapm_to_component(w->dapm);
338 return vag_and_mute_control(component, event, HP_POWER_EVENT);
341 /* As manual describes, ADC/DAC powering up/down requires
342 * to mute outputs to avoid pops.
343 * Control VAG power on ADC/DAC power path.
345 static int adc_updown_depop(struct snd_soc_dapm_widget *w,
346 struct snd_kcontrol *kcontrol, int event)
348 struct snd_soc_component *component =
349 snd_soc_dapm_to_component(w->dapm);
351 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
354 static int dac_updown_depop(struct snd_soc_dapm_widget *w,
355 struct snd_kcontrol *kcontrol, int event)
357 struct snd_soc_component *component =
358 snd_soc_dapm_to_component(w->dapm);
360 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
363 /* input sources for ADC */
364 static const char *adc_mux_text[] = {
368 static SOC_ENUM_SINGLE_DECL(adc_enum,
369 SGTL5000_CHIP_ANA_CTRL, 2,
372 static const struct snd_kcontrol_new adc_mux =
373 SOC_DAPM_ENUM("Capture Mux", adc_enum);
375 /* input sources for headphone */
376 static const char *hp_mux_text[] = {
380 static SOC_ENUM_SINGLE_DECL(hp_enum,
381 SGTL5000_CHIP_ANA_CTRL, 6,
384 static const struct snd_kcontrol_new hp_mux =
385 SOC_DAPM_ENUM("Headphone Mux", hp_enum);
387 /* input sources for DAC */
388 static const char *dac_mux_text[] = {
389 "ADC", "I2S", "Rsvrd", "DAP"
392 static SOC_ENUM_SINGLE_DECL(dac_enum,
393 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
396 static const struct snd_kcontrol_new dac_mux =
397 SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
399 /* input sources for DAP */
400 static const char *dap_mux_text[] = {
404 static SOC_ENUM_SINGLE_DECL(dap_enum,
405 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
408 static const struct snd_kcontrol_new dap_mux =
409 SOC_DAPM_ENUM("DAP Mux", dap_enum);
411 /* input sources for DAP mix */
412 static const char *dapmix_mux_text[] = {
416 static SOC_ENUM_SINGLE_DECL(dapmix_enum,
417 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
420 static const struct snd_kcontrol_new dapmix_mux =
421 SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
424 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
425 SND_SOC_DAPM_INPUT("LINE_IN"),
426 SND_SOC_DAPM_INPUT("MIC_IN"),
428 SND_SOC_DAPM_OUTPUT("HP_OUT"),
429 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
431 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
433 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
435 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
437 SND_SOC_DAPM_PRE_POST_PMU |
438 SND_SOC_DAPM_PRE_POST_PMD),
439 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
441 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
442 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
443 SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
444 SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
445 SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
446 SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
449 /* aif for i2s input */
450 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
451 0, SGTL5000_CHIP_DIG_POWER,
454 /* aif for i2s output */
455 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
456 0, SGTL5000_CHIP_DIG_POWER,
459 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
460 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
461 SND_SOC_DAPM_PRE_POST_PMD),
462 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
463 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
464 SND_SOC_DAPM_PRE_POST_PMD),
467 /* routes for sgtl5000 */
468 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
469 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
470 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
472 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
473 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
475 {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */
476 {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */
477 {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */
479 {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */
480 {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */
481 {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */
483 {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */
484 {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */
485 {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
486 {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
488 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
489 {"LO", NULL, "DAC"}, /* dac --> line_out */
491 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
492 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
494 {"LINE_OUT", NULL, "LO"},
495 {"HP_OUT", NULL, "HP"},
498 /* custom function to fetch info of PCM playback volume */
499 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
500 struct snd_ctl_elem_info *uinfo)
502 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
504 uinfo->value.integer.min = 0;
505 uinfo->value.integer.max = 0xfc - 0x3c;
510 * custom function to get of PCM playback volume
512 * dac volume register
513 * 15-------------8-7--------------0
514 * | R channel vol | L channel vol |
515 * -------------------------------
517 * PCM volume with 0.5017 dB steps from 0 to -90 dB
519 * register values map to dB
520 * 0x3B and less = Reserved
524 * 0xFC and greater = Muted
526 * register value map to userspace value
528 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
529 * ------------------------------
530 * userspace value 0xc0 0
532 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
533 struct snd_ctl_elem_value *ucontrol)
535 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
540 reg = snd_soc_component_read32(component, SGTL5000_CHIP_DAC_VOL);
542 /* get left channel volume */
543 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
545 /* get right channel volume */
546 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
548 /* make sure value fall in (0x3c,0xfc) */
549 l = clamp(l, 0x3c, 0xfc);
550 r = clamp(r, 0x3c, 0xfc);
552 /* invert it and map to userspace value */
556 ucontrol->value.integer.value[0] = l;
557 ucontrol->value.integer.value[1] = r;
563 * custom function to put of PCM playback volume
565 * dac volume register
566 * 15-------------8-7--------------0
567 * | R channel vol | L channel vol |
568 * -------------------------------
570 * PCM volume with 0.5017 dB steps from 0 to -90 dB
572 * register values map to dB
573 * 0x3B and less = Reserved
577 * 0xFC and greater = Muted
579 * userspace value map to register value
581 * userspace value 0xc0 0
582 * ------------------------------
583 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
585 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
586 struct snd_ctl_elem_value *ucontrol)
588 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
593 l = ucontrol->value.integer.value[0];
594 r = ucontrol->value.integer.value[1];
596 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
597 l = clamp(l, 0, 0xfc - 0x3c);
598 r = clamp(r, 0, 0xfc - 0x3c);
600 /* invert it, get the value can be set to register */
604 /* shift to get the register value */
605 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
606 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
608 snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
614 * custom function to get AVC threshold
616 * The threshold dB is calculated by rearranging the calculation from the
617 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
618 * dB = ( fls(register_value) - 14.347 ) * 6.02
620 * As this calculation is expensive and the threshold dB values may not exceed
621 * 0 to 96 we use pre-calculated values.
623 static int avc_get_threshold(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_value *ucontrol)
626 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
628 u16 reg = snd_soc_component_read32(component, SGTL5000_DAP_AVC_THRESHOLD);
630 /* register value 0 => -96dB */
632 ucontrol->value.integer.value[0] = 96;
633 ucontrol->value.integer.value[1] = 96;
637 /* get dB from register value (rounded down) */
638 for (i = 0; avc_thr_db2reg[i] > reg; i++)
642 ucontrol->value.integer.value[0] = db;
643 ucontrol->value.integer.value[1] = db;
649 * custom function to put AVC threshold
651 * The register value is calculated by following formula:
652 * register_value = 10^(dB/20) * 0.636 * 2^15
653 * As this calculation is expensive and the threshold dB values may not exceed
654 * 0 to 96 we use pre-calculated values.
656 static int avc_put_threshold(struct snd_kcontrol *kcontrol,
657 struct snd_ctl_elem_value *ucontrol)
659 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
663 db = (int)ucontrol->value.integer.value[0];
664 if (db < 0 || db > 96)
666 reg = avc_thr_db2reg[db];
667 snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
672 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
674 /* tlv for mic gain, 0db 20db 30db 40db */
675 static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
676 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
677 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
680 /* tlv for DAP channels, 0% - 100% - 200% */
681 static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
683 /* tlv for bass bands, -11.75db to 12.0db, step .25db */
684 static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
686 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
687 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
689 /* tlv for lineout volume, 31 steps of .5db each */
690 static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
692 /* tlv for dap avc max gain, 0db, 6db, 12db */
693 static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
695 /* tlv for dap avc threshold, */
696 static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
698 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
699 /* SOC_DOUBLE_S8_TLV with invert */
701 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
702 .name = "PCM Playback Volume",
703 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
704 SNDRV_CTL_ELEM_ACCESS_READWRITE,
705 .info = dac_info_volsw,
706 .get = dac_get_volsw,
707 .put = dac_put_volsw,
710 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
711 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
712 SGTL5000_CHIP_ANA_ADC_CTRL,
713 8, 1, 0, capture_6db_attenuate),
714 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
716 SOC_DOUBLE_TLV("Headphone Playback Volume",
717 SGTL5000_CHIP_ANA_HP_CTRL,
721 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
723 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
726 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
727 0, 3, 0, mic_gain_tlv),
729 SOC_DOUBLE_TLV("Lineout Playback Volume",
730 SGTL5000_CHIP_LINE_OUT_VOL,
731 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
732 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
735 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
737 SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
738 0, 0xffff, 0, dap_volume),
740 SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
741 0, 0xffff, 0, dap_volume),
742 /* Automatic Volume Control (DAP AVC) */
743 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
744 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
745 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
747 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
748 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
749 0, 96, 0, avc_get_threshold, avc_put_threshold,
752 SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
753 0, 0x5F, 0, bass_band),
755 SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
756 0, 0x5F, 0, bass_band),
758 SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
759 0, 0x5F, 0, bass_band),
761 SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
762 0, 0x5F, 0, bass_band),
764 SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
765 0, 0x5F, 0, bass_band),
768 /* mute the codec used by alsa core */
769 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
771 struct snd_soc_component *component = codec_dai->component;
772 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
775 * During 'digital mute' do not mute DAC
776 * because LINE_IN would be muted aswell. We want to mute
777 * only I2S block - this can be done by powering it off
779 snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
780 i2s_pwr, mute ? 0 : i2s_pwr);
785 /* set codec format */
786 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
788 struct snd_soc_component *component = codec_dai->component;
789 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
792 sgtl5000->master = 0;
794 * i2s clock and frame master setting.
796 * - clock and frame slave,
797 * - clock and frame master
799 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
800 case SND_SOC_DAIFMT_CBS_CFS:
802 case SND_SOC_DAIFMT_CBM_CFM:
803 i2sctl |= SGTL5000_I2S_MASTER;
804 sgtl5000->master = 1;
810 /* setting i2s data format */
811 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
812 case SND_SOC_DAIFMT_DSP_A:
813 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
815 case SND_SOC_DAIFMT_DSP_B:
816 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
817 i2sctl |= SGTL5000_I2S_LRALIGN;
819 case SND_SOC_DAIFMT_I2S:
820 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
822 case SND_SOC_DAIFMT_RIGHT_J:
823 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
824 i2sctl |= SGTL5000_I2S_LRPOL;
826 case SND_SOC_DAIFMT_LEFT_J:
827 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
828 i2sctl |= SGTL5000_I2S_LRALIGN;
834 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
836 /* Clock inversion */
837 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
838 case SND_SOC_DAIFMT_NB_NF:
840 case SND_SOC_DAIFMT_IB_NF:
841 i2sctl |= SGTL5000_I2S_SCLK_INV;
847 snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
852 /* set codec sysclk */
853 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
854 int clk_id, unsigned int freq, int dir)
856 struct snd_soc_component *component = codec_dai->component;
857 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
860 case SGTL5000_SYSCLK:
861 sgtl5000->sysclk = freq;
871 * set clock according to i2s frame clock,
872 * sgtl5000 provides 2 clock sources:
873 * 1. sys_mclk: sample freq can only be configured to
874 * 1/256, 1/384, 1/512 of sys_mclk.
875 * 2. pll: can derive any audio clocks.
877 * clock setting rules:
878 * 1. in slave mode, only sys_mclk can be used
879 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
881 * 3. usage of sys_mclk is preferred over pll to save power.
883 static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
885 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
887 int sys_fs; /* sample freq */
890 * sample freq should be divided by frame clock,
891 * if frame clock is lower than 44.1 kHz, sample freq should be set to
892 * 32 kHz or 44.1 kHz.
894 switch (frame_rate) {
908 /* set divided factor of frame clock */
909 switch (sys_fs / frame_rate) {
911 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
914 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
917 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
923 /* set the sys_fs according to frame rate */
926 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
929 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
932 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
935 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
938 dev_err(component->dev, "frame rate %d not supported\n",
944 * calculate the divider of mclk/sample_freq,
945 * factor of freq = 96 kHz can only be 256, since mclk is in the range
948 switch (sgtl5000->sysclk / frame_rate) {
950 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
951 SGTL5000_MCLK_FREQ_SHIFT;
954 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
955 SGTL5000_MCLK_FREQ_SHIFT;
958 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
959 SGTL5000_MCLK_FREQ_SHIFT;
962 /* if mclk does not satisfy the divider, use pll */
963 if (sgtl5000->master) {
964 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
965 SGTL5000_MCLK_FREQ_SHIFT;
967 dev_err(component->dev,
968 "PLL not supported in slave mode\n");
969 dev_err(component->dev, "%d ratio is not supported. "
970 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
971 sgtl5000->sysclk / frame_rate);
976 /* if using pll, please check manual 6.4.2 for detail */
977 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
981 unsigned int in, int_div, frac_div;
983 if (sgtl5000->sysclk > 17000000) {
985 in = sgtl5000->sysclk / 2;
988 in = sgtl5000->sysclk;
999 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
1000 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
1002 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
1004 snd_soc_component_update_bits(component,
1005 SGTL5000_CHIP_CLK_TOP_CTRL,
1006 SGTL5000_INPUT_FREQ_DIV2,
1007 SGTL5000_INPUT_FREQ_DIV2);
1009 snd_soc_component_update_bits(component,
1010 SGTL5000_CHIP_CLK_TOP_CTRL,
1011 SGTL5000_INPUT_FREQ_DIV2,
1015 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1016 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1017 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
1019 /* if using pll, clk_ctrl must be set after pll power up */
1020 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1022 /* otherwise, clk_ctrl must be set before pll power down */
1023 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1025 /* power down pll */
1026 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1027 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1035 * Set PCM DAI bit size and sample rate.
1036 * input: params_rate, params_fmt
1038 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
1039 struct snd_pcm_hw_params *params,
1040 struct snd_soc_dai *dai)
1042 struct snd_soc_component *component = dai->component;
1043 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1044 int channels = params_channels(params);
1049 /* sysclk should already set */
1050 if (!sgtl5000->sysclk) {
1051 dev_err(component->dev, "%s: set sysclk first!\n", __func__);
1055 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1056 stereo = SGTL5000_DAC_STEREO;
1058 stereo = SGTL5000_ADC_STEREO;
1060 /* set mono to save power */
1061 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
1062 channels == 1 ? 0 : stereo);
1064 /* set codec clock base on lrclk */
1065 ret = sgtl5000_set_clock(component, params_rate(params));
1069 /* set i2s data format */
1070 switch (params_width(params)) {
1072 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1074 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
1075 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
1076 SGTL5000_I2S_SCLKFREQ_SHIFT;
1079 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
1080 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1081 SGTL5000_I2S_SCLKFREQ_SHIFT;
1084 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
1085 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1086 SGTL5000_I2S_SCLKFREQ_SHIFT;
1089 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1091 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
1092 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1093 SGTL5000_I2S_SCLKFREQ_SHIFT;
1099 snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
1100 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
1108 * common state changes:
1110 * off --> standby --> prepare --> on
1111 * standby --> prepare --> on
1114 * on --> prepare --> standby
1116 static int sgtl5000_set_bias_level(struct snd_soc_component *component,
1117 enum snd_soc_bias_level level)
1119 struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
1123 case SND_SOC_BIAS_ON:
1124 case SND_SOC_BIAS_PREPARE:
1125 case SND_SOC_BIAS_STANDBY:
1126 regcache_cache_only(sgtl->regmap, false);
1127 ret = regcache_sync(sgtl->regmap);
1129 regcache_cache_only(sgtl->regmap, true);
1133 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1134 SGTL5000_REFTOP_POWERUP,
1135 SGTL5000_REFTOP_POWERUP);
1137 case SND_SOC_BIAS_OFF:
1138 regcache_cache_only(sgtl->regmap, true);
1139 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1140 SGTL5000_REFTOP_POWERUP, 0);
1147 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1148 SNDRV_PCM_FMTBIT_S20_3LE |\
1149 SNDRV_PCM_FMTBIT_S24_LE |\
1150 SNDRV_PCM_FMTBIT_S32_LE)
1152 static const struct snd_soc_dai_ops sgtl5000_ops = {
1153 .hw_params = sgtl5000_pcm_hw_params,
1154 .digital_mute = sgtl5000_digital_mute,
1155 .set_fmt = sgtl5000_set_dai_fmt,
1156 .set_sysclk = sgtl5000_set_dai_sysclk,
1159 static struct snd_soc_dai_driver sgtl5000_dai = {
1162 .stream_name = "Playback",
1166 * only support 8~48K + 96K,
1167 * TODO modify hw_param to support more
1169 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1170 .formats = SGTL5000_FORMATS,
1173 .stream_name = "Capture",
1176 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1177 .formats = SGTL5000_FORMATS,
1179 .ops = &sgtl5000_ops,
1180 .symmetric_rates = 1,
1183 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1186 case SGTL5000_CHIP_ID:
1187 case SGTL5000_CHIP_ADCDAC_CTRL:
1188 case SGTL5000_CHIP_ANA_STATUS:
1195 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1198 case SGTL5000_CHIP_ID:
1199 case SGTL5000_CHIP_DIG_POWER:
1200 case SGTL5000_CHIP_CLK_CTRL:
1201 case SGTL5000_CHIP_I2S_CTRL:
1202 case SGTL5000_CHIP_SSS_CTRL:
1203 case SGTL5000_CHIP_ADCDAC_CTRL:
1204 case SGTL5000_CHIP_DAC_VOL:
1205 case SGTL5000_CHIP_PAD_STRENGTH:
1206 case SGTL5000_CHIP_ANA_ADC_CTRL:
1207 case SGTL5000_CHIP_ANA_HP_CTRL:
1208 case SGTL5000_CHIP_ANA_CTRL:
1209 case SGTL5000_CHIP_LINREG_CTRL:
1210 case SGTL5000_CHIP_REF_CTRL:
1211 case SGTL5000_CHIP_MIC_CTRL:
1212 case SGTL5000_CHIP_LINE_OUT_CTRL:
1213 case SGTL5000_CHIP_LINE_OUT_VOL:
1214 case SGTL5000_CHIP_ANA_POWER:
1215 case SGTL5000_CHIP_PLL_CTRL:
1216 case SGTL5000_CHIP_CLK_TOP_CTRL:
1217 case SGTL5000_CHIP_ANA_STATUS:
1218 case SGTL5000_CHIP_SHORT_CTRL:
1219 case SGTL5000_CHIP_ANA_TEST2:
1220 case SGTL5000_DAP_CTRL:
1221 case SGTL5000_DAP_PEQ:
1222 case SGTL5000_DAP_BASS_ENHANCE:
1223 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1224 case SGTL5000_DAP_AUDIO_EQ:
1225 case SGTL5000_DAP_SURROUND:
1226 case SGTL5000_DAP_FLT_COEF_ACCESS:
1227 case SGTL5000_DAP_COEF_WR_B0_MSB:
1228 case SGTL5000_DAP_COEF_WR_B0_LSB:
1229 case SGTL5000_DAP_EQ_BASS_BAND0:
1230 case SGTL5000_DAP_EQ_BASS_BAND1:
1231 case SGTL5000_DAP_EQ_BASS_BAND2:
1232 case SGTL5000_DAP_EQ_BASS_BAND3:
1233 case SGTL5000_DAP_EQ_BASS_BAND4:
1234 case SGTL5000_DAP_MAIN_CHAN:
1235 case SGTL5000_DAP_MIX_CHAN:
1236 case SGTL5000_DAP_AVC_CTRL:
1237 case SGTL5000_DAP_AVC_THRESHOLD:
1238 case SGTL5000_DAP_AVC_ATTACK:
1239 case SGTL5000_DAP_AVC_DECAY:
1240 case SGTL5000_DAP_COEF_WR_B1_MSB:
1241 case SGTL5000_DAP_COEF_WR_B1_LSB:
1242 case SGTL5000_DAP_COEF_WR_B2_MSB:
1243 case SGTL5000_DAP_COEF_WR_B2_LSB:
1244 case SGTL5000_DAP_COEF_WR_A1_MSB:
1245 case SGTL5000_DAP_COEF_WR_A1_LSB:
1246 case SGTL5000_DAP_COEF_WR_A2_MSB:
1247 case SGTL5000_DAP_COEF_WR_A2_LSB:
1256 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1257 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1258 * The calculatation was done for all possible register values which
1259 * is the array index and the following formula: 10^((idx−15)/40) * 100
1261 static const u8 vol_quot_table[] = {
1262 42, 45, 47, 50, 53, 56, 60, 63,
1263 67, 71, 75, 79, 84, 89, 94, 100,
1264 106, 112, 119, 126, 133, 141, 150, 158,
1265 168, 178, 188, 200, 211, 224, 237, 251
1269 * sgtl5000 has 3 internal power supplies:
1270 * 1. VAG, normally set to vdda/2
1271 * 2. charge pump, set to different value
1272 * according to voltage of vdda and vddio
1273 * 3. line out VAG, normally set to vddio/2
1275 * and should be set according to:
1276 * 1. vddd provided by external or not
1277 * 2. vdda and vddio voltage value. > 3.1v or not
1279 static int sgtl5000_set_power_regs(struct snd_soc_component *component)
1291 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1293 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1294 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1295 vddd = (sgtl5000->num_supplies > VDDD)
1296 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1300 vddio = vddio / 1000;
1303 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1304 dev_err(component->dev, "regulator voltage not set correctly\n");
1309 /* according to datasheet, maximum voltage of supplies */
1310 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1311 dev_err(component->dev,
1312 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1319 ana_pwr = snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER);
1320 ana_pwr |= SGTL5000_DAC_STEREO |
1321 SGTL5000_ADC_STEREO |
1322 SGTL5000_REFTOP_POWERUP;
1323 lreg_ctrl = snd_soc_component_read32(component, SGTL5000_CHIP_LINREG_CTRL);
1325 if (vddio < 3100 && vdda < 3100) {
1326 /* enable internal oscillator used for charge pump */
1327 snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
1328 SGTL5000_INT_OSC_EN,
1329 SGTL5000_INT_OSC_EN);
1330 /* Enable VDDC charge pump */
1331 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1333 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1335 * if vddio == vdda the source of charge pump should be
1336 * assigned manually to VDDIO
1338 if (vddio == vdda) {
1339 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1340 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1341 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1345 snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1347 snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1350 * set ADC/DAC VAG to vdda / 2,
1351 * should stay in range (0.8v, 1.575v)
1354 if (vag <= SGTL5000_ANA_GND_BASE)
1356 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1357 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1358 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1360 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1362 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1363 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1365 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1367 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1369 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1370 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1371 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1373 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1374 SGTL5000_LINE_OUT_GND_STP;
1376 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
1377 SGTL5000_LINE_OUT_CURRENT_MASK |
1378 SGTL5000_LINE_OUT_GND_MASK,
1379 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1380 SGTL5000_LINE_OUT_CURRENT_360u <<
1381 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1384 * Set lineout output level in range (0..31)
1385 * the same value is used for right and left channel
1387 * Searching for a suitable index solving this formula:
1388 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1390 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1392 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1393 if (vol_quot >= vol_quot_table[i])
1399 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
1400 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1401 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1402 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1403 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1408 static int sgtl5000_enable_regulators(struct i2c_client *client)
1412 int external_vddd = 0;
1413 struct regulator *vddd;
1414 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1416 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1417 sgtl5000->supplies[i].supply = supply_names[i];
1419 vddd = regulator_get_optional(&client->dev, "VDDD");
1421 /* See if it's just not registered yet */
1422 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1423 return -EPROBE_DEFER;
1426 regulator_put(vddd);
1429 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1430 - 1 + external_vddd;
1431 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1432 sgtl5000->supplies);
1436 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1437 sgtl5000->supplies);
1439 usleep_range(10, 20);
1441 regulator_bulk_free(sgtl5000->num_supplies,
1442 sgtl5000->supplies);
1447 static int sgtl5000_probe(struct snd_soc_component *component)
1451 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1452 unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN;
1454 /* power up sgtl5000 */
1455 ret = sgtl5000_set_power_regs(component);
1459 /* enable small pop, introduce 400ms delay in turning off */
1460 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1461 SGTL5000_SMALL_POP, 1);
1463 /* disable short cut detector */
1464 snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
1466 snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
1467 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1469 /* enable dac volume ramp by default */
1470 snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
1471 SGTL5000_DAC_VOL_RAMP_EN |
1472 SGTL5000_DAC_MUTE_RIGHT |
1473 SGTL5000_DAC_MUTE_LEFT);
1475 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
1476 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
1478 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
1479 zcd_mask, zcd_mask);
1481 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1482 SGTL5000_BIAS_R_MASK,
1483 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1485 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1486 SGTL5000_BIAS_VOLT_MASK,
1487 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1489 * enable DAP Graphic EQ
1491 * Add control for changing between PEQ/Tone Control/GEQ
1493 snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
1495 /* Unmute DAC after start */
1496 snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
1497 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
1505 static const struct snd_soc_component_driver sgtl5000_driver = {
1506 .probe = sgtl5000_probe,
1507 .set_bias_level = sgtl5000_set_bias_level,
1508 .controls = sgtl5000_snd_controls,
1509 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1510 .dapm_widgets = sgtl5000_dapm_widgets,
1511 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1512 .dapm_routes = sgtl5000_dapm_routes,
1513 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1514 .suspend_bias_off = 1,
1516 .use_pmdown_time = 1,
1518 .non_legacy_dai_naming = 1,
1521 static const struct regmap_config sgtl5000_regmap = {
1526 .max_register = SGTL5000_MAX_REG_OFFSET,
1527 .volatile_reg = sgtl5000_volatile,
1528 .readable_reg = sgtl5000_readable,
1530 .cache_type = REGCACHE_RBTREE,
1531 .reg_defaults = sgtl5000_reg_defaults,
1532 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1536 * Write all the default values from sgtl5000_reg_defaults[] array into the
1537 * sgtl5000 registers, to make sure we always start with the sane registers
1538 * values as stated in the datasheet.
1540 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1541 * we follow this approach to guarantee we always start from the default values
1542 * and avoid problems like, not being able to probe after an audio playback
1543 * followed by a system reset or a 'reboot' command in Linux
1545 static void sgtl5000_fill_defaults(struct i2c_client *client)
1547 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1548 int i, ret, val, index;
1550 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1551 val = sgtl5000_reg_defaults[i].def;
1552 index = sgtl5000_reg_defaults[i].reg;
1553 ret = regmap_write(sgtl5000->regmap, index, val);
1555 dev_err(&client->dev,
1556 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1557 __func__, ret, index, val);
1561 static int sgtl5000_i2c_probe(struct i2c_client *client,
1562 const struct i2c_device_id *id)
1564 struct sgtl5000_priv *sgtl5000;
1566 struct device_node *np = client->dev.of_node;
1570 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1574 i2c_set_clientdata(client, sgtl5000);
1576 ret = sgtl5000_enable_regulators(client);
1580 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1581 if (IS_ERR(sgtl5000->regmap)) {
1582 ret = PTR_ERR(sgtl5000->regmap);
1583 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1587 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1588 if (IS_ERR(sgtl5000->mclk)) {
1589 ret = PTR_ERR(sgtl5000->mclk);
1590 /* Defer the probe to see if the clk will be provided later */
1592 ret = -EPROBE_DEFER;
1594 if (ret != -EPROBE_DEFER)
1595 dev_err(&client->dev, "Failed to get mclock: %d\n",
1600 ret = clk_prepare_enable(sgtl5000->mclk);
1602 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1606 /* Need 8 clocks before I2C accesses */
1609 /* read chip information */
1610 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1612 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1616 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1617 SGTL5000_PARTID_PART_ID) {
1618 dev_err(&client->dev,
1619 "Device with ID register %x is not a sgtl5000\n", reg);
1624 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1625 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1626 sgtl5000->revision = rev;
1628 /* reconfigure the clocks in case we're using the PLL */
1629 ret = regmap_write(sgtl5000->regmap,
1630 SGTL5000_CHIP_CLK_CTRL,
1631 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1633 dev_err(&client->dev,
1634 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1636 /* Mute everything to avoid pop from the following power-up */
1637 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
1638 SGTL5000_CHIP_ANA_CTRL_DEFAULT);
1640 dev_err(&client->dev,
1641 "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
1646 * If VAG is powered-on (e.g. from previous boot), it would be disabled
1647 * by the write to ANA_POWER in later steps of the probe code. This
1648 * may create a loud pop even with all outputs muted. The proper way
1649 * to circumvent this is disabling the bit first and waiting the proper
1652 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
1654 dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
1657 if (value & SGTL5000_VAG_POWERUP) {
1658 ret = regmap_update_bits(sgtl5000->regmap,
1659 SGTL5000_CHIP_ANA_POWER,
1660 SGTL5000_VAG_POWERUP,
1663 dev_err(&client->dev, "Error %d disabling VAG\n", ret);
1667 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
1670 /* Follow section 2.2.1.1 of AN3663 */
1671 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1672 if (sgtl5000->num_supplies <= VDDD) {
1673 /* internal VDDD at 1.2V */
1674 ret = regmap_update_bits(sgtl5000->regmap,
1675 SGTL5000_CHIP_LINREG_CTRL,
1676 SGTL5000_LINREG_VDDD_MASK,
1679 dev_err(&client->dev,
1680 "Error %d setting LINREG_VDDD\n", ret);
1682 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1683 dev_info(&client->dev,
1684 "Using internal LDO instead of VDDD: check ER1 erratum\n");
1686 /* using external LDO for VDDD
1687 * Clear startup powerup and simple powerup
1688 * bits to save power
1690 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1691 | SGTL5000_LINREG_SIMPLE_POWERUP);
1692 dev_dbg(&client->dev, "Using external VDDD\n");
1694 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1696 dev_err(&client->dev,
1697 "Error %d setting CHIP_ANA_POWER to %04x\n",
1701 if (!of_property_read_u32(np,
1702 "micbias-resistor-k-ohms", &value)) {
1704 case SGTL5000_MICBIAS_OFF:
1705 sgtl5000->micbias_resistor = 0;
1707 case SGTL5000_MICBIAS_2K:
1708 sgtl5000->micbias_resistor = 1;
1710 case SGTL5000_MICBIAS_4K:
1711 sgtl5000->micbias_resistor = 2;
1713 case SGTL5000_MICBIAS_8K:
1714 sgtl5000->micbias_resistor = 3;
1717 sgtl5000->micbias_resistor = 2;
1718 dev_err(&client->dev,
1719 "Unsuitable MicBias resistor\n");
1722 /* default is 4Kohms */
1723 sgtl5000->micbias_resistor = 2;
1725 if (!of_property_read_u32(np,
1726 "micbias-voltage-m-volts", &value)) {
1728 /* steps of 250mV */
1729 if ((value >= 1250) && (value <= 3000))
1730 sgtl5000->micbias_voltage = (value / 250) - 5;
1732 sgtl5000->micbias_voltage = 0;
1733 dev_err(&client->dev,
1734 "Unsuitable MicBias voltage\n");
1737 sgtl5000->micbias_voltage = 0;
1741 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1742 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1743 if (value > I2S_LRCLK_STRENGTH_HIGH)
1744 value = I2S_LRCLK_STRENGTH_LOW;
1745 sgtl5000->lrclk_strength = value;
1748 /* Ensure sgtl5000 will start with sane register values */
1749 sgtl5000_fill_defaults(client);
1751 ret = devm_snd_soc_register_component(&client->dev,
1752 &sgtl5000_driver, &sgtl5000_dai, 1);
1759 clk_disable_unprepare(sgtl5000->mclk);
1762 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1763 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1768 static int sgtl5000_i2c_remove(struct i2c_client *client)
1770 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1772 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_CLK_CTRL, SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1773 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_DIG_POWER, SGTL5000_DIG_POWER_DEFAULT);
1774 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, SGTL5000_ANA_POWER_DEFAULT);
1776 clk_disable_unprepare(sgtl5000->mclk);
1777 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1778 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1783 static void sgtl5000_i2c_shutdown(struct i2c_client *client)
1785 sgtl5000_i2c_remove(client);
1788 static const struct i2c_device_id sgtl5000_id[] = {
1793 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1795 static const struct of_device_id sgtl5000_dt_ids[] = {
1796 { .compatible = "fsl,sgtl5000", },
1799 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1801 static struct i2c_driver sgtl5000_i2c_driver = {
1804 .of_match_table = sgtl5000_dt_ids,
1806 .probe = sgtl5000_i2c_probe,
1807 .remove = sgtl5000_i2c_remove,
1808 .shutdown = sgtl5000_i2c_shutdown,
1809 .id_table = sgtl5000_id,
1812 module_i2c_driver(sgtl5000_i2c_driver);
1814 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1815 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1816 MODULE_LICENSE("GPL");