1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/bits.h>
4 #include <linux/bitfield.h>
5 #include <linux/delay.h>
6 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h>
13 #include <sound/pcm.h>
14 #include <sound/pcm_params.h>
15 #include <sound/soc.h>
16 #include <sound/tlv.h>
18 #define RT9120_REG_DEVID 0x00
19 #define RT9120_REG_I2SFMT 0x02
20 #define RT9120_REG_I2SWL 0x03
21 #define RT9120_REG_SDIOSEL 0x04
22 #define RT9120_REG_SYSCTL 0x05
23 #define RT9120_REG_SPKGAIN 0x07
24 #define RT9120_REG_VOLRAMP 0x0A
25 #define RT9120_REG_ERRRPT 0x10
26 #define RT9120_REG_MSVOL 0x20
27 #define RT9120_REG_SWRESET 0x40
28 #define RT9120_REG_INTERCFG 0x63
29 #define RT9120_REG_INTERNAL0 0x65
30 #define RT9120_REG_INTERNAL1 0x69
31 #define RT9120_REG_UVPOPT 0x6C
32 #define RT9120_REG_DIGCFG 0xF8
34 #define RT9120_VID_MASK GENMASK(15, 8)
35 #define RT9120_SWRST_MASK BIT(7)
36 #define RT9120_MUTE_MASK GENMASK(5, 4)
37 #define RT9120_I2SFMT_MASK GENMASK(4, 2)
38 #define RT9120_I2SFMT_SHIFT 2
39 #define RT9120_CFG_FMT_I2S 0
40 #define RT9120_CFG_FMT_LEFTJ 1
41 #define RT9120_CFG_FMT_RIGHTJ 2
42 #define RT9120_CFG_FMT_DSPA 3
43 #define RT9120_CFG_FMT_DSPB 7
44 #define RT9120_AUDBIT_MASK GENMASK(1, 0)
45 #define RT9120_CFG_AUDBIT_16 0
46 #define RT9120_CFG_AUDBIT_20 1
47 #define RT9120_CFG_AUDBIT_24 2
48 #define RT9120_AUDWL_MASK GENMASK(5, 0)
49 #define RT9120_CFG_WORDLEN_16 16
50 #define RT9120_CFG_WORDLEN_24 24
51 #define RT9120_CFG_WORDLEN_32 32
52 #define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
53 #define RT9120_AUTOSYNC_MASK BIT(6)
55 #define RT9120_VENDOR_ID 0x42
56 #define RT9120S_VENDOR_ID 0x43
57 #define RT9120_RESET_WAITMS 20
58 #define RT9120_CHIPON_WAITMS 20
59 #define RT9120_AMPON_WAITMS 50
60 #define RT9120_AMPOFF_WAITMS 100
61 #define RT9120_LVAPP_THRESUV 2000000
63 /* 8000 to 192000 supported , only 176400 not support */
64 #define RT9120_RATES_MASK (SNDRV_PCM_RATE_8000_192000 &\
65 ~SNDRV_PCM_RATE_176400)
66 #define RT9120_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE |\
67 SNDRV_PCM_FMTBIT_S24_LE |\
68 SNDRV_PCM_FMTBIT_S32_LE)
78 struct regmap *regmap;
79 struct gpio_desc *pwdnn_gpio;
83 /* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
84 static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1);
86 /* {6, 8, 10, 12, 13, 14, 15, 16}dB */
87 static const DECLARE_TLV_DB_RANGE(classd_tlv,
88 0, 3, TLV_DB_SCALE_ITEM(600, 200, 0),
89 4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0)
92 static const char * const sdo_select_text[] = {
93 "None", "INTF", "Final", "RMS Detect"
96 static const struct soc_enum sdo_select_enum =
97 SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text),
100 static const struct snd_kcontrol_new rt9120_snd_controls[] = {
101 SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv),
102 SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv),
103 SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0),
104 SOC_ENUM("SDO Select", sdo_select_enum),
107 static int internal_power_event(struct snd_soc_dapm_widget *w,
108 struct snd_kcontrol *kcontrol, int event)
110 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
113 case SND_SOC_DAPM_PRE_PMU:
114 snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0);
116 case SND_SOC_DAPM_POST_PMU:
117 msleep(RT9120_AMPON_WAITMS);
119 case SND_SOC_DAPM_POST_PMD:
120 msleep(RT9120_AMPOFF_WAITMS);
129 static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = {
130 SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0),
131 SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0),
132 SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0),
133 SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1,
134 internal_power_event, SND_SOC_DAPM_PRE_PMU |
135 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
136 SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0),
137 SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0),
138 SND_SOC_DAPM_OUTPUT("SPKL"),
139 SND_SOC_DAPM_OUTPUT("SPKR"),
142 static const struct snd_soc_dapm_route rt9120_dapm_routes[] = {
143 { "DMIX", NULL, "AIF Playback" },
145 { "LDAC", NULL, "PWND" },
146 { "LDAC", NULL, "DMIX" },
147 { "SPKL PA", NULL, "LDAC" },
148 { "SPKL", NULL, "SPKL PA" },
150 { "RDAC", NULL, "PWND" },
151 { "RDAC", NULL, "DMIX" },
152 { "SPKR PA", NULL, "RDAC" },
153 { "SPKR", NULL, "SPKR PA" },
155 { "AIF Capture", NULL, "LDAC" },
156 { "AIF Capture", NULL, "RDAC" },
159 static int rt9120_codec_probe(struct snd_soc_component *comp)
161 struct rt9120_data *data = snd_soc_component_get_drvdata(comp);
163 snd_soc_component_init_regmap(comp, data->regmap);
165 pm_runtime_get_sync(comp->dev);
167 /* Internal setting */
168 if (data->chip_idx == CHIP_IDX_RT9120S) {
169 snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
170 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
172 snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
174 pm_runtime_mark_last_busy(comp->dev);
175 pm_runtime_put(comp->dev);
180 static const struct snd_soc_component_driver rt9120_component_driver = {
181 .probe = rt9120_codec_probe,
182 .controls = rt9120_snd_controls,
183 .num_controls = ARRAY_SIZE(rt9120_snd_controls),
184 .dapm_widgets = rt9120_dapm_widgets,
185 .num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets),
186 .dapm_routes = rt9120_dapm_routes,
187 .num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes),
191 static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
193 struct snd_soc_component *comp = dai->component;
196 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
197 case SND_SOC_DAIFMT_I2S:
198 format = RT9120_CFG_FMT_I2S;
200 case SND_SOC_DAIFMT_LEFT_J:
201 format = RT9120_CFG_FMT_LEFTJ;
203 case SND_SOC_DAIFMT_RIGHT_J:
204 format = RT9120_CFG_FMT_RIGHTJ;
206 case SND_SOC_DAIFMT_DSP_A:
207 format = RT9120_CFG_FMT_DSPA;
209 case SND_SOC_DAIFMT_DSP_B:
210 format = RT9120_CFG_FMT_DSPB;
213 dev_err(dai->dev, "Unknown dai format\n");
217 snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
219 format << RT9120_I2SFMT_SHIFT);
223 static int rt9120_hw_params(struct snd_pcm_substream *substream,
224 struct snd_pcm_hw_params *param,
225 struct snd_soc_dai *dai)
227 struct snd_soc_component *comp = dai->component;
228 unsigned int param_width, param_slot_width, auto_sync;
231 switch (width = params_width(param)) {
233 param_width = RT9120_CFG_AUDBIT_16;
236 param_width = RT9120_CFG_AUDBIT_20;
240 param_width = RT9120_CFG_AUDBIT_24;
243 dev_err(dai->dev, "Unsupported data width [%d]\n", width);
247 snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT,
248 RT9120_AUDBIT_MASK, param_width);
250 switch (width = params_physical_width(param)) {
252 param_slot_width = RT9120_CFG_WORDLEN_16;
255 param_slot_width = RT9120_CFG_WORDLEN_24;
258 param_slot_width = RT9120_CFG_WORDLEN_32;
261 dev_err(dai->dev, "Unsupported slot width [%d]\n", width);
265 snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
266 RT9120_AUDWL_MASK, param_slot_width);
268 fs = width * params_channels(param);
269 /* If fs is divided by 48, disable auto sync */
273 auto_sync = RT9120_AUTOSYNC_MASK;
275 snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
276 RT9120_AUTOSYNC_MASK, auto_sync);
280 static const struct snd_soc_dai_ops rt9120_dai_ops = {
281 .set_fmt = rt9120_set_fmt,
282 .hw_params = rt9120_hw_params,
285 static struct snd_soc_dai_driver rt9120_dai = {
286 .name = "rt9120_aif",
288 .stream_name = "AIF Playback",
289 .rates = RT9120_RATES_MASK,
290 .formats = RT9120_FMTS_MASK,
297 .stream_name = "AIF Capture",
298 .rates = RT9120_RATES_MASK,
299 .formats = RT9120_FMTS_MASK,
305 .ops = &rt9120_dai_ops,
307 .symmetric_sample_bits = 1,
310 static const struct regmap_range rt9120_rd_yes_ranges[] = {
311 regmap_reg_range(0x00, 0x0C),
312 regmap_reg_range(0x10, 0x15),
313 regmap_reg_range(0x20, 0x27),
314 regmap_reg_range(0x30, 0x38),
315 regmap_reg_range(0x3A, 0x40),
316 regmap_reg_range(0x63, 0x63),
317 regmap_reg_range(0x65, 0x65),
318 regmap_reg_range(0x69, 0x69),
319 regmap_reg_range(0x6C, 0x6C),
320 regmap_reg_range(0xF8, 0xF8)
323 static const struct regmap_access_table rt9120_rd_table = {
324 .yes_ranges = rt9120_rd_yes_ranges,
325 .n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges),
328 static const struct regmap_range rt9120_wr_yes_ranges[] = {
329 regmap_reg_range(0x00, 0x00),
330 regmap_reg_range(0x02, 0x0A),
331 regmap_reg_range(0x10, 0x15),
332 regmap_reg_range(0x20, 0x27),
333 regmap_reg_range(0x30, 0x38),
334 regmap_reg_range(0x3A, 0x3D),
335 regmap_reg_range(0x40, 0x40),
336 regmap_reg_range(0x63, 0x63),
337 regmap_reg_range(0x65, 0x65),
338 regmap_reg_range(0x69, 0x69),
339 regmap_reg_range(0x6C, 0x6C),
340 regmap_reg_range(0xF8, 0xF8)
343 static const struct regmap_access_table rt9120_wr_table = {
344 .yes_ranges = rt9120_wr_yes_ranges,
345 .n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges),
348 static bool rt9120_volatile_reg(struct device *dev, unsigned int reg)
360 static int rt9120_get_reg_size(unsigned int reg)
375 static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val)
377 struct rt9120_data *data = context;
378 struct i2c_client *i2c = to_i2c_client(data->dev);
379 int size = rt9120_get_reg_size(reg);
383 ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw);
386 else if (ret != size)
391 *val = be32_to_cpup((__be32 *)raw);
394 *val = raw[0] << 16 | raw[1] << 8 | raw[2];
397 *val = be16_to_cpup((__be16 *)raw);
406 static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
408 struct rt9120_data *data = context;
409 struct i2c_client *i2c = to_i2c_client(data->dev);
410 int size = rt9120_get_reg_size(reg);
412 u8 *rawp = (u8 *)&be32_val;
415 be32_val = cpu_to_be32(val);
416 return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs);
419 static const struct reg_default rt9120_reg_defaults[] = {
420 { .reg = 0x02, .def = 0x02 },
421 { .reg = 0x03, .def = 0xf2 },
422 { .reg = 0x04, .def = 0x01 },
423 { .reg = 0x05, .def = 0xc0 },
424 { .reg = 0x06, .def = 0x28 },
425 { .reg = 0x07, .def = 0x04 },
426 { .reg = 0x08, .def = 0xff },
427 { .reg = 0x09, .def = 0x01 },
428 { .reg = 0x0a, .def = 0x01 },
429 { .reg = 0x0b, .def = 0x00 },
430 { .reg = 0x0c, .def = 0x04 },
431 { .reg = 0x11, .def = 0x30 },
432 { .reg = 0x12, .def = 0x08 },
433 { .reg = 0x13, .def = 0x12 },
434 { .reg = 0x14, .def = 0x09 },
435 { .reg = 0x15, .def = 0x00 },
436 { .reg = 0x20, .def = 0x7ff },
437 { .reg = 0x21, .def = 0x180 },
438 { .reg = 0x22, .def = 0x180 },
439 { .reg = 0x23, .def = 0x00 },
440 { .reg = 0x24, .def = 0x80 },
441 { .reg = 0x25, .def = 0x180 },
442 { .reg = 0x26, .def = 0x640 },
443 { .reg = 0x27, .def = 0x180 },
444 { .reg = 0x63, .def = 0x5e },
445 { .reg = 0x65, .def = 0x66 },
446 { .reg = 0x6c, .def = 0xe0 },
447 { .reg = 0xf8, .def = 0x44 },
450 static const struct regmap_config rt9120_regmap_config = {
453 .max_register = RT9120_REG_DIGCFG,
454 .reg_defaults = rt9120_reg_defaults,
455 .num_reg_defaults = ARRAY_SIZE(rt9120_reg_defaults),
456 .cache_type = REGCACHE_RBTREE,
458 .reg_read = rt9120_reg_read,
459 .reg_write = rt9120_reg_write,
461 .volatile_reg = rt9120_volatile_reg,
462 .wr_table = &rt9120_wr_table,
463 .rd_table = &rt9120_rd_table,
466 static int rt9120_check_vendor_info(struct rt9120_data *data)
471 ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid);
475 devid = FIELD_GET(RT9120_VID_MASK, devid);
477 case RT9120_VENDOR_ID:
478 data->chip_idx = CHIP_IDX_RT9120;
480 case RT9120S_VENDOR_ID:
481 data->chip_idx = CHIP_IDX_RT9120S;
484 dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
491 static int rt9120_do_register_reset(struct rt9120_data *data)
495 ret = regmap_write(data->regmap, RT9120_REG_SWRESET,
500 msleep(RT9120_RESET_WAITMS);
504 static int rt9120_probe(struct i2c_client *i2c)
506 struct rt9120_data *data;
507 struct regulator *dvdd_supply;
508 int dvdd_supply_volt, ret;
510 data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL);
514 data->dev = &i2c->dev;
515 i2c_set_clientdata(i2c, data);
517 data->pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn",
519 if (IS_ERR(data->pwdnn_gpio)) {
520 dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n");
521 return PTR_ERR(data->pwdnn_gpio);
522 } else if (data->pwdnn_gpio) {
523 dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n");
524 msleep(RT9120_CHIPON_WAITMS);
527 data->regmap = devm_regmap_init(&i2c->dev, NULL, data,
528 &rt9120_regmap_config);
529 if (IS_ERR(data->regmap)) {
530 ret = PTR_ERR(data->regmap);
531 dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret);
535 ret = rt9120_check_vendor_info(data);
537 dev_err(&i2c->dev, "Failed to check vendor info\n");
541 ret = rt9120_do_register_reset(data);
543 dev_err(&i2c->dev, "Failed to do register reset\n");
547 dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd");
548 if (IS_ERR(dvdd_supply)) {
549 dev_err(&i2c->dev, "No dvdd regulator found\n");
550 return PTR_ERR(dvdd_supply);
553 dvdd_supply_volt = regulator_get_voltage(dvdd_supply);
554 if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) {
555 dev_dbg(&i2c->dev, "dvdd low voltage design\n");
556 ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT,
557 RT9120_DVDD_UVSEL_MASK, 0);
559 dev_err(&i2c->dev, "Failed to config dvdd uvsel\n");
564 pm_runtime_set_autosuspend_delay(&i2c->dev, 1000);
565 pm_runtime_use_autosuspend(&i2c->dev);
566 pm_runtime_set_active(&i2c->dev);
567 pm_runtime_mark_last_busy(&i2c->dev);
568 pm_runtime_enable(&i2c->dev);
570 return devm_snd_soc_register_component(&i2c->dev,
571 &rt9120_component_driver,
575 static int rt9120_remove(struct i2c_client *i2c)
577 pm_runtime_disable(&i2c->dev);
578 pm_runtime_set_suspended(&i2c->dev);
582 static int __maybe_unused rt9120_runtime_suspend(struct device *dev)
584 struct rt9120_data *data = dev_get_drvdata(dev);
586 if (data->pwdnn_gpio) {
587 regcache_cache_only(data->regmap, true);
588 regcache_mark_dirty(data->regmap);
589 gpiod_set_value(data->pwdnn_gpio, 0);
595 static int __maybe_unused rt9120_runtime_resume(struct device *dev)
597 struct rt9120_data *data = dev_get_drvdata(dev);
599 if (data->pwdnn_gpio) {
600 gpiod_set_value(data->pwdnn_gpio, 1);
601 msleep(RT9120_CHIPON_WAITMS);
602 regcache_cache_only(data->regmap, false);
603 regcache_sync(data->regmap);
609 static const struct dev_pm_ops rt9120_pm_ops = {
610 SET_RUNTIME_PM_OPS(rt9120_runtime_suspend, rt9120_runtime_resume, NULL)
613 static const struct of_device_id __maybe_unused rt9120_device_table[] = {
614 { .compatible = "richtek,rt9120", },
617 MODULE_DEVICE_TABLE(of, rt9120_device_table);
619 static struct i2c_driver rt9120_driver = {
622 .of_match_table = rt9120_device_table,
623 .pm = &rt9120_pm_ops,
625 .probe_new = rt9120_probe,
626 .remove = rt9120_remove,
628 module_i2c_driver(rt9120_driver);
630 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
631 MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver");
632 MODULE_LICENSE("GPL");