sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // rt5682.c  --  RT5682 ALSA SoC audio component driver
   4 //
   5 // Copyright 2018 Realtek Semiconductor Corp.
   6 // Author: Bard Liao <bardliao@realtek.com>
   7 //
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/mutex.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/jack.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/rt5682.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5682.h"
  33
  34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  35         "AVDD",
  36         "MICVDD",
  37         "VBAT",
  38 };
  39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
  40
  41 static const struct reg_sequence patch_list[] = {
  42         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  43         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  44         {RT5682_I2C_CTRL, 0x000f},
  45         {RT5682_PLL2_INTERNAL, 0x8266},
  46         {RT5682_SAR_IL_CMD_3, 0x8365},
  47         {RT5682_SAR_IL_CMD_6, 0x0180},
  48 };
  49
  50 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
  51 {
  52         int ret;
  53
  54         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
  55                                      ARRAY_SIZE(patch_list));
  56         if (ret)
  57                 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
  58 }
  59 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
  60
  61 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
  62         {0x0002, 0x8080},
  63         {0x0003, 0x8000},
  64         {0x0005, 0x0000},
  65         {0x0006, 0x0000},
  66         {0x0008, 0x800f},
  67         {0x000b, 0x0000},
  68         {0x0010, 0x4040},
  69         {0x0011, 0x0000},
  70         {0x0012, 0x1404},
  71         {0x0013, 0x1000},
  72         {0x0014, 0xa00a},
  73         {0x0015, 0x0404},
  74         {0x0016, 0x0404},
  75         {0x0019, 0xafaf},
  76         {0x001c, 0x2f2f},
  77         {0x001f, 0x0000},
  78         {0x0022, 0x5757},
  79         {0x0023, 0x0039},
  80         {0x0024, 0x000b},
  81         {0x0026, 0xc0c4},
  82         {0x0029, 0x8080},
  83         {0x002a, 0xa0a0},
  84         {0x002b, 0x0300},
  85         {0x0030, 0x0000},
  86         {0x003c, 0x0080},
  87         {0x0044, 0x0c0c},
  88         {0x0049, 0x0000},
  89         {0x0061, 0x0000},
  90         {0x0062, 0x0000},
  91         {0x0063, 0x003f},
  92         {0x0064, 0x0000},
  93         {0x0065, 0x0000},
  94         {0x0066, 0x0030},
  95         {0x0067, 0x0000},
  96         {0x006b, 0x0000},
  97         {0x006c, 0x0000},
  98         {0x006d, 0x2200},
  99         {0x006e, 0x0a10},
 100         {0x0070, 0x8000},
 101         {0x0071, 0x8000},
 102         {0x0073, 0x0000},
 103         {0x0074, 0x0000},
 104         {0x0075, 0x0002},
 105         {0x0076, 0x0001},
 106         {0x0079, 0x0000},
 107         {0x007a, 0x0000},
 108         {0x007b, 0x0000},
 109         {0x007c, 0x0100},
 110         {0x007e, 0x0000},
 111         {0x0080, 0x0000},
 112         {0x0081, 0x0000},
 113         {0x0082, 0x0000},
 114         {0x0083, 0x0000},
 115         {0x0084, 0x0000},
 116         {0x0085, 0x0000},
 117         {0x0086, 0x0005},
 118         {0x0087, 0x0000},
 119         {0x0088, 0x0000},
 120         {0x008c, 0x0003},
 121         {0x008d, 0x0000},
 122         {0x008e, 0x0060},
 123         {0x008f, 0x1000},
 124         {0x0091, 0x0c26},
 125         {0x0092, 0x0073},
 126         {0x0093, 0x0000},
 127         {0x0094, 0x0080},
 128         {0x0098, 0x0000},
 129         {0x009a, 0x0000},
 130         {0x009b, 0x0000},
 131         {0x009c, 0x0000},
 132         {0x009d, 0x0000},
 133         {0x009e, 0x100c},
 134         {0x009f, 0x0000},
 135         {0x00a0, 0x0000},
 136         {0x00a3, 0x0002},
 137         {0x00a4, 0x0001},
 138         {0x00ae, 0x2040},
 139         {0x00af, 0x0000},
 140         {0x00b6, 0x0000},
 141         {0x00b7, 0x0000},
 142         {0x00b8, 0x0000},
 143         {0x00b9, 0x0002},
 144         {0x00be, 0x0000},
 145         {0x00c0, 0x0160},
 146         {0x00c1, 0x82a0},
 147         {0x00c2, 0x0000},
 148         {0x00d0, 0x0000},
 149         {0x00d1, 0x2244},
 150         {0x00d2, 0x3300},
 151         {0x00d3, 0x2200},
 152         {0x00d4, 0x0000},
 153         {0x00d9, 0x0009},
 154         {0x00da, 0x0000},
 155         {0x00db, 0x0000},
 156         {0x00dc, 0x00c0},
 157         {0x00dd, 0x2220},
 158         {0x00de, 0x3131},
 159         {0x00df, 0x3131},
 160         {0x00e0, 0x3131},
 161         {0x00e2, 0x0000},
 162         {0x00e3, 0x4000},
 163         {0x00e4, 0x0aa0},
 164         {0x00e5, 0x3131},
 165         {0x00e6, 0x3131},
 166         {0x00e7, 0x3131},
 167         {0x00e8, 0x3131},
 168         {0x00ea, 0xb320},
 169         {0x00eb, 0x0000},
 170         {0x00f0, 0x0000},
 171         {0x00f1, 0x00d0},
 172         {0x00f2, 0x00d0},
 173         {0x00f6, 0x0000},
 174         {0x00fa, 0x0000},
 175         {0x00fb, 0x0000},
 176         {0x00fc, 0x0000},
 177         {0x00fd, 0x0000},
 178         {0x00fe, 0x10ec},
 179         {0x00ff, 0x6530},
 180         {0x0100, 0xa0a0},
 181         {0x010b, 0x0000},
 182         {0x010c, 0xae00},
 183         {0x010d, 0xaaa0},
 184         {0x010e, 0x8aa2},
 185         {0x010f, 0x02a2},
 186         {0x0110, 0xc000},
 187         {0x0111, 0x04a2},
 188         {0x0112, 0x2800},
 189         {0x0113, 0x0000},
 190         {0x0117, 0x0100},
 191         {0x0125, 0x0410},
 192         {0x0132, 0x6026},
 193         {0x0136, 0x5555},
 194         {0x0138, 0x3700},
 195         {0x013a, 0x2000},
 196         {0x013b, 0x2000},
 197         {0x013c, 0x2005},
 198         {0x013f, 0x0000},
 199         {0x0142, 0x0000},
 200         {0x0145, 0x0002},
 201         {0x0146, 0x0000},
 202         {0x0147, 0x0000},
 203         {0x0148, 0x0000},
 204         {0x0149, 0x0000},
 205         {0x0150, 0x79a1},
 206         {0x0156, 0xaaaa},
 207         {0x0160, 0x4ec0},
 208         {0x0161, 0x0080},
 209         {0x0162, 0x0200},
 210         {0x0163, 0x0800},
 211         {0x0164, 0x0000},
 212         {0x0165, 0x0000},
 213         {0x0166, 0x0000},
 214         {0x0167, 0x000f},
 215         {0x0168, 0x000f},
 216         {0x0169, 0x0021},
 217         {0x0190, 0x413d},
 218         {0x0194, 0x0000},
 219         {0x0195, 0x0000},
 220         {0x0197, 0x0022},
 221         {0x0198, 0x0000},
 222         {0x0199, 0x0000},
 223         {0x01af, 0x0000},
 224         {0x01b0, 0x0400},
 225         {0x01b1, 0x0000},
 226         {0x01b2, 0x0000},
 227         {0x01b3, 0x0000},
 228         {0x01b4, 0x0000},
 229         {0x01b5, 0x0000},
 230         {0x01b6, 0x01c3},
 231         {0x01b7, 0x02a0},
 232         {0x01b8, 0x03e9},
 233         {0x01b9, 0x1389},
 234         {0x01ba, 0xc351},
 235         {0x01bb, 0x0009},
 236         {0x01bc, 0x0018},
 237         {0x01bd, 0x002a},
 238         {0x01be, 0x004c},
 239         {0x01bf, 0x0097},
 240         {0x01c0, 0x433d},
 241         {0x01c2, 0x0000},
 242         {0x01c3, 0x0000},
 243         {0x01c4, 0x0000},
 244         {0x01c5, 0x0000},
 245         {0x01c6, 0x0000},
 246         {0x01c7, 0x0000},
 247         {0x01c8, 0x40af},
 248         {0x01c9, 0x0702},
 249         {0x01ca, 0x0000},
 250         {0x01cb, 0x0000},
 251         {0x01cc, 0x5757},
 252         {0x01cd, 0x5757},
 253         {0x01ce, 0x5757},
 254         {0x01cf, 0x5757},
 255         {0x01d0, 0x5757},
 256         {0x01d1, 0x5757},
 257         {0x01d2, 0x5757},
 258         {0x01d3, 0x5757},
 259         {0x01d4, 0x5757},
 260         {0x01d5, 0x5757},
 261         {0x01d6, 0x0000},
 262         {0x01d7, 0x0008},
 263         {0x01d8, 0x0029},
 264         {0x01d9, 0x3333},
 265         {0x01da, 0x0000},
 266         {0x01db, 0x0004},
 267         {0x01dc, 0x0000},
 268         {0x01de, 0x7c00},
 269         {0x01df, 0x0320},
 270         {0x01e0, 0x06a1},
 271         {0x01e1, 0x0000},
 272         {0x01e2, 0x0000},
 273         {0x01e3, 0x0000},
 274         {0x01e4, 0x0000},
 275         {0x01e6, 0x0001},
 276         {0x01e7, 0x0000},
 277         {0x01e8, 0x0000},
 278         {0x01ea, 0x0000},
 279         {0x01eb, 0x0000},
 280         {0x01ec, 0x0000},
 281         {0x01ed, 0x0000},
 282         {0x01ee, 0x0000},
 283         {0x01ef, 0x0000},
 284         {0x01f0, 0x0000},
 285         {0x01f1, 0x0000},
 286         {0x01f2, 0x0000},
 287         {0x01f3, 0x0000},
 288         {0x01f4, 0x0000},
 289         {0x0210, 0x6297},
 290         {0x0211, 0xa005},
 291         {0x0212, 0x824c},
 292         {0x0213, 0xf7ff},
 293         {0x0214, 0xf24c},
 294         {0x0215, 0x0102},
 295         {0x0216, 0x00a3},
 296         {0x0217, 0x0048},
 297         {0x0218, 0xa2c0},
 298         {0x0219, 0x0400},
 299         {0x021a, 0x00c8},
 300         {0x021b, 0x00c0},
 301         {0x021c, 0x0000},
 302         {0x0250, 0x4500},
 303         {0x0251, 0x40b3},
 304         {0x0252, 0x0000},
 305         {0x0253, 0x0000},
 306         {0x0254, 0x0000},
 307         {0x0255, 0x0000},
 308         {0x0256, 0x0000},
 309         {0x0257, 0x0000},
 310         {0x0258, 0x0000},
 311         {0x0259, 0x0000},
 312         {0x025a, 0x0005},
 313         {0x0270, 0x0000},
 314         {0x02ff, 0x0110},
 315         {0x0300, 0x001f},
 316         {0x0301, 0x032c},
 317         {0x0302, 0x5f21},
 318         {0x0303, 0x4000},
 319         {0x0304, 0x4000},
 320         {0x0305, 0x06d5},
 321         {0x0306, 0x8000},
 322         {0x0307, 0x0700},
 323         {0x0310, 0x4560},
 324         {0x0311, 0xa4a8},
 325         {0x0312, 0x7418},
 326         {0x0313, 0x0000},
 327         {0x0314, 0x0006},
 328         {0x0315, 0xffff},
 329         {0x0316, 0xc400},
 330         {0x0317, 0x0000},
 331         {0x03c0, 0x7e00},
 332         {0x03c1, 0x8000},
 333         {0x03c2, 0x8000},
 334         {0x03c3, 0x8000},
 335         {0x03c4, 0x8000},
 336         {0x03c5, 0x8000},
 337         {0x03c6, 0x8000},
 338         {0x03c7, 0x8000},
 339         {0x03c8, 0x8000},
 340         {0x03c9, 0x8000},
 341         {0x03ca, 0x8000},
 342         {0x03cb, 0x8000},
 343         {0x03cc, 0x8000},
 344         {0x03d0, 0x0000},
 345         {0x03d1, 0x0000},
 346         {0x03d2, 0x0000},
 347         {0x03d3, 0x0000},
 348         {0x03d4, 0x2000},
 349         {0x03d5, 0x2000},
 350         {0x03d6, 0x0000},
 351         {0x03d7, 0x0000},
 352         {0x03d8, 0x2000},
 353         {0x03d9, 0x2000},
 354         {0x03da, 0x2000},
 355         {0x03db, 0x2000},
 356         {0x03dc, 0x0000},
 357         {0x03dd, 0x0000},
 358         {0x03de, 0x0000},
 359         {0x03df, 0x2000},
 360         {0x03e0, 0x0000},
 361         {0x03e1, 0x0000},
 362         {0x03e2, 0x0000},
 363         {0x03e3, 0x0000},
 364         {0x03e4, 0x0000},
 365         {0x03e5, 0x0000},
 366         {0x03e6, 0x0000},
 367         {0x03e7, 0x0000},
 368         {0x03e8, 0x0000},
 369         {0x03e9, 0x0000},
 370         {0x03ea, 0x0000},
 371         {0x03eb, 0x0000},
 372         {0x03ec, 0x0000},
 373         {0x03ed, 0x0000},
 374         {0x03ee, 0x0000},
 375         {0x03ef, 0x0000},
 376         {0x03f0, 0x0800},
 377         {0x03f1, 0x0800},
 378         {0x03f2, 0x0800},
 379         {0x03f3, 0x0800},
 380 };
 381 EXPORT_SYMBOL_GPL(rt5682_reg);
 382
 383 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 384 {
 385         switch (reg) {
 386         case RT5682_RESET:
 387         case RT5682_CBJ_CTRL_2:
 388         case RT5682_INT_ST_1:
 389         case RT5682_4BTN_IL_CMD_1:
 390         case RT5682_AJD1_CTRL:
 391         case RT5682_HP_CALIB_CTRL_1:
 392         case RT5682_DEVICE_ID:
 393         case RT5682_I2C_MODE:
 394         case RT5682_HP_CALIB_CTRL_10:
 395         case RT5682_EFUSE_CTRL_2:
 396         case RT5682_JD_TOP_VC_VTRL:
 397         case RT5682_HP_IMP_SENS_CTRL_19:
 398         case RT5682_IL_CMD_1:
 399         case RT5682_SAR_IL_CMD_2:
 400         case RT5682_SAR_IL_CMD_4:
 401         case RT5682_SAR_IL_CMD_10:
 402         case RT5682_SAR_IL_CMD_11:
 403         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 404         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 405                 return true;
 406         default:
 407                 return false;
 408         }
 409 }
 410 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
 411
 412 bool rt5682_readable_register(struct device *dev, unsigned int reg)
 413 {
 414         switch (reg) {
 415         case RT5682_RESET:
 416         case RT5682_VERSION_ID:
 417         case RT5682_VENDOR_ID:
 418         case RT5682_DEVICE_ID:
 419         case RT5682_HP_CTRL_1:
 420         case RT5682_HP_CTRL_2:
 421         case RT5682_HPL_GAIN:
 422         case RT5682_HPR_GAIN:
 423         case RT5682_I2C_CTRL:
 424         case RT5682_CBJ_BST_CTRL:
 425         case RT5682_CBJ_CTRL_1:
 426         case RT5682_CBJ_CTRL_2:
 427         case RT5682_CBJ_CTRL_3:
 428         case RT5682_CBJ_CTRL_4:
 429         case RT5682_CBJ_CTRL_5:
 430         case RT5682_CBJ_CTRL_6:
 431         case RT5682_CBJ_CTRL_7:
 432         case RT5682_DAC1_DIG_VOL:
 433         case RT5682_STO1_ADC_DIG_VOL:
 434         case RT5682_STO1_ADC_BOOST:
 435         case RT5682_HP_IMP_GAIN_1:
 436         case RT5682_HP_IMP_GAIN_2:
 437         case RT5682_SIDETONE_CTRL:
 438         case RT5682_STO1_ADC_MIXER:
 439         case RT5682_AD_DA_MIXER:
 440         case RT5682_STO1_DAC_MIXER:
 441         case RT5682_A_DAC1_MUX:
 442         case RT5682_DIG_INF2_DATA:
 443         case RT5682_REC_MIXER:
 444         case RT5682_CAL_REC:
 445         case RT5682_ALC_BACK_GAIN:
 446         case RT5682_PWR_DIG_1:
 447         case RT5682_PWR_DIG_2:
 448         case RT5682_PWR_ANLG_1:
 449         case RT5682_PWR_ANLG_2:
 450         case RT5682_PWR_ANLG_3:
 451         case RT5682_PWR_MIXER:
 452         case RT5682_PWR_VOL:
 453         case RT5682_CLK_DET:
 454         case RT5682_RESET_LPF_CTRL:
 455         case RT5682_RESET_HPF_CTRL:
 456         case RT5682_DMIC_CTRL_1:
 457         case RT5682_I2S1_SDP:
 458         case RT5682_I2S2_SDP:
 459         case RT5682_ADDA_CLK_1:
 460         case RT5682_ADDA_CLK_2:
 461         case RT5682_I2S1_F_DIV_CTRL_1:
 462         case RT5682_I2S1_F_DIV_CTRL_2:
 463         case RT5682_TDM_CTRL:
 464         case RT5682_TDM_ADDA_CTRL_1:
 465         case RT5682_TDM_ADDA_CTRL_2:
 466         case RT5682_DATA_SEL_CTRL_1:
 467         case RT5682_TDM_TCON_CTRL:
 468         case RT5682_GLB_CLK:
 469         case RT5682_PLL_CTRL_1:
 470         case RT5682_PLL_CTRL_2:
 471         case RT5682_PLL_TRACK_1:
 472         case RT5682_PLL_TRACK_2:
 473         case RT5682_PLL_TRACK_3:
 474         case RT5682_PLL_TRACK_4:
 475         case RT5682_PLL_TRACK_5:
 476         case RT5682_PLL_TRACK_6:
 477         case RT5682_PLL_TRACK_11:
 478         case RT5682_SDW_REF_CLK:
 479         case RT5682_DEPOP_1:
 480         case RT5682_DEPOP_2:
 481         case RT5682_HP_CHARGE_PUMP_1:
 482         case RT5682_HP_CHARGE_PUMP_2:
 483         case RT5682_MICBIAS_1:
 484         case RT5682_MICBIAS_2:
 485         case RT5682_PLL_TRACK_12:
 486         case RT5682_PLL_TRACK_14:
 487         case RT5682_PLL2_CTRL_1:
 488         case RT5682_PLL2_CTRL_2:
 489         case RT5682_PLL2_CTRL_3:
 490         case RT5682_PLL2_CTRL_4:
 491         case RT5682_RC_CLK_CTRL:
 492         case RT5682_I2S_M_CLK_CTRL_1:
 493         case RT5682_I2S2_F_DIV_CTRL_1:
 494         case RT5682_I2S2_F_DIV_CTRL_2:
 495         case RT5682_EQ_CTRL_1:
 496         case RT5682_EQ_CTRL_2:
 497         case RT5682_IRQ_CTRL_1:
 498         case RT5682_IRQ_CTRL_2:
 499         case RT5682_IRQ_CTRL_3:
 500         case RT5682_IRQ_CTRL_4:
 501         case RT5682_INT_ST_1:
 502         case RT5682_GPIO_CTRL_1:
 503         case RT5682_GPIO_CTRL_2:
 504         case RT5682_GPIO_CTRL_3:
 505         case RT5682_HP_AMP_DET_CTRL_1:
 506         case RT5682_HP_AMP_DET_CTRL_2:
 507         case RT5682_MID_HP_AMP_DET:
 508         case RT5682_LOW_HP_AMP_DET:
 509         case RT5682_DELAY_BUF_CTRL:
 510         case RT5682_SV_ZCD_1:
 511         case RT5682_SV_ZCD_2:
 512         case RT5682_IL_CMD_1:
 513         case RT5682_IL_CMD_2:
 514         case RT5682_IL_CMD_3:
 515         case RT5682_IL_CMD_4:
 516         case RT5682_IL_CMD_5:
 517         case RT5682_IL_CMD_6:
 518         case RT5682_4BTN_IL_CMD_1:
 519         case RT5682_4BTN_IL_CMD_2:
 520         case RT5682_4BTN_IL_CMD_3:
 521         case RT5682_4BTN_IL_CMD_4:
 522         case RT5682_4BTN_IL_CMD_5:
 523         case RT5682_4BTN_IL_CMD_6:
 524         case RT5682_4BTN_IL_CMD_7:
 525         case RT5682_ADC_STO1_HP_CTRL_1:
 526         case RT5682_ADC_STO1_HP_CTRL_2:
 527         case RT5682_AJD1_CTRL:
 528         case RT5682_JD1_THD:
 529         case RT5682_JD2_THD:
 530         case RT5682_JD_CTRL_1:
 531         case RT5682_DUMMY_1:
 532         case RT5682_DUMMY_2:
 533         case RT5682_DUMMY_3:
 534         case RT5682_DAC_ADC_DIG_VOL1:
 535         case RT5682_BIAS_CUR_CTRL_2:
 536         case RT5682_BIAS_CUR_CTRL_3:
 537         case RT5682_BIAS_CUR_CTRL_4:
 538         case RT5682_BIAS_CUR_CTRL_5:
 539         case RT5682_BIAS_CUR_CTRL_6:
 540         case RT5682_BIAS_CUR_CTRL_7:
 541         case RT5682_BIAS_CUR_CTRL_8:
 542         case RT5682_BIAS_CUR_CTRL_9:
 543         case RT5682_BIAS_CUR_CTRL_10:
 544         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 545         case RT5682_CHARGE_PUMP_1:
 546         case RT5682_DIG_IN_CTRL_1:
 547         case RT5682_PAD_DRIVING_CTRL:
 548         case RT5682_SOFT_RAMP_DEPOP:
 549         case RT5682_CHOP_DAC:
 550         case RT5682_CHOP_ADC:
 551         case RT5682_CALIB_ADC_CTRL:
 552         case RT5682_VOL_TEST:
 553         case RT5682_SPKVDD_DET_STA:
 554         case RT5682_TEST_MODE_CTRL_1:
 555         case RT5682_TEST_MODE_CTRL_2:
 556         case RT5682_TEST_MODE_CTRL_3:
 557         case RT5682_TEST_MODE_CTRL_4:
 558         case RT5682_TEST_MODE_CTRL_5:
 559         case RT5682_PLL1_INTERNAL:
 560         case RT5682_PLL2_INTERNAL:
 561         case RT5682_STO_NG2_CTRL_1:
 562         case RT5682_STO_NG2_CTRL_2:
 563         case RT5682_STO_NG2_CTRL_3:
 564         case RT5682_STO_NG2_CTRL_4:
 565         case RT5682_STO_NG2_CTRL_5:
 566         case RT5682_STO_NG2_CTRL_6:
 567         case RT5682_STO_NG2_CTRL_7:
 568         case RT5682_STO_NG2_CTRL_8:
 569         case RT5682_STO_NG2_CTRL_9:
 570         case RT5682_STO_NG2_CTRL_10:
 571         case RT5682_STO1_DAC_SIL_DET:
 572         case RT5682_SIL_PSV_CTRL1:
 573         case RT5682_SIL_PSV_CTRL2:
 574         case RT5682_SIL_PSV_CTRL3:
 575         case RT5682_SIL_PSV_CTRL4:
 576         case RT5682_SIL_PSV_CTRL5:
 577         case RT5682_HP_IMP_SENS_CTRL_01:
 578         case RT5682_HP_IMP_SENS_CTRL_02:
 579         case RT5682_HP_IMP_SENS_CTRL_03:
 580         case RT5682_HP_IMP_SENS_CTRL_04:
 581         case RT5682_HP_IMP_SENS_CTRL_05:
 582         case RT5682_HP_IMP_SENS_CTRL_06:
 583         case RT5682_HP_IMP_SENS_CTRL_07:
 584         case RT5682_HP_IMP_SENS_CTRL_08:
 585         case RT5682_HP_IMP_SENS_CTRL_09:
 586         case RT5682_HP_IMP_SENS_CTRL_10:
 587         case RT5682_HP_IMP_SENS_CTRL_11:
 588         case RT5682_HP_IMP_SENS_CTRL_12:
 589         case RT5682_HP_IMP_SENS_CTRL_13:
 590         case RT5682_HP_IMP_SENS_CTRL_14:
 591         case RT5682_HP_IMP_SENS_CTRL_15:
 592         case RT5682_HP_IMP_SENS_CTRL_16:
 593         case RT5682_HP_IMP_SENS_CTRL_17:
 594         case RT5682_HP_IMP_SENS_CTRL_18:
 595         case RT5682_HP_IMP_SENS_CTRL_19:
 596         case RT5682_HP_IMP_SENS_CTRL_20:
 597         case RT5682_HP_IMP_SENS_CTRL_21:
 598         case RT5682_HP_IMP_SENS_CTRL_22:
 599         case RT5682_HP_IMP_SENS_CTRL_23:
 600         case RT5682_HP_IMP_SENS_CTRL_24:
 601         case RT5682_HP_IMP_SENS_CTRL_25:
 602         case RT5682_HP_IMP_SENS_CTRL_26:
 603         case RT5682_HP_IMP_SENS_CTRL_27:
 604         case RT5682_HP_IMP_SENS_CTRL_28:
 605         case RT5682_HP_IMP_SENS_CTRL_29:
 606         case RT5682_HP_IMP_SENS_CTRL_30:
 607         case RT5682_HP_IMP_SENS_CTRL_31:
 608         case RT5682_HP_IMP_SENS_CTRL_32:
 609         case RT5682_HP_IMP_SENS_CTRL_33:
 610         case RT5682_HP_IMP_SENS_CTRL_34:
 611         case RT5682_HP_IMP_SENS_CTRL_35:
 612         case RT5682_HP_IMP_SENS_CTRL_36:
 613         case RT5682_HP_IMP_SENS_CTRL_37:
 614         case RT5682_HP_IMP_SENS_CTRL_38:
 615         case RT5682_HP_IMP_SENS_CTRL_39:
 616         case RT5682_HP_IMP_SENS_CTRL_40:
 617         case RT5682_HP_IMP_SENS_CTRL_41:
 618         case RT5682_HP_IMP_SENS_CTRL_42:
 619         case RT5682_HP_IMP_SENS_CTRL_43:
 620         case RT5682_HP_LOGIC_CTRL_1:
 621         case RT5682_HP_LOGIC_CTRL_2:
 622         case RT5682_HP_LOGIC_CTRL_3:
 623         case RT5682_HP_CALIB_CTRL_1:
 624         case RT5682_HP_CALIB_CTRL_2:
 625         case RT5682_HP_CALIB_CTRL_3:
 626         case RT5682_HP_CALIB_CTRL_4:
 627         case RT5682_HP_CALIB_CTRL_5:
 628         case RT5682_HP_CALIB_CTRL_6:
 629         case RT5682_HP_CALIB_CTRL_7:
 630         case RT5682_HP_CALIB_CTRL_9:
 631         case RT5682_HP_CALIB_CTRL_10:
 632         case RT5682_HP_CALIB_CTRL_11:
 633         case RT5682_HP_CALIB_STA_1:
 634         case RT5682_HP_CALIB_STA_2:
 635         case RT5682_HP_CALIB_STA_3:
 636         case RT5682_HP_CALIB_STA_4:
 637         case RT5682_HP_CALIB_STA_5:
 638         case RT5682_HP_CALIB_STA_6:
 639         case RT5682_HP_CALIB_STA_7:
 640         case RT5682_HP_CALIB_STA_8:
 641         case RT5682_HP_CALIB_STA_9:
 642         case RT5682_HP_CALIB_STA_10:
 643         case RT5682_HP_CALIB_STA_11:
 644         case RT5682_SAR_IL_CMD_1:
 645         case RT5682_SAR_IL_CMD_2:
 646         case RT5682_SAR_IL_CMD_3:
 647         case RT5682_SAR_IL_CMD_4:
 648         case RT5682_SAR_IL_CMD_5:
 649         case RT5682_SAR_IL_CMD_6:
 650         case RT5682_SAR_IL_CMD_7:
 651         case RT5682_SAR_IL_CMD_8:
 652         case RT5682_SAR_IL_CMD_9:
 653         case RT5682_SAR_IL_CMD_10:
 654         case RT5682_SAR_IL_CMD_11:
 655         case RT5682_SAR_IL_CMD_12:
 656         case RT5682_SAR_IL_CMD_13:
 657         case RT5682_EFUSE_CTRL_1:
 658         case RT5682_EFUSE_CTRL_2:
 659         case RT5682_EFUSE_CTRL_3:
 660         case RT5682_EFUSE_CTRL_4:
 661         case RT5682_EFUSE_CTRL_5:
 662         case RT5682_EFUSE_CTRL_6:
 663         case RT5682_EFUSE_CTRL_7:
 664         case RT5682_EFUSE_CTRL_8:
 665         case RT5682_EFUSE_CTRL_9:
 666         case RT5682_EFUSE_CTRL_10:
 667         case RT5682_EFUSE_CTRL_11:
 668         case RT5682_JD_TOP_VC_VTRL:
 669         case RT5682_DRC1_CTRL_0:
 670         case RT5682_DRC1_CTRL_1:
 671         case RT5682_DRC1_CTRL_2:
 672         case RT5682_DRC1_CTRL_3:
 673         case RT5682_DRC1_CTRL_4:
 674         case RT5682_DRC1_CTRL_5:
 675         case RT5682_DRC1_CTRL_6:
 676         case RT5682_DRC1_HARD_LMT_CTRL_1:
 677         case RT5682_DRC1_HARD_LMT_CTRL_2:
 678         case RT5682_DRC1_PRIV_1:
 679         case RT5682_DRC1_PRIV_2:
 680         case RT5682_DRC1_PRIV_3:
 681         case RT5682_DRC1_PRIV_4:
 682         case RT5682_DRC1_PRIV_5:
 683         case RT5682_DRC1_PRIV_6:
 684         case RT5682_DRC1_PRIV_7:
 685         case RT5682_DRC1_PRIV_8:
 686         case RT5682_EQ_AUTO_RCV_CTRL1:
 687         case RT5682_EQ_AUTO_RCV_CTRL2:
 688         case RT5682_EQ_AUTO_RCV_CTRL3:
 689         case RT5682_EQ_AUTO_RCV_CTRL4:
 690         case RT5682_EQ_AUTO_RCV_CTRL5:
 691         case RT5682_EQ_AUTO_RCV_CTRL6:
 692         case RT5682_EQ_AUTO_RCV_CTRL7:
 693         case RT5682_EQ_AUTO_RCV_CTRL8:
 694         case RT5682_EQ_AUTO_RCV_CTRL9:
 695         case RT5682_EQ_AUTO_RCV_CTRL10:
 696         case RT5682_EQ_AUTO_RCV_CTRL11:
 697         case RT5682_EQ_AUTO_RCV_CTRL12:
 698         case RT5682_EQ_AUTO_RCV_CTRL13:
 699         case RT5682_ADC_L_EQ_LPF1_A1:
 700         case RT5682_R_EQ_LPF1_A1:
 701         case RT5682_L_EQ_LPF1_H0:
 702         case RT5682_R_EQ_LPF1_H0:
 703         case RT5682_L_EQ_BPF1_A1:
 704         case RT5682_R_EQ_BPF1_A1:
 705         case RT5682_L_EQ_BPF1_A2:
 706         case RT5682_R_EQ_BPF1_A2:
 707         case RT5682_L_EQ_BPF1_H0:
 708         case RT5682_R_EQ_BPF1_H0:
 709         case RT5682_L_EQ_BPF2_A1:
 710         case RT5682_R_EQ_BPF2_A1:
 711         case RT5682_L_EQ_BPF2_A2:
 712         case RT5682_R_EQ_BPF2_A2:
 713         case RT5682_L_EQ_BPF2_H0:
 714         case RT5682_R_EQ_BPF2_H0:
 715         case RT5682_L_EQ_BPF3_A1:
 716         case RT5682_R_EQ_BPF3_A1:
 717         case RT5682_L_EQ_BPF3_A2:
 718         case RT5682_R_EQ_BPF3_A2:
 719         case RT5682_L_EQ_BPF3_H0:
 720         case RT5682_R_EQ_BPF3_H0:
 721         case RT5682_L_EQ_BPF4_A1:
 722         case RT5682_R_EQ_BPF4_A1:
 723         case RT5682_L_EQ_BPF4_A2:
 724         case RT5682_R_EQ_BPF4_A2:
 725         case RT5682_L_EQ_BPF4_H0:
 726         case RT5682_R_EQ_BPF4_H0:
 727         case RT5682_L_EQ_HPF1_A1:
 728         case RT5682_R_EQ_HPF1_A1:
 729         case RT5682_L_EQ_HPF1_H0:
 730         case RT5682_R_EQ_HPF1_H0:
 731         case RT5682_L_EQ_PRE_VOL:
 732         case RT5682_R_EQ_PRE_VOL:
 733         case RT5682_L_EQ_POST_VOL:
 734         case RT5682_R_EQ_POST_VOL:
 735         case RT5682_I2C_MODE:
 736                 return true;
 737         default:
 738                 return false;
 739         }
 740 }
 741 EXPORT_SYMBOL_GPL(rt5682_readable_register);
 742
 743 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 744 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 745 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 746
 747 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 748 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 749         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 750         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 751         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 752         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 753         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 754         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 755         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 756 );
 757
 758 /* Interface data select */
 759 static const char * const rt5682_data_select[] = {
 760         "L/R", "R/L", "L/L", "R/R"
 761 };
 762
 763 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 764         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 765
 766 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 767         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 768
 769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 770         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 771
 772 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 773         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 774
 775 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 776         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 777
 778 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 779         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 780
 781 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 782         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 783
 784 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 785         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 786
 787 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 788         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 789
 790 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 791         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 792
 793 static const char * const rt5682_dac_select[] = {
 794         "IF1", "SOUND"
 795 };
 796
 797 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
 798         RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
 799
 800 static const struct snd_kcontrol_new rt5682_dac_l_mux =
 801         SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
 802
 803 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
 804         RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
 805
 806 static const struct snd_kcontrol_new rt5682_dac_r_mux =
 807         SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
 808
 809 void rt5682_reset(struct rt5682_priv *rt5682)
 810 {
 811         regmap_write(rt5682->regmap, RT5682_RESET, 0);
 812         if (!rt5682->is_sdw)
 813                 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
 814 }
 815 EXPORT_SYMBOL_GPL(rt5682_reset);
 816
 817 /**
 818  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 819  * @component: SoC audio component device.
 820  * @filter_mask: mask of filters.
 821  * @clk_src: clock source
 822  *
 823  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 824  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 825  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 826  * ASRC function will track i2s clock and generate a corresponding system clock
 827  * for codec. This function provides an API to select the clock source for a
 828  * set of filters specified by the mask. And the component driver will turn on
 829  * ASRC for these filters if ASRC is selected as their clock source.
 830  */
 831 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 832                 unsigned int filter_mask, unsigned int clk_src)
 833 {
 834         switch (clk_src) {
 835         case RT5682_CLK_SEL_SYS:
 836         case RT5682_CLK_SEL_I2S1_ASRC:
 837         case RT5682_CLK_SEL_I2S2_ASRC:
 838                 break;
 839
 840         default:
 841                 return -EINVAL;
 842         }
 843
 844         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 845                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 846                         RT5682_FILTER_CLK_SEL_MASK,
 847                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 848         }
 849
 850         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 851                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 852                         RT5682_FILTER_CLK_SEL_MASK,
 853                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 854         }
 855
 856         return 0;
 857 }
 858 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 859
 860 static int rt5682_button_detect(struct snd_soc_component *component)
 861 {
 862         int btn_type, val;
 863
 864         val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
 865         btn_type = val & 0xfff0;
 866         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 867         dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
 868         snd_soc_component_update_bits(component,
 869                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 870
 871         return btn_type;
 872 }
 873
 874 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 875                 bool enable)
 876 {
 877         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 878
 879         if (enable) {
 880                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 881                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 882                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 883                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 884                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 885                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 886                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 887                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 888                 if (rt5682->is_sdw)
 889                         snd_soc_component_update_bits(component,
 890                                 RT5682_IRQ_CTRL_3,
 891                                 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
 892                                 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
 893                 else
 894                         snd_soc_component_update_bits(component,
 895                                 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
 896                                 RT5682_IL_IRQ_EN);
 897         } else {
 898                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 899                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 900                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 901                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 902                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 903                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 904                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 905                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 906                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 907                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 908         }
 909 }
 910
 911 /**
 912  * rt5682_headset_detect - Detect headset.
 913  * @component: SoC audio component device.
 914  * @jack_insert: Jack insert or not.
 915  *
 916  * Detect whether is headset or not when jack inserted.
 917  *
 918  * Returns detect status.
 919  */
 920 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
 921 {
 922         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 923         struct snd_soc_dapm_context *dapm = &component->dapm;
 924         unsigned int val, count;
 925
 926         if (jack_insert) {
 927                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 928                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 929                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 930                 snd_soc_component_update_bits(component,
 931                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 932                 usleep_range(15000, 20000);
 933                 snd_soc_component_update_bits(component,
 934                         RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 935                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 936                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 937                 snd_soc_component_update_bits(component,
 938                         RT5682_HP_CHARGE_PUMP_1,
 939                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
 940                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 941                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 942
 943                 count = 0;
 944                 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
 945                         & RT5682_JACK_TYPE_MASK;
 946                 while (val == 0 && count < 50) {
 947                         usleep_range(10000, 15000);
 948                         val = snd_soc_component_read(component,
 949                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 950                         count++;
 951                 }
 952
 953                 switch (val) {
 954                 case 0x1:
 955                 case 0x2:
 956                         rt5682->jack_type = SND_JACK_HEADSET;
 957                         rt5682_enable_push_button_irq(component, true);
 958                         break;
 959                 default:
 960                         rt5682->jack_type = SND_JACK_HEADPHONE;
 961                         break;
 962                 }
 963
 964                 snd_soc_component_update_bits(component,
 965                         RT5682_HP_CHARGE_PUMP_1,
 966                         RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
 967                         RT5682_OSW_L_EN | RT5682_OSW_R_EN);
 968                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 969                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 970                         RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
 971         } else {
 972                 rt5682_enable_push_button_irq(component, false);
 973                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 974                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 975                 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
 976                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 977                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 978                         snd_soc_component_update_bits(component,
 979                                 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
 980                 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
 981                         !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
 982                         !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
 983                         snd_soc_component_update_bits(component,
 984                                 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
 985                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 986                         RT5682_PWR_CBJ, 0);
 987                 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
 988                         RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
 989                         RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
 990
 991                 rt5682->jack_type = 0;
 992         }
 993
 994         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
 995         return rt5682->jack_type;
 996 }
 997 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
 998
 999 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1000                 struct snd_soc_jack *hs_jack, void *data)
1001 {
1002         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1003
1004         rt5682->hs_jack = hs_jack;
1005
1006         if (!hs_jack) {
1007                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1008                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1009                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1010                         RT5682_POW_JDH | RT5682_POW_JDL, 0);
1011                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1012
1013                 return 0;
1014         }
1015
1016         if (!rt5682->is_sdw) {
1017                 switch (rt5682->pdata.jd_src) {
1018                 case RT5682_JD1:
1019                         snd_soc_component_update_bits(component,
1020                                 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1021                                 RT5682_EXT_JD_SRC_MANUAL);
1022                         snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1023                                 0xd042);
1024                         snd_soc_component_update_bits(component,
1025                                 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1026                                 RT5682_CBJ_IN_BUF_EN);
1027                         snd_soc_component_update_bits(component,
1028                                 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1029                                 RT5682_SAR_POW_EN);
1030                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1031                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1032                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1033                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1034                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1035                                 RT5682_POW_JDH | RT5682_POW_ANA);
1036                         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1037                                 RT5682_PWR_JDH, RT5682_PWR_JDH);
1038                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1039                                 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1040                                 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1041                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1042                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1043                                 rt5682->pdata.btndet_delay));
1044                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1045                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1046                                 rt5682->pdata.btndet_delay));
1047                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1048                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1049                                 rt5682->pdata.btndet_delay));
1050                         regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1051                                 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1052                                 rt5682->pdata.btndet_delay));
1053                         mod_delayed_work(system_power_efficient_wq,
1054                                 &rt5682->jack_detect_work,
1055                                 msecs_to_jiffies(250));
1056                         break;
1057
1058                 case RT5682_JD_NULL:
1059                         regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1060                                 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1061                         regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1062                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1063                         break;
1064
1065                 default:
1066                         dev_warn(component->dev, "Wrong JD source\n");
1067                         break;
1068                 }
1069         }
1070
1071         return 0;
1072 }
1073
1074 void rt5682_jack_detect_handler(struct work_struct *work)
1075 {
1076         struct rt5682_priv *rt5682 =
1077                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1078         int val, btn_type;
1079
1080         while (!rt5682->component)
1081                 usleep_range(10000, 15000);
1082
1083         while (!rt5682->component->card->instantiated)
1084                 usleep_range(10000, 15000);
1085
1086         mutex_lock(&rt5682->calibrate_mutex);
1087
1088         val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1089                 & RT5682_JDH_RS_MASK;
1090         if (!val) {
1091                 /* jack in */
1092                 if (rt5682->jack_type == 0) {
1093                         /* jack was out, report jack type */
1094                         rt5682->jack_type =
1095                                 rt5682_headset_detect(rt5682->component, 1);
1096                 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1097                         SND_JACK_HEADSET) {
1098                         /* jack is already in, report button event */
1099                         rt5682->jack_type = SND_JACK_HEADSET;
1100                         btn_type = rt5682_button_detect(rt5682->component);
1101                         /**
1102                          * rt5682 can report three kinds of button behavior,
1103                          * one click, double click and hold. However,
1104                          * currently we will report button pressed/released
1105                          * event. So all the three button behaviors are
1106                          * treated as button pressed.
1107                          */
1108                         switch (btn_type) {
1109                         case 0x8000:
1110                         case 0x4000:
1111                         case 0x2000:
1112                                 rt5682->jack_type |= SND_JACK_BTN_0;
1113                                 break;
1114                         case 0x1000:
1115                         case 0x0800:
1116                         case 0x0400:
1117                                 rt5682->jack_type |= SND_JACK_BTN_1;
1118                                 break;
1119                         case 0x0200:
1120                         case 0x0100:
1121                         case 0x0080:
1122                                 rt5682->jack_type |= SND_JACK_BTN_2;
1123                                 break;
1124                         case 0x0040:
1125                         case 0x0020:
1126                         case 0x0010:
1127                                 rt5682->jack_type |= SND_JACK_BTN_3;
1128                                 break;
1129                         case 0x0000: /* unpressed */
1130                                 break;
1131                         default:
1132                                 dev_err(rt5682->component->dev,
1133                                         "Unexpected button code 0x%04x\n",
1134                                         btn_type);
1135                                 break;
1136                         }
1137                 }
1138         } else {
1139                 /* jack out */
1140                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1141         }
1142
1143         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1144                 SND_JACK_HEADSET |
1145                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1146                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1147
1148         if (!rt5682->is_sdw) {
1149                 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1150                         SND_JACK_BTN_2 | SND_JACK_BTN_3))
1151                         schedule_delayed_work(&rt5682->jd_check_work, 0);
1152                 else
1153                         cancel_delayed_work_sync(&rt5682->jd_check_work);
1154         }
1155
1156         mutex_unlock(&rt5682->calibrate_mutex);
1157 }
1158 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1159
1160 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1161         /* DAC Digital Volume */
1162         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1163                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1164
1165         /* IN Boost Volume */
1166         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1167                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1168
1169         /* ADC Digital Volume Control */
1170         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1171                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1172         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1173                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1174
1175         /* ADC Boost Volume Control */
1176         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1177                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1178                 3, 0, adc_bst_tlv),
1179 };
1180
1181 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1182                 int target, const int div[], int size)
1183 {
1184         int i;
1185
1186         if (rt5682->sysclk < target) {
1187                 dev_err(rt5682->component->dev,
1188                         "sysclk rate %d is too low\n", rt5682->sysclk);
1189                 return 0;
1190         }
1191
1192         for (i = 0; i < size - 1; i++) {
1193                 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1194                 if (target * div[i] == rt5682->sysclk)
1195                         return i;
1196                 if (target * div[i + 1] > rt5682->sysclk) {
1197                         dev_dbg(rt5682->component->dev,
1198                                 "can't find div for sysclk %d\n",
1199                                 rt5682->sysclk);
1200                         return i;
1201                 }
1202         }
1203
1204         if (target * div[i] < rt5682->sysclk)
1205                 dev_err(rt5682->component->dev,
1206                         "sysclk rate %d is too high\n", rt5682->sysclk);
1207
1208         return size - 1;
1209 }
1210
1211 /**
1212  * set_dmic_clk - Set parameter of dmic.
1213  *
1214  * @w: DAPM widget.
1215  * @kcontrol: The kcontrol of this widget.
1216  * @event: Event id.
1217  *
1218  * Choose dmic clock between 1MHz and 3MHz.
1219  * It is better for clock to approximate 3MHz.
1220  */
1221 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1222                 struct snd_kcontrol *kcontrol, int event)
1223 {
1224         struct snd_soc_component *component =
1225                 snd_soc_dapm_to_component(w->dapm);
1226         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1227         int idx = -EINVAL, dmic_clk_rate = 3072000;
1228         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1229
1230         if (rt5682->pdata.dmic_clk_rate)
1231                 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1232
1233         idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1234
1235         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1236                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1237
1238         return 0;
1239 }
1240
1241 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1242                 struct snd_kcontrol *kcontrol, int event)
1243 {
1244         struct snd_soc_component *component =
1245                 snd_soc_dapm_to_component(w->dapm);
1246         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1247         int ref, val, reg, idx = -EINVAL;
1248         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1249         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1250
1251         if (rt5682->is_sdw)
1252                 return 0;
1253
1254         val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1255                 RT5682_GP4_PIN_MASK;
1256         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1257                 val == RT5682_GP4_PIN_ADCDAT2)
1258                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1259         else
1260                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1261
1262         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1263
1264         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1265                 reg = RT5682_PLL_TRACK_3;
1266         else
1267                 reg = RT5682_PLL_TRACK_2;
1268
1269         snd_soc_component_update_bits(component, reg,
1270                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1271
1272         /* select over sample rate */
1273         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1274                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1275                         break;
1276         }
1277
1278         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1279                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1280                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1281
1282         return 0;
1283 }
1284
1285 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1286                 struct snd_soc_dapm_widget *sink)
1287 {
1288         unsigned int val;
1289         struct snd_soc_component *component =
1290                 snd_soc_dapm_to_component(w->dapm);
1291
1292         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1293         val &= RT5682_SCLK_SRC_MASK;
1294         if (val == RT5682_SCLK_SRC_PLL1)
1295                 return 1;
1296         else
1297                 return 0;
1298 }
1299
1300 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1301                 struct snd_soc_dapm_widget *sink)
1302 {
1303         unsigned int val;
1304         struct snd_soc_component *component =
1305                 snd_soc_dapm_to_component(w->dapm);
1306
1307         val = snd_soc_component_read(component, RT5682_GLB_CLK);
1308         val &= RT5682_SCLK_SRC_MASK;
1309         if (val == RT5682_SCLK_SRC_PLL2)
1310                 return 1;
1311         else
1312                 return 0;
1313 }
1314
1315 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1316                 struct snd_soc_dapm_widget *sink)
1317 {
1318         unsigned int reg, shift, val;
1319         struct snd_soc_component *component =
1320                 snd_soc_dapm_to_component(w->dapm);
1321
1322         switch (w->shift) {
1323         case RT5682_ADC_STO1_ASRC_SFT:
1324                 reg = RT5682_PLL_TRACK_3;
1325                 shift = RT5682_FILTER_CLK_SEL_SFT;
1326                 break;
1327         case RT5682_DAC_STO1_ASRC_SFT:
1328                 reg = RT5682_PLL_TRACK_2;
1329                 shift = RT5682_FILTER_CLK_SEL_SFT;
1330                 break;
1331         default:
1332                 return 0;
1333         }
1334
1335         val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1336         switch (val) {
1337         case RT5682_CLK_SEL_I2S1_ASRC:
1338         case RT5682_CLK_SEL_I2S2_ASRC:
1339                 return 1;
1340         default:
1341                 return 0;
1342         }
1343 }
1344
1345 /* Digital Mixer */
1346 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1347         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1348                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1349         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1350                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1351 };
1352
1353 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1354         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1355                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1356         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1357                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1358 };
1359
1360 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1361         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1362                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1363         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1364                         RT5682_M_DAC1_L_SFT, 1, 1),
1365 };
1366
1367 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1368         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1369                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1370         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1371                         RT5682_M_DAC1_R_SFT, 1, 1),
1372 };
1373
1374 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1375         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1376                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1377         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1378                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1379 };
1380
1381 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1382         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1383                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1384         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1385                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1386 };
1387
1388 /* Analog Input Mixer */
1389 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1390         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1391                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1392 };
1393
1394 /* STO1 ADC1 Source */
1395 /* MX-26 [13] [5] */
1396 static const char * const rt5682_sto1_adc1_src[] = {
1397         "DAC MIX", "ADC"
1398 };
1399
1400 static SOC_ENUM_SINGLE_DECL(
1401         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1402         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1403
1404 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1405         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1406
1407 static SOC_ENUM_SINGLE_DECL(
1408         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1409         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1410
1411 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1412         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1413
1414 /* STO1 ADC Source */
1415 /* MX-26 [11:10] [3:2] */
1416 static const char * const rt5682_sto1_adc_src[] = {
1417         "ADC1 L", "ADC1 R"
1418 };
1419
1420 static SOC_ENUM_SINGLE_DECL(
1421         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1422         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1423
1424 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1425         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1426
1427 static SOC_ENUM_SINGLE_DECL(
1428         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1429         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1430
1431 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1432         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1433
1434 /* STO1 ADC2 Source */
1435 /* MX-26 [12] [4] */
1436 static const char * const rt5682_sto1_adc2_src[] = {
1437         "DAC MIX", "DMIC"
1438 };
1439
1440 static SOC_ENUM_SINGLE_DECL(
1441         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1442         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1443
1444 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1445         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1446
1447 static SOC_ENUM_SINGLE_DECL(
1448         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1449         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1450
1451 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1452         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1453
1454 /* MX-79 [6:4] I2S1 ADC data location */
1455 static const unsigned int rt5682_if1_adc_slot_values[] = {
1456         0,
1457         2,
1458         4,
1459         6,
1460 };
1461
1462 static const char * const rt5682_if1_adc_slot_src[] = {
1463         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1464 };
1465
1466 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1467         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1468         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1469
1470 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1471         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1472
1473 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1474 /* MX-2B [4], MX-2B [0]*/
1475 static const char * const rt5682_alg_dac1_src[] = {
1476         "Stereo1 DAC Mixer", "DAC1"
1477 };
1478
1479 static SOC_ENUM_SINGLE_DECL(
1480         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1481         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1482
1483 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1484         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1485
1486 static SOC_ENUM_SINGLE_DECL(
1487         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1488         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1489
1490 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1491         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1492
1493 /* Out Switch */
1494 static const struct snd_kcontrol_new hpol_switch =
1495         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1496                 RT5682_L_MUTE_SFT, 1, 1);
1497 static const struct snd_kcontrol_new hpor_switch =
1498         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1499                 RT5682_R_MUTE_SFT, 1, 1);
1500
1501 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1502                 struct snd_kcontrol *kcontrol, int event)
1503 {
1504         struct snd_soc_component *component =
1505                 snd_soc_dapm_to_component(w->dapm);
1506
1507         switch (event) {
1508         case SND_SOC_DAPM_PRE_PMU:
1509                 snd_soc_component_write(component,
1510                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1511                 snd_soc_component_write(component,
1512                         RT5682_HP_CTRL_2, 0x6000);
1513                 snd_soc_component_update_bits(component,
1514                         RT5682_DEPOP_1, 0x60, 0x60);
1515                 snd_soc_component_update_bits(component,
1516                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1517                 break;
1518
1519         case SND_SOC_DAPM_POST_PMD:
1520                 snd_soc_component_update_bits(component,
1521                         RT5682_DEPOP_1, 0x60, 0x0);
1522                 snd_soc_component_write(component,
1523                         RT5682_HP_CTRL_2, 0x0000);
1524                 snd_soc_component_update_bits(component,
1525                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1526                 break;
1527         }
1528
1529         return 0;
1530 }
1531
1532 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1533                 struct snd_kcontrol *kcontrol, int event)
1534 {
1535         struct snd_soc_component *component =
1536                 snd_soc_dapm_to_component(w->dapm);
1537         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1538         unsigned int delay = 50, val;
1539
1540         if (rt5682->pdata.dmic_delay)
1541                 delay = rt5682->pdata.dmic_delay;
1542
1543         switch (event) {
1544         case SND_SOC_DAPM_POST_PMU:
1545                 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1546                 val &= RT5682_SCLK_SRC_MASK;
1547                 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1548                         snd_soc_component_update_bits(component,
1549                                 RT5682_PWR_ANLG_1,
1550                                 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1551                                 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1552
1553                 /*Add delay to avoid pop noise*/
1554                 msleep(delay);
1555                 break;
1556
1557         case SND_SOC_DAPM_POST_PMD:
1558                 if (!rt5682->jack_type) {
1559                         if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1560                                 snd_soc_component_update_bits(component,
1561                                         RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1562                         if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1563                                 snd_soc_component_update_bits(component,
1564                                         RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1565                 }
1566                 break;
1567         }
1568
1569         return 0;
1570 }
1571
1572 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1573                 struct snd_kcontrol *kcontrol, int event)
1574 {
1575         struct snd_soc_component *component =
1576                 snd_soc_dapm_to_component(w->dapm);
1577
1578         switch (event) {
1579         case SND_SOC_DAPM_PRE_PMU:
1580                 switch (w->shift) {
1581                 case RT5682_PWR_VREF1_BIT:
1582                         snd_soc_component_update_bits(component,
1583                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1584                         break;
1585
1586                 case RT5682_PWR_VREF2_BIT:
1587                         snd_soc_component_update_bits(component,
1588                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1589                         break;
1590                 }
1591                 break;
1592
1593         case SND_SOC_DAPM_POST_PMU:
1594                 usleep_range(15000, 20000);
1595                 switch (w->shift) {
1596                 case RT5682_PWR_VREF1_BIT:
1597                         snd_soc_component_update_bits(component,
1598                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1599                                 RT5682_PWR_FV1);
1600                         break;
1601
1602                 case RT5682_PWR_VREF2_BIT:
1603                         snd_soc_component_update_bits(component,
1604                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1605                                 RT5682_PWR_FV2);
1606                         break;
1607                 }
1608                 break;
1609         }
1610
1611         return 0;
1612 }
1613
1614 static const unsigned int rt5682_adcdat_pin_values[] = {
1615         1,
1616         3,
1617 };
1618
1619 static const char * const rt5682_adcdat_pin_select[] = {
1620         "ADCDAT1",
1621         "ADCDAT2",
1622 };
1623
1624 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1625         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1626         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1627
1628 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1629         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1630
1631 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1632         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1633                 0, NULL, 0),
1634         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1635                 0, NULL, 0),
1636         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1637                 0, NULL, 0),
1638         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1639                 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1640         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1641                 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1642         SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1643         SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1644
1645         /* ASRC */
1646         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1647                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1648         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1649                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1650         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1651                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1652         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1653                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1654         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1655                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1656
1657         /* Input Side */
1658         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1659                 0, NULL, 0),
1660         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1661                 0, NULL, 0),
1662
1663         /* Input Lines */
1664         SND_SOC_DAPM_INPUT("DMIC L1"),
1665         SND_SOC_DAPM_INPUT("DMIC R1"),
1666
1667         SND_SOC_DAPM_INPUT("IN1P"),
1668
1669         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1670                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1671         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1672                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1673                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1674
1675         /* Boost */
1676         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1677                 0, 0, NULL, 0),
1678
1679         /* REC Mixer */
1680         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1681                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1682         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1683                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1684
1685         /* ADCs */
1686         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1687         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1688
1689         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1690                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1691         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1692                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1693         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1694                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1695
1696         /* ADC Mux */
1697         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1698                 &rt5682_sto1_adc1l_mux),
1699         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1700                 &rt5682_sto1_adc1r_mux),
1701         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1702                 &rt5682_sto1_adc2l_mux),
1703         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1704                 &rt5682_sto1_adc2r_mux),
1705         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1706                 &rt5682_sto1_adcl_mux),
1707         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1708                 &rt5682_sto1_adcr_mux),
1709         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1710                 &rt5682_if1_adc_slot_mux),
1711
1712         /* ADC Mixer */
1713         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1714                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1715                 SND_SOC_DAPM_PRE_PMU),
1716         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1717                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1718                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1719         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1720                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1721                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1722         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1723                 14, 1, NULL, 0),
1724
1725         /* ADC PGA */
1726         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1727
1728         /* Digital Interface */
1729         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1730                 0, NULL, 0),
1731         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1732                 0, NULL, 0),
1733         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1734         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1735         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1736         SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1737         SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1738
1739         /* Digital Interface Select */
1740         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1741                 &rt5682_if1_01_adc_swap_mux),
1742         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1743                 &rt5682_if1_23_adc_swap_mux),
1744         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1745                 &rt5682_if1_45_adc_swap_mux),
1746         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1747                 &rt5682_if1_67_adc_swap_mux),
1748         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1749                 &rt5682_if2_adc_swap_mux),
1750
1751         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1752                 &rt5682_adcdat_pin_ctrl),
1753
1754         SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1755                 &rt5682_dac_l_mux),
1756         SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1757                 &rt5682_dac_r_mux),
1758
1759         /* Audio Interface */
1760         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1761                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1762         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1763                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1764         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1765         SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1766         SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1767
1768         /* Output Side */
1769         /* DAC mixer before sound effect  */
1770         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1771                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1772         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1773                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1774
1775         /* DAC channel Mux */
1776         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1777                 &rt5682_alg_dac_l1_mux),
1778         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1779                 &rt5682_alg_dac_r1_mux),
1780
1781         /* DAC Mixer */
1782         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1783                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1784                 SND_SOC_DAPM_PRE_PMU),
1785         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1786                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1787         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1788                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1789
1790         /* DACs */
1791         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1792                 RT5682_PWR_DAC_L1_BIT, 0),
1793         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1794                 RT5682_PWR_DAC_R1_BIT, 0),
1795         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1796                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1797
1798         /* HPO */
1799         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1800                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1801
1802         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1803                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1804         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1805                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1806         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1807                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1808         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1809                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1810
1811         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1812                 &hpol_switch),
1813         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1814                 &hpor_switch),
1815
1816         /* CLK DET */
1817         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1818                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1819         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1820                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1821         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1822                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1823         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1824                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1825
1826         /* Output Lines */
1827         SND_SOC_DAPM_OUTPUT("HPOL"),
1828         SND_SOC_DAPM_OUTPUT("HPOR"),
1829 };
1830
1831 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1832         /*PLL*/
1833         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1834         {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1835         {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1836         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1837         {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1838         {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1839
1840         /*ASRC*/
1841         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1842         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1843         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1844         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1845         {"ADC STO1 ASRC", NULL, "CLKDET"},
1846         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1847         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1848         {"DAC STO1 ASRC", NULL, "CLKDET"},
1849
1850         /*Vref*/
1851         {"MICBIAS1", NULL, "Vref1"},
1852         {"MICBIAS2", NULL, "Vref1"},
1853
1854         {"CLKDET SYS", NULL, "CLKDET"},
1855
1856         {"IN1P", NULL, "LDO2"},
1857
1858         {"BST1 CBJ", NULL, "IN1P"},
1859
1860         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1861         {"RECMIX1L", NULL, "RECMIX1L Power"},
1862
1863         {"ADC1 L", NULL, "RECMIX1L"},
1864         {"ADC1 L", NULL, "ADC1 L Power"},
1865         {"ADC1 L", NULL, "ADC1 clock"},
1866
1867         {"DMIC L1", NULL, "DMIC CLK"},
1868         {"DMIC L1", NULL, "DMIC1 Power"},
1869         {"DMIC R1", NULL, "DMIC CLK"},
1870         {"DMIC R1", NULL, "DMIC1 Power"},
1871         {"DMIC CLK", NULL, "DMIC ASRC"},
1872
1873         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1874         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1875         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1876         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1877
1878         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1879         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1880         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1881         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1882
1883         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1884         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1885         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1886         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1887
1888         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1889         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1890         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1891
1892         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1893         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1894         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1895
1896         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1897
1898         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1899         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1900
1901         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1902         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1903         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1904         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1905         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1906         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1907         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1908         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1909         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1910         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1911         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1912         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1913         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1914         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1915         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1916         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1917
1918         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1919         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1920         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1921         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1922         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1923         {"AIF1TX", NULL, "I2S1"},
1924         {"AIF1TX", NULL, "ADCDAT Mux"},
1925         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1926         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1927         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1928         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1929         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1930         {"AIF2TX", NULL, "ADCDAT Mux"},
1931
1932         {"SDWTX", NULL, "PLL2B"},
1933         {"SDWTX", NULL, "PLL2F"},
1934         {"SDWTX", NULL, "ADCDAT Mux"},
1935
1936         {"IF1 DAC1 L", NULL, "AIF1RX"},
1937         {"IF1 DAC1 L", NULL, "I2S1"},
1938         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1939         {"IF1 DAC1 R", NULL, "AIF1RX"},
1940         {"IF1 DAC1 R", NULL, "I2S1"},
1941         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1942
1943         {"SOUND DAC L", NULL, "SDWRX"},
1944         {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1945         {"SOUND DAC L", NULL, "PLL2B"},
1946         {"SOUND DAC L", NULL, "PLL2F"},
1947         {"SOUND DAC R", NULL, "SDWRX"},
1948         {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1949         {"SOUND DAC R", NULL, "PLL2B"},
1950         {"SOUND DAC R", NULL, "PLL2F"},
1951
1952         {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1953         {"DAC L Mux", "SOUND", "SOUND DAC L"},
1954         {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1955         {"DAC R Mux", "SOUND", "SOUND DAC R"},
1956
1957         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1958         {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1959         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1960         {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1961
1962         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1963         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1964
1965         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1966         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1967
1968         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1969         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1970         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1971         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1972
1973         {"DAC L1", NULL, "DAC L1 Source"},
1974         {"DAC R1", NULL, "DAC R1 Source"},
1975
1976         {"DAC L1", NULL, "DAC 1 Clock"},
1977         {"DAC R1", NULL, "DAC 1 Clock"},
1978
1979         {"HP Amp", NULL, "DAC L1"},
1980         {"HP Amp", NULL, "DAC R1"},
1981         {"HP Amp", NULL, "HP Amp L"},
1982         {"HP Amp", NULL, "HP Amp R"},
1983         {"HP Amp", NULL, "Capless"},
1984         {"HP Amp", NULL, "Charge Pump"},
1985         {"HP Amp", NULL, "CLKDET SYS"},
1986         {"HP Amp", NULL, "Vref1"},
1987         {"HPOL Playback", "Switch", "HP Amp"},
1988         {"HPOR Playback", "Switch", "HP Amp"},
1989         {"HPOL", NULL, "HPOL Playback"},
1990         {"HPOR", NULL, "HPOR Playback"},
1991 };
1992
1993 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1994                 unsigned int rx_mask, int slots, int slot_width)
1995 {
1996         struct snd_soc_component *component = dai->component;
1997         unsigned int cl, val = 0;
1998
1999         if (tx_mask || rx_mask)
2000                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2001                         RT5682_TDM_EN, RT5682_TDM_EN);
2002         else
2003                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2004                         RT5682_TDM_EN, 0);
2005
2006         switch (slots) {
2007         case 4:
2008                 val |= RT5682_TDM_TX_CH_4;
2009                 val |= RT5682_TDM_RX_CH_4;
2010                 break;
2011         case 6:
2012                 val |= RT5682_TDM_TX_CH_6;
2013                 val |= RT5682_TDM_RX_CH_6;
2014                 break;
2015         case 8:
2016                 val |= RT5682_TDM_TX_CH_8;
2017                 val |= RT5682_TDM_RX_CH_8;
2018                 break;
2019         case 2:
2020                 break;
2021         default:
2022                 return -EINVAL;
2023         }
2024
2025         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2026                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2027
2028         switch (slot_width) {
2029         case 8:
2030                 if (tx_mask || rx_mask)
2031                         return -EINVAL;
2032                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2033                 break;
2034         case 16:
2035                 val = RT5682_TDM_CL_16;
2036                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2037                 break;
2038         case 20:
2039                 val = RT5682_TDM_CL_20;
2040                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2041                 break;
2042         case 24:
2043                 val = RT5682_TDM_CL_24;
2044                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2045                 break;
2046         case 32:
2047                 val = RT5682_TDM_CL_32;
2048                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2049                 break;
2050         default:
2051                 return -EINVAL;
2052         }
2053
2054         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2055                 RT5682_TDM_CL_MASK, val);
2056         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2057                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2058
2059         return 0;
2060 }
2061
2062 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2063                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2064 {
2065         struct snd_soc_component *component = dai->component;
2066         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2067         unsigned int len_1 = 0, len_2 = 0;
2068         int pre_div, frame_size;
2069
2070         rt5682->lrck[dai->id] = params_rate(params);
2071         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2072
2073         frame_size = snd_soc_params_to_frame_size(params);
2074         if (frame_size < 0) {
2075                 dev_err(component->dev, "Unsupported frame size: %d\n",
2076                         frame_size);
2077                 return -EINVAL;
2078         }
2079
2080         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2081                 rt5682->lrck[dai->id], pre_div, dai->id);
2082
2083         switch (params_width(params)) {
2084         case 16:
2085                 break;
2086         case 20:
2087                 len_1 |= RT5682_I2S1_DL_20;
2088                 len_2 |= RT5682_I2S2_DL_20;
2089                 break;
2090         case 24:
2091                 len_1 |= RT5682_I2S1_DL_24;
2092                 len_2 |= RT5682_I2S2_DL_24;
2093                 break;
2094         case 32:
2095                 len_1 |= RT5682_I2S1_DL_32;
2096                 len_2 |= RT5682_I2S2_DL_24;
2097                 break;
2098         case 8:
2099                 len_1 |= RT5682_I2S2_DL_8;
2100                 len_2 |= RT5682_I2S2_DL_8;
2101                 break;
2102         default:
2103                 return -EINVAL;
2104         }
2105
2106         switch (dai->id) {
2107         case RT5682_AIF1:
2108                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2109                         RT5682_I2S1_DL_MASK, len_1);
2110                 if (rt5682->master[RT5682_AIF1]) {
2111                         snd_soc_component_update_bits(component,
2112                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2113                                 RT5682_I2S_CLK_SRC_MASK,
2114                                 pre_div << RT5682_I2S_M_DIV_SFT |
2115                                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2116                 }
2117                 if (params_channels(params) == 1) /* mono mode */
2118                         snd_soc_component_update_bits(component,
2119                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2120                                 RT5682_I2S1_MONO_EN);
2121                 else
2122                         snd_soc_component_update_bits(component,
2123                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2124                                 RT5682_I2S1_MONO_DIS);
2125                 break;
2126         case RT5682_AIF2:
2127                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2128                         RT5682_I2S2_DL_MASK, len_2);
2129                 if (rt5682->master[RT5682_AIF2]) {
2130                         snd_soc_component_update_bits(component,
2131                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2132                                 pre_div << RT5682_I2S2_M_PD_SFT);
2133                 }
2134                 if (params_channels(params) == 1) /* mono mode */
2135                         snd_soc_component_update_bits(component,
2136                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2137                                 RT5682_I2S2_MONO_EN);
2138                 else
2139                         snd_soc_component_update_bits(component,
2140                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2141                                 RT5682_I2S2_MONO_DIS);
2142                 break;
2143         default:
2144                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2145                 return -EINVAL;
2146         }
2147
2148         return 0;
2149 }
2150
2151 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2152 {
2153         struct snd_soc_component *component = dai->component;
2154         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2155         unsigned int reg_val = 0, tdm_ctrl = 0;
2156
2157         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2158         case SND_SOC_DAIFMT_CBM_CFM:
2159                 rt5682->master[dai->id] = 1;
2160                 break;
2161         case SND_SOC_DAIFMT_CBS_CFS:
2162                 rt5682->master[dai->id] = 0;
2163                 break;
2164         default:
2165                 return -EINVAL;
2166         }
2167
2168         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2169         case SND_SOC_DAIFMT_NB_NF:
2170                 break;
2171         case SND_SOC_DAIFMT_IB_NF:
2172                 reg_val |= RT5682_I2S_BP_INV;
2173                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2174                 break;
2175         case SND_SOC_DAIFMT_NB_IF:
2176                 if (dai->id == RT5682_AIF1)
2177                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2178                 else
2179                         return -EINVAL;
2180                 break;
2181         case SND_SOC_DAIFMT_IB_IF:
2182                 if (dai->id == RT5682_AIF1)
2183                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2184                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2185                 else
2186                         return -EINVAL;
2187                 break;
2188         default:
2189                 return -EINVAL;
2190         }
2191
2192         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2193         case SND_SOC_DAIFMT_I2S:
2194                 break;
2195         case SND_SOC_DAIFMT_LEFT_J:
2196                 reg_val |= RT5682_I2S_DF_LEFT;
2197                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2198                 break;
2199         case SND_SOC_DAIFMT_DSP_A:
2200                 reg_val |= RT5682_I2S_DF_PCM_A;
2201                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2202                 break;
2203         case SND_SOC_DAIFMT_DSP_B:
2204                 reg_val |= RT5682_I2S_DF_PCM_B;
2205                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2206                 break;
2207         default:
2208                 return -EINVAL;
2209         }
2210
2211         switch (dai->id) {
2212         case RT5682_AIF1:
2213                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2214                         RT5682_I2S_DF_MASK, reg_val);
2215                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2216                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2217                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2218                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2219                         tdm_ctrl | rt5682->master[dai->id]);
2220                 break;
2221         case RT5682_AIF2:
2222                 if (rt5682->master[dai->id] == 0)
2223                         reg_val |= RT5682_I2S2_MS_S;
2224                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2225                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2226                         RT5682_I2S_DF_MASK, reg_val);
2227                 break;
2228         default:
2229                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2230                 return -EINVAL;
2231         }
2232         return 0;
2233 }
2234
2235 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2236                 int clk_id, int source, unsigned int freq, int dir)
2237 {
2238         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2239         unsigned int reg_val = 0, src = 0;
2240
2241         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2242                 return 0;
2243
2244         switch (clk_id) {
2245         case RT5682_SCLK_S_MCLK:
2246                 reg_val |= RT5682_SCLK_SRC_MCLK;
2247                 src = RT5682_CLK_SRC_MCLK;
2248                 break;
2249         case RT5682_SCLK_S_PLL1:
2250                 reg_val |= RT5682_SCLK_SRC_PLL1;
2251                 src = RT5682_CLK_SRC_PLL1;
2252                 break;
2253         case RT5682_SCLK_S_PLL2:
2254                 reg_val |= RT5682_SCLK_SRC_PLL2;
2255                 src = RT5682_CLK_SRC_PLL2;
2256                 break;
2257         case RT5682_SCLK_S_RCCLK:
2258                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2259                 src = RT5682_CLK_SRC_RCCLK;
2260                 break;
2261         default:
2262                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2263                 return -EINVAL;
2264         }
2265         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2266                 RT5682_SCLK_SRC_MASK, reg_val);
2267
2268         if (rt5682->master[RT5682_AIF2]) {
2269                 snd_soc_component_update_bits(component,
2270                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2271                         src << RT5682_I2S2_SRC_SFT);
2272         }
2273
2274         rt5682->sysclk = freq;
2275         rt5682->sysclk_src = clk_id;
2276
2277         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2278                 freq, clk_id);
2279
2280         return 0;
2281 }
2282
2283 static int rt5682_set_component_pll(struct snd_soc_component *component,
2284                 int pll_id, int source, unsigned int freq_in,
2285                 unsigned int freq_out)
2286 {
2287         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2288         struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2289         unsigned int pll2_fout1, pll2_ps_val;
2290         int ret;
2291
2292         if (source == rt5682->pll_src[pll_id] &&
2293             freq_in == rt5682->pll_in[pll_id] &&
2294             freq_out == rt5682->pll_out[pll_id])
2295                 return 0;
2296
2297         if (!freq_in || !freq_out) {
2298                 dev_dbg(component->dev, "PLL disabled\n");
2299
2300                 rt5682->pll_in[pll_id] = 0;
2301                 rt5682->pll_out[pll_id] = 0;
2302                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2303                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2304                 return 0;
2305         }
2306
2307         if (pll_id == RT5682_PLL2) {
2308                 switch (source) {
2309                 case RT5682_PLL2_S_MCLK:
2310                         snd_soc_component_update_bits(component,
2311                                 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2312                                 RT5682_PLL2_SRC_MCLK);
2313                         break;
2314                 default:
2315                         dev_err(component->dev, "Unknown PLL2 Source %d\n",
2316                                 source);
2317                         return -EINVAL;
2318                 }
2319
2320                 /**
2321                  * PLL2 concatenates 2 PLL units.
2322                  * We suggest the Fout of the front PLL is 3.84MHz.
2323                  */
2324                 pll2_fout1 = 3840000;
2325                 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2326                 if (ret < 0) {
2327                         dev_err(component->dev, "Unsupport input clock %d\n",
2328                                 freq_in);
2329                         return ret;
2330                 }
2331                 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2332                         freq_in, pll2_fout1,
2333                         pll2f_code.m_bp,
2334                         (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2335                         pll2f_code.n_code, pll2f_code.k_code);
2336
2337                 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2338                 if (ret < 0) {
2339                         dev_err(component->dev, "Unsupport input clock %d\n",
2340                                 pll2_fout1);
2341                         return ret;
2342                 }
2343                 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2344                         pll2_fout1, freq_out,
2345                         pll2b_code.m_bp,
2346                         (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2347                         pll2b_code.n_code, pll2b_code.k_code);
2348
2349                 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2350                         pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2351                         pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2352                         pll2b_code.m_code);
2353                 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2354                         pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2355                         pll2b_code.n_code);
2356                 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2357                         pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2358
2359                 if (freq_out == 22579200)
2360                         pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2361                 else
2362                         pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2363                 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2364                         RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2365                         RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2366                         pll2_ps_val |
2367                         (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2368                         (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2369                         0xf);
2370         } else {
2371                 switch (source) {
2372                 case RT5682_PLL1_S_MCLK:
2373                         snd_soc_component_update_bits(component,
2374                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2375                                 RT5682_PLL1_SRC_MCLK);
2376                         break;
2377                 case RT5682_PLL1_S_BCLK1:
2378                         snd_soc_component_update_bits(component,
2379                                 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2380                                 RT5682_PLL1_SRC_BCLK1);
2381                         break;
2382                 default:
2383                         dev_err(component->dev, "Unknown PLL1 Source %d\n",
2384                                 source);
2385                         return -EINVAL;
2386                 }
2387
2388                 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2389                 if (ret < 0) {
2390                         dev_err(component->dev, "Unsupport input clock %d\n",
2391                                 freq_in);
2392                         return ret;
2393                 }
2394
2395                 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2396                         pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2397                         pll_code.n_code, pll_code.k_code);
2398
2399                 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2400                         pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2401                 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2402                     (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2403                     pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2404         }
2405
2406         rt5682->pll_in[pll_id] = freq_in;
2407         rt5682->pll_out[pll_id] = freq_out;
2408         rt5682->pll_src[pll_id] = source;
2409
2410         return 0;
2411 }
2412
2413 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2414 {
2415         struct snd_soc_component *component = dai->component;
2416         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2417
2418         rt5682->bclk[dai->id] = ratio;
2419
2420         switch (ratio) {
2421         case 256:
2422                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2423                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2424                 break;
2425         case 128:
2426                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2427                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2428                 break;
2429         case 64:
2430                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2431                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2432                 break;
2433         case 32:
2434                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2435                         RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2436                 break;
2437         default:
2438                 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2439                 return -EINVAL;
2440         }
2441
2442         return 0;
2443 }
2444
2445 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2446 {
2447         struct snd_soc_component *component = dai->component;
2448         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2449
2450         rt5682->bclk[dai->id] = ratio;
2451
2452         switch (ratio) {
2453         case 64:
2454                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2455                         RT5682_I2S2_BCLK_MS2_MASK,
2456                         RT5682_I2S2_BCLK_MS2_64);
2457                 break;
2458         case 32:
2459                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2460                         RT5682_I2S2_BCLK_MS2_MASK,
2461                         RT5682_I2S2_BCLK_MS2_32);
2462                 break;
2463         default:
2464                 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2465                 return -EINVAL;
2466         }
2467
2468         return 0;
2469 }
2470
2471 static int rt5682_set_bias_level(struct snd_soc_component *component,
2472                 enum snd_soc_bias_level level)
2473 {
2474         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2475
2476         switch (level) {
2477         case SND_SOC_BIAS_PREPARE:
2478                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2479                         RT5682_PWR_BG, RT5682_PWR_BG);
2480                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2481                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2482                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2483                 break;
2484
2485         case SND_SOC_BIAS_STANDBY:
2486                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2487                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2488                 break;
2489         case SND_SOC_BIAS_OFF:
2490                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2491                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2492                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2493                         RT5682_PWR_BG, 0);
2494                 break;
2495         case SND_SOC_BIAS_ON:
2496                 break;
2497         }
2498
2499         return 0;
2500 }
2501
2502 #ifdef CONFIG_COMMON_CLK
2503 #define CLK_PLL2_FIN 48000000
2504 #define CLK_48 48000
2505 #define CLK_44 44100
2506
2507 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2508 {
2509         if (!rt5682->master[RT5682_AIF1]) {
2510                 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2511                 return false;
2512         }
2513         return true;
2514 }
2515
2516 static int rt5682_wclk_prepare(struct clk_hw *hw)
2517 {
2518         struct rt5682_priv *rt5682 =
2519                 container_of(hw, struct rt5682_priv,
2520                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2521         struct snd_soc_component *component = rt5682->component;
2522         struct snd_soc_dapm_context *dapm =
2523                         snd_soc_component_get_dapm(component);
2524
2525         if (!rt5682_clk_check(rt5682))
2526                 return -EINVAL;
2527
2528         snd_soc_dapm_mutex_lock(dapm);
2529
2530         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2531         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2532                                 RT5682_PWR_MB, RT5682_PWR_MB);
2533
2534         snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2535         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2536                         RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2537                         RT5682_PWR_VREF2);
2538         usleep_range(55000, 60000);
2539         snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2540                         RT5682_PWR_FV2, RT5682_PWR_FV2);
2541
2542         snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2543         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2544         snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2545         snd_soc_dapm_sync_unlocked(dapm);
2546
2547         snd_soc_dapm_mutex_unlock(dapm);
2548
2549         return 0;
2550 }
2551
2552 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2553 {
2554         struct rt5682_priv *rt5682 =
2555                 container_of(hw, struct rt5682_priv,
2556                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2557         struct snd_soc_component *component = rt5682->component;
2558         struct snd_soc_dapm_context *dapm =
2559                         snd_soc_component_get_dapm(component);
2560
2561         if (!rt5682_clk_check(rt5682))
2562                 return;
2563
2564         snd_soc_dapm_mutex_lock(dapm);
2565
2566         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2567         snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2568         if (!rt5682->jack_type)
2569                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2570                                 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2571                                 RT5682_PWR_MB, 0);
2572
2573         snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2574         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2575         snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2576         snd_soc_dapm_sync_unlocked(dapm);
2577
2578         snd_soc_dapm_mutex_unlock(dapm);
2579 }
2580
2581 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2582                                              unsigned long parent_rate)
2583 {
2584         struct rt5682_priv *rt5682 =
2585                 container_of(hw, struct rt5682_priv,
2586                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2587         struct snd_soc_component *component = rt5682->component;
2588         const char * const clk_name = clk_hw_get_name(hw);
2589
2590         if (!rt5682_clk_check(rt5682))
2591                 return 0;
2592         /*
2593          * Only accept to set wclk rate to 44.1k or 48kHz.
2594          */
2595         if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2596             rt5682->lrck[RT5682_AIF1] != CLK_44) {
2597                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2598                         __func__, clk_name, CLK_44, CLK_48);
2599                 return 0;
2600         }
2601
2602         return rt5682->lrck[RT5682_AIF1];
2603 }
2604
2605 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2606                                    unsigned long *parent_rate)
2607 {
2608         struct rt5682_priv *rt5682 =
2609                 container_of(hw, struct rt5682_priv,
2610                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2611         struct snd_soc_component *component = rt5682->component;
2612         const char * const clk_name = clk_hw_get_name(hw);
2613
2614         if (!rt5682_clk_check(rt5682))
2615                 return -EINVAL;
2616         /*
2617          * Only accept to set wclk rate to 44.1k or 48kHz.
2618          * It will force to 48kHz if not both.
2619          */
2620         if (rate != CLK_48 && rate != CLK_44) {
2621                 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2622                         __func__, clk_name, CLK_44, CLK_48);
2623                 rate = CLK_48;
2624         }
2625
2626         return rate;
2627 }
2628
2629 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2630                                 unsigned long parent_rate)
2631 {
2632         struct rt5682_priv *rt5682 =
2633                 container_of(hw, struct rt5682_priv,
2634                              dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2635         struct snd_soc_component *component = rt5682->component;
2636         struct clk *parent_clk;
2637         const char * const clk_name = clk_hw_get_name(hw);
2638         int pre_div;
2639         unsigned int clk_pll2_out;
2640
2641         if (!rt5682_clk_check(rt5682))
2642                 return -EINVAL;
2643
2644         /*
2645          * Whether the wclk's parent clk (mclk) exists or not, please ensure
2646          * it is fixed or set to 48MHz before setting wclk rate. It's a
2647          * temporary limitation. Only accept 48MHz clk as the clk provider.
2648          *
2649          * It will set the codec anyway by assuming mclk is 48MHz.
2650          */
2651         parent_clk = clk_get_parent(hw->clk);
2652         if (!parent_clk)
2653                 dev_warn(component->dev,
2654                         "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2655                         CLK_PLL2_FIN);
2656
2657         if (parent_rate != CLK_PLL2_FIN)
2658                 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2659                         clk_name, CLK_PLL2_FIN);
2660
2661         /*
2662          * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2663          * PLL2 is needed.
2664          */
2665         clk_pll2_out = rate * 512;
2666         rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2667                 CLK_PLL2_FIN, clk_pll2_out);
2668
2669         rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2670                 clk_pll2_out, SND_SOC_CLOCK_IN);
2671
2672         rt5682->lrck[RT5682_AIF1] = rate;
2673
2674         pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2675
2676         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2677                 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2678                 pre_div << RT5682_I2S_M_DIV_SFT |
2679                 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2680
2681         return 0;
2682 }
2683
2684 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2685                                              unsigned long parent_rate)
2686 {
2687         struct rt5682_priv *rt5682 =
2688                 container_of(hw, struct rt5682_priv,
2689                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2690         struct snd_soc_component *component = rt5682->component;
2691         unsigned int bclks_per_wclk;
2692
2693         bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2694
2695         switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2696         case RT5682_TDM_BCLK_MS1_256:
2697                 return parent_rate * 256;
2698         case RT5682_TDM_BCLK_MS1_128:
2699                 return parent_rate * 128;
2700         case RT5682_TDM_BCLK_MS1_64:
2701                 return parent_rate * 64;
2702         case RT5682_TDM_BCLK_MS1_32:
2703                 return parent_rate * 32;
2704         default:
2705                 return 0;
2706         }
2707 }
2708
2709 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2710                                             unsigned long parent_rate)
2711 {
2712         unsigned long factor;
2713
2714         factor = rate / parent_rate;
2715         if (factor < 64)
2716                 return 32;
2717         else if (factor < 128)
2718                 return 64;
2719         else if (factor < 256)
2720                 return 128;
2721         else
2722                 return 256;
2723 }
2724
2725 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2726                                    unsigned long *parent_rate)
2727 {
2728         struct rt5682_priv *rt5682 =
2729                 container_of(hw, struct rt5682_priv,
2730                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2731         unsigned long factor;
2732
2733         if (!*parent_rate || !rt5682_clk_check(rt5682))
2734                 return -EINVAL;
2735
2736         /*
2737          * BCLK rates are set as a multiplier of WCLK in HW.
2738          * We don't allow changing the parent WCLK. We just do
2739          * some rounding down based on the parent WCLK rate
2740          * and find the appropriate multiplier of BCLK to
2741          * get the rounded down BCLK value.
2742          */
2743         factor = rt5682_bclk_get_factor(rate, *parent_rate);
2744
2745         return *parent_rate * factor;
2746 }
2747
2748 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2749                                 unsigned long parent_rate)
2750 {
2751         struct rt5682_priv *rt5682 =
2752                 container_of(hw, struct rt5682_priv,
2753                              dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2754         struct snd_soc_component *component = rt5682->component;
2755         struct snd_soc_dai *dai = NULL;
2756         unsigned long factor;
2757
2758         if (!rt5682_clk_check(rt5682))
2759                 return -EINVAL;
2760
2761         factor = rt5682_bclk_get_factor(rate, parent_rate);
2762
2763         for_each_component_dais(component, dai)
2764                 if (dai->id == RT5682_AIF1)
2765                         break;
2766         if (!dai) {
2767                 dev_err(component->dev, "dai %d not found in component\n",
2768                         RT5682_AIF1);
2769                 return -ENODEV;
2770         }
2771
2772         return rt5682_set_bclk1_ratio(dai, factor);
2773 }
2774
2775 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2776         [RT5682_DAI_WCLK_IDX] = {
2777                 .prepare = rt5682_wclk_prepare,
2778                 .unprepare = rt5682_wclk_unprepare,
2779                 .recalc_rate = rt5682_wclk_recalc_rate,
2780                 .round_rate = rt5682_wclk_round_rate,
2781                 .set_rate = rt5682_wclk_set_rate,
2782         },
2783         [RT5682_DAI_BCLK_IDX] = {
2784                 .recalc_rate = rt5682_bclk_recalc_rate,
2785                 .round_rate = rt5682_bclk_round_rate,
2786                 .set_rate = rt5682_bclk_set_rate,
2787         },
2788 };
2789
2790 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2791 {
2792         struct device *dev = component->dev;
2793         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2794         struct rt5682_platform_data *pdata = &rt5682->pdata;
2795         struct clk_hw *dai_clk_hw;
2796         int i, ret;
2797
2798         for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2799                 struct clk_init_data init = { };
2800
2801                 dai_clk_hw = &rt5682->dai_clks_hw[i];
2802
2803                 switch (i) {
2804                 case RT5682_DAI_WCLK_IDX:
2805                         /* Make MCLK the parent of WCLK */
2806                         if (rt5682->mclk) {
2807                                 init.parent_data = &(struct clk_parent_data){
2808                                         .fw_name = "mclk",
2809                                 };
2810                                 init.num_parents = 1;
2811                         }
2812                         break;
2813                 case RT5682_DAI_BCLK_IDX:
2814                         /* Make WCLK the parent of BCLK */
2815                         init.parent_hws = &(const struct clk_hw *){
2816                                 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]
2817                         };
2818                         init.num_parents = 1;
2819                         break;
2820                 default:
2821                         dev_err(dev, "Invalid clock index\n");
2822                         return -EINVAL;
2823                 }
2824
2825                 init.name = pdata->dai_clk_names[i];
2826                 init.ops = &rt5682_dai_clk_ops[i];
2827                 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2828                 dai_clk_hw->init = &init;
2829
2830                 ret = devm_clk_hw_register(dev, dai_clk_hw);
2831                 if (ret) {
2832                         dev_warn(dev, "Failed to register %s: %d\n",
2833                                  init.name, ret);
2834                         return ret;
2835                 }
2836
2837                 if (dev->of_node) {
2838                         devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2839                                                     dai_clk_hw);
2840                 } else {
2841                         ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2842                                                           init.name,
2843                                                           dev_name(dev));
2844                         if (ret)
2845                                 return ret;
2846                 }
2847         }
2848
2849         return 0;
2850 }
2851 #endif /* CONFIG_COMMON_CLK */
2852
2853 static int rt5682_probe(struct snd_soc_component *component)
2854 {
2855         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2856         struct sdw_slave *slave;
2857         unsigned long time;
2858         struct snd_soc_dapm_context *dapm = &component->dapm;
2859
2860 #ifdef CONFIG_COMMON_CLK
2861         int ret;
2862 #endif
2863         rt5682->component = component;
2864
2865         if (rt5682->is_sdw) {
2866                 slave = rt5682->slave;
2867                 time = wait_for_completion_timeout(
2868                         &slave->initialization_complete,
2869                         msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2870                 if (!time) {
2871                         dev_err(&slave->dev, "Initialization not complete, timed out\n");
2872                         return -ETIMEDOUT;
2873                 }
2874         } else {
2875 #ifdef CONFIG_COMMON_CLK
2876                 /* Check if MCLK provided */
2877                 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2878                 if (IS_ERR(rt5682->mclk)) {
2879                         if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2880                                 ret = PTR_ERR(rt5682->mclk);
2881                                 return ret;
2882                         }
2883                         rt5682->mclk = NULL;
2884                 }
2885
2886                 /* Register CCF DAI clock control */
2887                 ret = rt5682_register_dai_clks(component);
2888                 if (ret)
2889                         return ret;
2890
2891                 /* Initial setup for CCF */
2892                 rt5682->lrck[RT5682_AIF1] = CLK_48;
2893 #endif
2894         }
2895
2896         snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2897         snd_soc_dapm_disable_pin(dapm, "Vref2");
2898         snd_soc_dapm_sync(dapm);
2899         return 0;
2900 }
2901
2902 static void rt5682_remove(struct snd_soc_component *component)
2903 {
2904         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2905
2906         rt5682_reset(rt5682);
2907 }
2908
2909 #ifdef CONFIG_PM
2910 static int rt5682_suspend(struct snd_soc_component *component)
2911 {
2912         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2913
2914         regcache_cache_only(rt5682->regmap, true);
2915         regcache_mark_dirty(rt5682->regmap);
2916         return 0;
2917 }
2918
2919 static int rt5682_resume(struct snd_soc_component *component)
2920 {
2921         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2922
2923         regcache_cache_only(rt5682->regmap, false);
2924         regcache_sync(rt5682->regmap);
2925
2926         mod_delayed_work(system_power_efficient_wq,
2927                 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2928
2929         return 0;
2930 }
2931 #else
2932 #define rt5682_suspend NULL
2933 #define rt5682_resume NULL
2934 #endif
2935
2936 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2937         .hw_params = rt5682_hw_params,
2938         .set_fmt = rt5682_set_dai_fmt,
2939         .set_tdm_slot = rt5682_set_tdm_slot,
2940         .set_bclk_ratio = rt5682_set_bclk1_ratio,
2941 };
2942 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2943
2944 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2945         .hw_params = rt5682_hw_params,
2946         .set_fmt = rt5682_set_dai_fmt,
2947         .set_bclk_ratio = rt5682_set_bclk2_ratio,
2948 };
2949 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2950
2951 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2952         .probe = rt5682_probe,
2953         .remove = rt5682_remove,
2954         .suspend = rt5682_suspend,
2955         .resume = rt5682_resume,
2956         .set_bias_level = rt5682_set_bias_level,
2957         .controls = rt5682_snd_controls,
2958         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2959         .dapm_widgets = rt5682_dapm_widgets,
2960         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2961         .dapm_routes = rt5682_dapm_routes,
2962         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2963         .set_sysclk = rt5682_set_component_sysclk,
2964         .set_pll = rt5682_set_component_pll,
2965         .set_jack = rt5682_set_jack_detect,
2966         .use_pmdown_time        = 1,
2967         .endianness             = 1,
2968         .non_legacy_dai_naming  = 1,
2969 };
2970 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2971
2972 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2973 {
2974
2975         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2976                 &rt5682->pdata.dmic1_data_pin);
2977         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2978                 &rt5682->pdata.dmic1_clk_pin);
2979         device_property_read_u32(dev, "realtek,jd-src",
2980                 &rt5682->pdata.jd_src);
2981         device_property_read_u32(dev, "realtek,btndet-delay",
2982                 &rt5682->pdata.btndet_delay);
2983         device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2984                 &rt5682->pdata.dmic_clk_rate);
2985         device_property_read_u32(dev, "realtek,dmic-delay-ms",
2986                 &rt5682->pdata.dmic_delay);
2987
2988         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2989                 "realtek,ldo1-en-gpios", 0);
2990
2991         if (device_property_read_string_array(dev, "clock-output-names",
2992                                               rt5682->pdata.dai_clk_names,
2993                                               RT5682_DAI_NUM_CLKS) < 0)
2994                 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2995                          rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
2996                          rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
2997
2998         return 0;
2999 }
3000 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3001
3002 void rt5682_calibrate(struct rt5682_priv *rt5682)
3003 {
3004         int value, count;
3005
3006         mutex_lock(&rt5682->calibrate_mutex);
3007
3008         rt5682_reset(rt5682);
3009         regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3010         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3011         usleep_range(15000, 20000);
3012         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3013         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3014         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3015         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3016         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3017         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3018         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3019         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3020         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3021         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3022         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3023         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3024         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3025         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3026         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3027
3028         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3029
3030         for (count = 0; count < 60; count++) {
3031                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3032                 if (!(value & 0x8000))
3033                         break;
3034
3035                 usleep_range(10000, 10005);
3036         }
3037
3038         if (count >= 60)
3039                 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3040
3041         /* restore settings */
3042         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3043         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3044         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3045         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3046         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3047         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3048         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3049         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3050
3051         mutex_unlock(&rt5682->calibrate_mutex);
3052 }
3053 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3054
3055 MODULE_DESCRIPTION("ASoC RT5682 driver");
3056 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3057 MODULE_LICENSE("GPL v2");