1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682-sdw.c -- RT5682 ALSA SoC audio component driver
5 // Copyright 2019 Realtek Semiconductor Corp.
6 // Author: Oder Chiou <oder_chiou@realtek.com>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/acpi.h>
15 #include <linux/gpio.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/mutex.h>
20 #include <linux/soundwire/sdw.h>
21 #include <linux/soundwire/sdw_type.h>
22 #include <linux/soundwire/sdw_registers.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/jack.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
34 #define RT5682_SDW_ADDR_L 0x3000
35 #define RT5682_SDW_ADDR_H 0x3001
36 #define RT5682_SDW_DATA_L 0x3004
37 #define RT5682_SDW_DATA_H 0x3005
38 #define RT5682_SDW_CMD 0x3008
40 static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
42 struct device *dev = context;
43 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
44 unsigned int data_l, data_h;
46 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
47 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
48 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
49 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
50 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
52 *val = (data_h << 8) | data_l;
54 dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
59 static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
61 struct device *dev = context;
62 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
64 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
65 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
66 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
67 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
68 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
70 dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
75 static const struct regmap_config rt5682_sdw_indirect_regmap = {
78 .max_register = RT5682_I2C_MODE,
79 .volatile_reg = rt5682_volatile_register,
80 .readable_reg = rt5682_readable_register,
81 .cache_type = REGCACHE_RBTREE,
82 .reg_defaults = rt5682_reg,
83 .num_reg_defaults = RT5682_REG_NUM,
84 .use_single_read = true,
85 .use_single_write = true,
86 .reg_read = rt5682_sdw_read,
87 .reg_write = rt5682_sdw_write,
90 struct sdw_stream_data {
91 struct sdw_stream_runtime *sdw_stream;
94 static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
97 struct sdw_stream_data *stream;
102 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
106 stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream;
108 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
109 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
110 dai->playback_dma_data = stream;
112 dai->capture_dma_data = stream;
117 static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
118 struct snd_soc_dai *dai)
120 struct sdw_stream_data *stream;
122 stream = snd_soc_dai_get_dma_data(dai, substream);
123 snd_soc_dai_set_dma_data(dai, substream, NULL);
127 static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
128 struct snd_pcm_hw_params *params,
129 struct snd_soc_dai *dai)
131 struct snd_soc_component *component = dai->component;
132 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
133 struct sdw_stream_config stream_config;
134 struct sdw_port_config port_config;
135 enum sdw_data_direction direction;
136 struct sdw_stream_data *stream;
137 int retval, port, num_channels;
138 unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
140 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
142 stream = snd_soc_dai_get_dma_data(dai, substream);
149 /* SoundWire specific configuration */
150 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
151 direction = SDW_DATA_DIR_RX;
154 direction = SDW_DATA_DIR_TX;
158 stream_config.frame_rate = params_rate(params);
159 stream_config.ch_count = params_channels(params);
160 stream_config.bps = snd_pcm_format_width(params_format(params));
161 stream_config.direction = direction;
163 num_channels = params_channels(params);
164 port_config.ch_mask = (1 << (num_channels)) - 1;
165 port_config.num = port;
167 retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
168 &port_config, 1, stream->sdw_stream);
170 dev_err(dai->dev, "Unable to configure port\n");
174 switch (params_rate(params)) {
176 val_p = RT5682_SDW_REF_1_48K;
177 val_c = RT5682_SDW_REF_2_48K;
180 val_p = RT5682_SDW_REF_1_96K;
181 val_c = RT5682_SDW_REF_2_96K;
184 val_p = RT5682_SDW_REF_1_192K;
185 val_c = RT5682_SDW_REF_2_192K;
188 val_p = RT5682_SDW_REF_1_32K;
189 val_c = RT5682_SDW_REF_2_32K;
192 val_p = RT5682_SDW_REF_1_24K;
193 val_c = RT5682_SDW_REF_2_24K;
196 val_p = RT5682_SDW_REF_1_16K;
197 val_c = RT5682_SDW_REF_2_16K;
200 val_p = RT5682_SDW_REF_1_12K;
201 val_c = RT5682_SDW_REF_2_12K;
204 val_p = RT5682_SDW_REF_1_8K;
205 val_c = RT5682_SDW_REF_2_8K;
208 val_p = RT5682_SDW_REF_1_44K;
209 val_c = RT5682_SDW_REF_2_44K;
212 val_p = RT5682_SDW_REF_1_88K;
213 val_c = RT5682_SDW_REF_2_88K;
216 val_p = RT5682_SDW_REF_1_176K;
217 val_c = RT5682_SDW_REF_2_176K;
220 val_p = RT5682_SDW_REF_1_22K;
221 val_c = RT5682_SDW_REF_2_22K;
224 val_p = RT5682_SDW_REF_1_11K;
225 val_c = RT5682_SDW_REF_2_11K;
231 if (params_rate(params) <= 48000) {
232 osr_p = RT5682_DAC_OSR_D_8;
233 osr_c = RT5682_ADC_OSR_D_8;
234 } else if (params_rate(params) <= 96000) {
235 osr_p = RT5682_DAC_OSR_D_4;
236 osr_c = RT5682_ADC_OSR_D_4;
238 osr_p = RT5682_DAC_OSR_D_2;
239 osr_c = RT5682_ADC_OSR_D_2;
242 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
243 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
244 RT5682_SDW_REF_1_MASK, val_p);
245 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
246 RT5682_DAC_OSR_MASK, osr_p);
248 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
249 RT5682_SDW_REF_2_MASK, val_c);
250 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
251 RT5682_ADC_OSR_MASK, osr_c);
257 static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
258 struct snd_soc_dai *dai)
260 struct snd_soc_component *component = dai->component;
261 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
262 struct sdw_stream_data *stream =
263 snd_soc_dai_get_dma_data(dai, substream);
268 sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream);
272 static struct snd_soc_dai_ops rt5682_sdw_ops = {
273 .hw_params = rt5682_sdw_hw_params,
274 .hw_free = rt5682_sdw_hw_free,
275 .set_stream = rt5682_set_sdw_stream,
276 .shutdown = rt5682_sdw_shutdown,
279 static struct snd_soc_dai_driver rt5682_dai[] = {
281 .name = "rt5682-aif1",
284 .stream_name = "AIF1 Playback",
287 .rates = RT5682_STEREO_RATES,
288 .formats = RT5682_FORMATS,
291 .stream_name = "AIF1 Capture",
294 .rates = RT5682_STEREO_RATES,
295 .formats = RT5682_FORMATS,
297 .ops = &rt5682_aif1_dai_ops,
300 .name = "rt5682-aif2",
303 .stream_name = "AIF2 Capture",
306 .rates = RT5682_STEREO_RATES,
307 .formats = RT5682_FORMATS,
309 .ops = &rt5682_aif2_dai_ops,
312 .name = "rt5682-sdw",
315 .stream_name = "SDW Playback",
318 .rates = RT5682_STEREO_RATES,
319 .formats = RT5682_FORMATS,
322 .stream_name = "SDW Capture",
325 .rates = RT5682_STEREO_RATES,
326 .formats = RT5682_FORMATS,
328 .ops = &rt5682_sdw_ops,
332 static int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
333 struct sdw_slave *slave)
335 struct rt5682_priv *rt5682;
338 rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
342 dev_set_drvdata(dev, rt5682);
343 rt5682->slave = slave;
344 rt5682->sdw_regmap = regmap;
345 rt5682->is_sdw = true;
347 rt5682->regmap = devm_regmap_init(dev, NULL, dev,
348 &rt5682_sdw_indirect_regmap);
349 if (IS_ERR(rt5682->regmap)) {
350 ret = PTR_ERR(rt5682->regmap);
351 dev_err(dev, "Failed to allocate register map: %d\n",
357 * Mark hw_init to false
358 * HW init will be performed when device reports present
360 rt5682->hw_init = false;
361 rt5682->first_hw_init = false;
363 mutex_init(&rt5682->calibrate_mutex);
364 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
365 rt5682_jack_detect_handler);
367 ret = devm_snd_soc_register_component(dev,
368 &rt5682_soc_component_dev,
369 rt5682_dai, ARRAY_SIZE(rt5682_dai));
370 dev_dbg(&slave->dev, "%s\n", __func__);
375 static int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
377 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
378 int ret = 0, loop = 10;
385 * PM runtime is only enabled when a Slave reports as Attached
387 if (!rt5682->first_hw_init) {
388 /* set autosuspend parameters */
389 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
390 pm_runtime_use_autosuspend(&slave->dev);
392 /* update count of parent 'active' children */
393 pm_runtime_set_active(&slave->dev);
395 /* make sure the device does not suspend immediately */
396 pm_runtime_mark_last_busy(&slave->dev);
398 pm_runtime_enable(&slave->dev);
401 pm_runtime_get_noresume(&slave->dev);
403 if (rt5682->first_hw_init) {
404 regcache_cache_only(rt5682->regmap, false);
405 regcache_cache_bypass(rt5682->regmap, true);
409 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
410 if (val == DEVICE_ID)
412 dev_warn(dev, "Device with ID register %x is not rt5682\n", val);
413 usleep_range(30000, 30005);
417 if (val != DEVICE_ID) {
418 dev_err(dev, "Device with ID register %x is not rt5682\n", val);
423 rt5682_calibrate(rt5682);
425 if (rt5682->first_hw_init) {
426 regcache_cache_bypass(rt5682->regmap, false);
427 regcache_mark_dirty(rt5682->regmap);
428 regcache_sync(rt5682->regmap);
430 /* volatile registers */
431 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
432 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
437 rt5682_apply_patch_list(rt5682, dev);
439 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
441 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
442 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
443 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
444 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
445 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
446 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
447 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
448 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
449 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
450 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
451 RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
454 regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
455 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
456 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
457 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
458 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
459 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
460 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
461 regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
462 RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
463 RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
465 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
466 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
467 regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd142);
468 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
469 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
470 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
471 regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
472 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
473 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
474 RT5682_POW_IRQ | RT5682_POW_JDH |
475 RT5682_POW_ANA, RT5682_POW_IRQ |
476 RT5682_POW_JDH | RT5682_POW_ANA);
477 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
478 RT5682_PWR_JDH, RT5682_PWR_JDH);
479 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
480 RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
481 RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
484 mod_delayed_work(system_power_efficient_wq,
485 &rt5682->jack_detect_work, msecs_to_jiffies(250));
487 /* Mark Slave initialization complete */
488 rt5682->hw_init = true;
489 rt5682->first_hw_init = true;
492 pm_runtime_mark_last_busy(&slave->dev);
493 pm_runtime_put_autosuspend(&slave->dev);
495 dev_dbg(&slave->dev, "%s hw_init complete: %d\n", __func__, ret);
500 static bool rt5682_sdw_readable_register(struct device *dev, unsigned int reg)
516 static const struct regmap_config rt5682_sdw_regmap = {
520 .max_register = RT5682_I2C_MODE,
521 .readable_reg = rt5682_sdw_readable_register,
522 .cache_type = REGCACHE_NONE,
523 .use_single_read = true,
524 .use_single_write = true,
527 static int rt5682_update_status(struct sdw_slave *slave,
528 enum sdw_slave_status status)
530 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
532 /* Update the status */
533 rt5682->status = status;
535 if (status == SDW_SLAVE_UNATTACHED)
536 rt5682->hw_init = false;
539 * Perform initialization only if slave status is present and
540 * hw_init flag is false
542 if (rt5682->hw_init || rt5682->status != SDW_SLAVE_ATTACHED)
545 /* perform I/O transfers required for Slave initialization */
546 return rt5682_io_init(&slave->dev, slave);
549 static int rt5682_read_prop(struct sdw_slave *slave)
551 struct sdw_slave_prop *prop = &slave->prop;
555 struct sdw_dpn_prop *dpn;
557 prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
559 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
561 prop->paging_support = false;
563 /* first we need to allocate memory for set bits in port lists */
564 prop->source_ports = 0x4; /* BITMAP: 00000100 */
565 prop->sink_ports = 0x2; /* BITMAP: 00000010 */
567 nval = hweight32(prop->source_ports);
568 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
569 sizeof(*prop->src_dpn_prop),
571 if (!prop->src_dpn_prop)
575 dpn = prop->src_dpn_prop;
576 addr = prop->source_ports;
577 for_each_set_bit(bit, &addr, 32) {
579 dpn[i].type = SDW_DPN_FULL;
580 dpn[i].simple_ch_prep_sm = true;
581 dpn[i].ch_prep_timeout = 10;
585 /* do this again for sink now */
586 nval = hweight32(prop->sink_ports);
587 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
588 sizeof(*prop->sink_dpn_prop),
590 if (!prop->sink_dpn_prop)
594 dpn = prop->sink_dpn_prop;
595 addr = prop->sink_ports;
596 for_each_set_bit(bit, &addr, 32) {
598 dpn[i].type = SDW_DPN_FULL;
599 dpn[i].simple_ch_prep_sm = true;
600 dpn[i].ch_prep_timeout = 10;
604 /* set the timeout values */
605 prop->clk_stop_timeout = 20;
608 prop->wake_capable = 1;
613 /* Bus clock frequency */
614 #define RT5682_CLK_FREQ_9600000HZ 9600000
615 #define RT5682_CLK_FREQ_12000000HZ 12000000
616 #define RT5682_CLK_FREQ_6000000HZ 6000000
617 #define RT5682_CLK_FREQ_4800000HZ 4800000
618 #define RT5682_CLK_FREQ_2400000HZ 2400000
619 #define RT5682_CLK_FREQ_12288000HZ 12288000
621 static int rt5682_clock_config(struct device *dev)
623 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
624 unsigned int clk_freq, value;
626 clk_freq = (rt5682->params.curr_dr_freq >> 1);
629 case RT5682_CLK_FREQ_12000000HZ:
632 case RT5682_CLK_FREQ_6000000HZ:
635 case RT5682_CLK_FREQ_9600000HZ:
638 case RT5682_CLK_FREQ_4800000HZ:
641 case RT5682_CLK_FREQ_2400000HZ:
644 case RT5682_CLK_FREQ_12288000HZ:
651 regmap_write(rt5682->sdw_regmap, 0xe0, value);
652 regmap_write(rt5682->sdw_regmap, 0xf0, value);
654 dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
659 static int rt5682_bus_config(struct sdw_slave *slave,
660 struct sdw_bus_params *params)
662 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
665 memcpy(&rt5682->params, params, sizeof(*params));
667 ret = rt5682_clock_config(&slave->dev);
669 dev_err(&slave->dev, "Invalid clk config");
674 static int rt5682_interrupt_callback(struct sdw_slave *slave,
675 struct sdw_slave_intr_status *status)
677 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
680 "%s control_port_stat=%x", __func__, status->control_port);
682 if (status->control_port & 0x4) {
683 mod_delayed_work(system_power_efficient_wq,
684 &rt5682->jack_detect_work, msecs_to_jiffies(250));
690 static struct sdw_slave_ops rt5682_slave_ops = {
691 .read_prop = rt5682_read_prop,
692 .interrupt_callback = rt5682_interrupt_callback,
693 .update_status = rt5682_update_status,
694 .bus_config = rt5682_bus_config,
697 static int rt5682_sdw_probe(struct sdw_slave *slave,
698 const struct sdw_device_id *id)
700 struct regmap *regmap;
702 /* Regmap Initialization */
703 regmap = devm_regmap_init_sdw(slave, &rt5682_sdw_regmap);
707 rt5682_sdw_init(&slave->dev, regmap, slave);
712 static int rt5682_sdw_remove(struct sdw_slave *slave)
714 struct rt5682_priv *rt5682 = dev_get_drvdata(&slave->dev);
716 if (rt5682 && rt5682->hw_init)
717 cancel_delayed_work(&rt5682->jack_detect_work);
722 static const struct sdw_device_id rt5682_id[] = {
723 SDW_SLAVE_ENTRY_EXT(0x025d, 0x5682, 0x2, 0, 0),
726 MODULE_DEVICE_TABLE(sdw, rt5682_id);
728 static int __maybe_unused rt5682_dev_suspend(struct device *dev)
730 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
732 if (!rt5682->hw_init)
735 regcache_cache_only(rt5682->regmap, true);
736 regcache_mark_dirty(rt5682->regmap);
741 static int __maybe_unused rt5682_dev_resume(struct device *dev)
743 struct sdw_slave *slave = dev_to_sdw_dev(dev);
744 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
747 if (!rt5682->first_hw_init)
750 if (!slave->unattach_request)
753 time = wait_for_completion_timeout(&slave->initialization_complete,
754 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
756 dev_err(&slave->dev, "Initialization not complete, timed out\n");
761 slave->unattach_request = 0;
762 regcache_cache_only(rt5682->regmap, false);
763 regcache_sync(rt5682->regmap);
768 static const struct dev_pm_ops rt5682_pm = {
769 SET_SYSTEM_SLEEP_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume)
770 SET_RUNTIME_PM_OPS(rt5682_dev_suspend, rt5682_dev_resume, NULL)
773 static struct sdw_driver rt5682_sdw_driver = {
776 .owner = THIS_MODULE,
779 .probe = rt5682_sdw_probe,
780 .remove = rt5682_sdw_remove,
781 .ops = &rt5682_slave_ops,
782 .id_table = rt5682_id,
784 module_sdw_driver(rt5682_sdw_driver);
786 MODULE_DESCRIPTION("ASoC RT5682 driver SDW");
787 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
788 MODULE_LICENSE("GPL v2");