2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/acpi.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/property.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #include "rt5677-spi.h"
37 #define RT5677_DEVICE_ID 0x6327
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
44 /* GPIO indexes defined by ACPI */
46 RT5677_GPIO_PLUG_DET = 0,
47 RT5677_GPIO_MIC_PRESENT_L = 1,
48 RT5677_GPIO_HOTWORD_DET_L = 2,
49 RT5677_GPIO_DSP_INT = 3,
50 RT5677_GPIO_HP_AMP_SHDN_L = 4,
53 static const struct regmap_range_cfg rt5677_ranges[] = {
56 .range_min = RT5677_PR_BASE,
57 .range_max = RT5677_PR_BASE + 0xfd,
58 .selector_reg = RT5677_PRIV_INDEX,
59 .selector_mask = 0xff,
60 .selector_shift = 0x0,
61 .window_start = RT5677_PRIV_DATA,
66 static const struct reg_sequence init_list[] = {
67 {RT5677_ASRC_12, 0x0018},
68 {RT5677_PR_BASE + 0x3d, 0x364d},
69 {RT5677_PR_BASE + 0x17, 0x4fc0},
70 {RT5677_PR_BASE + 0x13, 0x0312},
71 {RT5677_PR_BASE + 0x1e, 0x0000},
72 {RT5677_PR_BASE + 0x12, 0x0eaa},
73 {RT5677_PR_BASE + 0x14, 0x018a},
74 {RT5677_PR_BASE + 0x15, 0x0490},
75 {RT5677_PR_BASE + 0x38, 0x0f71},
76 {RT5677_PR_BASE + 0x39, 0x0f71},
78 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
80 static const struct reg_default rt5677_reg[] = {
81 {RT5677_RESET , 0x0000},
82 {RT5677_LOUT1 , 0xa800},
83 {RT5677_IN1 , 0x0000},
84 {RT5677_MICBIAS , 0x0000},
85 {RT5677_SLIMBUS_PARAM , 0x0000},
86 {RT5677_SLIMBUS_RX , 0x0000},
87 {RT5677_SLIMBUS_CTRL , 0x0000},
88 {RT5677_SIDETONE_CTRL , 0x000b},
89 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
90 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
91 {RT5677_DAC4_DIG_VOL , 0xafaf},
92 {RT5677_DAC3_DIG_VOL , 0xafaf},
93 {RT5677_DAC1_DIG_VOL , 0xafaf},
94 {RT5677_DAC2_DIG_VOL , 0xafaf},
95 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
96 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
97 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
98 {RT5677_STO1_2_ADC_BST , 0x0000},
99 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
100 {RT5677_ADC_BST_CTRL2 , 0x0000},
101 {RT5677_STO3_4_ADC_BST , 0x0000},
102 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
103 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
104 {RT5677_STO4_ADC_MIXER , 0xd4c0},
105 {RT5677_STO3_ADC_MIXER , 0xd4c0},
106 {RT5677_STO2_ADC_MIXER , 0xd4c0},
107 {RT5677_STO1_ADC_MIXER , 0xd4c0},
108 {RT5677_MONO_ADC_MIXER , 0xd4d1},
109 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
110 {RT5677_STO1_DAC_MIXER , 0xaaaa},
111 {RT5677_MONO_DAC_MIXER , 0xaaaa},
112 {RT5677_DD1_MIXER , 0xaaaa},
113 {RT5677_DD2_MIXER , 0xaaaa},
114 {RT5677_IF3_DATA , 0x0000},
115 {RT5677_IF4_DATA , 0x0000},
116 {RT5677_PDM_OUT_CTRL , 0x8888},
117 {RT5677_PDM_DATA_CTRL1 , 0x0000},
118 {RT5677_PDM_DATA_CTRL2 , 0x0000},
119 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
120 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
121 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
122 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
123 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
124 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
125 {RT5677_TDM1_CTRL1 , 0x0300},
126 {RT5677_TDM1_CTRL2 , 0x0000},
127 {RT5677_TDM1_CTRL3 , 0x4000},
128 {RT5677_TDM1_CTRL4 , 0x0123},
129 {RT5677_TDM1_CTRL5 , 0x4567},
130 {RT5677_TDM2_CTRL1 , 0x0300},
131 {RT5677_TDM2_CTRL2 , 0x0000},
132 {RT5677_TDM2_CTRL3 , 0x4000},
133 {RT5677_TDM2_CTRL4 , 0x0123},
134 {RT5677_TDM2_CTRL5 , 0x4567},
135 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
136 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
137 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
138 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
139 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
140 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
141 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
142 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
143 {RT5677_DMIC_CTRL1 , 0x1505},
144 {RT5677_DMIC_CTRL2 , 0x0055},
145 {RT5677_HAP_GENE_CTRL1 , 0x0111},
146 {RT5677_HAP_GENE_CTRL2 , 0x0064},
147 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
148 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
149 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
150 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
151 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
152 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
153 {RT5677_HAP_GENE_CTRL9 , 0xf000},
154 {RT5677_HAP_GENE_CTRL10 , 0x0000},
155 {RT5677_PWR_DIG1 , 0x0000},
156 {RT5677_PWR_DIG2 , 0x0000},
157 {RT5677_PWR_ANLG1 , 0x0055},
158 {RT5677_PWR_ANLG2 , 0x0000},
159 {RT5677_PWR_DSP1 , 0x0001},
160 {RT5677_PWR_DSP_ST , 0x0000},
161 {RT5677_PWR_DSP2 , 0x0000},
162 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
163 {RT5677_PRIV_INDEX , 0x0000},
164 {RT5677_PRIV_DATA , 0x0000},
165 {RT5677_I2S4_SDP , 0x8000},
166 {RT5677_I2S1_SDP , 0x8000},
167 {RT5677_I2S2_SDP , 0x8000},
168 {RT5677_I2S3_SDP , 0x8000},
169 {RT5677_CLK_TREE_CTRL1 , 0x1111},
170 {RT5677_CLK_TREE_CTRL2 , 0x1111},
171 {RT5677_CLK_TREE_CTRL3 , 0x0000},
172 {RT5677_PLL1_CTRL1 , 0x0000},
173 {RT5677_PLL1_CTRL2 , 0x0000},
174 {RT5677_PLL2_CTRL1 , 0x0c60},
175 {RT5677_PLL2_CTRL2 , 0x2000},
176 {RT5677_GLB_CLK1 , 0x0000},
177 {RT5677_GLB_CLK2 , 0x0000},
178 {RT5677_ASRC_1 , 0x0000},
179 {RT5677_ASRC_2 , 0x0000},
180 {RT5677_ASRC_3 , 0x0000},
181 {RT5677_ASRC_4 , 0x0000},
182 {RT5677_ASRC_5 , 0x0000},
183 {RT5677_ASRC_6 , 0x0000},
184 {RT5677_ASRC_7 , 0x0000},
185 {RT5677_ASRC_8 , 0x0000},
186 {RT5677_ASRC_9 , 0x0000},
187 {RT5677_ASRC_10 , 0x0000},
188 {RT5677_ASRC_11 , 0x0000},
189 {RT5677_ASRC_12 , 0x0018},
190 {RT5677_ASRC_13 , 0x0000},
191 {RT5677_ASRC_14 , 0x0000},
192 {RT5677_ASRC_15 , 0x0000},
193 {RT5677_ASRC_16 , 0x0000},
194 {RT5677_ASRC_17 , 0x0000},
195 {RT5677_ASRC_18 , 0x0000},
196 {RT5677_ASRC_19 , 0x0000},
197 {RT5677_ASRC_20 , 0x0000},
198 {RT5677_ASRC_21 , 0x000c},
199 {RT5677_ASRC_22 , 0x0000},
200 {RT5677_ASRC_23 , 0x0000},
201 {RT5677_VAD_CTRL1 , 0x2184},
202 {RT5677_VAD_CTRL2 , 0x010a},
203 {RT5677_VAD_CTRL3 , 0x0aea},
204 {RT5677_VAD_CTRL4 , 0x000c},
205 {RT5677_VAD_CTRL5 , 0x0000},
206 {RT5677_DSP_INB_CTRL1 , 0x0000},
207 {RT5677_DSP_INB_CTRL2 , 0x0000},
208 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
209 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
210 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
211 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
212 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
213 {RT5677_ADC_EQ_CTRL1 , 0x6000},
214 {RT5677_ADC_EQ_CTRL2 , 0x0000},
215 {RT5677_EQ_CTRL1 , 0xc000},
216 {RT5677_EQ_CTRL2 , 0x0000},
217 {RT5677_EQ_CTRL3 , 0x0000},
218 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
219 {RT5677_JD_CTRL1 , 0x0000},
220 {RT5677_JD_CTRL2 , 0x0000},
221 {RT5677_JD_CTRL3 , 0x0000},
222 {RT5677_IRQ_CTRL1 , 0x0000},
223 {RT5677_IRQ_CTRL2 , 0x0000},
224 {RT5677_GPIO_ST , 0x0000},
225 {RT5677_GPIO_CTRL1 , 0x0000},
226 {RT5677_GPIO_CTRL2 , 0x0000},
227 {RT5677_GPIO_CTRL3 , 0x0000},
228 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
229 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
230 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
231 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
232 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
233 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
234 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
235 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
236 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
237 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
238 {RT5677_MB_DRC_CTRL1 , 0x0f20},
239 {RT5677_DRC1_CTRL1 , 0x001f},
240 {RT5677_DRC1_CTRL2 , 0x020c},
241 {RT5677_DRC1_CTRL3 , 0x1f00},
242 {RT5677_DRC1_CTRL4 , 0x0000},
243 {RT5677_DRC1_CTRL5 , 0x0000},
244 {RT5677_DRC1_CTRL6 , 0x0029},
245 {RT5677_DRC2_CTRL1 , 0x001f},
246 {RT5677_DRC2_CTRL2 , 0x020c},
247 {RT5677_DRC2_CTRL3 , 0x1f00},
248 {RT5677_DRC2_CTRL4 , 0x0000},
249 {RT5677_DRC2_CTRL5 , 0x0000},
250 {RT5677_DRC2_CTRL6 , 0x0029},
251 {RT5677_DRC1_HL_CTRL1 , 0x8000},
252 {RT5677_DRC1_HL_CTRL2 , 0x0200},
253 {RT5677_DRC2_HL_CTRL1 , 0x8000},
254 {RT5677_DRC2_HL_CTRL2 , 0x0200},
255 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
264 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
265 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
266 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
267 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
268 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
269 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
270 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
271 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
272 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
273 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
274 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
275 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
276 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
277 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
278 {RT5677_DIG_MISC , 0x0000},
279 {RT5677_GEN_CTRL1 , 0x0000},
280 {RT5677_GEN_CTRL2 , 0x0000},
281 {RT5677_VENDOR_ID , 0x0000},
282 {RT5677_VENDOR_ID1 , 0x10ec},
283 {RT5677_VENDOR_ID2 , 0x6327},
286 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
290 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
291 if (reg >= rt5677_ranges[i].range_min &&
292 reg <= rt5677_ranges[i].range_max) {
299 case RT5677_SLIMBUS_PARAM:
300 case RT5677_PDM_DATA_CTRL1:
301 case RT5677_PDM_DATA_CTRL2:
302 case RT5677_PDM1_DATA_CTRL4:
303 case RT5677_PDM2_DATA_CTRL4:
304 case RT5677_I2C_MASTER_CTRL1:
305 case RT5677_I2C_MASTER_CTRL7:
306 case RT5677_I2C_MASTER_CTRL8:
307 case RT5677_HAP_GENE_CTRL2:
308 case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
309 case RT5677_PWR_DSP_ST:
310 case RT5677_PRIV_DATA:
313 case RT5677_VAD_CTRL5:
314 case RT5677_ADC_EQ_CTRL1:
315 case RT5677_EQ_CTRL1:
316 case RT5677_IRQ_CTRL1:
317 case RT5677_IRQ_CTRL2:
319 case RT5677_DSP_INB1_SRC_CTRL4:
320 case RT5677_DSP_INB2_SRC_CTRL4:
321 case RT5677_DSP_INB3_SRC_CTRL4:
322 case RT5677_DSP_OUTB1_SRC_CTRL4:
323 case RT5677_DSP_OUTB2_SRC_CTRL4:
324 case RT5677_VENDOR_ID:
325 case RT5677_VENDOR_ID1:
326 case RT5677_VENDOR_ID2:
333 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
337 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
338 if (reg >= rt5677_ranges[i].range_min &&
339 reg <= rt5677_ranges[i].range_max) {
349 case RT5677_SLIMBUS_PARAM:
350 case RT5677_SLIMBUS_RX:
351 case RT5677_SLIMBUS_CTRL:
352 case RT5677_SIDETONE_CTRL:
353 case RT5677_ANA_DAC1_2_3_SRC:
354 case RT5677_IF_DSP_DAC3_4_MIXER:
355 case RT5677_DAC4_DIG_VOL:
356 case RT5677_DAC3_DIG_VOL:
357 case RT5677_DAC1_DIG_VOL:
358 case RT5677_DAC2_DIG_VOL:
359 case RT5677_IF_DSP_DAC2_MIXER:
360 case RT5677_STO1_ADC_DIG_VOL:
361 case RT5677_MONO_ADC_DIG_VOL:
362 case RT5677_STO1_2_ADC_BST:
363 case RT5677_STO2_ADC_DIG_VOL:
364 case RT5677_ADC_BST_CTRL2:
365 case RT5677_STO3_4_ADC_BST:
366 case RT5677_STO3_ADC_DIG_VOL:
367 case RT5677_STO4_ADC_DIG_VOL:
368 case RT5677_STO4_ADC_MIXER:
369 case RT5677_STO3_ADC_MIXER:
370 case RT5677_STO2_ADC_MIXER:
371 case RT5677_STO1_ADC_MIXER:
372 case RT5677_MONO_ADC_MIXER:
373 case RT5677_ADC_IF_DSP_DAC1_MIXER:
374 case RT5677_STO1_DAC_MIXER:
375 case RT5677_MONO_DAC_MIXER:
376 case RT5677_DD1_MIXER:
377 case RT5677_DD2_MIXER:
378 case RT5677_IF3_DATA:
379 case RT5677_IF4_DATA:
380 case RT5677_PDM_OUT_CTRL:
381 case RT5677_PDM_DATA_CTRL1:
382 case RT5677_PDM_DATA_CTRL2:
383 case RT5677_PDM1_DATA_CTRL2:
384 case RT5677_PDM1_DATA_CTRL3:
385 case RT5677_PDM1_DATA_CTRL4:
386 case RT5677_PDM2_DATA_CTRL2:
387 case RT5677_PDM2_DATA_CTRL3:
388 case RT5677_PDM2_DATA_CTRL4:
389 case RT5677_TDM1_CTRL1:
390 case RT5677_TDM1_CTRL2:
391 case RT5677_TDM1_CTRL3:
392 case RT5677_TDM1_CTRL4:
393 case RT5677_TDM1_CTRL5:
394 case RT5677_TDM2_CTRL1:
395 case RT5677_TDM2_CTRL2:
396 case RT5677_TDM2_CTRL3:
397 case RT5677_TDM2_CTRL4:
398 case RT5677_TDM2_CTRL5:
399 case RT5677_I2C_MASTER_CTRL1:
400 case RT5677_I2C_MASTER_CTRL2:
401 case RT5677_I2C_MASTER_CTRL3:
402 case RT5677_I2C_MASTER_CTRL4:
403 case RT5677_I2C_MASTER_CTRL5:
404 case RT5677_I2C_MASTER_CTRL6:
405 case RT5677_I2C_MASTER_CTRL7:
406 case RT5677_I2C_MASTER_CTRL8:
407 case RT5677_DMIC_CTRL1:
408 case RT5677_DMIC_CTRL2:
409 case RT5677_HAP_GENE_CTRL1:
410 case RT5677_HAP_GENE_CTRL2:
411 case RT5677_HAP_GENE_CTRL3:
412 case RT5677_HAP_GENE_CTRL4:
413 case RT5677_HAP_GENE_CTRL5:
414 case RT5677_HAP_GENE_CTRL6:
415 case RT5677_HAP_GENE_CTRL7:
416 case RT5677_HAP_GENE_CTRL8:
417 case RT5677_HAP_GENE_CTRL9:
418 case RT5677_HAP_GENE_CTRL10:
419 case RT5677_PWR_DIG1:
420 case RT5677_PWR_DIG2:
421 case RT5677_PWR_ANLG1:
422 case RT5677_PWR_ANLG2:
423 case RT5677_PWR_DSP1:
424 case RT5677_PWR_DSP_ST:
425 case RT5677_PWR_DSP2:
426 case RT5677_ADC_DAC_HPF_CTRL1:
427 case RT5677_PRIV_INDEX:
428 case RT5677_PRIV_DATA:
429 case RT5677_I2S4_SDP:
430 case RT5677_I2S1_SDP:
431 case RT5677_I2S2_SDP:
432 case RT5677_I2S3_SDP:
433 case RT5677_CLK_TREE_CTRL1:
434 case RT5677_CLK_TREE_CTRL2:
435 case RT5677_CLK_TREE_CTRL3:
436 case RT5677_PLL1_CTRL1:
437 case RT5677_PLL1_CTRL2:
438 case RT5677_PLL2_CTRL1:
439 case RT5677_PLL2_CTRL2:
440 case RT5677_GLB_CLK1:
441 case RT5677_GLB_CLK2:
465 case RT5677_VAD_CTRL1:
466 case RT5677_VAD_CTRL2:
467 case RT5677_VAD_CTRL3:
468 case RT5677_VAD_CTRL4:
469 case RT5677_VAD_CTRL5:
470 case RT5677_DSP_INB_CTRL1:
471 case RT5677_DSP_INB_CTRL2:
472 case RT5677_DSP_IN_OUTB_CTRL:
473 case RT5677_DSP_OUTB0_1_DIG_VOL:
474 case RT5677_DSP_OUTB2_3_DIG_VOL:
475 case RT5677_DSP_OUTB4_5_DIG_VOL:
476 case RT5677_DSP_OUTB6_7_DIG_VOL:
477 case RT5677_ADC_EQ_CTRL1:
478 case RT5677_ADC_EQ_CTRL2:
479 case RT5677_EQ_CTRL1:
480 case RT5677_EQ_CTRL2:
481 case RT5677_EQ_CTRL3:
482 case RT5677_SOFT_VOL_ZERO_CROSS1:
483 case RT5677_JD_CTRL1:
484 case RT5677_JD_CTRL2:
485 case RT5677_JD_CTRL3:
486 case RT5677_IRQ_CTRL1:
487 case RT5677_IRQ_CTRL2:
489 case RT5677_GPIO_CTRL1:
490 case RT5677_GPIO_CTRL2:
491 case RT5677_GPIO_CTRL3:
492 case RT5677_STO1_ADC_HI_FILTER1:
493 case RT5677_STO1_ADC_HI_FILTER2:
494 case RT5677_MONO_ADC_HI_FILTER1:
495 case RT5677_MONO_ADC_HI_FILTER2:
496 case RT5677_STO2_ADC_HI_FILTER1:
497 case RT5677_STO2_ADC_HI_FILTER2:
498 case RT5677_STO3_ADC_HI_FILTER1:
499 case RT5677_STO3_ADC_HI_FILTER2:
500 case RT5677_STO4_ADC_HI_FILTER1:
501 case RT5677_STO4_ADC_HI_FILTER2:
502 case RT5677_MB_DRC_CTRL1:
503 case RT5677_DRC1_CTRL1:
504 case RT5677_DRC1_CTRL2:
505 case RT5677_DRC1_CTRL3:
506 case RT5677_DRC1_CTRL4:
507 case RT5677_DRC1_CTRL5:
508 case RT5677_DRC1_CTRL6:
509 case RT5677_DRC2_CTRL1:
510 case RT5677_DRC2_CTRL2:
511 case RT5677_DRC2_CTRL3:
512 case RT5677_DRC2_CTRL4:
513 case RT5677_DRC2_CTRL5:
514 case RT5677_DRC2_CTRL6:
515 case RT5677_DRC1_HL_CTRL1:
516 case RT5677_DRC1_HL_CTRL2:
517 case RT5677_DRC2_HL_CTRL1:
518 case RT5677_DRC2_HL_CTRL2:
519 case RT5677_DSP_INB1_SRC_CTRL1:
520 case RT5677_DSP_INB1_SRC_CTRL2:
521 case RT5677_DSP_INB1_SRC_CTRL3:
522 case RT5677_DSP_INB1_SRC_CTRL4:
523 case RT5677_DSP_INB2_SRC_CTRL1:
524 case RT5677_DSP_INB2_SRC_CTRL2:
525 case RT5677_DSP_INB2_SRC_CTRL3:
526 case RT5677_DSP_INB2_SRC_CTRL4:
527 case RT5677_DSP_INB3_SRC_CTRL1:
528 case RT5677_DSP_INB3_SRC_CTRL2:
529 case RT5677_DSP_INB3_SRC_CTRL3:
530 case RT5677_DSP_INB3_SRC_CTRL4:
531 case RT5677_DSP_OUTB1_SRC_CTRL1:
532 case RT5677_DSP_OUTB1_SRC_CTRL2:
533 case RT5677_DSP_OUTB1_SRC_CTRL3:
534 case RT5677_DSP_OUTB1_SRC_CTRL4:
535 case RT5677_DSP_OUTB2_SRC_CTRL1:
536 case RT5677_DSP_OUTB2_SRC_CTRL2:
537 case RT5677_DSP_OUTB2_SRC_CTRL3:
538 case RT5677_DSP_OUTB2_SRC_CTRL4:
539 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
540 case RT5677_DSP_OUTB_45_MIXER_CTRL:
541 case RT5677_DSP_OUTB_67_MIXER_CTRL:
542 case RT5677_DIG_MISC:
543 case RT5677_GEN_CTRL1:
544 case RT5677_GEN_CTRL2:
545 case RT5677_VENDOR_ID:
546 case RT5677_VENDOR_ID1:
547 case RT5677_VENDOR_ID2:
555 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
556 * @rt5677: Private Data.
557 * @addr: Address index.
558 * @value: Address data.
561 * Returns 0 for success or negative error code.
563 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
564 unsigned int addr, unsigned int value, unsigned int opcode)
566 struct snd_soc_codec *codec = rt5677->codec;
569 mutex_lock(&rt5677->dsp_cmd_lock);
571 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
574 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
578 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
581 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
585 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
588 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
592 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
595 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
599 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
602 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
607 mutex_unlock(&rt5677->dsp_cmd_lock);
613 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
614 * rt5677: Private Data.
615 * @addr: Address index.
616 * @value: Address data.
619 * Returns 0 for success or negative error code.
621 static int rt5677_dsp_mode_i2c_read_addr(
622 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
624 struct snd_soc_codec *codec = rt5677->codec;
626 unsigned int msb, lsb;
628 mutex_lock(&rt5677->dsp_cmd_lock);
630 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
633 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
637 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
640 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
644 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
647 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
651 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
652 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
653 *value = (msb << 16) | lsb;
656 mutex_unlock(&rt5677->dsp_cmd_lock);
662 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
663 * rt5677: Private Data.
664 * @reg: Register index.
665 * @value: Register data.
668 * Returns 0 for success or negative error code.
670 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
671 unsigned int reg, unsigned int value)
673 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
678 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
679 * @codec: SoC audio codec device.
680 * @reg: Register index.
681 * @value: Register data.
684 * Returns 0 for success or negative error code.
686 static int rt5677_dsp_mode_i2c_read(
687 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
689 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
697 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
699 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
703 rt5677->is_dsp_mode = true;
705 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
706 rt5677->is_dsp_mode = false;
710 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
712 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
713 static bool activity;
716 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
719 if (on && !activity) {
722 regcache_cache_only(rt5677->regmap, false);
723 regcache_cache_bypass(rt5677->regmap, true);
725 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
726 regmap_update_bits(rt5677->regmap,
727 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
728 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
729 RT5677_LDO1_SEL_MASK, 0x0);
730 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
731 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
732 switch (rt5677->type) {
734 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
735 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
736 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
737 RT5677_PLL2_PR_SRC_MASK |
738 RT5677_DSP_CLK_SRC_MASK,
739 RT5677_PLL2_PR_SRC_MCLK2 |
740 RT5677_DSP_CLK_SRC_BYPASS);
743 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
744 RT5677_DSP_CLK_SRC_MASK,
745 RT5677_DSP_CLK_SRC_BYPASS);
750 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
751 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
752 rt5677_set_dsp_mode(codec, true);
754 ret = reject_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
757 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
758 release_firmware(rt5677->fw1);
761 ret = reject_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
764 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
765 release_firmware(rt5677->fw2);
768 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
770 regcache_cache_bypass(rt5677->regmap, false);
771 regcache_cache_only(rt5677->regmap, true);
772 } else if (!on && activity) {
775 regcache_cache_only(rt5677->regmap, false);
776 regcache_cache_bypass(rt5677->regmap, true);
778 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
779 rt5677_set_dsp_mode(codec, false);
780 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
782 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
784 regcache_cache_bypass(rt5677->regmap, false);
785 regcache_mark_dirty(rt5677->regmap);
786 regcache_sync(rt5677->regmap);
792 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
793 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
794 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
795 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
796 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
797 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
799 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
800 static const DECLARE_TLV_DB_RANGE(bst_tlv,
801 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
802 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
803 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
804 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
805 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
806 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
807 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
810 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
811 struct snd_ctl_elem_value *ucontrol)
813 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
814 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
816 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
821 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
822 struct snd_ctl_elem_value *ucontrol)
824 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
825 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
826 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
828 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
830 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
831 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
836 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
838 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
839 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
840 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
841 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
842 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
843 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
845 /* DAC Digital Volume */
846 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
847 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
848 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
849 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
850 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
851 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
852 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
853 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
855 /* IN1/IN2 Control */
856 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
857 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
859 /* ADC Digital Volume Control */
860 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
861 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
862 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
863 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
864 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
865 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
866 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
867 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
868 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
869 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
871 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
872 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
874 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
875 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
877 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
878 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
880 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
881 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
883 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
884 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
887 /* Sidetone Control */
888 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
889 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
891 /* ADC Boost Volume Control */
892 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
893 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
895 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
896 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
898 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
899 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
901 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
902 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
904 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
905 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
908 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
909 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
913 * set_dmic_clk - Set parameter of dmic.
916 * @kcontrol: The kcontrol of this widget.
919 * Choose dmic clock between 1MHz and 3MHz.
920 * It is better for clock to approximate 3MHz.
922 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
923 struct snd_kcontrol *kcontrol, int event)
925 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
926 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
929 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
930 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
931 idx = rl6231_calc_dmic_clk(rate);
933 dev_err(codec->dev, "Failed to set DMIC clock\n");
935 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
936 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
940 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
941 struct snd_soc_dapm_widget *sink)
943 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
944 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
947 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
948 val &= RT5677_SCLK_SRC_MASK;
949 if (val == RT5677_SCLK_SRC_PLL1)
955 static int is_using_asrc(struct snd_soc_dapm_widget *source,
956 struct snd_soc_dapm_widget *sink)
958 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
959 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
960 unsigned int reg, shift, val;
962 if (source->reg == RT5677_ASRC_1) {
963 switch (source->shift) {
984 switch (source->shift) {
1002 reg = RT5677_ASRC_5;
1006 reg = RT5677_ASRC_5;
1010 reg = RT5677_ASRC_3;
1014 reg = RT5677_ASRC_3;
1018 reg = RT5677_ASRC_3;
1026 regmap_read(rt5677->regmap, reg, &val);
1027 val = (val >> shift) & 0xf;
1038 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1039 struct snd_soc_dapm_widget *sink)
1041 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1042 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1044 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1051 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1052 * @codec: SoC audio codec device.
1053 * @filter_mask: mask of filters.
1054 * @clk_src: clock source
1056 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1057 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1058 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1059 * ASRC function will track i2s clock and generate a corresponding system clock
1060 * for codec. This function provides an API to select the clock source for a
1061 * set of filters specified by the mask. And the codec driver will turn on ASRC
1062 * for these filters if ASRC is selected as their clock source.
1064 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1065 unsigned int filter_mask, unsigned int clk_src)
1067 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1068 unsigned int asrc3_mask = 0, asrc3_value = 0;
1069 unsigned int asrc4_mask = 0, asrc4_value = 0;
1070 unsigned int asrc5_mask = 0, asrc5_value = 0;
1071 unsigned int asrc6_mask = 0, asrc6_value = 0;
1072 unsigned int asrc7_mask = 0, asrc7_value = 0;
1073 unsigned int asrc8_mask = 0, asrc8_value = 0;
1076 case RT5677_CLK_SEL_SYS:
1077 case RT5677_CLK_SEL_I2S1_ASRC:
1078 case RT5677_CLK_SEL_I2S2_ASRC:
1079 case RT5677_CLK_SEL_I2S3_ASRC:
1080 case RT5677_CLK_SEL_I2S4_ASRC:
1081 case RT5677_CLK_SEL_I2S5_ASRC:
1082 case RT5677_CLK_SEL_I2S6_ASRC:
1083 case RT5677_CLK_SEL_SYS2:
1084 case RT5677_CLK_SEL_SYS3:
1085 case RT5677_CLK_SEL_SYS4:
1086 case RT5677_CLK_SEL_SYS5:
1087 case RT5677_CLK_SEL_SYS6:
1088 case RT5677_CLK_SEL_SYS7:
1096 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1097 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1098 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1099 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1102 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1103 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1104 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1105 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1108 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1109 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1110 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1111 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1115 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1119 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1120 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1121 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1122 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1125 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1126 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1127 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1128 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1131 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1132 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1133 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1134 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1137 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1138 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1139 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1140 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1144 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1148 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1149 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1150 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1151 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1154 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1155 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1156 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1157 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1160 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1161 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1162 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1163 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1166 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1167 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1168 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1169 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1173 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1177 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1178 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1179 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1180 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1183 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1184 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1185 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1186 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1190 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1194 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1195 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1196 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1197 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1200 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1201 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1202 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1203 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1207 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1211 if (filter_mask & RT5677_I2S1_SOURCE) {
1212 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1213 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1214 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1217 if (filter_mask & RT5677_I2S2_SOURCE) {
1218 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1219 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1220 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1223 if (filter_mask & RT5677_I2S3_SOURCE) {
1224 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1225 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1226 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1229 if (filter_mask & RT5677_I2S4_SOURCE) {
1230 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1231 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1232 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1236 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1241 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1243 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1244 struct snd_soc_dapm_widget *sink)
1246 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1247 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1248 unsigned int asrc_setting;
1250 switch (source->shift) {
1252 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1253 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1254 RT5677_AD_STO1_CLK_SEL_SFT;
1258 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1259 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1260 RT5677_AD_STO2_CLK_SEL_SFT;
1264 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1265 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1266 RT5677_AD_STO3_CLK_SEL_SFT;
1270 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1271 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1272 RT5677_AD_STO4_CLK_SEL_SFT;
1276 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1277 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1278 RT5677_AD_MONOL_CLK_SEL_SFT;
1282 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1283 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1284 RT5677_AD_MONOR_CLK_SEL_SFT;
1291 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1292 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1299 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1300 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1301 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1302 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1303 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1306 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1307 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1308 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1309 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1310 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1313 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1314 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1315 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1316 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1317 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1320 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1321 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1322 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1323 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1324 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1327 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1328 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1329 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1330 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1331 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1334 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1335 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1336 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1337 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1338 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1341 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1342 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1343 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1344 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1345 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1348 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1349 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1350 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1351 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1352 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1355 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1356 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1357 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1358 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1359 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1362 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1363 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1364 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1365 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1366 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1369 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1370 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1371 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1372 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1373 RT5677_M_DAC1_L_SFT, 1, 1),
1376 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1377 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1378 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1379 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1380 RT5677_M_DAC1_R_SFT, 1, 1),
1383 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1384 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1385 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1386 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1387 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1388 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1389 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1390 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1391 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1394 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1395 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1396 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1397 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1398 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1399 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1400 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1401 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1402 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1405 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1406 SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1407 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1408 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1409 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1410 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1411 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1412 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1413 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1416 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1417 SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1418 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1419 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1420 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1421 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1422 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1423 SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1424 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1427 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1428 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1429 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1430 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1431 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1432 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1433 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1434 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1435 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1438 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1439 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1440 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1441 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1442 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1443 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
1444 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1445 SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
1446 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1449 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1450 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1451 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1452 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1453 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1454 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1455 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1456 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1457 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1460 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1461 SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1462 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1463 SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1464 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1465 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
1466 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1467 SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
1468 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1471 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1472 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1473 RT5677_DSP_IB_01_H_SFT, 1, 1),
1474 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1475 RT5677_DSP_IB_23_H_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1477 RT5677_DSP_IB_45_H_SFT, 1, 1),
1478 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1479 RT5677_DSP_IB_6_H_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_7_H_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_8_H_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_9_H_SFT, 1, 1),
1488 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1489 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1490 RT5677_DSP_IB_01_L_SFT, 1, 1),
1491 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1492 RT5677_DSP_IB_23_L_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1494 RT5677_DSP_IB_45_L_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1496 RT5677_DSP_IB_6_L_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1498 RT5677_DSP_IB_7_L_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1500 RT5677_DSP_IB_8_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1502 RT5677_DSP_IB_9_L_SFT, 1, 1),
1505 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1506 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1507 RT5677_DSP_IB_01_H_SFT, 1, 1),
1508 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1509 RT5677_DSP_IB_23_H_SFT, 1, 1),
1510 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1511 RT5677_DSP_IB_45_H_SFT, 1, 1),
1512 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1513 RT5677_DSP_IB_6_H_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_7_H_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_8_H_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_9_H_SFT, 1, 1),
1522 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1523 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1524 RT5677_DSP_IB_01_L_SFT, 1, 1),
1525 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1526 RT5677_DSP_IB_23_L_SFT, 1, 1),
1527 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1528 RT5677_DSP_IB_45_L_SFT, 1, 1),
1529 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1530 RT5677_DSP_IB_6_L_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1532 RT5677_DSP_IB_7_L_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1534 RT5677_DSP_IB_8_L_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1536 RT5677_DSP_IB_9_L_SFT, 1, 1),
1539 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1540 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1541 RT5677_DSP_IB_01_H_SFT, 1, 1),
1542 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1543 RT5677_DSP_IB_23_H_SFT, 1, 1),
1544 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1545 RT5677_DSP_IB_45_H_SFT, 1, 1),
1546 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1547 RT5677_DSP_IB_6_H_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_7_H_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_8_H_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_9_H_SFT, 1, 1),
1556 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1557 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1558 RT5677_DSP_IB_01_L_SFT, 1, 1),
1559 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1560 RT5677_DSP_IB_23_L_SFT, 1, 1),
1561 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1562 RT5677_DSP_IB_45_L_SFT, 1, 1),
1563 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1564 RT5677_DSP_IB_6_L_SFT, 1, 1),
1565 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1566 RT5677_DSP_IB_7_L_SFT, 1, 1),
1567 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1568 RT5677_DSP_IB_8_L_SFT, 1, 1),
1569 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1570 RT5677_DSP_IB_9_L_SFT, 1, 1),
1575 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1576 static const char * const rt5677_dac1_src[] = {
1577 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1581 static SOC_ENUM_SINGLE_DECL(
1582 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1583 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1585 static const struct snd_kcontrol_new rt5677_dac1_mux =
1586 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1588 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1589 static const char * const rt5677_adda1_src[] = {
1590 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1593 static SOC_ENUM_SINGLE_DECL(
1594 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1595 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1597 static const struct snd_kcontrol_new rt5677_adda1_mux =
1598 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1601 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1602 static const char * const rt5677_dac2l_src[] = {
1603 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1607 static SOC_ENUM_SINGLE_DECL(
1608 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1609 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1611 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1612 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1614 static const char * const rt5677_dac2r_src[] = {
1615 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1616 "OB 3", "Haptic Generator", "VAD ADC"
1619 static SOC_ENUM_SINGLE_DECL(
1620 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1621 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1623 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1624 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1626 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1627 static const char * const rt5677_dac3l_src[] = {
1628 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1632 static SOC_ENUM_SINGLE_DECL(
1633 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1634 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1636 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1637 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1639 static const char * const rt5677_dac3r_src[] = {
1640 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1644 static SOC_ENUM_SINGLE_DECL(
1645 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1646 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1648 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1649 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1651 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1652 static const char * const rt5677_dac4l_src[] = {
1653 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1657 static SOC_ENUM_SINGLE_DECL(
1658 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1659 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1661 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1662 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1664 static const char * const rt5677_dac4r_src[] = {
1665 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1669 static SOC_ENUM_SINGLE_DECL(
1670 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1671 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1673 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1674 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1676 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1677 static const char * const rt5677_iob_bypass_src[] = {
1678 "Bypass", "Pass SRC"
1681 static SOC_ENUM_SINGLE_DECL(
1682 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1683 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1685 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1686 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1688 static SOC_ENUM_SINGLE_DECL(
1689 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1690 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1692 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1693 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1695 static SOC_ENUM_SINGLE_DECL(
1696 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1697 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1699 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1700 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1702 static SOC_ENUM_SINGLE_DECL(
1703 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1704 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1706 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1707 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1709 static SOC_ENUM_SINGLE_DECL(
1710 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1711 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1713 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1714 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1716 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1717 static const char * const rt5677_stereo_adc2_src[] = {
1718 "DD MIX1", "DMIC", "Stereo DAC MIX"
1721 static SOC_ENUM_SINGLE_DECL(
1722 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1723 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1725 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1726 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1728 static SOC_ENUM_SINGLE_DECL(
1729 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1730 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1732 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1733 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1735 static SOC_ENUM_SINGLE_DECL(
1736 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1737 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1739 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1740 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1742 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1743 static const char * const rt5677_dmic_src[] = {
1744 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1747 static SOC_ENUM_SINGLE_DECL(
1748 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1749 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1751 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1752 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1754 static SOC_ENUM_SINGLE_DECL(
1755 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1756 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1758 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1759 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1761 static SOC_ENUM_SINGLE_DECL(
1762 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1763 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1765 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1766 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1768 static SOC_ENUM_SINGLE_DECL(
1769 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1770 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1772 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1773 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1775 static SOC_ENUM_SINGLE_DECL(
1776 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1777 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1779 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1780 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1782 static SOC_ENUM_SINGLE_DECL(
1783 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1784 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1786 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1787 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1789 /* Stereo2 ADC Source */ /* MX-26 [0] */
1790 static const char * const rt5677_stereo2_adc_lr_src[] = {
1794 static SOC_ENUM_SINGLE_DECL(
1795 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1796 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1798 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1799 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1801 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1802 static const char * const rt5677_stereo_adc1_src[] = {
1803 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1806 static SOC_ENUM_SINGLE_DECL(
1807 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1808 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1810 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1811 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1813 static SOC_ENUM_SINGLE_DECL(
1814 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1815 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1817 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1818 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1820 static SOC_ENUM_SINGLE_DECL(
1821 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1822 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1824 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1825 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1827 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1828 static const char * const rt5677_mono_adc2_l_src[] = {
1829 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1832 static SOC_ENUM_SINGLE_DECL(
1833 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1834 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1836 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1837 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1839 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1840 static const char * const rt5677_mono_adc1_l_src[] = {
1841 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1844 static SOC_ENUM_SINGLE_DECL(
1845 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1846 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1848 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1849 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1851 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1852 static const char * const rt5677_mono_adc2_r_src[] = {
1853 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1856 static SOC_ENUM_SINGLE_DECL(
1857 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1858 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1860 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1861 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1863 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1864 static const char * const rt5677_mono_adc1_r_src[] = {
1865 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1868 static SOC_ENUM_SINGLE_DECL(
1869 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1870 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1872 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1873 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1875 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1876 static const char * const rt5677_stereo4_adc2_src[] = {
1877 "DD MIX1", "DMIC", "DD MIX2"
1880 static SOC_ENUM_SINGLE_DECL(
1881 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1882 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1884 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1885 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1888 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1889 static const char * const rt5677_stereo4_adc1_src[] = {
1890 "DD MIX1", "ADC1/2", "DD MIX2"
1893 static SOC_ENUM_SINGLE_DECL(
1894 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1895 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1897 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1898 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1900 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1901 static const char * const rt5677_inbound01_src[] = {
1902 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1906 static SOC_ENUM_SINGLE_DECL(
1907 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1908 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1910 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1911 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1913 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1914 static const char * const rt5677_inbound23_src[] = {
1915 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1916 "DAC1 FS", "IF4 DAC"
1919 static SOC_ENUM_SINGLE_DECL(
1920 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1921 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1923 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1924 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1926 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1927 static const char * const rt5677_inbound45_src[] = {
1928 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1932 static SOC_ENUM_SINGLE_DECL(
1933 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1934 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1936 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1937 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1939 /* InBound6 Source */ /* MX-A3 [2:0] */
1940 static const char * const rt5677_inbound6_src[] = {
1941 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1942 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1945 static SOC_ENUM_SINGLE_DECL(
1946 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1947 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1949 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1950 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1952 /* InBound7 Source */ /* MX-A4 [14:12] */
1953 static const char * const rt5677_inbound7_src[] = {
1954 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1955 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1958 static SOC_ENUM_SINGLE_DECL(
1959 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1960 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1962 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1963 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1965 /* InBound8 Source */ /* MX-A4 [10:8] */
1966 static const char * const rt5677_inbound8_src[] = {
1967 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1968 "MONO ADC MIX L", "DACL1 FS"
1971 static SOC_ENUM_SINGLE_DECL(
1972 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1973 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1975 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1976 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1978 /* InBound9 Source */ /* MX-A4 [6:4] */
1979 static const char * const rt5677_inbound9_src[] = {
1980 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1981 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1984 static SOC_ENUM_SINGLE_DECL(
1985 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1986 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1988 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1989 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1991 /* VAD Source */ /* MX-9F [6:4] */
1992 static const char * const rt5677_vad_src[] = {
1993 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1997 static SOC_ENUM_SINGLE_DECL(
1998 rt5677_vad_enum, RT5677_VAD_CTRL4,
1999 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2001 static const struct snd_kcontrol_new rt5677_vad_src_mux =
2002 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2004 /* Sidetone Source */ /* MX-13 [11:9] */
2005 static const char * const rt5677_sidetone_src[] = {
2006 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2009 static SOC_ENUM_SINGLE_DECL(
2010 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2011 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2013 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2014 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2016 /* DAC1/2 Source */ /* MX-15 [1:0] */
2017 static const char * const rt5677_dac12_src[] = {
2018 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2021 static SOC_ENUM_SINGLE_DECL(
2022 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2023 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2025 static const struct snd_kcontrol_new rt5677_dac12_mux =
2026 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2028 /* DAC3 Source */ /* MX-15 [5:4] */
2029 static const char * const rt5677_dac3_src[] = {
2030 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2033 static SOC_ENUM_SINGLE_DECL(
2034 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2035 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2037 static const struct snd_kcontrol_new rt5677_dac3_mux =
2038 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2040 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2041 static const char * const rt5677_pdm_src[] = {
2042 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2045 static SOC_ENUM_SINGLE_DECL(
2046 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2047 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2049 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2050 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2052 static SOC_ENUM_SINGLE_DECL(
2053 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2054 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2056 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2057 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2059 static SOC_ENUM_SINGLE_DECL(
2060 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2061 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2063 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2064 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2066 static SOC_ENUM_SINGLE_DECL(
2067 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2068 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2070 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2071 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2073 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2074 static const char * const rt5677_if12_adc1_src[] = {
2075 "STO1 ADC MIX", "OB01", "VAD ADC"
2078 static SOC_ENUM_SINGLE_DECL(
2079 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2080 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2082 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2083 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2085 static SOC_ENUM_SINGLE_DECL(
2086 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2087 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2089 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2090 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2092 static SOC_ENUM_SINGLE_DECL(
2093 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2094 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2096 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2097 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2099 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2100 static const char * const rt5677_if12_adc2_src[] = {
2101 "STO2 ADC MIX", "OB23"
2104 static SOC_ENUM_SINGLE_DECL(
2105 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2106 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2108 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2109 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2111 static SOC_ENUM_SINGLE_DECL(
2112 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2113 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2115 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2116 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2118 static SOC_ENUM_SINGLE_DECL(
2119 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2120 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2122 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2123 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2125 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2126 static const char * const rt5677_if12_adc3_src[] = {
2127 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2130 static SOC_ENUM_SINGLE_DECL(
2131 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2132 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2134 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2135 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2137 static SOC_ENUM_SINGLE_DECL(
2138 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2139 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2141 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2142 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2144 static SOC_ENUM_SINGLE_DECL(
2145 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2146 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2148 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2149 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2151 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2152 static const char * const rt5677_if12_adc4_src[] = {
2153 "STO4 ADC MIX", "OB67", "OB01"
2156 static SOC_ENUM_SINGLE_DECL(
2157 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2158 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2160 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2161 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2163 static SOC_ENUM_SINGLE_DECL(
2164 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2165 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2167 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2168 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2170 static SOC_ENUM_SINGLE_DECL(
2171 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2172 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2174 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2175 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2177 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2178 static const char * const rt5677_if34_adc_src[] = {
2179 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2180 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2183 static SOC_ENUM_SINGLE_DECL(
2184 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2185 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2187 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2188 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2190 static SOC_ENUM_SINGLE_DECL(
2191 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2192 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2194 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2195 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2197 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2198 static const char * const rt5677_if12_adc_swap_src[] = {
2199 "L/R", "R/L", "L/L", "R/R"
2202 static SOC_ENUM_SINGLE_DECL(
2203 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2204 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2206 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2207 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2209 static SOC_ENUM_SINGLE_DECL(
2210 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2211 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2213 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2214 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2216 static SOC_ENUM_SINGLE_DECL(
2217 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2218 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2220 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2221 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2223 static SOC_ENUM_SINGLE_DECL(
2224 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2225 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2227 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2228 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2230 static SOC_ENUM_SINGLE_DECL(
2231 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2232 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2234 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2235 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2237 static SOC_ENUM_SINGLE_DECL(
2238 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2239 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2241 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2242 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2244 static SOC_ENUM_SINGLE_DECL(
2245 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2246 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2248 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2249 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2251 static SOC_ENUM_SINGLE_DECL(
2252 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2253 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2255 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2256 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2258 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2259 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2260 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2261 "3/1/2/4", "3/4/1/2"
2264 static SOC_ENUM_SINGLE_DECL(
2265 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2266 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2268 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2269 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2271 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2272 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2273 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2274 "2/3/1/4", "3/4/1/2"
2277 static SOC_ENUM_SINGLE_DECL(
2278 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2279 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2281 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2282 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2284 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2285 MX-3F[14:12][10:8][6:4][2:0]
2286 MX-43[14:12][10:8][6:4][2:0]
2287 MX-44[14:12][10:8][6:4][2:0] */
2288 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2289 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2292 static SOC_ENUM_SINGLE_DECL(
2293 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2294 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2296 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2297 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2299 static SOC_ENUM_SINGLE_DECL(
2300 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2301 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2303 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2304 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2306 static SOC_ENUM_SINGLE_DECL(
2307 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2308 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2310 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2311 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2313 static SOC_ENUM_SINGLE_DECL(
2314 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2315 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2317 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2318 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2320 static SOC_ENUM_SINGLE_DECL(
2321 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2322 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2324 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2325 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2327 static SOC_ENUM_SINGLE_DECL(
2328 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2329 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2331 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2332 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2334 static SOC_ENUM_SINGLE_DECL(
2335 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2336 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2338 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2339 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2341 static SOC_ENUM_SINGLE_DECL(
2342 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2343 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2345 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2346 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2348 static SOC_ENUM_SINGLE_DECL(
2349 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2350 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2352 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2353 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2355 static SOC_ENUM_SINGLE_DECL(
2356 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2357 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2359 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2360 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2362 static SOC_ENUM_SINGLE_DECL(
2363 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2364 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2366 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2367 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2369 static SOC_ENUM_SINGLE_DECL(
2370 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2371 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2373 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2374 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2376 static SOC_ENUM_SINGLE_DECL(
2377 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2378 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2380 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2381 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2383 static SOC_ENUM_SINGLE_DECL(
2384 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2385 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2387 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2388 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2390 static SOC_ENUM_SINGLE_DECL(
2391 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2392 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2394 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2395 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2397 static SOC_ENUM_SINGLE_DECL(
2398 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2399 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2401 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2402 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2404 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2405 struct snd_kcontrol *kcontrol, int event)
2407 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2408 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2411 case SND_SOC_DAPM_POST_PMU:
2412 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2413 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2416 case SND_SOC_DAPM_PRE_PMD:
2417 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2418 RT5677_PWR_BST1_P, 0);
2428 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2429 struct snd_kcontrol *kcontrol, int event)
2431 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2432 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2435 case SND_SOC_DAPM_POST_PMU:
2436 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2437 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2440 case SND_SOC_DAPM_PRE_PMD:
2441 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2442 RT5677_PWR_BST2_P, 0);
2452 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2453 struct snd_kcontrol *kcontrol, int event)
2455 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2456 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2459 case SND_SOC_DAPM_PRE_PMU:
2460 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2463 case SND_SOC_DAPM_POST_PMU:
2464 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2474 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2475 struct snd_kcontrol *kcontrol, int event)
2477 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2478 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2481 case SND_SOC_DAPM_PRE_PMU:
2482 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2485 case SND_SOC_DAPM_POST_PMU:
2486 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2496 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2497 struct snd_kcontrol *kcontrol, int event)
2499 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2500 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2503 case SND_SOC_DAPM_POST_PMU:
2504 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2505 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2506 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2507 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2510 case SND_SOC_DAPM_PRE_PMD:
2511 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2512 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2513 RT5677_PWR_CLK_MB, 0);
2523 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2524 struct snd_kcontrol *kcontrol, int event)
2526 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2527 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2531 case SND_SOC_DAPM_PRE_PMU:
2532 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2533 if (value & RT5677_IF1_ADC_CTRL_MASK)
2534 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2535 RT5677_IF1_ADC_MODE_MASK,
2536 RT5677_IF1_ADC_MODE_TDM);
2546 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2547 struct snd_kcontrol *kcontrol, int event)
2549 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2550 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2554 case SND_SOC_DAPM_PRE_PMU:
2555 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2556 if (value & RT5677_IF2_ADC_CTRL_MASK)
2557 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2558 RT5677_IF2_ADC_MODE_MASK,
2559 RT5677_IF2_ADC_MODE_TDM);
2569 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2570 struct snd_kcontrol *kcontrol, int event)
2572 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2573 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2576 case SND_SOC_DAPM_POST_PMU:
2577 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2578 !rt5677->is_vref_slow) {
2580 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2581 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2582 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2583 rt5677->is_vref_slow = true;
2594 static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
2595 struct snd_kcontrol *kcontrol, int event)
2598 case SND_SOC_DAPM_POST_PMU:
2609 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2610 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2611 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2612 SND_SOC_DAPM_POST_PMU),
2613 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2614 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2615 SND_SOC_DAPM_POST_PMU),
2618 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2619 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2620 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2621 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2623 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2625 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2627 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2629 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2631 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2633 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2635 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2637 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2639 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2641 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2643 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2645 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2647 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2648 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2649 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2650 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2651 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2653 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2658 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2659 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2660 SND_SOC_DAPM_POST_PMU),
2663 SND_SOC_DAPM_INPUT("DMIC L1"),
2664 SND_SOC_DAPM_INPUT("DMIC R1"),
2665 SND_SOC_DAPM_INPUT("DMIC L2"),
2666 SND_SOC_DAPM_INPUT("DMIC R2"),
2667 SND_SOC_DAPM_INPUT("DMIC L3"),
2668 SND_SOC_DAPM_INPUT("DMIC R3"),
2669 SND_SOC_DAPM_INPUT("DMIC L4"),
2670 SND_SOC_DAPM_INPUT("DMIC R4"),
2672 SND_SOC_DAPM_INPUT("IN1P"),
2673 SND_SOC_DAPM_INPUT("IN1N"),
2674 SND_SOC_DAPM_INPUT("IN2P"),
2675 SND_SOC_DAPM_INPUT("IN2N"),
2677 SND_SOC_DAPM_INPUT("Haptic Generator"),
2679 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2680 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2681 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2682 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2684 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2685 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2686 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2687 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2688 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2689 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2690 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2691 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2694 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2697 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2698 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2699 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2700 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2701 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2702 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2705 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2707 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2709 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2711 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2712 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2713 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2714 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2715 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2716 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2717 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2718 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2721 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_sto1_dmic_mux),
2723 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2724 &rt5677_sto1_adc1_mux),
2725 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2726 &rt5677_sto1_adc2_mux),
2727 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2728 &rt5677_sto2_dmic_mux),
2729 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2730 &rt5677_sto2_adc1_mux),
2731 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2732 &rt5677_sto2_adc2_mux),
2733 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2734 &rt5677_sto2_adc_lr_mux),
2735 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2736 &rt5677_sto3_dmic_mux),
2737 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2738 &rt5677_sto3_adc1_mux),
2739 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2740 &rt5677_sto3_adc2_mux),
2741 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2742 &rt5677_sto4_dmic_mux),
2743 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2744 &rt5677_sto4_adc1_mux),
2745 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2746 &rt5677_sto4_adc2_mux),
2747 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2748 &rt5677_mono_dmic_l_mux),
2749 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2750 &rt5677_mono_dmic_r_mux),
2751 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2752 &rt5677_mono_adc2_l_mux),
2753 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2754 &rt5677_mono_adc1_l_mux),
2755 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2756 &rt5677_mono_adc1_r_mux),
2757 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2758 &rt5677_mono_adc2_r_mux),
2761 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2762 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2763 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2764 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2765 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2766 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2767 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2768 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2769 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2770 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2771 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2772 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2773 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2774 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2775 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2776 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2777 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2778 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2779 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2780 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2781 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2782 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2783 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2784 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2785 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2786 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2788 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2789 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2790 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2791 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2792 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2795 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2803 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2804 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2805 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2806 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2807 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2813 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2814 &rt5677_ib9_src_mux),
2815 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2816 &rt5677_ib8_src_mux),
2817 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2818 &rt5677_ib7_src_mux),
2819 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2820 &rt5677_ib6_src_mux),
2821 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2822 &rt5677_ib45_src_mux),
2823 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2824 &rt5677_ib23_src_mux),
2825 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2826 &rt5677_ib01_src_mux),
2827 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2828 &rt5677_ib45_bypass_src_mux),
2829 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2830 &rt5677_ib23_bypass_src_mux),
2831 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2832 &rt5677_ib01_bypass_src_mux),
2833 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2834 &rt5677_ob23_bypass_src_mux),
2835 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2836 &rt5677_ob01_bypass_src_mux),
2838 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2839 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 /* Digital Interface */
2849 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2850 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2869 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2888 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2897 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2906 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2914 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2915 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2916 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2917 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2924 /* Digital Interface Select */
2925 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2926 &rt5677_if1_adc1_mux),
2927 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2928 &rt5677_if1_adc2_mux),
2929 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2930 &rt5677_if1_adc3_mux),
2931 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2932 &rt5677_if1_adc4_mux),
2933 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5677_if1_adc1_swap_mux),
2935 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5677_if1_adc2_swap_mux),
2937 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if1_adc3_swap_mux),
2939 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if1_adc4_swap_mux),
2941 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2943 SND_SOC_DAPM_PRE_PMU),
2944 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5677_if2_adc1_mux),
2946 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5677_if2_adc2_mux),
2948 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5677_if2_adc3_mux),
2950 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5677_if2_adc4_mux),
2952 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5677_if2_adc1_swap_mux),
2954 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5677_if2_adc2_swap_mux),
2956 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_if2_adc3_swap_mux),
2958 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_if2_adc4_swap_mux),
2960 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2962 SND_SOC_DAPM_PRE_PMU),
2963 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5677_if3_adc_mux),
2965 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_if4_adc_mux),
2967 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_slb_adc1_mux),
2969 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_slb_adc2_mux),
2971 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_slb_adc3_mux),
2973 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_slb_adc4_mux),
2976 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5677_if1_dac0_tdm_sel_mux),
2978 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5677_if1_dac1_tdm_sel_mux),
2980 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5677_if1_dac2_tdm_sel_mux),
2982 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5677_if1_dac3_tdm_sel_mux),
2984 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5677_if1_dac4_tdm_sel_mux),
2986 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if1_dac5_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if1_dac6_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if1_dac7_tdm_sel_mux),
2993 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5677_if2_dac0_tdm_sel_mux),
2995 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5677_if2_dac1_tdm_sel_mux),
2997 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5677_if2_dac2_tdm_sel_mux),
2999 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5677_if2_dac3_tdm_sel_mux),
3001 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
3002 &rt5677_if2_dac4_tdm_sel_mux),
3003 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
3004 &rt5677_if2_dac5_tdm_sel_mux),
3005 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
3006 &rt5677_if2_dac6_tdm_sel_mux),
3007 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3008 &rt5677_if2_dac7_tdm_sel_mux),
3010 /* Audio Interface */
3011 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3013 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3014 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3015 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3016 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3017 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3018 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3019 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3020 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3023 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3024 &rt5677_sidetone_mux),
3025 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3026 RT5677_ST_EN_SFT, 0, NULL, 0),
3029 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3030 &rt5677_vad_src_mux),
3033 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3034 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3035 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3036 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3037 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3038 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3039 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3040 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3041 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3042 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3043 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3044 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3045 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3048 /* DAC mixer before sound effect */
3049 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3050 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3051 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3052 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3053 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3056 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3058 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3060 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3062 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3065 /* DAC2 channel Mux */
3066 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3067 &rt5677_dac2_l_mux),
3068 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3069 &rt5677_dac2_r_mux),
3071 /* DAC3 channel Mux */
3072 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3073 &rt5677_dac3_l_mux),
3074 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3075 &rt5677_dac3_r_mux),
3077 /* DAC4 channel Mux */
3078 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3079 &rt5677_dac4_l_mux),
3080 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3081 &rt5677_dac4_r_mux),
3084 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3085 RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event,
3086 SND_SOC_DAPM_POST_PMU),
3087 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3088 RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event,
3089 SND_SOC_DAPM_POST_PMU),
3090 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3091 RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event,
3092 SND_SOC_DAPM_POST_PMU),
3093 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3094 RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event,
3095 SND_SOC_DAPM_POST_PMU),
3096 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3097 RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event,
3098 SND_SOC_DAPM_POST_PMU),
3099 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3100 RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event,
3101 SND_SOC_DAPM_POST_PMU),
3102 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3103 RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event,
3104 SND_SOC_DAPM_POST_PMU),
3106 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3107 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3108 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3109 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3110 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3111 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3112 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3113 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3114 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3115 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3116 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3117 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3118 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3119 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3120 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3121 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3122 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3123 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3124 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3125 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3128 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3129 RT5677_PWR_DAC1_BIT, 0),
3130 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3131 RT5677_PWR_DAC2_BIT, 0),
3132 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3133 RT5677_PWR_DAC3_BIT, 0),
3136 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3137 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3138 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3139 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3141 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3142 1, &rt5677_pdm1_l_mux),
3143 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3144 1, &rt5677_pdm1_r_mux),
3145 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3146 1, &rt5677_pdm2_l_mux),
3147 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3148 1, &rt5677_pdm2_r_mux),
3150 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3152 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3154 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3157 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3158 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3159 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3160 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3161 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3162 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3165 SND_SOC_DAPM_OUTPUT("LOUT1"),
3166 SND_SOC_DAPM_OUTPUT("LOUT2"),
3167 SND_SOC_DAPM_OUTPUT("LOUT3"),
3168 SND_SOC_DAPM_OUTPUT("PDM1L"),
3169 SND_SOC_DAPM_OUTPUT("PDM1R"),
3170 SND_SOC_DAPM_OUTPUT("PDM2L"),
3171 SND_SOC_DAPM_OUTPUT("PDM2R"),
3173 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3176 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3177 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3178 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3179 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3180 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3181 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3182 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3183 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3184 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3185 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3186 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3188 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3189 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3190 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3191 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3192 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3193 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3194 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3195 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3196 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3197 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3198 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3199 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3200 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3202 { "DMIC1", NULL, "DMIC L1" },
3203 { "DMIC1", NULL, "DMIC R1" },
3204 { "DMIC2", NULL, "DMIC L2" },
3205 { "DMIC2", NULL, "DMIC R2" },
3206 { "DMIC3", NULL, "DMIC L3" },
3207 { "DMIC3", NULL, "DMIC R3" },
3208 { "DMIC4", NULL, "DMIC L4" },
3209 { "DMIC4", NULL, "DMIC R4" },
3211 { "DMIC L1", NULL, "DMIC CLK" },
3212 { "DMIC R1", NULL, "DMIC CLK" },
3213 { "DMIC L2", NULL, "DMIC CLK" },
3214 { "DMIC R2", NULL, "DMIC CLK" },
3215 { "DMIC L3", NULL, "DMIC CLK" },
3216 { "DMIC R3", NULL, "DMIC CLK" },
3217 { "DMIC L4", NULL, "DMIC CLK" },
3218 { "DMIC R4", NULL, "DMIC CLK" },
3220 { "DMIC L1", NULL, "DMIC1 power" },
3221 { "DMIC R1", NULL, "DMIC1 power" },
3222 { "DMIC L3", NULL, "DMIC3 power" },
3223 { "DMIC R3", NULL, "DMIC3 power" },
3224 { "DMIC L4", NULL, "DMIC4 power" },
3225 { "DMIC R4", NULL, "DMIC4 power" },
3227 { "BST1", NULL, "IN1P" },
3228 { "BST1", NULL, "IN1N" },
3229 { "BST2", NULL, "IN2P" },
3230 { "BST2", NULL, "IN2N" },
3232 { "IN1P", NULL, "MICBIAS1" },
3233 { "IN1N", NULL, "MICBIAS1" },
3234 { "IN2P", NULL, "MICBIAS1" },
3235 { "IN2N", NULL, "MICBIAS1" },
3237 { "ADC 1", NULL, "BST1" },
3238 { "ADC 1", NULL, "ADC 1 power" },
3239 { "ADC 1", NULL, "ADC1 clock" },
3240 { "ADC 2", NULL, "BST2" },
3241 { "ADC 2", NULL, "ADC 2 power" },
3242 { "ADC 2", NULL, "ADC2 clock" },
3244 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3245 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3246 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3247 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3249 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3250 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3251 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3252 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3254 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3255 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3256 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3257 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3259 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3260 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3261 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3262 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3264 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3265 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3266 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3267 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3269 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3270 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3271 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3272 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3274 { "ADC 1_2", NULL, "ADC 1" },
3275 { "ADC 1_2", NULL, "ADC 2" },
3277 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3278 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3279 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3282 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3283 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3286 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3287 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3289 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3290 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3291 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3293 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3294 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3295 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3297 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3298 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3299 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3301 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3302 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3303 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3305 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3306 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3307 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3309 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3310 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3311 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3313 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3314 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3315 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3317 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3318 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3319 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3321 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3322 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3323 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3325 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3326 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3327 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3328 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3330 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3331 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3332 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3333 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3334 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3336 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3337 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3339 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3340 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3341 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3342 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3344 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3345 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3347 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3348 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3350 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3351 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3352 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3353 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3354 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3356 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3357 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3359 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3360 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3361 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3362 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3364 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3365 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3366 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3367 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3368 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3370 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3371 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3373 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3374 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3375 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3376 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3378 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3379 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3380 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3381 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3382 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3384 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3385 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3387 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3388 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3389 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3390 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3392 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3393 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3394 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3395 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3397 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3398 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3400 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3401 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3402 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3403 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3404 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3406 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3407 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3408 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3410 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3411 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3413 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3414 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3415 { "IF1 ADC3 Mux", "OB45", "OB45" },
3417 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3418 { "IF1 ADC4 Mux", "OB67", "OB67" },
3419 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3421 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3422 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3423 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3424 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3426 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3427 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3428 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3429 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3431 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3432 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3433 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3434 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3436 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3437 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3438 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3439 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3441 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3442 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3443 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3444 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3446 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3447 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3448 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3449 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3450 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3451 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3452 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3453 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3455 { "AIF1TX", NULL, "I2S1" },
3456 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3458 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3459 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3460 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3462 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3463 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3465 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3466 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3467 { "IF2 ADC3 Mux", "OB45", "OB45" },
3469 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3470 { "IF2 ADC4 Mux", "OB67", "OB67" },
3471 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3473 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3474 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3475 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3476 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3478 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3479 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3480 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3481 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3483 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3484 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3485 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3486 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3488 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3489 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3490 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3491 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3493 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3494 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3495 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3496 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3498 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3499 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3500 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3501 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3502 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3503 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3504 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3505 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3507 { "AIF2TX", NULL, "I2S2" },
3508 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3510 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3511 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3512 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3513 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3514 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3515 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3516 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3517 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3519 { "AIF3TX", NULL, "I2S3" },
3520 { "AIF3TX", NULL, "IF3 ADC Mux" },
3522 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3523 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3524 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3525 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3526 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3527 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3528 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3529 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3531 { "AIF4TX", NULL, "I2S4" },
3532 { "AIF4TX", NULL, "IF4 ADC Mux" },
3534 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3535 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3536 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3538 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3539 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3541 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3542 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3543 { "SLB ADC3 Mux", "OB45", "OB45" },
3545 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3546 { "SLB ADC4 Mux", "OB67", "OB67" },
3547 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3549 { "SLBTX", NULL, "SLB" },
3550 { "SLBTX", NULL, "SLB ADC1 Mux" },
3551 { "SLBTX", NULL, "SLB ADC2 Mux" },
3552 { "SLBTX", NULL, "SLB ADC3 Mux" },
3553 { "SLBTX", NULL, "SLB ADC4 Mux" },
3555 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3556 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3557 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3558 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3559 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3561 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3562 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3564 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3565 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3566 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3567 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3568 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3569 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3571 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3572 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3574 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3575 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3576 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3577 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3578 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3580 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3581 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3583 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3584 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3585 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3586 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3587 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3588 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3589 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3590 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3592 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3593 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3594 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3595 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3596 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3597 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3598 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3599 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3601 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3602 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3603 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3604 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3605 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3606 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3608 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3609 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3610 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3611 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3612 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3613 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3614 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3616 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3617 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3618 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3619 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3620 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3621 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3622 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3624 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3625 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3626 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3627 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3628 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3629 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3630 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3632 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3633 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3634 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3635 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3636 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3637 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3638 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3640 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3641 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3642 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3643 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3644 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3645 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3646 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3648 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3649 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3650 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3651 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3652 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3653 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3654 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3656 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3657 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3658 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3659 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3660 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3661 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3662 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3664 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3665 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3666 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3667 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3669 { "OutBound2", NULL, "OB23 Bypass Mux" },
3670 { "OutBound3", NULL, "OB23 Bypass Mux" },
3671 { "OutBound4", NULL, "OB4 MIX" },
3672 { "OutBound5", NULL, "OB5 MIX" },
3673 { "OutBound6", NULL, "OB6 MIX" },
3674 { "OutBound7", NULL, "OB7 MIX" },
3676 { "OB45", NULL, "OutBound4" },
3677 { "OB45", NULL, "OutBound5" },
3678 { "OB67", NULL, "OutBound6" },
3679 { "OB67", NULL, "OutBound7" },
3681 { "IF1 DAC0", NULL, "AIF1RX" },
3682 { "IF1 DAC1", NULL, "AIF1RX" },
3683 { "IF1 DAC2", NULL, "AIF1RX" },
3684 { "IF1 DAC3", NULL, "AIF1RX" },
3685 { "IF1 DAC4", NULL, "AIF1RX" },
3686 { "IF1 DAC5", NULL, "AIF1RX" },
3687 { "IF1 DAC6", NULL, "AIF1RX" },
3688 { "IF1 DAC7", NULL, "AIF1RX" },
3689 { "IF1 DAC0", NULL, "I2S1" },
3690 { "IF1 DAC1", NULL, "I2S1" },
3691 { "IF1 DAC2", NULL, "I2S1" },
3692 { "IF1 DAC3", NULL, "I2S1" },
3693 { "IF1 DAC4", NULL, "I2S1" },
3694 { "IF1 DAC5", NULL, "I2S1" },
3695 { "IF1 DAC6", NULL, "I2S1" },
3696 { "IF1 DAC7", NULL, "I2S1" },
3698 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3699 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3700 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3701 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3702 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3703 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3704 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3705 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3707 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3708 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3709 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3710 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3711 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3712 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3713 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3714 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3716 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3717 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3718 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3719 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3720 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3721 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3722 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3723 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3725 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3726 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3727 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3728 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3729 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3730 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3731 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3732 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3734 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3735 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3736 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3737 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3738 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3739 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3740 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3741 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3743 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3744 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3745 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3746 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3747 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3748 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3749 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3750 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3752 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3753 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3754 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3755 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3756 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3757 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3758 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3759 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3761 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3762 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3763 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3764 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3765 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3766 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3767 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3768 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3770 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3771 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3772 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3773 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3774 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3775 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3776 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3777 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3779 { "IF2 DAC0", NULL, "AIF2RX" },
3780 { "IF2 DAC1", NULL, "AIF2RX" },
3781 { "IF2 DAC2", NULL, "AIF2RX" },
3782 { "IF2 DAC3", NULL, "AIF2RX" },
3783 { "IF2 DAC4", NULL, "AIF2RX" },
3784 { "IF2 DAC5", NULL, "AIF2RX" },
3785 { "IF2 DAC6", NULL, "AIF2RX" },
3786 { "IF2 DAC7", NULL, "AIF2RX" },
3787 { "IF2 DAC0", NULL, "I2S2" },
3788 { "IF2 DAC1", NULL, "I2S2" },
3789 { "IF2 DAC2", NULL, "I2S2" },
3790 { "IF2 DAC3", NULL, "I2S2" },
3791 { "IF2 DAC4", NULL, "I2S2" },
3792 { "IF2 DAC5", NULL, "I2S2" },
3793 { "IF2 DAC6", NULL, "I2S2" },
3794 { "IF2 DAC7", NULL, "I2S2" },
3796 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3797 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3798 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3799 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3800 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3801 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3802 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3803 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3805 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3806 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3807 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3808 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3809 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3810 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3811 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3812 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3814 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3815 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3816 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3817 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3818 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3819 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3820 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3821 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3823 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3824 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3825 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3826 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3827 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3828 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3829 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3830 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3832 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3833 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3834 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3835 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3836 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3837 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3838 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3839 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3841 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3842 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3843 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3844 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3845 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3846 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3847 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3848 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3850 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3851 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3852 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3853 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3854 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3855 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3856 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3857 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3859 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3860 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3861 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3862 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3863 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3864 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3865 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3866 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3868 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3869 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3870 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3871 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3872 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3873 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3874 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3875 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3877 { "IF3 DAC", NULL, "AIF3RX" },
3878 { "IF3 DAC", NULL, "I2S3" },
3880 { "IF4 DAC", NULL, "AIF4RX" },
3881 { "IF4 DAC", NULL, "I2S4" },
3883 { "IF3 DAC L", NULL, "IF3 DAC" },
3884 { "IF3 DAC R", NULL, "IF3 DAC" },
3886 { "IF4 DAC L", NULL, "IF4 DAC" },
3887 { "IF4 DAC R", NULL, "IF4 DAC" },
3889 { "SLB DAC0", NULL, "SLBRX" },
3890 { "SLB DAC1", NULL, "SLBRX" },
3891 { "SLB DAC2", NULL, "SLBRX" },
3892 { "SLB DAC3", NULL, "SLBRX" },
3893 { "SLB DAC4", NULL, "SLBRX" },
3894 { "SLB DAC5", NULL, "SLBRX" },
3895 { "SLB DAC6", NULL, "SLBRX" },
3896 { "SLB DAC7", NULL, "SLBRX" },
3897 { "SLB DAC0", NULL, "SLB" },
3898 { "SLB DAC1", NULL, "SLB" },
3899 { "SLB DAC2", NULL, "SLB" },
3900 { "SLB DAC3", NULL, "SLB" },
3901 { "SLB DAC4", NULL, "SLB" },
3902 { "SLB DAC5", NULL, "SLB" },
3903 { "SLB DAC6", NULL, "SLB" },
3904 { "SLB DAC7", NULL, "SLB" },
3906 { "SLB DAC01", NULL, "SLB DAC0" },
3907 { "SLB DAC01", NULL, "SLB DAC1" },
3908 { "SLB DAC23", NULL, "SLB DAC2" },
3909 { "SLB DAC23", NULL, "SLB DAC3" },
3910 { "SLB DAC45", NULL, "SLB DAC4" },
3911 { "SLB DAC45", NULL, "SLB DAC5" },
3912 { "SLB DAC67", NULL, "SLB DAC6" },
3913 { "SLB DAC67", NULL, "SLB DAC7" },
3915 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3916 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3917 { "ADDA1 Mux", "OB 67", "OB67" },
3919 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3920 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3921 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3922 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3923 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3924 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3926 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3927 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3928 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3929 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3931 { "DAC1 FS", NULL, "DAC1 MIXL" },
3932 { "DAC1 FS", NULL, "DAC1 MIXR" },
3934 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3935 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3936 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3937 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3938 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3939 { "DAC2 L Mux", "OB 2", "OutBound2" },
3941 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3942 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3943 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3944 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3945 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3946 { "DAC2 R Mux", "OB 3", "OutBound3" },
3947 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3948 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3950 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3951 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3952 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3953 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3954 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3955 { "DAC3 L Mux", "OB 4", "OutBound4" },
3957 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3958 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3959 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3960 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3961 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3962 { "DAC3 R Mux", "OB 5", "OutBound5" },
3964 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3965 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3966 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3967 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3968 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3969 { "DAC4 L Mux", "OB 6", "OutBound6" },
3971 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3972 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3973 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3974 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3975 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3976 { "DAC4 R Mux", "OB 7", "OutBound7" },
3978 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3979 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3980 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3981 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3982 { "Sidetone Mux", "ADC1", "ADC 1" },
3983 { "Sidetone Mux", "ADC2", "ADC 2" },
3984 { "Sidetone Mux", NULL, "Sidetone Power" },
3986 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3987 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3988 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3989 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3990 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3991 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3992 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3993 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3994 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3995 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3996 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3998 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3999 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
4000 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
4001 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
4002 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
4003 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4004 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
4005 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
4006 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4007 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
4008 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
4009 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4011 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4012 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4013 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4014 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4015 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4016 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4017 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4018 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4019 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4020 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4021 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4022 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4024 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4025 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4026 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4027 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4028 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4029 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4030 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4031 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4032 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4033 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4034 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4035 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4037 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4038 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4039 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4040 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4041 { "DD1 MIX", NULL, "DD1 MIXL" },
4042 { "DD1 MIX", NULL, "DD1 MIXR" },
4043 { "DD2 MIX", NULL, "DD2 MIXL" },
4044 { "DD2 MIX", NULL, "DD2 MIXR" },
4046 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4047 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4048 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4049 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4051 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4052 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4053 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4054 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4056 { "DAC 1", NULL, "DAC12 SRC Mux" },
4057 { "DAC 2", NULL, "DAC12 SRC Mux" },
4058 { "DAC 3", NULL, "DAC3 SRC Mux" },
4060 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4061 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4062 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4063 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4064 { "PDM1 L Mux", NULL, "PDM1 Power" },
4065 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4066 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4067 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4068 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4069 { "PDM1 R Mux", NULL, "PDM1 Power" },
4070 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4071 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4072 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4073 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4074 { "PDM2 L Mux", NULL, "PDM2 Power" },
4075 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4076 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4077 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4078 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4079 { "PDM2 R Mux", NULL, "PDM2 Power" },
4081 { "LOUT1 amp", NULL, "DAC 1" },
4082 { "LOUT2 amp", NULL, "DAC 2" },
4083 { "LOUT3 amp", NULL, "DAC 3" },
4085 { "LOUT1 vref", NULL, "LOUT1 amp" },
4086 { "LOUT2 vref", NULL, "LOUT2 amp" },
4087 { "LOUT3 vref", NULL, "LOUT3 amp" },
4089 { "LOUT1", NULL, "LOUT1 vref" },
4090 { "LOUT2", NULL, "LOUT2 vref" },
4091 { "LOUT3", NULL, "LOUT3 vref" },
4093 { "PDM1L", NULL, "PDM1 L Mux" },
4094 { "PDM1R", NULL, "PDM1 R Mux" },
4095 { "PDM2L", NULL, "PDM2 L Mux" },
4096 { "PDM2R", NULL, "PDM2 R Mux" },
4099 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4100 { "DMIC L2", NULL, "DMIC1 power" },
4101 { "DMIC R2", NULL, "DMIC1 power" },
4104 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4105 { "DMIC L2", NULL, "DMIC2 power" },
4106 { "DMIC R2", NULL, "DMIC2 power" },
4109 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4110 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4112 struct snd_soc_codec *codec = dai->codec;
4113 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4114 unsigned int val_len = 0, val_clk, mask_clk;
4115 int pre_div, bclk_ms, frame_size;
4117 rt5677->lrck[dai->id] = params_rate(params);
4118 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4120 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4121 rt5677->sysclk, rt5677->lrck[dai->id]);
4124 frame_size = snd_soc_params_to_frame_size(params);
4125 if (frame_size < 0) {
4126 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4129 bclk_ms = frame_size > 32;
4130 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4132 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4133 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4134 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4135 bclk_ms, pre_div, dai->id);
4137 switch (params_width(params)) {
4141 val_len |= RT5677_I2S_DL_20;
4144 val_len |= RT5677_I2S_DL_24;
4147 val_len |= RT5677_I2S_DL_8;
4155 mask_clk = RT5677_I2S_PD1_MASK;
4156 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4157 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4158 RT5677_I2S_DL_MASK, val_len);
4159 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4163 mask_clk = RT5677_I2S_PD2_MASK;
4164 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4165 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4166 RT5677_I2S_DL_MASK, val_len);
4167 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4171 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4172 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4173 pre_div << RT5677_I2S_PD3_SFT;
4174 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4175 RT5677_I2S_DL_MASK, val_len);
4176 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4180 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4181 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4182 pre_div << RT5677_I2S_PD4_SFT;
4183 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4184 RT5677_I2S_DL_MASK, val_len);
4185 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4195 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4197 struct snd_soc_codec *codec = dai->codec;
4198 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4199 unsigned int reg_val = 0;
4201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4202 case SND_SOC_DAIFMT_CBM_CFM:
4203 rt5677->master[dai->id] = 1;
4205 case SND_SOC_DAIFMT_CBS_CFS:
4206 reg_val |= RT5677_I2S_MS_S;
4207 rt5677->master[dai->id] = 0;
4213 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4214 case SND_SOC_DAIFMT_NB_NF:
4216 case SND_SOC_DAIFMT_IB_NF:
4217 reg_val |= RT5677_I2S_BP_INV;
4223 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4224 case SND_SOC_DAIFMT_I2S:
4226 case SND_SOC_DAIFMT_LEFT_J:
4227 reg_val |= RT5677_I2S_DF_LEFT;
4229 case SND_SOC_DAIFMT_DSP_A:
4230 reg_val |= RT5677_I2S_DF_PCM_A;
4232 case SND_SOC_DAIFMT_DSP_B:
4233 reg_val |= RT5677_I2S_DF_PCM_B;
4241 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4242 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4243 RT5677_I2S_DF_MASK, reg_val);
4246 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4247 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4248 RT5677_I2S_DF_MASK, reg_val);
4251 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4252 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4253 RT5677_I2S_DF_MASK, reg_val);
4256 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4257 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4258 RT5677_I2S_DF_MASK, reg_val);
4268 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4269 int clk_id, unsigned int freq, int dir)
4271 struct snd_soc_codec *codec = dai->codec;
4272 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4273 unsigned int reg_val = 0;
4275 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4279 case RT5677_SCLK_S_MCLK:
4280 reg_val |= RT5677_SCLK_SRC_MCLK;
4282 case RT5677_SCLK_S_PLL1:
4283 reg_val |= RT5677_SCLK_SRC_PLL1;
4285 case RT5677_SCLK_S_RCCLK:
4286 reg_val |= RT5677_SCLK_SRC_RCCLK;
4289 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4292 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4293 RT5677_SCLK_SRC_MASK, reg_val);
4294 rt5677->sysclk = freq;
4295 rt5677->sysclk_src = clk_id;
4297 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4303 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4304 * @freq_in: external clock provided to codec.
4305 * @freq_out: target clock which codec works on.
4306 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4308 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4310 * Returns 0 for success or negative error code.
4312 static int rt5677_pll_calc(const unsigned int freq_in,
4313 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4315 if (RT5677_PLL_INP_MIN > freq_in)
4318 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4321 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4322 unsigned int freq_in, unsigned int freq_out)
4324 struct snd_soc_codec *codec = dai->codec;
4325 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4326 struct rl6231_pll_code pll_code;
4329 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4330 freq_out == rt5677->pll_out)
4333 if (!freq_in || !freq_out) {
4334 dev_dbg(codec->dev, "PLL disabled\n");
4337 rt5677->pll_out = 0;
4338 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4339 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4344 case RT5677_PLL1_S_MCLK:
4345 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4346 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4348 case RT5677_PLL1_S_BCLK1:
4349 case RT5677_PLL1_S_BCLK2:
4350 case RT5677_PLL1_S_BCLK3:
4351 case RT5677_PLL1_S_BCLK4:
4354 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4355 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4358 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4359 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4362 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4363 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4366 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4367 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4374 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4378 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4380 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4384 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4385 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4386 pll_code.n_code, pll_code.k_code);
4388 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4389 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4390 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4391 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4392 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4394 rt5677->pll_in = freq_in;
4395 rt5677->pll_out = freq_out;
4396 rt5677->pll_src = source;
4401 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4402 unsigned int rx_mask, int slots, int slot_width)
4404 struct snd_soc_codec *codec = dai->codec;
4405 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4406 unsigned int val = 0, slot_width_25 = 0;
4408 if (rx_mask || tx_mask)
4426 switch (slot_width) {
4431 slot_width_25 = 0x8080;
4445 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4447 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4451 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4453 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4463 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4464 enum snd_soc_bias_level level)
4466 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4469 case SND_SOC_BIAS_ON:
4472 case SND_SOC_BIAS_PREPARE:
4473 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4474 rt5677_set_dsp_vad(codec, false);
4476 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4477 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4479 regmap_update_bits(rt5677->regmap,
4480 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4482 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4483 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4484 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4485 RT5677_PWR_BG | RT5677_PWR_VREF2,
4486 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4487 RT5677_PWR_BG | RT5677_PWR_VREF2);
4488 rt5677->is_vref_slow = false;
4489 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4490 RT5677_PWR_CORE, RT5677_PWR_CORE);
4491 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4496 case SND_SOC_BIAS_STANDBY:
4499 case SND_SOC_BIAS_OFF:
4500 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4501 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4502 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4503 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4504 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4505 regmap_update_bits(rt5677->regmap,
4506 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4508 if (rt5677->dsp_vad_en)
4509 rt5677_set_dsp_vad(codec, true);
4519 #ifdef CONFIG_GPIOLIB
4520 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4522 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4525 case RT5677_GPIO1 ... RT5677_GPIO5:
4526 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4527 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4531 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4532 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4540 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4541 unsigned offset, int value)
4543 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4546 case RT5677_GPIO1 ... RT5677_GPIO5:
4547 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4548 0x3 << (offset * 3 + 1),
4549 (0x2 | !!value) << (offset * 3 + 1));
4553 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4554 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4555 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4565 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4567 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4570 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4574 return (value & (0x1 << offset)) >> offset;
4577 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4579 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4582 case RT5677_GPIO1 ... RT5677_GPIO5:
4583 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4584 0x1 << (offset * 3 + 2), 0x0);
4588 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4589 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4599 /** Configures the gpio as
4604 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4610 case RT5677_GPIO1 ... RT5677_GPIO2:
4611 shift = 2 * (1 - offset);
4612 regmap_update_bits(rt5677->regmap,
4613 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4615 (value & 0x3) << shift);
4618 case RT5677_GPIO3 ... RT5677_GPIO6:
4619 shift = 2 * (9 - offset);
4620 regmap_update_bits(rt5677->regmap,
4621 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4623 (value & 0x3) << shift);
4631 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4633 struct rt5677_priv *rt5677 = gpiochip_get_data(chip);
4634 struct regmap_irq_chip_data *data = rt5677->irq_data;
4637 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4638 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4639 (rt5677->pdata.jd1_gpio == 2 &&
4640 offset == RT5677_GPIO2) ||
4641 (rt5677->pdata.jd1_gpio == 3 &&
4642 offset == RT5677_GPIO3)) {
4643 irq = RT5677_IRQ_JD1;
4649 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4650 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4651 (rt5677->pdata.jd2_gpio == 2 &&
4652 offset == RT5677_GPIO5) ||
4653 (rt5677->pdata.jd2_gpio == 3 &&
4654 offset == RT5677_GPIO6)) {
4655 irq = RT5677_IRQ_JD2;
4656 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4657 offset == RT5677_GPIO4) ||
4658 (rt5677->pdata.jd3_gpio == 2 &&
4659 offset == RT5677_GPIO5) ||
4660 (rt5677->pdata.jd3_gpio == 3 &&
4661 offset == RT5677_GPIO6)) {
4662 irq = RT5677_IRQ_JD3;
4668 return regmap_irq_get_virq(data, irq);
4671 static const struct gpio_chip rt5677_template_chip = {
4673 .owner = THIS_MODULE,
4674 .direction_output = rt5677_gpio_direction_out,
4675 .set = rt5677_gpio_set,
4676 .direction_input = rt5677_gpio_direction_in,
4677 .get = rt5677_gpio_get,
4678 .to_irq = rt5677_to_irq,
4682 static void rt5677_init_gpio(struct i2c_client *i2c)
4684 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4687 rt5677->gpio_chip = rt5677_template_chip;
4688 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4689 rt5677->gpio_chip.parent = &i2c->dev;
4690 rt5677->gpio_chip.base = -1;
4692 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677);
4694 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4697 static void rt5677_free_gpio(struct i2c_client *i2c)
4699 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4701 gpiochip_remove(&rt5677->gpio_chip);
4704 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4709 static void rt5677_init_gpio(struct i2c_client *i2c)
4713 static void rt5677_free_gpio(struct i2c_client *i2c)
4718 static int rt5677_probe(struct snd_soc_codec *codec)
4720 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4721 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4724 rt5677->codec = codec;
4726 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4727 snd_soc_dapm_add_routes(dapm,
4729 ARRAY_SIZE(rt5677_dmic2_clk_2));
4730 } else { /*use dmic1 clock by default*/
4731 snd_soc_dapm_add_routes(dapm,
4733 ARRAY_SIZE(rt5677_dmic2_clk_1));
4736 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4738 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4739 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4741 for (i = 0; i < RT5677_GPIO_NUM; i++)
4742 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4744 if (rt5677->irq_data) {
4745 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4747 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4750 if (rt5677->pdata.jd1_gpio)
4751 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4752 RT5677_SEL_GPIO_JD1_MASK,
4753 rt5677->pdata.jd1_gpio <<
4754 RT5677_SEL_GPIO_JD1_SFT);
4756 if (rt5677->pdata.jd2_gpio)
4757 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4758 RT5677_SEL_GPIO_JD2_MASK,
4759 rt5677->pdata.jd2_gpio <<
4760 RT5677_SEL_GPIO_JD2_SFT);
4762 if (rt5677->pdata.jd3_gpio)
4763 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4764 RT5677_SEL_GPIO_JD3_MASK,
4765 rt5677->pdata.jd3_gpio <<
4766 RT5677_SEL_GPIO_JD3_SFT);
4769 mutex_init(&rt5677->dsp_cmd_lock);
4770 mutex_init(&rt5677->dsp_pri_lock);
4775 static int rt5677_remove(struct snd_soc_codec *codec)
4777 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4779 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4780 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4781 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4787 static int rt5677_suspend(struct snd_soc_codec *codec)
4789 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4791 if (!rt5677->dsp_vad_en) {
4792 regcache_cache_only(rt5677->regmap, true);
4793 regcache_mark_dirty(rt5677->regmap);
4795 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4796 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4802 static int rt5677_resume(struct snd_soc_codec *codec)
4804 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4806 if (!rt5677->dsp_vad_en) {
4807 rt5677->pll_src = 0;
4809 rt5677->pll_out = 0;
4810 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4811 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4812 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4815 regcache_cache_only(rt5677->regmap, false);
4816 regcache_sync(rt5677->regmap);
4822 #define rt5677_suspend NULL
4823 #define rt5677_resume NULL
4826 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4828 struct i2c_client *client = context;
4829 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4831 if (rt5677->is_dsp_mode) {
4833 mutex_lock(&rt5677->dsp_pri_lock);
4834 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4836 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4837 mutex_unlock(&rt5677->dsp_pri_lock);
4839 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4842 regmap_read(rt5677->regmap_physical, reg, val);
4848 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4850 struct i2c_client *client = context;
4851 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4853 if (rt5677->is_dsp_mode) {
4855 mutex_lock(&rt5677->dsp_pri_lock);
4856 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4858 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4860 mutex_unlock(&rt5677->dsp_pri_lock);
4862 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4865 regmap_write(rt5677->regmap_physical, reg, val);
4871 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4872 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4873 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4875 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4876 .hw_params = rt5677_hw_params,
4877 .set_fmt = rt5677_set_dai_fmt,
4878 .set_sysclk = rt5677_set_dai_sysclk,
4879 .set_pll = rt5677_set_dai_pll,
4880 .set_tdm_slot = rt5677_set_tdm_slot,
4883 static struct snd_soc_dai_driver rt5677_dai[] = {
4885 .name = "rt5677-aif1",
4888 .stream_name = "AIF1 Playback",
4891 .rates = RT5677_STEREO_RATES,
4892 .formats = RT5677_FORMATS,
4895 .stream_name = "AIF1 Capture",
4898 .rates = RT5677_STEREO_RATES,
4899 .formats = RT5677_FORMATS,
4901 .ops = &rt5677_aif_dai_ops,
4904 .name = "rt5677-aif2",
4907 .stream_name = "AIF2 Playback",
4910 .rates = RT5677_STEREO_RATES,
4911 .formats = RT5677_FORMATS,
4914 .stream_name = "AIF2 Capture",
4917 .rates = RT5677_STEREO_RATES,
4918 .formats = RT5677_FORMATS,
4920 .ops = &rt5677_aif_dai_ops,
4923 .name = "rt5677-aif3",
4926 .stream_name = "AIF3 Playback",
4929 .rates = RT5677_STEREO_RATES,
4930 .formats = RT5677_FORMATS,
4933 .stream_name = "AIF3 Capture",
4936 .rates = RT5677_STEREO_RATES,
4937 .formats = RT5677_FORMATS,
4939 .ops = &rt5677_aif_dai_ops,
4942 .name = "rt5677-aif4",
4945 .stream_name = "AIF4 Playback",
4948 .rates = RT5677_STEREO_RATES,
4949 .formats = RT5677_FORMATS,
4952 .stream_name = "AIF4 Capture",
4955 .rates = RT5677_STEREO_RATES,
4956 .formats = RT5677_FORMATS,
4958 .ops = &rt5677_aif_dai_ops,
4961 .name = "rt5677-slimbus",
4964 .stream_name = "SLIMBus Playback",
4967 .rates = RT5677_STEREO_RATES,
4968 .formats = RT5677_FORMATS,
4971 .stream_name = "SLIMBus Capture",
4974 .rates = RT5677_STEREO_RATES,
4975 .formats = RT5677_FORMATS,
4977 .ops = &rt5677_aif_dai_ops,
4981 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4982 .probe = rt5677_probe,
4983 .remove = rt5677_remove,
4984 .suspend = rt5677_suspend,
4985 .resume = rt5677_resume,
4986 .set_bias_level = rt5677_set_bias_level,
4987 .idle_bias_off = true,
4988 .component_driver = {
4989 .controls = rt5677_snd_controls,
4990 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4991 .dapm_widgets = rt5677_dapm_widgets,
4992 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4993 .dapm_routes = rt5677_dapm_routes,
4994 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4998 static const struct regmap_config rt5677_regmap_physical = {
5003 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5005 .readable_reg = rt5677_readable_register,
5007 .cache_type = REGCACHE_NONE,
5008 .ranges = rt5677_ranges,
5009 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5012 static const struct regmap_config rt5677_regmap = {
5016 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5019 .volatile_reg = rt5677_volatile_register,
5020 .readable_reg = rt5677_readable_register,
5021 .reg_read = rt5677_read,
5022 .reg_write = rt5677_write,
5024 .cache_type = REGCACHE_RBTREE,
5025 .reg_defaults = rt5677_reg,
5026 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5027 .ranges = rt5677_ranges,
5028 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5031 static const struct i2c_device_id rt5677_i2c_id[] = {
5032 { "rt5677", RT5677 },
5033 { "rt5676", RT5676 },
5034 { "RT5677CE:00", RT5677 },
5037 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5039 static const struct of_device_id rt5677_of_match[] = {
5040 { .compatible = "realtek,rt5677", },
5043 MODULE_DEVICE_TABLE(of, rt5677_of_match);
5045 static const struct acpi_gpio_params plug_det_gpio = { RT5677_GPIO_PLUG_DET, 0, false };
5046 static const struct acpi_gpio_params mic_present_gpio = { RT5677_GPIO_MIC_PRESENT_L, 0, false };
5047 static const struct acpi_gpio_params headphone_enable_gpio = { RT5677_GPIO_HP_AMP_SHDN_L, 0, false };
5049 static const struct acpi_gpio_mapping bdw_rt5677_gpios[] = {
5050 { "plug-det-gpios", &plug_det_gpio, 1 },
5051 { "mic-present-gpios", &mic_present_gpio, 1 },
5052 { "headphone-enable-gpios", &headphone_enable_gpio, 1 },
5056 static void rt5677_read_acpi_properties(struct rt5677_priv *rt5677,
5062 ret = acpi_dev_add_driver_gpios(ACPI_COMPANION(dev),
5065 dev_warn(dev, "Failed to add driver gpios\n");
5067 if (!device_property_read_u32(dev, "DCLK", &val))
5068 rt5677->pdata.dmic2_clk_pin = val;
5070 rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1");
5071 rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2");
5072 rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1");
5073 rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2");
5074 rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3");
5076 device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio);
5077 device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio);
5078 device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio);
5081 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5084 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5085 "realtek,in1-differential");
5086 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5087 "realtek,in2-differential");
5088 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5089 "realtek,lout1-differential");
5090 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5091 "realtek,lout2-differential");
5092 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5093 "realtek,lout3-differential");
5095 device_property_read_u8_array(dev, "realtek,gpio-config",
5096 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5098 device_property_read_u32(dev, "realtek,jd1-gpio",
5099 &rt5677->pdata.jd1_gpio);
5100 device_property_read_u32(dev, "realtek,jd2-gpio",
5101 &rt5677->pdata.jd2_gpio);
5102 device_property_read_u32(dev, "realtek,jd3-gpio",
5103 &rt5677->pdata.jd3_gpio);
5106 static struct regmap_irq rt5677_irqs[] = {
5107 [RT5677_IRQ_JD1] = {
5109 .mask = RT5677_EN_IRQ_GPIO_JD1,
5111 [RT5677_IRQ_JD2] = {
5113 .mask = RT5677_EN_IRQ_GPIO_JD2,
5115 [RT5677_IRQ_JD3] = {
5117 .mask = RT5677_EN_IRQ_GPIO_JD3,
5121 static struct regmap_irq_chip rt5677_irq_chip = {
5123 .irqs = rt5677_irqs,
5124 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5127 .status_base = RT5677_IRQ_CTRL1,
5128 .mask_base = RT5677_IRQ_CTRL1,
5132 static int rt5677_init_irq(struct i2c_client *i2c)
5135 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5137 if (!rt5677->pdata.jd1_gpio &&
5138 !rt5677->pdata.jd2_gpio &&
5139 !rt5677->pdata.jd3_gpio)
5143 dev_err(&i2c->dev, "No interrupt specified\n");
5147 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5148 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5149 &rt5677_irq_chip, &rt5677->irq_data);
5152 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5159 static void rt5677_free_irq(struct i2c_client *i2c)
5161 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5163 if (rt5677->irq_data)
5164 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5167 static int rt5677_i2c_probe(struct i2c_client *i2c,
5168 const struct i2c_device_id *id)
5170 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5171 struct rt5677_priv *rt5677;
5175 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5180 i2c_set_clientdata(i2c, rt5677);
5182 rt5677->type = id->driver_data;
5185 rt5677->pdata = *pdata;
5186 else if (i2c->dev.of_node)
5187 rt5677_read_device_properties(rt5677, &i2c->dev);
5188 else if (ACPI_HANDLE(&i2c->dev))
5189 rt5677_read_acpi_properties(rt5677, &i2c->dev);
5193 /* pow-ldo2 and reset are optional. The codec pins may be statically
5194 * connected on the board without gpios. If the gpio device property
5195 * isn't specified, devm_gpiod_get_optional returns NULL.
5197 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5198 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5199 if (IS_ERR(rt5677->pow_ldo2)) {
5200 ret = PTR_ERR(rt5677->pow_ldo2);
5201 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5204 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5205 "realtek,reset", GPIOD_OUT_LOW);
5206 if (IS_ERR(rt5677->reset_pin)) {
5207 ret = PTR_ERR(rt5677->reset_pin);
5208 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5212 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5213 /* Wait a while until I2C bus becomes available. The datasheet
5214 * does not specify the exact we should wait but startup
5215 * sequence mentiones at least a few milliseconds.
5220 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5221 &rt5677_regmap_physical);
5222 if (IS_ERR(rt5677->regmap_physical)) {
5223 ret = PTR_ERR(rt5677->regmap_physical);
5224 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5229 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5230 if (IS_ERR(rt5677->regmap)) {
5231 ret = PTR_ERR(rt5677->regmap);
5232 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5237 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5238 if (val != RT5677_DEVICE_ID) {
5240 "Device with ID register %#x is not rt5677\n", val);
5244 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5246 ret = regmap_register_patch(rt5677->regmap, init_list,
5247 ARRAY_SIZE(init_list));
5249 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5251 if (rt5677->pdata.in1_diff)
5252 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5253 RT5677_IN_DF1, RT5677_IN_DF1);
5255 if (rt5677->pdata.in2_diff)
5256 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5257 RT5677_IN_DF2, RT5677_IN_DF2);
5259 if (rt5677->pdata.lout1_diff)
5260 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5261 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5263 if (rt5677->pdata.lout2_diff)
5264 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5265 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5267 if (rt5677->pdata.lout3_diff)
5268 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5269 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5271 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5272 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5273 RT5677_GPIO5_FUNC_MASK,
5274 RT5677_GPIO5_FUNC_DMIC);
5275 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5276 RT5677_GPIO5_DIR_MASK,
5277 RT5677_GPIO5_DIR_OUT);
5280 if (rt5677->pdata.micbias1_vdd_3v3)
5281 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5282 RT5677_MICBIAS1_CTRL_VDD_MASK,
5283 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5285 rt5677_init_gpio(i2c);
5286 rt5677_init_irq(i2c);
5288 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5289 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5292 static int rt5677_i2c_remove(struct i2c_client *i2c)
5294 snd_soc_unregister_codec(&i2c->dev);
5295 rt5677_free_irq(i2c);
5296 rt5677_free_gpio(i2c);
5301 static struct i2c_driver rt5677_i2c_driver = {
5304 .of_match_table = rt5677_of_match,
5306 .probe = rt5677_i2c_probe,
5307 .remove = rt5677_i2c_remove,
5308 .id_table = rt5677_i2c_id,
5310 module_i2c_driver(rt5677_i2c_driver);
5312 MODULE_DESCRIPTION("ASoC RT5677 driver");
5313 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5314 MODULE_LICENSE("GPL v2");