sound/soc/codecs/rt5663.h

   1 /*
   2  * rt5663.h  --  RT5663 ALSA SoC audio driver
   3  *
   4  * Copyright 2016 Realtek Microelectronics
   5  * Author: Jack Yu <jack.yu@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef __RT5663_H__
  13 #define __RT5663_H__
  14
  15 /* Info */
  16 #define RT5663_RESET                            0x0000
  17 #define RT5663_VENDOR_ID                        0x00fd
  18 #define RT5663_VENDOR_ID_1                      0x00fe
  19 #define RT5663_VENDOR_ID_2                      0x00ff
  20
  21 #define RT5668_LOUT_CTRL                        0x0001
  22 #define RT5668_HP_AMP_2                         0x0003
  23 #define RT5668_MONO_OUT                         0x0004
  24 #define RT5668_MONO_GAIN                        0x0007
  25
  26 #define RT5668_AEC_BST                          0x000b
  27 #define RT5668_IN1_IN2                          0x000c
  28 #define RT5668_IN3_IN4                          0x000d
  29 #define RT5668_INL1_INR1                        0x000f
  30 #define RT5668_CBJ_TYPE_2                       0x0011
  31 #define RT5668_CBJ_TYPE_3                       0x0012
  32 #define RT5668_CBJ_TYPE_4                       0x0013
  33 #define RT5668_CBJ_TYPE_5                       0x0014
  34 #define RT5668_CBJ_TYPE_8                       0x0017
  35
  36 /* I/O - ADC/DAC/DMIC */
  37 #define RT5668_DAC3_DIG_VOL                     0x001a
  38 #define RT5668_DAC3_CTRL                        0x001b
  39 #define RT5668_MONO_ADC_DIG_VOL                 0x001d
  40 #define RT5668_STO2_ADC_DIG_VOL                 0x001e
  41 #define RT5668_MONO_ADC_BST_GAIN                0x0020
  42 #define RT5668_STO2_ADC_BST_GAIN                0x0021
  43 #define RT5668_SIDETONE_CTRL                    0x0024
  44 /* Mixer - D-D */
  45 #define RT5668_MONO1_ADC_MIXER                  0x0027
  46 #define RT5668_STO2_ADC_MIXER                   0x0028
  47 #define RT5668_MONO_DAC_MIXER                   0x002b
  48 #define RT5668_DAC2_SRC_CTRL                    0x002e
  49 #define RT5668_IF_3_4_DATA_CTL                  0x002f
  50 #define RT5668_IF_5_DATA_CTL                    0x0030
  51 #define RT5668_PDM_OUT_CTL                      0x0031
  52 #define RT5668_PDM_I2C_DATA_CTL1                0x0032
  53 #define RT5668_PDM_I2C_DATA_CTL2                0x0033
  54 #define RT5668_PDM_I2C_DATA_CTL3                0x0034
  55 #define RT5668_PDM_I2C_DATA_CTL4                0x0035
  56
  57 /*Mixer - Analog*/
  58 #define RT5668_RECMIX1_NEW                      0x003a
  59 #define RT5668_RECMIX1L_0                       0x003b
  60 #define RT5668_RECMIX1L                         0x003c
  61 #define RT5668_RECMIX1R_0                       0x003d
  62 #define RT5668_RECMIX1R                         0x003e
  63 #define RT5668_RECMIX2_NEW                      0x003f
  64 #define RT5668_RECMIX2_L_2                      0x0041
  65 #define RT5668_RECMIX2_R                        0x0042
  66 #define RT5668_RECMIX2_R_2                      0x0043
  67 #define RT5668_CALIB_REC_LR                     0x0044
  68 #define RT5668_ALC_BK_GAIN                      0x0049
  69 #define RT5668_MONOMIX_GAIN                     0x004a
  70 #define RT5668_MONOMIX_IN_GAIN                  0x004b
  71 #define RT5668_OUT_MIXL_GAIN                    0x004d
  72 #define RT5668_OUT_LMIX_IN_GAIN                 0x004e
  73 #define RT5668_OUT_RMIX_IN_GAIN                 0x004f
  74 #define RT5668_OUT_RMIX_IN_GAIN1                0x0050
  75 #define RT5668_LOUT_MIXER_CTRL                  0x0052
  76 /* Power */
  77 #define RT5668_PWR_VOL                          0x0067
  78
  79 #define RT5668_ADCDAC_RST                       0x006d
  80 /* Format - ADC/DAC */
  81 #define RT5668_I2S34_SDP                        0x0071
  82 #define RT5668_I2S5_SDP                         0x0072
  83 /* Format - TDM Control */
  84 #define RT5668_TDM_5                            0x007c
  85 #define RT5668_TDM_6                            0x007d
  86 #define RT5668_TDM_7                            0x007e
  87 #define RT5668_TDM_8                            0x007f
  88
  89 /* Function - Analog */
  90 #define RT5668_ASRC_3                           0x0085
  91 #define RT5668_ASRC_6                           0x0088
  92 #define RT5668_ASRC_7                           0x0089
  93 #define RT5668_PLL_TRK_13                       0x0099
  94 #define RT5668_I2S_M_CLK_CTL                    0x00a0
  95 #define RT5668_FDIV_I2S34_M_CLK                 0x00a1
  96 #define RT5668_FDIV_I2S34_M_CLK2                0x00a2
  97 #define RT5668_FDIV_I2S5_M_CLK                  0x00a3
  98 #define RT5668_FDIV_I2S5_M_CLK2                 0x00a4
  99
 100 /* Function - Digital */
 101 #define RT5668_IRQ_4                            0x00b9
 102 #define RT5668_GPIO_3                           0x00c2
 103 #define RT5668_GPIO_4                           0x00c3
 104 #define RT5668_GPIO_STA                         0x00c4
 105 #define RT5668_HP_AMP_DET1                      0x00d0
 106 #define RT5668_HP_AMP_DET2                      0x00d1
 107 #define RT5668_HP_AMP_DET3                      0x00d2
 108 #define RT5668_MID_BD_HP_AMP                    0x00d3
 109 #define RT5668_LOW_BD_HP_AMP                    0x00d4
 110 #define RT5668_SOF_VOL_ZC2                      0x00da
 111 #define RT5668_ADC_STO2_ADJ1                    0x00ee
 112 #define RT5668_ADC_STO2_ADJ2                    0x00ef
 113 /* General Control */
 114 #define RT5668_A_JD_CTRL                        0x00f0
 115 #define RT5668_JD1_TRES_CTRL                    0x00f1
 116 #define RT5668_JD2_TRES_CTRL                    0x00f2
 117 #define RT5668_JD_CTRL2                         0x00f7
 118 #define RT5668_DUM_REG_2                        0x00fb
 119 #define RT5668_DUM_REG_3                        0x00fc
 120
 121
 122 #define RT5668_DACADC_DIG_VOL2                  0x0101
 123 #define RT5668_DIG_IN_PIN2                      0x0133
 124 #define RT5668_PAD_DRV_CTL1                     0x0136
 125 #define RT5668_SOF_RAM_DEPOP                    0x0138
 126 #define RT5668_VOL_TEST                         0x013f
 127 #define RT5668_TEST_MODE_3                      0x0147
 128 #define RT5668_TEST_MODE_4                      0x0148
 129 #define RT5668_MONO_DYNA_1                      0x0170
 130 #define RT5668_MONO_DYNA_2                      0x0171
 131 #define RT5668_MONO_DYNA_3                      0x0172
 132 #define RT5668_MONO_DYNA_4                      0x0173
 133 #define RT5668_MONO_DYNA_5                      0x0174
 134 #define RT5668_MONO_DYNA_6                      0x0175
 135 #define RT5668_STO1_SIL_DET                     0x0190
 136 #define RT5668_MONOL_SIL_DET                    0x0191
 137 #define RT5668_MONOR_SIL_DET                    0x0192
 138 #define RT5668_STO2_DAC_SIL                     0x0193
 139 #define RT5668_PWR_SAV_CTL1                     0x0194
 140 #define RT5668_PWR_SAV_CTL2                     0x0195
 141 #define RT5668_PWR_SAV_CTL3                     0x0196
 142 #define RT5668_PWR_SAV_CTL4                     0x0197
 143 #define RT5668_PWR_SAV_CTL5                     0x0198
 144 #define RT5668_PWR_SAV_CTL6                     0x0199
 145 #define RT5668_MONO_AMP_CAL1                    0x01a0
 146 #define RT5668_MONO_AMP_CAL2                    0x01a1
 147 #define RT5668_MONO_AMP_CAL3                    0x01a2
 148 #define RT5668_MONO_AMP_CAL4                    0x01a3
 149 #define RT5668_MONO_AMP_CAL5                    0x01a4
 150 #define RT5668_MONO_AMP_CAL6                    0x01a5
 151 #define RT5668_MONO_AMP_CAL7                    0x01a6
 152 #define RT5668_MONO_AMP_CAL_ST1                 0x01a7
 153 #define RT5668_MONO_AMP_CAL_ST2                 0x01a8
 154 #define RT5668_MONO_AMP_CAL_ST3                 0x01a9
 155 #define RT5668_MONO_AMP_CAL_ST4                 0x01aa
 156 #define RT5668_MONO_AMP_CAL_ST5                 0x01ab
 157 #define RT5668_HP_IMP_SEN_13                    0x01b9
 158 #define RT5668_HP_IMP_SEN_14                    0x01ba
 159 #define RT5668_HP_IMP_SEN_6                     0x01bb
 160 #define RT5668_HP_IMP_SEN_7                     0x01bc
 161 #define RT5668_HP_IMP_SEN_8                     0x01bd
 162 #define RT5668_HP_IMP_SEN_9                     0x01be
 163 #define RT5668_HP_IMP_SEN_10                    0x01bf
 164 #define RT5668_HP_LOGIC_3                       0x01dc
 165 #define RT5668_HP_CALIB_ST10                    0x01f3
 166 #define RT5668_HP_CALIB_ST11                    0x01f4
 167 #define RT5668_PRO_REG_TBL_4                    0x0203
 168 #define RT5668_PRO_REG_TBL_5                    0x0204
 169 #define RT5668_PRO_REG_TBL_6                    0x0205
 170 #define RT5668_PRO_REG_TBL_7                    0x0206
 171 #define RT5668_PRO_REG_TBL_8                    0x0207
 172 #define RT5668_PRO_REG_TBL_9                    0x0208
 173 #define RT5668_SAR_ADC_INL_1                    0x0210
 174 #define RT5668_SAR_ADC_INL_2                    0x0211
 175 #define RT5668_SAR_ADC_INL_3                    0x0212
 176 #define RT5668_SAR_ADC_INL_4                    0x0213
 177 #define RT5668_SAR_ADC_INL_5                    0x0214
 178 #define RT5668_SAR_ADC_INL_6                    0x0215
 179 #define RT5668_SAR_ADC_INL_7                    0x0216
 180 #define RT5668_SAR_ADC_INL_8                    0x0217
 181 #define RT5668_SAR_ADC_INL_9                    0x0218
 182 #define RT5668_SAR_ADC_INL_10                   0x0219
 183 #define RT5668_SAR_ADC_INL_11                   0x021a
 184 #define RT5668_SAR_ADC_INL_12                   0x021b
 185 #define RT5668_DRC_CTRL_1                       0x02ff
 186 #define RT5668_DRC1_CTRL_2                      0x0301
 187 #define RT5668_DRC1_CTRL_3                      0x0302
 188 #define RT5668_DRC1_CTRL_4                      0x0303
 189 #define RT5668_DRC1_CTRL_5                      0x0304
 190 #define RT5668_DRC1_CTRL_6                      0x0305
 191 #define RT5668_DRC1_HD_CTRL_1                   0x0306
 192 #define RT5668_DRC1_HD_CTRL_2                   0x0307
 193 #define RT5668_DRC1_PRI_REG_1                   0x0310
 194 #define RT5668_DRC1_PRI_REG_2                   0x0311
 195 #define RT5668_DRC1_PRI_REG_3                   0x0312
 196 #define RT5668_DRC1_PRI_REG_4                   0x0313
 197 #define RT5668_DRC1_PRI_REG_5                   0x0314
 198 #define RT5668_DRC1_PRI_REG_6                   0x0315
 199 #define RT5668_DRC1_PRI_REG_7                   0x0316
 200 #define RT5668_DRC1_PRI_REG_8                   0x0317
 201 #define RT5668_ALC_PGA_CTL_1                    0x0330
 202 #define RT5668_ALC_PGA_CTL_2                    0x0331
 203 #define RT5668_ALC_PGA_CTL_3                    0x0332
 204 #define RT5668_ALC_PGA_CTL_4                    0x0333
 205 #define RT5668_ALC_PGA_CTL_5                    0x0334
 206 #define RT5668_ALC_PGA_CTL_6                    0x0335
 207 #define RT5668_ALC_PGA_CTL_7                    0x0336
 208 #define RT5668_ALC_PGA_CTL_8                    0x0337
 209 #define RT5668_ALC_PGA_REG_1                    0x0338
 210 #define RT5668_ALC_PGA_REG_2                    0x0339
 211 #define RT5668_ALC_PGA_REG_3                    0x033a
 212 #define RT5668_ADC_EQ_RECOV_1                   0x03c0
 213 #define RT5668_ADC_EQ_RECOV_2                   0x03c1
 214 #define RT5668_ADC_EQ_RECOV_3                   0x03c2
 215 #define RT5668_ADC_EQ_RECOV_4                   0x03c3
 216 #define RT5668_ADC_EQ_RECOV_5                   0x03c4
 217 #define RT5668_ADC_EQ_RECOV_6                   0x03c5
 218 #define RT5668_ADC_EQ_RECOV_7                   0x03c6
 219 #define RT5668_ADC_EQ_RECOV_8                   0x03c7
 220 #define RT5668_ADC_EQ_RECOV_9                   0x03c8
 221 #define RT5668_ADC_EQ_RECOV_10                  0x03c9
 222 #define RT5668_ADC_EQ_RECOV_11                  0x03ca
 223 #define RT5668_ADC_EQ_RECOV_12                  0x03cb
 224 #define RT5668_ADC_EQ_RECOV_13                  0x03cc
 225 #define RT5668_VID_HIDDEN                       0x03fe
 226 #define RT5668_VID_CUSTOMER                     0x03ff
 227 #define RT5668_SCAN_MODE                        0x07f0
 228 #define RT5668_I2C_BYPA                         0x07fa
 229
 230 /* Headphone Amp Control 2 (0x0003) */
 231 #define RT5668_EN_DAC_HPO_MASK                  (0x1 << 14)
 232 #define RT5668_EN_DAC_HPO_SHIFT                 14
 233 #define RT5668_EN_DAC_HPO_DIS                   (0x0 << 14)
 234 #define RT5668_EN_DAC_HPO_EN                    (0x1 << 14)
 235
 236 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
 237 #define RT5668_GAIN_HP                          (0x1f << 8)
 238 #define RT5668_GAIN_HP_SHIFT                    8
 239
 240 /* AEC BST Control (0x000b) */
 241 #define RT5668_GAIN_CBJ_MASK                    (0xf << 8)
 242 #define RT5668_GAIN_CBJ_SHIFT                   8
 243
 244 /* IN1 Control / MIC GND REF (0x000c) */
 245 #define RT5668_IN1_DF_MASK                      (0x1 << 15)
 246 #define RT5668_IN1_DF_SHIFT                     15
 247
 248 /* Combo Jack and Type Detection Control 1 (0x0010) */
 249 #define RT5668_CBJ_DET_MASK                     (0x1 << 15)
 250 #define RT5668_CBJ_DET_SHIFT                    15
 251 #define RT5668_CBJ_DET_DIS                      (0x0 << 15)
 252 #define RT5668_CBJ_DET_EN                       (0x1 << 15)
 253 #define RT5668_DET_TYPE_MASK                    (0x1 << 12)
 254 #define RT5668_DET_TYPE_SHIFT                   12
 255 #define RT5668_DET_TYPE_WLCSP                   (0x0 << 12)
 256 #define RT5668_DET_TYPE_QFN                     (0x1 << 12)
 257 #define RT5668_VREF_BIAS_MASK                   (0x1 << 6)
 258 #define RT5668_VREF_BIAS_SHIFT                  6
 259 #define RT5668_VREF_BIAS_FSM                    (0x0 << 6)
 260 #define RT5668_VREF_BIAS_REG                    (0x1 << 6)
 261
 262 /* REC Left Mixer Control 2 (0x003c) */
 263 #define RT5668_RECMIX1L_BST1_CBJ                (0x1 << 7)
 264 #define RT5668_RECMIX1L_BST1_CBJ_SHIFT          7
 265 #define RT5668_RECMIX1L_BST2                    (0x1 << 4)
 266 #define RT5668_RECMIX1L_BST2_SHIFT              4
 267
 268 /* REC Right Mixer Control 2 (0x003e) */
 269 #define RT5668_RECMIX1R_BST2                    (0x1 << 4)
 270 #define RT5668_RECMIX1R_BST2_SHIFT              4
 271
 272 /* DAC1 Digital Volume (0x0019) */
 273 #define RT5668_DAC_L1_VOL_MASK                  (0xff << 8)
 274 #define RT5668_DAC_L1_VOL_SHIFT                 8
 275 #define RT5668_DAC_R1_VOL_MASK                  (0xff)
 276 #define RT5668_DAC_R1_VOL_SHIFT                 0
 277
 278 /* ADC Digital Volume Control (0x001c) */
 279 #define RT5668_ADC_L_MUTE_MASK                  (0x1 << 15)
 280 #define RT5668_ADC_L_MUTE_SHIFT                 15
 281 #define RT5668_ADC_L_VOL_MASK                   (0x7f << 8)
 282 #define RT5668_ADC_L_VOL_SHIFT                  8
 283 #define RT5668_ADC_R_MUTE_MASK                  (0x1 << 7)
 284 #define RT5668_ADC_R_MUTE_SHIFT                 7
 285 #define RT5668_ADC_R_VOL_MASK                   (0x7f)
 286 #define RT5668_ADC_R_VOL_SHIFT                  0
 287
 288 /* Stereo ADC Mixer Control (0x0026) */
 289 #define RT5668_M_STO1_ADC_L1                    (0x1 << 15)
 290 #define RT5668_M_STO1_ADC_L1_SHIFT              15
 291 #define RT5668_M_STO1_ADC_L2                    (0x1 << 14)
 292 #define RT5668_M_STO1_ADC_L2_SHIFT              14
 293 #define RT5668_STO1_ADC_L1_SRC                  (0x1 << 13)
 294 #define RT5668_STO1_ADC_L1_SRC_SHIFT            13
 295 #define RT5668_STO1_ADC_L2_SRC                  (0x1 << 12)
 296 #define RT5668_STO1_ADC_L2_SRC_SHIFT            12
 297 #define RT5668_STO1_ADC_L_SRC                   (0x3 << 10)
 298 #define RT5668_STO1_ADC_L_SRC_SHIFT             10
 299 #define RT5668_M_STO1_ADC_R1                    (0x1 << 7)
 300 #define RT5668_M_STO1_ADC_R1_SHIFT              7
 301 #define RT5668_M_STO1_ADC_R2                    (0x1 << 6)
 302 #define RT5668_M_STO1_ADC_R2_SHIFT              6
 303 #define RT5668_STO1_ADC_R1_SRC                  (0x1 << 5)
 304 #define RT5668_STO1_ADC_R1_SRC_SHIFT            5
 305 #define RT5668_STO1_ADC_R2_SRC                  (0x1 << 4)
 306 #define RT5668_STO1_ADC_R2_SRC_SHIFT            4
 307 #define RT5668_STO1_ADC_R_SRC                   (0x3 << 2)
 308 #define RT5668_STO1_ADC_R_SRC_SHIFT             2
 309
 310 /* ADC Mixer to DAC Mixer Control (0x0029) */
 311 #define RT5668_M_ADCMIX_L                       (0x1 << 15)
 312 #define RT5668_M_ADCMIX_L_SHIFT                 15
 313 #define RT5668_M_DAC1_L                         (0x1 << 14)
 314 #define RT5668_M_DAC1_L_SHIFT                   14
 315 #define RT5668_M_ADCMIX_R                       (0x1 << 7)
 316 #define RT5668_M_ADCMIX_R_SHIFT                 7
 317 #define RT5668_M_DAC1_R                         (0x1 << 6)
 318 #define RT5668_M_DAC1_R_SHIFT                   6
 319
 320 /* Stereo DAC Mixer Control (0x002a) */
 321 #define RT5668_M_DAC_L1_STO_L                   (0x1 << 15)
 322 #define RT5668_M_DAC_L1_STO_L_SHIFT             15
 323 #define RT5668_M_DAC_R1_STO_L                   (0x1 << 13)
 324 #define RT5668_M_DAC_R1_STO_L_SHIFT             13
 325 #define RT5668_M_DAC_L1_STO_R                   (0x1 << 7)
 326 #define RT5668_M_DAC_L1_STO_R_SHIFT             7
 327 #define RT5668_M_DAC_R1_STO_R                   (0x1 << 5)
 328 #define RT5668_M_DAC_R1_STO_R_SHIFT             5
 329
 330 /* Power Management for Digital 1 (0x0061) */
 331 #define RT5668_PWR_I2S1                         (0x1 << 15)
 332 #define RT5668_PWR_I2S1_SHIFT                   15
 333 #define RT5668_PWR_DAC_L1                       (0x1 << 11)
 334 #define RT5668_PWR_DAC_L1_SHIFT                 11
 335 #define RT5668_PWR_DAC_R1                       (0x1 << 10)
 336 #define RT5668_PWR_DAC_R1_SHIFT                 10
 337 #define RT5668_PWR_LDO_DACREF_MASK              (0x1 << 8)
 338 #define RT5668_PWR_LDO_DACREF_SHIFT             8
 339 #define RT5668_PWR_LDO_DACREF_ON                (0x1 << 8)
 340 #define RT5668_PWR_LDO_DACREF_DOWN              (0x0 << 8)
 341 #define RT5668_PWR_LDO_SHIFT                    8
 342 #define RT5668_PWR_ADC_L1                       (0x1 << 4)
 343 #define RT5668_PWR_ADC_L1_SHIFT                 4
 344 #define RT5668_PWR_ADC_R1                       (0x1 << 3)
 345 #define RT5668_PWR_ADC_R1_SHIFT                 3
 346
 347 /* Power Management for Digital 2 (0x0062) */
 348 #define RT5668_PWR_ADC_S1F                      (0x1 << 15)
 349 #define RT5668_PWR_ADC_S1F_SHIFT                15
 350 #define RT5668_PWR_DAC_S1F                      (0x1 << 10)
 351 #define RT5668_PWR_DAC_S1F_SHIFT                10
 352
 353 /* Power Management for Analog 1 (0x0063) */
 354 #define RT5668_PWR_VREF1                        (0x1 << 15)
 355 #define RT5668_PWR_VREF1_MASK                   (0x1 << 15)
 356 #define RT5668_PWR_VREF1_SHIFT                  15
 357 #define RT5668_PWR_FV1                          (0x1 << 14)
 358 #define RT5668_PWR_FV1_MASK                     (0x1 << 14)
 359 #define RT5668_PWR_FV1_SHIFT                    14
 360 #define RT5668_PWR_VREF2                        (0x1 << 13)
 361 #define RT5668_PWR_VREF2_MASK                   (0x1 << 13)
 362 #define RT5668_PWR_VREF2_SHIFT                  13
 363 #define RT5668_PWR_FV2                          (0x1 << 12)
 364 #define RT5668_PWR_FV2_MASK                     (0x1 << 12)
 365 #define RT5668_PWR_FV2_SHIFT                    12
 366 #define RT5668_PWR_MB                           (0x1 << 9)
 367 #define RT5668_PWR_MB_MASK                      (0x1 << 9)
 368 #define RT5668_PWR_MB_SHIFT                     9
 369 #define RT5668_AMP_HP_MASK                      (0x3 << 2)
 370 #define RT5668_AMP_HP_SHIFT                     2
 371 #define RT5668_AMP_HP_1X                        (0x0 << 2)
 372 #define RT5668_AMP_HP_3X                        (0x1 << 2)
 373 #define RT5668_AMP_HP_5X                        (0x3 << 2)
 374 #define RT5668_LDO1_DVO_MASK                    (0x3)
 375 #define RT5668_LDO1_DVO_SHIFT                   0
 376 #define RT5668_LDO1_DVO_0_9V                    (0x0)
 377 #define RT5668_LDO1_DVO_1_0V                    (0x1)
 378 #define RT5668_LDO1_DVO_1_2V                    (0x2)
 379 #define RT5668_LDO1_DVO_1_4V                    (0x3)
 380
 381 /* Power Management for Analog 2 (0x0064) */
 382 #define RT5668_PWR_BST1                         (0x1 << 15)
 383 #define RT5668_PWR_BST1_MASK                    (0x1 << 15)
 384 #define RT5668_PWR_BST1_SHIFT                   15
 385 #define RT5668_PWR_BST1_OFF                     (0x0 << 15)
 386 #define RT5668_PWR_BST1_ON                      (0x1 << 15)
 387 #define RT5668_PWR_BST2                         (0x1 << 14)
 388 #define RT5668_PWR_BST2_MASK                    (0x1 << 14)
 389 #define RT5668_PWR_BST2_SHIFT                   14
 390 #define RT5668_PWR_MB1                          (0x1 << 11)
 391 #define RT5668_PWR_MB1_SHIFT                    11
 392 #define RT5668_PWR_MB2                          (0x1 << 10)
 393 #define RT5668_PWR_MB2_SHIFT                    10
 394 #define RT5668_PWR_BST2_OP                      (0x1 << 6)
 395 #define RT5668_PWR_BST2_OP_MASK                 (0x1 << 6)
 396 #define RT5668_PWR_BST2_OP_SHIFT                6
 397 #define RT5668_PWR_JD1                          (0x1 << 3)
 398 #define RT5668_PWR_JD1_MASK                     (0x1 << 3)
 399 #define RT5668_PWR_JD1_SHIFT                    3
 400 #define RT5668_PWR_JD2                          (0x1 << 2)
 401 #define RT5668_PWR_JD2_MASK                     (0x1 << 2)
 402 #define RT5668_PWR_JD2_SHIFT                    2
 403 #define RT5668_PWR_RECMIX1                      (0x1 << 1)
 404 #define RT5668_PWR_RECMIX1_SHIFT                1
 405 #define RT5668_PWR_RECMIX2                      (0x1)
 406 #define RT5668_PWR_RECMIX2_SHIFT                0
 407
 408 /* Power Management for Analog 3 (0x0065) */
 409 #define RT5668_PWR_CBJ_MASK                     (0x1 << 9)
 410 #define RT5668_PWR_CBJ_SHIFT                    9
 411 #define RT5668_PWR_CBJ_OFF                      (0x0 << 9)
 412 #define RT5668_PWR_CBJ_ON                       (0x1 << 9)
 413 #define RT5668_PWR_PLL                          (0x1 << 6)
 414 #define RT5668_PWR_PLL_SHIFT                    6
 415 #define RT5668_PWR_LDO2                         (0x1 << 2)
 416 #define RT5668_PWR_LDO2_SHIFT                   2
 417
 418 /* Power Management for Volume (0x0067) */
 419 #define RT5668_PWR_MIC_DET                      (0x1 << 5)
 420 #define RT5668_PWR_MIC_DET_SHIFT                5
 421
 422 /* MCLK and System Clock Detection Control (0x006b) */
 423 #define RT5668_EN_ANA_CLK_DET_MASK              (0x1 << 15)
 424 #define RT5668_EN_ANA_CLK_DET_SHIFT             15
 425 #define RT5668_EN_ANA_CLK_DET_DIS               (0x0 << 15)
 426 #define RT5668_EN_ANA_CLK_DET_AUTO              (0x1 << 15)
 427 #define RT5668_PWR_CLK_DET_MASK                 (0x1)
 428 #define RT5668_PWR_CLK_DET_SHIFT                0
 429 #define RT5668_PWR_CLK_DET_DIS                  (0x0)
 430 #define RT5668_PWR_CLK_DET_EN                   (0x1)
 431
 432 /* I2S1 Audio Serial Data Port Control (0x0070) */
 433 #define RT5668_I2S_MS_MASK                      (0x1 << 15)
 434 #define RT5668_I2S_MS_SHIFT                     15
 435 #define RT5668_I2S_MS_M                         (0x0 << 15)
 436 #define RT5668_I2S_MS_S                         (0x1 << 15)
 437 #define RT5668_I2S_BP_MASK                      (0x1 << 8)
 438 #define RT5668_I2S_BP_SHIFT                     8
 439 #define RT5668_I2S_BP_NOR                       (0x0 << 8)
 440 #define RT5668_I2S_BP_INV                       (0x1 << 8)
 441 #define RT5668_I2S_DL_MASK                      (0x3 << 4)
 442 #define RT5668_I2S_DL_SHIFT                     4
 443 #define RT5668_I2S_DL_16                        (0x0 << 4)
 444 #define RT5668_I2S_DL_20                        (0x1 << 4)
 445 #define RT5668_I2S_DL_24                        (0x2 << 4)
 446 #define RT5668_I2S_DL_8                         (0x3 << 4)
 447 #define RT5668_I2S_DF_MASK                      (0x7)
 448 #define RT5668_I2S_DF_SHIFT                     0
 449 #define RT5668_I2S_DF_I2S                       (0x0)
 450 #define RT5668_I2S_DF_LEFT                      (0x1)
 451 #define RT5668_I2S_DF_PCM_A                     (0x2)
 452 #define RT5668_I2S_DF_PCM_B                     (0x3)
 453 #define RT5668_I2S_DF_PCM_A_N                   (0x6)
 454 #define RT5668_I2S_DF_PCM_B_N                   (0x7)
 455
 456 /* ADC/DAC Clock Control 1 (0x0073) */
 457 #define RT5668_I2S_PD1_MASK                     (0x7 << 12)
 458 #define RT5668_I2S_PD1_SHIFT                    12
 459 #define RT5668_M_I2S_DIV_MASK                   (0x7 << 8)
 460 #define RT5668_M_I2S_DIV_SHIFT                  8
 461 #define RT5668_CLK_SRC_MASK                     (0x3 << 4)
 462 #define RT5668_CLK_SRC_MCLK                     (0x0 << 4)
 463 #define RT5668_CLK_SRC_PLL_OUT                  (0x1 << 4)
 464 #define RT5668_CLK_SRC_DIV                      (0x2 << 4)
 465 #define RT5668_CLK_SRC_RC                       (0x3 << 4)
 466 #define RT5668_DAC_OSR_MASK                     (0x3 << 2)
 467 #define RT5668_DAC_OSR_SHIFT                    2
 468 #define RT5668_DAC_OSR_128                      (0x0 << 2)
 469 #define RT5668_DAC_OSR_64                       (0x1 << 2)
 470 #define RT5668_DAC_OSR_32                       (0x2 << 2)
 471 #define RT5668_ADC_OSR_MASK                     (0x3)
 472 #define RT5668_ADC_OSR_SHIFT                    0
 473 #define RT5668_ADC_OSR_128                      (0x0)
 474 #define RT5668_ADC_OSR_64                       (0x1)
 475 #define RT5668_ADC_OSR_32                       (0x2)
 476
 477 /* TDM1 control 1 (0x0078) */
 478 #define RT5668_TDM_MODE_MASK                    (0x1 << 15)
 479 #define RT5668_TDM_MODE_SHIFT                   15
 480 #define RT5668_TDM_MODE_I2S                     (0x0 << 15)
 481 #define RT5668_TDM_MODE_TDM                     (0x1 << 15)
 482 #define RT5668_TDM_IN_CH_MASK                   (0x3 << 10)
 483 #define RT5668_TDM_IN_CH_SHIFT                  10
 484 #define RT5668_TDM_IN_CH_2                      (0x0 << 10)
 485 #define RT5668_TDM_IN_CH_4                      (0x1 << 10)
 486 #define RT5668_TDM_IN_CH_6                      (0x2 << 10)
 487 #define RT5668_TDM_IN_CH_8                      (0x3 << 10)
 488 #define RT5668_TDM_OUT_CH_MASK                  (0x3 << 8)
 489 #define RT5668_TDM_OUT_CH_SHIFT                 8
 490 #define RT5668_TDM_OUT_CH_2                     (0x0 << 8)
 491 #define RT5668_TDM_OUT_CH_4                     (0x1 << 8)
 492 #define RT5668_TDM_OUT_CH_6                     (0x2 << 8)
 493 #define RT5668_TDM_OUT_CH_8                     (0x3 << 8)
 494 #define RT5668_TDM_IN_LEN_MASK                  (0x3 << 6)
 495 #define RT5668_TDM_IN_LEN_SHIFT                 6
 496 #define RT5668_TDM_IN_LEN_16                    (0x0 << 6)
 497 #define RT5668_TDM_IN_LEN_20                    (0x1 << 6)
 498 #define RT5668_TDM_IN_LEN_24                    (0x2 << 6)
 499 #define RT5668_TDM_IN_LEN_32                    (0x3 << 6)
 500 #define RT5668_TDM_OUT_LEN_MASK                 (0x3 << 4)
 501 #define RT5668_TDM_OUT_LEN_SHIFT                4
 502 #define RT5668_TDM_OUT_LEN_16                   (0x0 << 4)
 503 #define RT5668_TDM_OUT_LEN_20                   (0x1 << 4)
 504 #define RT5668_TDM_OUT_LEN_24                   (0x2 << 4)
 505 #define RT5668_TDM_OUT_LEN_32                   (0x3 << 4)
 506
 507 /* Global Clock Control (0x0080) */
 508 #define RT5668_SCLK_SRC_MASK                    (0x3 << 14)
 509 #define RT5668_SCLK_SRC_SHIFT                   14
 510 #define RT5668_SCLK_SRC_MCLK                    (0x0 << 14)
 511 #define RT5668_SCLK_SRC_PLL1                    (0x1 << 14)
 512 #define RT5668_SCLK_SRC_RCCLK                   (0x2 << 14)
 513 #define RT5668_PLL1_SRC_MASK                    (0x7 << 8)
 514 #define RT5668_PLL1_SRC_SHIFT                   8
 515 #define RT5668_PLL1_SRC_MCLK                    (0x0 << 8)
 516 #define RT5668_PLL1_SRC_BCLK1                   (0x1 << 8)
 517 #define RT5668_PLL1_PD_MASK                     (0x1 << 4)
 518 #define RT5668_PLL1_PD_SHIFT                    4
 519
 520 #define RT5668_PLL_INP_MAX                      40000000
 521 #define RT5668_PLL_INP_MIN                      256000
 522 /* PLL M/N/K Code Control 1 (0x0081) */
 523 #define RT5668_PLL_N_MAX                        0x001ff
 524 #define RT5668_PLL_N_MASK                       (RT5668_PLL_N_MAX << 7)
 525 #define RT5668_PLL_N_SHIFT                      7
 526 #define RT5668_PLL_K_MAX                        0x001f
 527 #define RT5668_PLL_K_MASK                       (RT5668_PLL_K_MAX)
 528 #define RT5668_PLL_K_SHIFT                      0
 529
 530 /* PLL M/N/K Code Control 2 (0x0082) */
 531 #define RT5668_PLL_M_MAX                        0x00f
 532 #define RT5668_PLL_M_MASK                       (RT5668_PLL_M_MAX << 12)
 533 #define RT5668_PLL_M_SHIFT                      12
 534 #define RT5668_PLL_M_BP                         (0x1 << 11)
 535 #define RT5668_PLL_M_BP_SHIFT                   11
 536
 537 /* PLL tracking mode 1 (0x0083) */
 538 #define RT5668_I2S1_ASRC_MASK                   (0x1 << 13)
 539 #define RT5668_I2S1_ASRC_SHIFT                  13
 540 #define RT5668_DAC_STO1_ASRC_MASK               (0x1 << 12)
 541 #define RT5668_DAC_STO1_ASRC_SHIFT              12
 542 #define RT5668_ADC_STO1_ASRC_MASK               (0x1 << 4)
 543 #define RT5668_ADC_STO1_ASRC_SHIFT              4
 544
 545 /* PLL tracking mode 2 (0x0084)*/
 546 #define RT5668_DA_STO1_TRACK_MASK               (0x7 << 12)
 547 #define RT5668_DA_STO1_TRACK_SHIFT              12
 548 #define RT5668_DA_STO1_TRACK_SYSCLK             (0x0 << 12)
 549 #define RT5668_DA_STO1_TRACK_I2S1               (0x1 << 12)
 550
 551 /* PLL tracking mode 3 (0x0085)*/
 552 #define RT5668_AD_STO1_TRACK_MASK               (0x7 << 12)
 553 #define RT5668_AD_STO1_TRACK_SHIFT              12
 554 #define RT5668_AD_STO1_TRACK_SYSCLK             (0x0 << 12)
 555 #define RT5668_AD_STO1_TRACK_I2S1               (0x1 << 12)
 556
 557 /* HPOUT Charge pump control 1 (0x0091) */
 558 #define RT5668_OSW_HP_L_MASK                    (0x1 << 11)
 559 #define RT5668_OSW_HP_L_SHIFT                   11
 560 #define RT5668_OSW_HP_L_EN                      (0x1 << 11)
 561 #define RT5668_OSW_HP_L_DIS                     (0x0 << 11)
 562 #define RT5668_OSW_HP_R_MASK                    (0x1 << 10)
 563 #define RT5668_OSW_HP_R_SHIFT                   10
 564 #define RT5668_OSW_HP_R_EN                      (0x1 << 10)
 565 #define RT5668_OSW_HP_R_DIS                     (0x0 << 10)
 566 #define RT5668_SEL_PM_HP_MASK                   (0x3 << 8)
 567 #define RT5668_SEL_PM_HP_SHIFT                  8
 568 #define RT5668_SEL_PM_HP_0_6                    (0x0 << 8)
 569 #define RT5668_SEL_PM_HP_0_9                    (0x1 << 8)
 570 #define RT5668_SEL_PM_HP_1_8                    (0x2 << 8)
 571 #define RT5668_SEL_PM_HP_HIGH                   (0x3 << 8)
 572 #define RT5668_OVCD_HP_MASK                     (0x1 << 2)
 573 #define RT5668_OVCD_HP_SHIFT                    2
 574 #define RT5668_OVCD_HP_EN                       (0x1 << 2)
 575 #define RT5668_OVCD_HP_DIS                      (0x0 << 2)
 576
 577 /* RC Clock Control (0x0094) */
 578 #define RT5668_DIG_25M_CLK_MASK                 (0x1 << 9)
 579 #define RT5668_DIG_25M_CLK_SHIFT                9
 580 #define RT5668_DIG_25M_CLK_DIS                  (0x0 << 9)
 581 #define RT5668_DIG_25M_CLK_EN                   (0x1 << 9)
 582 #define RT5668_DIG_1M_CLK_MASK                  (0x1 << 8)
 583 #define RT5668_DIG_1M_CLK_SHIFT                 8
 584 #define RT5668_DIG_1M_CLK_DIS                   (0x0 << 8)
 585 #define RT5668_DIG_1M_CLK_EN                    (0x1 << 8)
 586
 587 /* Auto Turn On 1M RC CLK (0x009f) */
 588 #define RT5668_IRQ_POW_SAV_MASK                 (0x1 << 15)
 589 #define RT5668_IRQ_POW_SAV_SHIFT                15
 590 #define RT5668_IRQ_POW_SAV_DIS                  (0x0 << 15)
 591 #define RT5668_IRQ_POW_SAV_EN                   (0x1 << 15)
 592 #define RT5668_IRQ_POW_SAV_JD1_MASK             (0x1 << 14)
 593 #define RT5668_IRQ_POW_SAV_JD1_SHIFT            14
 594 #define RT5668_IRQ_POW_SAV_JD1_DIS              (0x0 << 14)
 595 #define RT5668_IRQ_POW_SAV_JD1_EN               (0x1 << 14)
 596
 597 /* IRQ Control 1 (0x00b6) */
 598 #define RT5668_EN_CB_JD_MASK                    (0x1 << 3)
 599 #define RT5668_EN_CB_JD_SHIFT                   3
 600 #define RT5668_EN_CB_JD_EN                      (0x1 << 3)
 601 #define RT5668_EN_CB_JD_DIS                     (0x0 << 3)
 602
 603 /* IRQ Control 3 (0x00b8) */
 604 #define RT5668_EN_IRQ_INLINE_MASK               (0x1 << 6)
 605 #define RT5668_EN_IRQ_INLINE_SHIFT              6
 606 #define RT5668_EN_IRQ_INLINE_BYP                (0x0 << 6)
 607 #define RT5668_EN_IRQ_INLINE_NOR                (0x1 << 6)
 608
 609 /* GPIO Control 1 (0x00c0) */
 610 #define RT5668_GP1_PIN_MASK                     (0x1 << 15)
 611 #define RT5668_GP1_PIN_SHIFT                    15
 612 #define RT5668_GP1_PIN_GPIO1                    (0x0 << 15)
 613 #define RT5668_GP1_PIN_IRQ                      (0x1 << 15)
 614
 615 /* GPIO Control 2 (0x00c1) */
 616 #define RT5668_GP4_PIN_CONF_MASK                (0x1 << 5)
 617 #define RT5668_GP4_PIN_CONF_SHIFT               5
 618 #define RT5668_GP4_PIN_CONF_INPUT               (0x0 << 5)
 619 #define RT5668_GP4_PIN_CONF_OUTPUT              (0x1 << 5)
 620
 621 /* GPIO Control 2 (0x00c2) */
 622 #define RT5668_GP8_PIN_CONF_MASK                (0x1 << 13)
 623 #define RT5668_GP8_PIN_CONF_SHIFT               13
 624 #define RT5668_GP8_PIN_CONF_INPUT               (0x0 << 13)
 625 #define RT5668_GP8_PIN_CONF_OUTPUT              (0x1 << 13)
 626
 627 /* 4 Buttons Inline Command Function 1 (0x00df) */
 628 #define RT5668_4BTN_CLK_DEB_MASK                (0x3 << 2)
 629 #define RT5668_4BTN_CLK_DEB_SHIFT               2
 630 #define RT5668_4BTN_CLK_DEB_8MS                 (0x0 << 2)
 631 #define RT5668_4BTN_CLK_DEB_16MS                (0x1 << 2)
 632 #define RT5668_4BTN_CLK_DEB_32MS                (0x2 << 2)
 633 #define RT5668_4BTN_CLK_DEB_65MS                (0x3 << 2)
 634
 635 /* Inline Command Function 6 (0x00e0) */
 636 #define RT5668_EN_4BTN_INL_MASK                 (0x1 << 15)
 637 #define RT5668_EN_4BTN_INL_SHIFT                15
 638 #define RT5668_EN_4BTN_INL_DIS                  (0x0 << 15)
 639 #define RT5668_EN_4BTN_INL_EN                   (0x1 << 15)
 640 #define RT5668_RESET_4BTN_INL_MASK              (0x1 << 14)
 641 #define RT5668_RESET_4BTN_INL_SHIFT             14
 642 #define RT5668_RESET_4BTN_INL_RESET             (0x0 << 14)
 643 #define RT5668_RESET_4BTN_INL_NOR               (0x1 << 14)
 644
 645 /* Digital Misc Control (0x00fa) */
 646 #define RT5668_DIG_GATE_CTRL_MASK               0x1
 647 #define RT5668_DIG_GATE_CTRL_SHIFT              (0)
 648 #define RT5668_DIG_GATE_CTRL_DIS                0x0
 649 #define RT5668_DIG_GATE_CTRL_EN                 0x1
 650
 651 /* Chopper and Clock control for DAC L (0x013a)*/
 652 #define RT5668_CKXEN_DAC1_MASK                  (0x1 << 13)
 653 #define RT5668_CKXEN_DAC1_SHIFT                 13
 654 #define RT5668_CKGEN_DAC1_MASK                  (0x1 << 12)
 655 #define RT5668_CKGEN_DAC1_SHIFT                 12
 656
 657 /* Chopper and Clock control for ADC (0x013b)*/
 658 #define RT5668_CKXEN_ADCC_MASK                  (0x1 << 13)
 659 #define RT5668_CKXEN_ADCC_SHIFT                 13
 660 #define RT5668_CKGEN_ADCC_MASK                  (0x1 << 12)
 661 #define RT5668_CKGEN_ADCC_SHIFT                 12
 662
 663 /* HP Behavior Logic Control 2 (0x01db) */
 664 #define RT5668_HP_SIG_SRC1_MASK                 (0x3)
 665 #define RT5668_HP_SIG_SRC1_SHIFT                0
 666 #define RT5668_HP_SIG_SRC1_HP_DC                (0x0)
 667 #define RT5668_HP_SIG_SRC1_HP_CALIB             (0x1)
 668 #define RT5668_HP_SIG_SRC1_REG                  (0x2)
 669 #define RT5668_HP_SIG_SRC1_SILENCE              (0x3)
 670
 671 /* RT5663 specific register */
 672 #define RT5663_HP_OUT_EN                        0x0002
 673 #define RT5663_HP_LCH_DRE                       0x0005
 674 #define RT5663_HP_RCH_DRE                       0x0006
 675 #define RT5663_CALIB_BST                        0x000a
 676 #define RT5663_RECMIX                           0x0010
 677 #define RT5663_SIL_DET_CTL                      0x0015
 678 #define RT5663_PWR_SAV_SILDET                   0x0016
 679 #define RT5663_SIDETONE_CTL                     0x0018
 680 #define RT5663_STO1_DAC_DIG_VOL                 0x0019
 681 #define RT5663_STO1_ADC_DIG_VOL                 0x001c
 682 #define RT5663_STO1_BOOST                       0x001f
 683 #define RT5663_HP_IMP_GAIN_1                    0x0022
 684 #define RT5663_HP_IMP_GAIN_2                    0x0023
 685 #define RT5663_STO1_ADC_MIXER                   0x0026
 686 #define RT5663_AD_DA_MIXER                      0x0029
 687 #define RT5663_STO_DAC_MIXER                    0x002a
 688 #define RT5663_DIG_SIDE_MIXER                   0x002c
 689 #define RT5663_BYPASS_STO_DAC                   0x002d
 690 #define RT5663_CALIB_REC_MIX                    0x0040
 691 #define RT5663_PWR_DIG_1                        0x0061
 692 #define RT5663_PWR_DIG_2                        0x0062
 693 #define RT5663_PWR_ANLG_1                       0x0063
 694 #define RT5663_PWR_ANLG_2                       0x0064
 695 #define RT5663_PWR_ANLG_3                       0x0065
 696 #define RT5663_PWR_MIXER                        0x0066
 697 #define RT5663_SIG_CLK_DET                      0x006b
 698 #define RT5663_PRE_DIV_GATING_1                 0x006e
 699 #define RT5663_PRE_DIV_GATING_2                 0x006f
 700 #define RT5663_I2S1_SDP                         0x0070
 701 #define RT5663_ADDA_CLK_1                       0x0073
 702 #define RT5663_ADDA_RST                         0x0074
 703 #define RT5663_FRAC_DIV_1                       0x0075
 704 #define RT5663_FRAC_DIV_2                       0x0076
 705 #define RT5663_TDM_1                            0x0077
 706 #define RT5663_TDM_2                            0x0078
 707 #define RT5663_TDM_3                            0x0079
 708 #define RT5663_TDM_4                            0x007a
 709 #define RT5663_TDM_5                            0x007b
 710 #define RT5663_GLB_CLK                          0x0080
 711 #define RT5663_PLL_1                            0x0081
 712 #define RT5663_PLL_2                            0x0082
 713 #define RT5663_ASRC_1                           0x0083
 714 #define RT5663_ASRC_2                           0x0084
 715 #define RT5663_ASRC_4                           0x0086
 716 #define RT5663_DUMMY_REG                        0x0087
 717 #define RT5663_ASRC_8                           0x008a
 718 #define RT5663_ASRC_9                           0x008b
 719 #define RT5663_ASRC_11                          0x008c
 720 #define RT5663_DEPOP_1                          0x008e
 721 #define RT5663_DEPOP_2                          0x008f
 722 #define RT5663_DEPOP_3                          0x0090
 723 #define RT5663_HP_CHARGE_PUMP_1                 0x0091
 724 #define RT5663_HP_CHARGE_PUMP_2                 0x0092
 725 #define RT5663_MICBIAS_1                        0x0093
 726 #define RT5663_RC_CLK                           0x0094
 727 #define RT5663_ASRC_11_2                        0x0097
 728 #define RT5663_DUMMY_REG_2                      0x0098
 729 #define RT5663_REC_PATH_GAIN                    0x009a
 730 #define RT5663_AUTO_1MRC_CLK                    0x009f
 731 #define RT5663_ADC_EQ_1                         0x00ae
 732 #define RT5663_ADC_EQ_2                         0x00af
 733 #define RT5663_IRQ_1                            0x00b6
 734 #define RT5663_IRQ_2                            0x00b7
 735 #define RT5663_IRQ_3                            0x00b8
 736 #define RT5663_IRQ_4                            0x00ba
 737 #define RT5663_IRQ_5                            0x00bb
 738 #define RT5663_INT_ST_1                         0x00be
 739 #define RT5663_INT_ST_2                         0x00bf
 740 #define RT5663_GPIO_1                           0x00c0
 741 #define RT5663_GPIO_2                           0x00c1
 742 #define RT5663_GPIO_STA                         0x00c5
 743 #define RT5663_SIN_GEN_1                        0x00cb
 744 #define RT5663_SIN_GEN_2                        0x00cc
 745 #define RT5663_SIN_GEN_3                        0x00cd
 746 #define RT5663_SOF_VOL_ZC1                      0x00d9
 747 #define RT5663_IL_CMD_1                         0x00db
 748 #define RT5663_IL_CMD_2                         0x00dc
 749 #define RT5663_IL_CMD_3                         0x00dd
 750 #define RT5663_IL_CMD_4                         0x00de
 751 #define RT5663_IL_CMD_5                         0x00df
 752 #define RT5663_IL_CMD_6                         0x00e0
 753 #define RT5663_IL_CMD_7                         0x00e1
 754 #define RT5663_IL_CMD_8                         0x00e2
 755 #define RT5663_IL_CMD_PWRSAV1                   0x00e4
 756 #define RT5663_IL_CMD_PWRSAV2                   0x00e5
 757 #define RT5663_EM_JACK_TYPE_1                   0x00e6
 758 #define RT5663_EM_JACK_TYPE_2                   0x00e7
 759 #define RT5663_EM_JACK_TYPE_3                   0x00e8
 760 #define RT5663_EM_JACK_TYPE_4                   0x00e9
 761 #define RT5663_EM_JACK_TYPE_5                   0x00ea
 762 #define RT5663_EM_JACK_TYPE_6                   0x00eb
 763 #define RT5663_STO1_HPF_ADJ1                    0x00ec
 764 #define RT5663_STO1_HPF_ADJ2                    0x00ed
 765 #define RT5663_FAST_OFF_MICBIAS                 0x00f4
 766 #define RT5663_JD_CTRL1                         0x00f6
 767 #define RT5663_JD_CTRL2                         0x00f8
 768 #define RT5663_DIG_MISC                         0x00fa
 769 #define RT5663_DIG_VOL_ZCD                      0x0100
 770 #define RT5663_ANA_BIAS_CUR_1                   0x0108
 771 #define RT5663_ANA_BIAS_CUR_2                   0x0109
 772 #define RT5663_ANA_BIAS_CUR_3                   0x010a
 773 #define RT5663_ANA_BIAS_CUR_4                   0x010b
 774 #define RT5663_ANA_BIAS_CUR_5                   0x010c
 775 #define RT5663_ANA_BIAS_CUR_6                   0x010d
 776 #define RT5663_BIAS_CUR_5                       0x010e
 777 #define RT5663_BIAS_CUR_6                       0x010f
 778 #define RT5663_BIAS_CUR_7                       0x0110
 779 #define RT5663_BIAS_CUR_8                       0x0111
 780 #define RT5663_DACREF_LDO                       0x0112
 781 #define RT5663_DUMMY_REG_3                      0x0113
 782 #define RT5663_BIAS_CUR_9                       0x0114
 783 #define RT5663_DUMMY_REG_4                      0x0116
 784 #define RT5663_VREFADJ_OP                       0x0117
 785 #define RT5663_VREF_RECMIX                      0x0118
 786 #define RT5663_CHARGE_PUMP_1                    0x0125
 787 #define RT5663_CHARGE_PUMP_1_2                  0x0126
 788 #define RT5663_CHARGE_PUMP_1_3                  0x0127
 789 #define RT5663_CHARGE_PUMP_2                    0x0128
 790 #define RT5663_DIG_IN_PIN1                      0x0132
 791 #define RT5663_PAD_DRV_CTL                      0x0137
 792 #define RT5663_PLL_INT_REG                      0x0139
 793 #define RT5663_CHOP_DAC_L                       0x013a
 794 #define RT5663_CHOP_ADC                         0x013b
 795 #define RT5663_CALIB_ADC                        0x013c
 796 #define RT5663_CHOP_DAC_R                       0x013d
 797 #define RT5663_DUMMY_CTL_DACLR                  0x013e
 798 #define RT5663_DUMMY_REG_5                      0x0140
 799 #define RT5663_SOFT_RAMP                        0x0141
 800 #define RT5663_TEST_MODE_1                      0x0144
 801 #define RT5663_TEST_MODE_2                      0x0145
 802 #define RT5663_TEST_MODE_3                      0x0146
 803 #define RT5663_STO_DRE_1                        0x0160
 804 #define RT5663_STO_DRE_2                        0x0161
 805 #define RT5663_STO_DRE_3                        0x0162
 806 #define RT5663_STO_DRE_4                        0x0163
 807 #define RT5663_STO_DRE_5                        0x0164
 808 #define RT5663_STO_DRE_6                        0x0165
 809 #define RT5663_STO_DRE_7                        0x0166
 810 #define RT5663_STO_DRE_8                        0x0167
 811 #define RT5663_STO_DRE_9                        0x0168
 812 #define RT5663_STO_DRE_10                       0x0169
 813 #define RT5663_MIC_DECRO_1                      0x0180
 814 #define RT5663_MIC_DECRO_2                      0x0181
 815 #define RT5663_MIC_DECRO_3                      0x0182
 816 #define RT5663_MIC_DECRO_4                      0x0183
 817 #define RT5663_MIC_DECRO_5                      0x0184
 818 #define RT5663_MIC_DECRO_6                      0x0185
 819 #define RT5663_HP_DECRO_1                       0x01b0
 820 #define RT5663_HP_DECRO_2                       0x01b1
 821 #define RT5663_HP_DECRO_3                       0x01b2
 822 #define RT5663_HP_DECRO_4                       0x01b3
 823 #define RT5663_HP_DECOUP                        0x01b4
 824 #define RT5663_HP_IMP_SEN_MAP8                  0x01b5
 825 #define RT5663_HP_IMP_SEN_MAP9                  0x01b6
 826 #define RT5663_HP_IMP_SEN_MAP10                 0x01b7
 827 #define RT5663_HP_IMP_SEN_MAP11                 0x01b8
 828 #define RT5663_HP_IMP_SEN_1                     0x01c0
 829 #define RT5663_HP_IMP_SEN_2                     0x01c1
 830 #define RT5663_HP_IMP_SEN_3                     0x01c2
 831 #define RT5663_HP_IMP_SEN_4                     0x01c3
 832 #define RT5663_HP_IMP_SEN_5                     0x01c4
 833 #define RT5663_HP_IMP_SEN_6                     0x01c5
 834 #define RT5663_HP_IMP_SEN_7                     0x01c6
 835 #define RT5663_HP_IMP_SEN_8                     0x01c7
 836 #define RT5663_HP_IMP_SEN_9                     0x01c8
 837 #define RT5663_HP_IMP_SEN_10                    0x01c9
 838 #define RT5663_HP_IMP_SEN_11                    0x01ca
 839 #define RT5663_HP_IMP_SEN_12                    0x01cb
 840 #define RT5663_HP_IMP_SEN_13                    0x01cc
 841 #define RT5663_HP_IMP_SEN_14                    0x01cd
 842 #define RT5663_HP_IMP_SEN_15                    0x01ce
 843 #define RT5663_HP_IMP_SEN_16                    0x01cf
 844 #define RT5663_HP_IMP_SEN_17                    0x01d0
 845 #define RT5663_HP_IMP_SEN_18                    0x01d1
 846 #define RT5663_HP_IMP_SEN_19                    0x01d2
 847 #define RT5663_HP_IMPSEN_DIG5                   0x01d3
 848 #define RT5663_HP_IMPSEN_MAP1                   0x01d4
 849 #define RT5663_HP_IMPSEN_MAP2                   0x01d5
 850 #define RT5663_HP_IMPSEN_MAP3                   0x01d6
 851 #define RT5663_HP_IMPSEN_MAP4                   0x01d7
 852 #define RT5663_HP_IMPSEN_MAP5                   0x01d8
 853 #define RT5663_HP_IMPSEN_MAP7                   0x01d9
 854 #define RT5663_HP_LOGIC_1                       0x01da
 855 #define RT5663_HP_LOGIC_2                       0x01db
 856 #define RT5663_HP_CALIB_1                       0x01dd
 857 #define RT5663_HP_CALIB_1_1                     0x01de
 858 #define RT5663_HP_CALIB_2                       0x01df
 859 #define RT5663_HP_CALIB_3                       0x01e0
 860 #define RT5663_HP_CALIB_4                       0x01e1
 861 #define RT5663_HP_CALIB_5                       0x01e2
 862 #define RT5663_HP_CALIB_5_1                     0x01e3
 863 #define RT5663_HP_CALIB_6                       0x01e4
 864 #define RT5663_HP_CALIB_7                       0x01e5
 865 #define RT5663_HP_CALIB_9                       0x01e6
 866 #define RT5663_HP_CALIB_10                      0x01e7
 867 #define RT5663_HP_CALIB_11                      0x01e8
 868 #define RT5663_HP_CALIB_ST1                     0x01ea
 869 #define RT5663_HP_CALIB_ST2                     0x01eb
 870 #define RT5663_HP_CALIB_ST3                     0x01ec
 871 #define RT5663_HP_CALIB_ST4                     0x01ed
 872 #define RT5663_HP_CALIB_ST5                     0x01ee
 873 #define RT5663_HP_CALIB_ST6                     0x01ef
 874 #define RT5663_HP_CALIB_ST7                     0x01f0
 875 #define RT5663_HP_CALIB_ST8                     0x01f1
 876 #define RT5663_HP_CALIB_ST9                     0x01f2
 877 #define RT5663_HP_AMP_DET                       0x0200
 878 #define RT5663_DUMMY_REG_6                      0x0201
 879 #define RT5663_HP_BIAS                          0x0202
 880 #define RT5663_CBJ_1                            0x0250
 881 #define RT5663_CBJ_2                            0x0251
 882 #define RT5663_CBJ_3                            0x0252
 883 #define RT5663_DUMMY_1                          0x02fa
 884 #define RT5663_DUMMY_2                          0x02fb
 885 #define RT5663_DUMMY_3                          0x02fc
 886 #define RT5663_ANA_JD                           0x0300
 887 #define RT5663_ADC_LCH_LPF1_A1                  0x03d0
 888 #define RT5663_ADC_RCH_LPF1_A1                  0x03d1
 889 #define RT5663_ADC_LCH_LPF1_H0                  0x03d2
 890 #define RT5663_ADC_RCH_LPF1_H0                  0x03d3
 891 #define RT5663_ADC_LCH_BPF1_A1                  0x03d4
 892 #define RT5663_ADC_RCH_BPF1_A1                  0x03d5
 893 #define RT5663_ADC_LCH_BPF1_A2                  0x03d6
 894 #define RT5663_ADC_RCH_BPF1_A2                  0x03d7
 895 #define RT5663_ADC_LCH_BPF1_H0                  0x03d8
 896 #define RT5663_ADC_RCH_BPF1_H0                  0x03d9
 897 #define RT5663_ADC_LCH_BPF2_A1                  0x03da
 898 #define RT5663_ADC_RCH_BPF2_A1                  0x03db
 899 #define RT5663_ADC_LCH_BPF2_A2                  0x03dc
 900 #define RT5663_ADC_RCH_BPF2_A2                  0x03dd
 901 #define RT5663_ADC_LCH_BPF2_H0                  0x03de
 902 #define RT5663_ADC_RCH_BPF2_H0                  0x03df
 903 #define RT5663_ADC_LCH_BPF3_A1                  0x03e0
 904 #define RT5663_ADC_RCH_BPF3_A1                  0x03e1
 905 #define RT5663_ADC_LCH_BPF3_A2                  0x03e2
 906 #define RT5663_ADC_RCH_BPF3_A2                  0x03e3
 907 #define RT5663_ADC_LCH_BPF3_H0                  0x03e4
 908 #define RT5663_ADC_RCH_BPF3_H0                  0x03e5
 909 #define RT5663_ADC_LCH_BPF4_A1                  0x03e6
 910 #define RT5663_ADC_RCH_BPF4_A1                  0x03e7
 911 #define RT5663_ADC_LCH_BPF4_A2                  0x03e8
 912 #define RT5663_ADC_RCH_BPF4_A2                  0x03e9
 913 #define RT5663_ADC_LCH_BPF4_H0                  0x03ea
 914 #define RT5663_ADC_RCH_BPF4_H0                  0x03eb
 915 #define RT5663_ADC_LCH_HPF1_A1                  0x03ec
 916 #define RT5663_ADC_RCH_HPF1_A1                  0x03ed
 917 #define RT5663_ADC_LCH_HPF1_H0                  0x03ee
 918 #define RT5663_ADC_RCH_HPF1_H0                  0x03ef
 919 #define RT5663_ADC_EQ_PRE_VOL_L                 0x03f0
 920 #define RT5663_ADC_EQ_PRE_VOL_R                 0x03f1
 921 #define RT5663_ADC_EQ_POST_VOL_L                0x03f2
 922 #define RT5663_ADC_EQ_POST_VOL_R                0x03f3
 923
 924 /* RT5663: RECMIX Control (0x0010) */
 925 #define RT5663_RECMIX1_BST1_MASK                (0x1)
 926 #define RT5663_RECMIX1_BST1_SHIFT               0
 927 #define RT5663_RECMIX1_BST1_ON                  (0x0)
 928 #define RT5663_RECMIX1_BST1_OFF                 (0x1)
 929
 930 /* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */
 931 #define RT5663_DACL1_SRC_MASK                   (0x1 << 3)
 932 #define RT5663_DACL1_SRC_SHIFT                  3
 933 #define RT5663_DACR1_SRC_MASK                   (0x1 << 2)
 934 #define RT5663_DACR1_SRC_SHIFT                  2
 935
 936 /* RT5663: TDM control 2 (0x0078) */
 937 #define RT5663_DATA_SWAP_ADCDAT1_MASK           (0x3 << 14)
 938 #define RT5663_DATA_SWAP_ADCDAT1_SHIFT          14
 939 #define RT5663_DATA_SWAP_ADCDAT1_LR             (0x0 << 14)
 940 #define RT5663_DATA_SWAP_ADCDAT1_RL             (0x1 << 14)
 941 #define RT5663_DATA_SWAP_ADCDAT1_LL             (0x2 << 14)
 942 #define RT5663_DATA_SWAP_ADCDAT1_RR             (0x3 << 14)
 943
 944 /* RT5663: TDM control 5 (0x007b) */
 945 #define RT5663_TDM_LENGTN_MASK                  (0x3)
 946 #define RT5663_TDM_LENGTN_SHIFT                 0
 947 #define RT5663_TDM_LENGTN_16                    (0x0)
 948 #define RT5663_TDM_LENGTN_20                    (0x1)
 949 #define RT5663_TDM_LENGTN_24                    (0x2)
 950 #define RT5663_TDM_LENGTN_32                    (0x3)
 951
 952 /* RT5663: Global Clock Control (0x0080) */
 953 #define RT5663_SCLK_SRC_MASK                    (0x3 << 14)
 954 #define RT5663_SCLK_SRC_SHIFT                   14
 955 #define RT5663_SCLK_SRC_MCLK                    (0x0 << 14)
 956 #define RT5663_SCLK_SRC_PLL1                    (0x1 << 14)
 957 #define RT5663_SCLK_SRC_RCCLK                   (0x2 << 14)
 958 #define RT5663_PLL1_SRC_MASK                    (0x7 << 11)
 959 #define RT5663_PLL1_SRC_SHIFT                   11
 960 #define RT5663_PLL1_SRC_MCLK                    (0x0 << 11)
 961 #define RT5663_PLL1_SRC_BCLK1                   (0x1 << 11)
 962
 963 /* PLL tracking mode 1 (0x0083) */
 964 #define RT5663_I2S1_ASRC_MASK                   (0x1 << 11)
 965 #define RT5663_I2S1_ASRC_SHIFT                  11
 966 #define RT5663_DAC_STO1_ASRC_MASK               (0x1 << 10)
 967 #define RT5663_DAC_STO1_ASRC_SHIFT              10
 968 #define RT5663_ADC_STO1_ASRC_MASK               (0x1 << 3)
 969 #define RT5663_ADC_STO1_ASRC_SHIFT              3
 970
 971 /* PLL tracking mode 2 (0x0084)*/
 972 #define RT5663_DA_STO1_TRACK_MASK               (0x7 << 12)
 973 #define RT5663_DA_STO1_TRACK_SHIFT              12
 974 #define RT5663_DA_STO1_TRACK_SYSCLK             (0x0 << 12)
 975 #define RT5663_DA_STO1_TRACK_I2S1               (0x1 << 12)
 976 #define RT5663_AD_STO1_TRACK_MASK               (0x7)
 977 #define RT5663_AD_STO1_TRACK_SHIFT              0
 978 #define RT5663_AD_STO1_TRACK_SYSCLK             (0x0)
 979 #define RT5663_AD_STO1_TRACK_I2S1               (0x1)
 980
 981 /* RT5663: HPOUT Charge pump control 1 (0x0091) */
 982 #define RT5663_SI_HP_MASK                       (0x1 << 12)
 983 #define RT5663_SI_HP_SHIFT                      12
 984 #define RT5663_SI_HP_EN                         (0x1 << 12)
 985 #define RT5663_SI_HP_DIS                        (0x0 << 12)
 986
 987 /* RT5663: GPIO Control 2 (0x00b6) */
 988 #define RT5663_GP1_PIN_CONF_MASK                (0x1 << 2)
 989 #define RT5663_GP1_PIN_CONF_SHIFT               2
 990 #define RT5663_GP1_PIN_CONF_OUTPUT              (0x1 << 2)
 991 #define RT5663_GP1_PIN_CONF_INPUT               (0x0 << 2)
 992
 993 /* RT5663: GPIO Control 2 (0x00b7) */
 994 #define RT5663_EN_IRQ_INLINE_MASK               (0x1 << 3)
 995 #define RT5663_EN_IRQ_INLINE_SHIFT              3
 996 #define RT5663_EN_IRQ_INLINE_NOR                (0x1 << 3)
 997 #define RT5663_EN_IRQ_INLINE_BYP                (0x0 << 3)
 998
 999 /* RT5663: IRQ Control 1 (0x00c1) */
1000 #define RT5663_EN_IRQ_JD1_MASK                  (0x1 << 6)
1001 #define RT5663_EN_IRQ_JD1_SHIFT                 6
1002 #define RT5663_EN_IRQ_JD1_EN                    (0x1 << 6)
1003 #define RT5663_EN_IRQ_JD1_DIS                   (0x0 << 6)
1004
1005 /* RT5663: Inline Command Function 2 (0x00dc) */
1006 #define RT5663_PWR_MIC_DET_MASK                 (0x1)
1007 #define RT5663_PWR_MIC_DET_SHIFT                0
1008 #define RT5663_PWR_MIC_DET_ON                   (0x1)
1009 #define RT5663_PWR_MIC_DET_OFF                  (0x0)
1010
1011 /* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/
1012 #define RT5663_CBJ_DET_MASK                     (0x1 << 15)
1013 #define RT5663_CBJ_DET_SHIFT                    15
1014 #define RT5663_CBJ_DET_DIS                      (0x0 << 15)
1015 #define RT5663_CBJ_DET_EN                       (0x1 << 15)
1016 #define RT5663_EXT_JD_MASK                      (0x1 << 11)
1017 #define RT5663_EXT_JD_SHIFT                     11
1018 #define RT5663_EXT_JD_EN                        (0x1 << 11)
1019 #define RT5663_EXT_JD_DIS                       (0x0 << 11)
1020 #define RT5663_POL_EXT_JD_MASK                  (0x1 << 10)
1021 #define RT5663_POL_EXT_JD_SHIFT                 10
1022 #define RT5663_POL_EXT_JD_EN                    (0x1 << 10)
1023 #define RT5663_POL_EXT_JD_DIS                   (0x0 << 10)
1024
1025 /* RT5663: DACREF LDO Control (0x0112)*/
1026 #define RT5663_PWR_LDO_DACREFL_MASK             (0x1 << 9)
1027 #define RT5663_PWR_LDO_DACREFL_SHIFT            9
1028 #define RT5663_PWR_LDO_DACREFR_MASK             (0x1 << 1)
1029 #define RT5663_PWR_LDO_DACREFR_SHIFT            1
1030
1031 /* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
1032 #define RT5663_DRE_GAIN_HP_MASK                 (0x1f)
1033 #define RT5663_DRE_GAIN_HP_SHIFT                0
1034
1035 /* RT5663: Combo Jack Control (0x0250) */
1036 #define RT5663_INBUF_CBJ_BST1_MASK              (0x1 << 11)
1037 #define RT5663_INBUF_CBJ_BST1_SHIFT             11
1038 #define RT5663_INBUF_CBJ_BST1_ON                (0x1 << 11)
1039 #define RT5663_INBUF_CBJ_BST1_OFF               (0x0 << 11)
1040 #define RT5663_CBJ_SENSE_BST1_MASK              (0x1 << 10)
1041 #define RT5663_CBJ_SENSE_BST1_SHIFT             10
1042 #define RT5663_CBJ_SENSE_BST1_L                 (0x1 << 10)
1043 #define RT5663_CBJ_SENSE_BST1_R                 (0x0 << 10)
1044
1045 /* RT5663: Combo Jack Control (0x0251) */
1046 #define RT5663_GAIN_BST1_MASK                   (0xf)
1047 #define RT5663_GAIN_BST1_SHIFT                  0
1048
1049 /* RT5663: Dummy register 1 (0x02fa) */
1050 #define RT5663_EMB_CLK_MASK                     (0x1 << 9)
1051 #define RT5663_EMB_CLK_SHIFT                    9
1052 #define RT5663_EMB_CLK_EN                       (0x1 << 9)
1053 #define RT5663_EMB_CLK_DIS                      (0x0 << 9)
1054 #define RT5663_HPA_CPL_BIAS_MASK                (0x7 << 6)
1055 #define RT5663_HPA_CPL_BIAS_SHIFT               6
1056 #define RT5663_HPA_CPL_BIAS_0_5                 (0x0 << 6)
1057 #define RT5663_HPA_CPL_BIAS_1                   (0x1 << 6)
1058 #define RT5663_HPA_CPL_BIAS_2                   (0x2 << 6)
1059 #define RT5663_HPA_CPL_BIAS_3                   (0x3 << 6)
1060 #define RT5663_HPA_CPL_BIAS_4_1                 (0x4 << 6)
1061 #define RT5663_HPA_CPL_BIAS_4_2                 (0x5 << 6)
1062 #define RT5663_HPA_CPL_BIAS_6                   (0x6 << 6)
1063 #define RT5663_HPA_CPL_BIAS_8                   (0x7 << 6)
1064 #define RT5663_HPA_CPR_BIAS_MASK                (0x7 << 3)
1065 #define RT5663_HPA_CPR_BIAS_SHIFT               3
1066 #define RT5663_HPA_CPR_BIAS_0_5                 (0x0 << 3)
1067 #define RT5663_HPA_CPR_BIAS_1                   (0x1 << 3)
1068 #define RT5663_HPA_CPR_BIAS_2                   (0x2 << 3)
1069 #define RT5663_HPA_CPR_BIAS_3                   (0x3 << 3)
1070 #define RT5663_HPA_CPR_BIAS_4_1                 (0x4 << 3)
1071 #define RT5663_HPA_CPR_BIAS_4_2                 (0x5 << 3)
1072 #define RT5663_HPA_CPR_BIAS_6                   (0x6 << 3)
1073 #define RT5663_HPA_CPR_BIAS_8                   (0x7 << 3)
1074 #define RT5663_DUMMY_BIAS_MASK                  (0x7)
1075 #define RT5663_DUMMY_BIAS_SHIFT                 0
1076 #define RT5663_DUMMY_BIAS_0_5                   (0x0)
1077 #define RT5663_DUMMY_BIAS_1                     (0x1)
1078 #define RT5663_DUMMY_BIAS_2                     (0x2)
1079 #define RT5663_DUMMY_BIAS_3                     (0x3)
1080 #define RT5663_DUMMY_BIAS_4_1                   (0x4)
1081 #define RT5663_DUMMY_BIAS_4_2                   (0x5)
1082 #define RT5663_DUMMY_BIAS_6                     (0x6)
1083 #define RT5663_DUMMY_BIAS_8                     (0x7)
1084
1085
1086 /* System Clock Source */
1087 enum {
1088         RT5663_SCLK_S_MCLK,
1089         RT5663_SCLK_S_PLL1,
1090         RT5663_SCLK_S_RCCLK,
1091 };
1092
1093 /* PLL1 Source */
1094 enum {
1095         RT5663_PLL1_S_MCLK,
1096         RT5663_PLL1_S_BCLK1,
1097 };
1098
1099 enum {
1100         RT5663_AIF,
1101         RT5663_AIFS,
1102 };
1103
1104 /* asrc clock source */
1105 enum {
1106         RT5663_CLK_SEL_SYS = 0x0,
1107         RT5663_CLK_SEL_I2S1_ASRC = 0x1,
1108 };
1109
1110 /* filter mask */
1111 enum {
1112         RT5663_DA_STEREO_FILTER = 0x1,
1113         RT5663_AD_STEREO_FILTER = 0x2,
1114 };
1115
1116 int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1117         struct snd_soc_jack *hs_jack);
1118 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1119         unsigned int filter_mask, unsigned int clk_src);
1120
1121 #endif /* __RT5663_H__ */