2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 #define RT5663_DEVICE_ID_2 0x6451
34 #define RT5663_DEVICE_ID_1 0x6406
41 struct impedance_mapping_table {
45 unsigned int dc_offset_l_manual;
46 unsigned int dc_offset_r_manual;
47 unsigned int dc_offset_l_manual_mic;
48 unsigned int dc_offset_r_manual_mic;
52 struct snd_soc_component *component;
53 struct rt5663_platform_data pdata;
54 struct regmap *regmap;
55 struct delayed_work jack_detect_work, jd_unplug_work;
56 struct snd_soc_jack *hs_jack;
57 struct timer_list btn_check_timer;
58 struct impedance_mapping_table *imp_table;
72 static const struct reg_sequence rt5663_patch_list[] = {
79 static const struct reg_default rt5663_v2_reg[] = {
481 static const struct reg_default rt5663_reg[] = {
739 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
743 case RT5663_SIL_DET_CTL:
744 case RT5663_HP_IMP_GAIN_2:
745 case RT5663_AD_DA_MIXER:
746 case RT5663_FRAC_DIV_2:
747 case RT5663_MICBIAS_1:
748 case RT5663_ASRC_11_2:
749 case RT5663_ADC_EQ_1:
750 case RT5663_INT_ST_1:
751 case RT5663_INT_ST_2:
752 case RT5663_GPIO_STA1:
753 case RT5663_SIN_GEN_1:
754 case RT5663_IL_CMD_1:
755 case RT5663_IL_CMD_5:
756 case RT5663_IL_CMD_PWRSAV1:
757 case RT5663_EM_JACK_TYPE_1:
758 case RT5663_EM_JACK_TYPE_2:
759 case RT5663_EM_JACK_TYPE_3:
760 case RT5663_JD_CTRL2:
761 case RT5663_VENDOR_ID:
762 case RT5663_VENDOR_ID_1:
763 case RT5663_VENDOR_ID_2:
764 case RT5663_PLL_INT_REG:
765 case RT5663_SOFT_RAMP:
766 case RT5663_STO_DRE_1:
767 case RT5663_STO_DRE_5:
768 case RT5663_STO_DRE_6:
769 case RT5663_STO_DRE_7:
770 case RT5663_MIC_DECRO_1:
771 case RT5663_MIC_DECRO_4:
772 case RT5663_HP_IMP_SEN_1:
773 case RT5663_HP_IMP_SEN_3:
774 case RT5663_HP_IMP_SEN_4:
775 case RT5663_HP_IMP_SEN_5:
776 case RT5663_HP_CALIB_1_1:
777 case RT5663_HP_CALIB_9:
778 case RT5663_HP_CALIB_ST1:
779 case RT5663_HP_CALIB_ST2:
780 case RT5663_HP_CALIB_ST3:
781 case RT5663_HP_CALIB_ST4:
782 case RT5663_HP_CALIB_ST5:
783 case RT5663_HP_CALIB_ST6:
784 case RT5663_HP_CALIB_ST7:
785 case RT5663_HP_CALIB_ST8:
786 case RT5663_HP_CALIB_ST9:
794 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
798 case RT5663_HP_OUT_EN:
799 case RT5663_HP_LCH_DRE:
800 case RT5663_HP_RCH_DRE:
801 case RT5663_CALIB_BST:
803 case RT5663_SIL_DET_CTL:
804 case RT5663_PWR_SAV_SILDET:
805 case RT5663_SIDETONE_CTL:
806 case RT5663_STO1_DAC_DIG_VOL:
807 case RT5663_STO1_ADC_DIG_VOL:
808 case RT5663_STO1_BOOST:
809 case RT5663_HP_IMP_GAIN_1:
810 case RT5663_HP_IMP_GAIN_2:
811 case RT5663_STO1_ADC_MIXER:
812 case RT5663_AD_DA_MIXER:
813 case RT5663_STO_DAC_MIXER:
814 case RT5663_DIG_SIDE_MIXER:
815 case RT5663_BYPASS_STO_DAC:
816 case RT5663_CALIB_REC_MIX:
817 case RT5663_PWR_DIG_1:
818 case RT5663_PWR_DIG_2:
819 case RT5663_PWR_ANLG_1:
820 case RT5663_PWR_ANLG_2:
821 case RT5663_PWR_ANLG_3:
822 case RT5663_PWR_MIXER:
823 case RT5663_SIG_CLK_DET:
824 case RT5663_PRE_DIV_GATING_1:
825 case RT5663_PRE_DIV_GATING_2:
826 case RT5663_I2S1_SDP:
827 case RT5663_ADDA_CLK_1:
828 case RT5663_ADDA_RST:
829 case RT5663_FRAC_DIV_1:
830 case RT5663_FRAC_DIV_2:
842 case RT5663_DUMMY_REG:
849 case RT5663_HP_CHARGE_PUMP_1:
850 case RT5663_HP_CHARGE_PUMP_2:
851 case RT5663_MICBIAS_1:
853 case RT5663_ASRC_11_2:
854 case RT5663_DUMMY_REG_2:
855 case RT5663_REC_PATH_GAIN:
856 case RT5663_AUTO_1MRC_CLK:
857 case RT5663_ADC_EQ_1:
858 case RT5663_ADC_EQ_2:
864 case RT5663_INT_ST_1:
865 case RT5663_INT_ST_2:
868 case RT5663_GPIO_STA1:
869 case RT5663_SIN_GEN_1:
870 case RT5663_SIN_GEN_2:
871 case RT5663_SIN_GEN_3:
872 case RT5663_SOF_VOL_ZC1:
873 case RT5663_IL_CMD_1:
874 case RT5663_IL_CMD_2:
875 case RT5663_IL_CMD_3:
876 case RT5663_IL_CMD_4:
877 case RT5663_IL_CMD_5:
878 case RT5663_IL_CMD_6:
879 case RT5663_IL_CMD_7:
880 case RT5663_IL_CMD_8:
881 case RT5663_IL_CMD_PWRSAV1:
882 case RT5663_IL_CMD_PWRSAV2:
883 case RT5663_EM_JACK_TYPE_1:
884 case RT5663_EM_JACK_TYPE_2:
885 case RT5663_EM_JACK_TYPE_3:
886 case RT5663_EM_JACK_TYPE_4:
887 case RT5663_EM_JACK_TYPE_5:
888 case RT5663_EM_JACK_TYPE_6:
889 case RT5663_STO1_HPF_ADJ1:
890 case RT5663_STO1_HPF_ADJ2:
891 case RT5663_FAST_OFF_MICBIAS:
892 case RT5663_JD_CTRL1:
893 case RT5663_JD_CTRL2:
894 case RT5663_DIG_MISC:
895 case RT5663_VENDOR_ID:
896 case RT5663_VENDOR_ID_1:
897 case RT5663_VENDOR_ID_2:
898 case RT5663_DIG_VOL_ZCD:
899 case RT5663_ANA_BIAS_CUR_1:
900 case RT5663_ANA_BIAS_CUR_2:
901 case RT5663_ANA_BIAS_CUR_3:
902 case RT5663_ANA_BIAS_CUR_4:
903 case RT5663_ANA_BIAS_CUR_5:
904 case RT5663_ANA_BIAS_CUR_6:
905 case RT5663_BIAS_CUR_5:
906 case RT5663_BIAS_CUR_6:
907 case RT5663_BIAS_CUR_7:
908 case RT5663_BIAS_CUR_8:
909 case RT5663_DACREF_LDO:
910 case RT5663_DUMMY_REG_3:
911 case RT5663_BIAS_CUR_9:
912 case RT5663_DUMMY_REG_4:
913 case RT5663_VREFADJ_OP:
914 case RT5663_VREF_RECMIX:
915 case RT5663_CHARGE_PUMP_1:
916 case RT5663_CHARGE_PUMP_1_2:
917 case RT5663_CHARGE_PUMP_1_3:
918 case RT5663_CHARGE_PUMP_2:
919 case RT5663_DIG_IN_PIN1:
920 case RT5663_PAD_DRV_CTL:
921 case RT5663_PLL_INT_REG:
922 case RT5663_CHOP_DAC_L:
923 case RT5663_CHOP_ADC:
924 case RT5663_CALIB_ADC:
925 case RT5663_CHOP_DAC_R:
926 case RT5663_DUMMY_CTL_DACLR:
927 case RT5663_DUMMY_REG_5:
928 case RT5663_SOFT_RAMP:
929 case RT5663_TEST_MODE_1:
930 case RT5663_TEST_MODE_2:
931 case RT5663_TEST_MODE_3:
932 case RT5663_STO_DRE_1:
933 case RT5663_STO_DRE_2:
934 case RT5663_STO_DRE_3:
935 case RT5663_STO_DRE_4:
936 case RT5663_STO_DRE_5:
937 case RT5663_STO_DRE_6:
938 case RT5663_STO_DRE_7:
939 case RT5663_STO_DRE_8:
940 case RT5663_STO_DRE_9:
941 case RT5663_STO_DRE_10:
942 case RT5663_MIC_DECRO_1:
943 case RT5663_MIC_DECRO_2:
944 case RT5663_MIC_DECRO_3:
945 case RT5663_MIC_DECRO_4:
946 case RT5663_MIC_DECRO_5:
947 case RT5663_MIC_DECRO_6:
948 case RT5663_HP_DECRO_1:
949 case RT5663_HP_DECRO_2:
950 case RT5663_HP_DECRO_3:
951 case RT5663_HP_DECRO_4:
952 case RT5663_HP_DECOUP:
953 case RT5663_HP_IMP_SEN_MAP8:
954 case RT5663_HP_IMP_SEN_MAP9:
955 case RT5663_HP_IMP_SEN_MAP10:
956 case RT5663_HP_IMP_SEN_MAP11:
957 case RT5663_HP_IMP_SEN_1:
958 case RT5663_HP_IMP_SEN_2:
959 case RT5663_HP_IMP_SEN_3:
960 case RT5663_HP_IMP_SEN_4:
961 case RT5663_HP_IMP_SEN_5:
962 case RT5663_HP_IMP_SEN_6:
963 case RT5663_HP_IMP_SEN_7:
964 case RT5663_HP_IMP_SEN_8:
965 case RT5663_HP_IMP_SEN_9:
966 case RT5663_HP_IMP_SEN_10:
967 case RT5663_HP_IMP_SEN_11:
968 case RT5663_HP_IMP_SEN_12:
969 case RT5663_HP_IMP_SEN_13:
970 case RT5663_HP_IMP_SEN_14:
971 case RT5663_HP_IMP_SEN_15:
972 case RT5663_HP_IMP_SEN_16:
973 case RT5663_HP_IMP_SEN_17:
974 case RT5663_HP_IMP_SEN_18:
975 case RT5663_HP_IMP_SEN_19:
976 case RT5663_HP_IMPSEN_DIG5:
977 case RT5663_HP_IMPSEN_MAP1:
978 case RT5663_HP_IMPSEN_MAP2:
979 case RT5663_HP_IMPSEN_MAP3:
980 case RT5663_HP_IMPSEN_MAP4:
981 case RT5663_HP_IMPSEN_MAP5:
982 case RT5663_HP_IMPSEN_MAP7:
983 case RT5663_HP_LOGIC_1:
984 case RT5663_HP_LOGIC_2:
985 case RT5663_HP_CALIB_1:
986 case RT5663_HP_CALIB_1_1:
987 case RT5663_HP_CALIB_2:
988 case RT5663_HP_CALIB_3:
989 case RT5663_HP_CALIB_4:
990 case RT5663_HP_CALIB_5:
991 case RT5663_HP_CALIB_5_1:
992 case RT5663_HP_CALIB_6:
993 case RT5663_HP_CALIB_7:
994 case RT5663_HP_CALIB_9:
995 case RT5663_HP_CALIB_10:
996 case RT5663_HP_CALIB_11:
997 case RT5663_HP_CALIB_ST1:
998 case RT5663_HP_CALIB_ST2:
999 case RT5663_HP_CALIB_ST3:
1000 case RT5663_HP_CALIB_ST4:
1001 case RT5663_HP_CALIB_ST5:
1002 case RT5663_HP_CALIB_ST6:
1003 case RT5663_HP_CALIB_ST7:
1004 case RT5663_HP_CALIB_ST8:
1005 case RT5663_HP_CALIB_ST9:
1006 case RT5663_HP_AMP_DET:
1007 case RT5663_DUMMY_REG_6:
1008 case RT5663_HP_BIAS:
1012 case RT5663_DUMMY_1:
1013 case RT5663_DUMMY_2:
1014 case RT5663_DUMMY_3:
1016 case RT5663_ADC_LCH_LPF1_A1:
1017 case RT5663_ADC_RCH_LPF1_A1:
1018 case RT5663_ADC_LCH_LPF1_H0:
1019 case RT5663_ADC_RCH_LPF1_H0:
1020 case RT5663_ADC_LCH_BPF1_A1:
1021 case RT5663_ADC_RCH_BPF1_A1:
1022 case RT5663_ADC_LCH_BPF1_A2:
1023 case RT5663_ADC_RCH_BPF1_A2:
1024 case RT5663_ADC_LCH_BPF1_H0:
1025 case RT5663_ADC_RCH_BPF1_H0:
1026 case RT5663_ADC_LCH_BPF2_A1:
1027 case RT5663_ADC_RCH_BPF2_A1:
1028 case RT5663_ADC_LCH_BPF2_A2:
1029 case RT5663_ADC_RCH_BPF2_A2:
1030 case RT5663_ADC_LCH_BPF2_H0:
1031 case RT5663_ADC_RCH_BPF2_H0:
1032 case RT5663_ADC_LCH_BPF3_A1:
1033 case RT5663_ADC_RCH_BPF3_A1:
1034 case RT5663_ADC_LCH_BPF3_A2:
1035 case RT5663_ADC_RCH_BPF3_A2:
1036 case RT5663_ADC_LCH_BPF3_H0:
1037 case RT5663_ADC_RCH_BPF3_H0:
1038 case RT5663_ADC_LCH_BPF4_A1:
1039 case RT5663_ADC_RCH_BPF4_A1:
1040 case RT5663_ADC_LCH_BPF4_A2:
1041 case RT5663_ADC_RCH_BPF4_A2:
1042 case RT5663_ADC_LCH_BPF4_H0:
1043 case RT5663_ADC_RCH_BPF4_H0:
1044 case RT5663_ADC_LCH_HPF1_A1:
1045 case RT5663_ADC_RCH_HPF1_A1:
1046 case RT5663_ADC_LCH_HPF1_H0:
1047 case RT5663_ADC_RCH_HPF1_H0:
1048 case RT5663_ADC_EQ_PRE_VOL_L:
1049 case RT5663_ADC_EQ_PRE_VOL_R:
1050 case RT5663_ADC_EQ_POST_VOL_L:
1051 case RT5663_ADC_EQ_POST_VOL_R:
1058 static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1062 case RT5663_CBJ_TYPE_2:
1063 case RT5663_PDM_OUT_CTL:
1064 case RT5663_PDM_I2C_DATA_CTL1:
1065 case RT5663_PDM_I2C_DATA_CTL4:
1066 case RT5663_ALC_BK_GAIN:
1068 case RT5663_MICBIAS_1:
1069 case RT5663_ADC_EQ_1:
1070 case RT5663_INT_ST_1:
1071 case RT5663_GPIO_STA2:
1072 case RT5663_IL_CMD_1:
1073 case RT5663_IL_CMD_5:
1074 case RT5663_A_JD_CTRL:
1075 case RT5663_JD_CTRL2:
1076 case RT5663_VENDOR_ID:
1077 case RT5663_VENDOR_ID_1:
1078 case RT5663_VENDOR_ID_2:
1079 case RT5663_STO_DRE_1:
1080 case RT5663_STO_DRE_5:
1081 case RT5663_STO_DRE_6:
1082 case RT5663_STO_DRE_7:
1083 case RT5663_MONO_DYNA_6:
1084 case RT5663_STO1_SIL_DET:
1085 case RT5663_MONOL_SIL_DET:
1086 case RT5663_MONOR_SIL_DET:
1087 case RT5663_STO2_DAC_SIL:
1088 case RT5663_MONO_AMP_CAL_ST1:
1089 case RT5663_MONO_AMP_CAL_ST2:
1090 case RT5663_MONO_AMP_CAL_ST3:
1091 case RT5663_MONO_AMP_CAL_ST4:
1092 case RT5663_HP_IMP_SEN_2:
1093 case RT5663_HP_IMP_SEN_3:
1094 case RT5663_HP_IMP_SEN_4:
1095 case RT5663_HP_IMP_SEN_10:
1096 case RT5663_HP_CALIB_1:
1097 case RT5663_HP_CALIB_10:
1098 case RT5663_HP_CALIB_ST1:
1099 case RT5663_HP_CALIB_ST4:
1100 case RT5663_HP_CALIB_ST5:
1101 case RT5663_HP_CALIB_ST6:
1102 case RT5663_HP_CALIB_ST7:
1103 case RT5663_HP_CALIB_ST8:
1104 case RT5663_HP_CALIB_ST9:
1105 case RT5663_HP_CALIB_ST10:
1106 case RT5663_HP_CALIB_ST11:
1113 static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1116 case RT5663_LOUT_CTRL:
1117 case RT5663_HP_AMP_2:
1118 case RT5663_MONO_OUT:
1119 case RT5663_MONO_GAIN:
1120 case RT5663_AEC_BST:
1121 case RT5663_IN1_IN2:
1122 case RT5663_IN3_IN4:
1123 case RT5663_INL1_INR1:
1124 case RT5663_CBJ_TYPE_2:
1125 case RT5663_CBJ_TYPE_3:
1126 case RT5663_CBJ_TYPE_4:
1127 case RT5663_CBJ_TYPE_5:
1128 case RT5663_CBJ_TYPE_8:
1129 case RT5663_DAC3_DIG_VOL:
1130 case RT5663_DAC3_CTRL:
1131 case RT5663_MONO_ADC_DIG_VOL:
1132 case RT5663_STO2_ADC_DIG_VOL:
1133 case RT5663_MONO_ADC_BST_GAIN:
1134 case RT5663_STO2_ADC_BST_GAIN:
1135 case RT5663_SIDETONE_CTRL:
1136 case RT5663_MONO1_ADC_MIXER:
1137 case RT5663_STO2_ADC_MIXER:
1138 case RT5663_MONO_DAC_MIXER:
1139 case RT5663_DAC2_SRC_CTRL:
1140 case RT5663_IF_3_4_DATA_CTL:
1141 case RT5663_IF_5_DATA_CTL:
1142 case RT5663_PDM_OUT_CTL:
1143 case RT5663_PDM_I2C_DATA_CTL1:
1144 case RT5663_PDM_I2C_DATA_CTL2:
1145 case RT5663_PDM_I2C_DATA_CTL3:
1146 case RT5663_PDM_I2C_DATA_CTL4:
1147 case RT5663_RECMIX1_NEW:
1148 case RT5663_RECMIX1L_0:
1149 case RT5663_RECMIX1L:
1150 case RT5663_RECMIX1R_0:
1151 case RT5663_RECMIX1R:
1152 case RT5663_RECMIX2_NEW:
1153 case RT5663_RECMIX2_L_2:
1154 case RT5663_RECMIX2_R:
1155 case RT5663_RECMIX2_R_2:
1156 case RT5663_CALIB_REC_LR:
1157 case RT5663_ALC_BK_GAIN:
1158 case RT5663_MONOMIX_GAIN:
1159 case RT5663_MONOMIX_IN_GAIN:
1160 case RT5663_OUT_MIXL_GAIN:
1161 case RT5663_OUT_LMIX_IN_GAIN:
1162 case RT5663_OUT_RMIX_IN_GAIN:
1163 case RT5663_OUT_RMIX_IN_GAIN1:
1164 case RT5663_LOUT_MIXER_CTRL:
1165 case RT5663_PWR_VOL:
1166 case RT5663_ADCDAC_RST:
1167 case RT5663_I2S34_SDP:
1168 case RT5663_I2S5_SDP:
1176 case RT5663_PLL_TRK_13:
1177 case RT5663_I2S_M_CLK_CTL:
1178 case RT5663_FDIV_I2S34_M_CLK:
1179 case RT5663_FDIV_I2S34_M_CLK2:
1180 case RT5663_FDIV_I2S5_M_CLK:
1181 case RT5663_FDIV_I2S5_M_CLK2:
1182 case RT5663_V2_IRQ_4:
1185 case RT5663_GPIO_STA2:
1186 case RT5663_HP_AMP_DET1:
1187 case RT5663_HP_AMP_DET2:
1188 case RT5663_HP_AMP_DET3:
1189 case RT5663_MID_BD_HP_AMP:
1190 case RT5663_LOW_BD_HP_AMP:
1191 case RT5663_SOF_VOL_ZC2:
1192 case RT5663_ADC_STO2_ADJ1:
1193 case RT5663_ADC_STO2_ADJ2:
1194 case RT5663_A_JD_CTRL:
1195 case RT5663_JD1_TRES_CTRL:
1196 case RT5663_JD2_TRES_CTRL:
1197 case RT5663_V2_JD_CTRL2:
1198 case RT5663_DUM_REG_2:
1199 case RT5663_DUM_REG_3:
1200 case RT5663_VENDOR_ID:
1201 case RT5663_VENDOR_ID_1:
1202 case RT5663_VENDOR_ID_2:
1203 case RT5663_DACADC_DIG_VOL2:
1204 case RT5663_DIG_IN_PIN2:
1205 case RT5663_PAD_DRV_CTL1:
1206 case RT5663_SOF_RAM_DEPOP:
1207 case RT5663_VOL_TEST:
1208 case RT5663_TEST_MODE_4:
1209 case RT5663_TEST_MODE_5:
1210 case RT5663_STO_DRE_9:
1211 case RT5663_MONO_DYNA_1:
1212 case RT5663_MONO_DYNA_2:
1213 case RT5663_MONO_DYNA_3:
1214 case RT5663_MONO_DYNA_4:
1215 case RT5663_MONO_DYNA_5:
1216 case RT5663_MONO_DYNA_6:
1217 case RT5663_STO1_SIL_DET:
1218 case RT5663_MONOL_SIL_DET:
1219 case RT5663_MONOR_SIL_DET:
1220 case RT5663_STO2_DAC_SIL:
1221 case RT5663_PWR_SAV_CTL1:
1222 case RT5663_PWR_SAV_CTL2:
1223 case RT5663_PWR_SAV_CTL3:
1224 case RT5663_PWR_SAV_CTL4:
1225 case RT5663_PWR_SAV_CTL5:
1226 case RT5663_PWR_SAV_CTL6:
1227 case RT5663_MONO_AMP_CAL1:
1228 case RT5663_MONO_AMP_CAL2:
1229 case RT5663_MONO_AMP_CAL3:
1230 case RT5663_MONO_AMP_CAL4:
1231 case RT5663_MONO_AMP_CAL5:
1232 case RT5663_MONO_AMP_CAL6:
1233 case RT5663_MONO_AMP_CAL7:
1234 case RT5663_MONO_AMP_CAL_ST1:
1235 case RT5663_MONO_AMP_CAL_ST2:
1236 case RT5663_MONO_AMP_CAL_ST3:
1237 case RT5663_MONO_AMP_CAL_ST4:
1238 case RT5663_MONO_AMP_CAL_ST5:
1239 case RT5663_V2_HP_IMP_SEN_13:
1240 case RT5663_V2_HP_IMP_SEN_14:
1241 case RT5663_V2_HP_IMP_SEN_6:
1242 case RT5663_V2_HP_IMP_SEN_7:
1243 case RT5663_V2_HP_IMP_SEN_8:
1244 case RT5663_V2_HP_IMP_SEN_9:
1245 case RT5663_V2_HP_IMP_SEN_10:
1246 case RT5663_HP_LOGIC_3:
1247 case RT5663_HP_CALIB_ST10:
1248 case RT5663_HP_CALIB_ST11:
1249 case RT5663_PRO_REG_TBL_4:
1250 case RT5663_PRO_REG_TBL_5:
1251 case RT5663_PRO_REG_TBL_6:
1252 case RT5663_PRO_REG_TBL_7:
1253 case RT5663_PRO_REG_TBL_8:
1254 case RT5663_PRO_REG_TBL_9:
1255 case RT5663_SAR_ADC_INL_1:
1256 case RT5663_SAR_ADC_INL_2:
1257 case RT5663_SAR_ADC_INL_3:
1258 case RT5663_SAR_ADC_INL_4:
1259 case RT5663_SAR_ADC_INL_5:
1260 case RT5663_SAR_ADC_INL_6:
1261 case RT5663_SAR_ADC_INL_7:
1262 case RT5663_SAR_ADC_INL_8:
1263 case RT5663_SAR_ADC_INL_9:
1264 case RT5663_SAR_ADC_INL_10:
1265 case RT5663_SAR_ADC_INL_11:
1266 case RT5663_SAR_ADC_INL_12:
1267 case RT5663_DRC_CTRL_1:
1268 case RT5663_DRC1_CTRL_2:
1269 case RT5663_DRC1_CTRL_3:
1270 case RT5663_DRC1_CTRL_4:
1271 case RT5663_DRC1_CTRL_5:
1272 case RT5663_DRC1_CTRL_6:
1273 case RT5663_DRC1_HD_CTRL_1:
1274 case RT5663_DRC1_HD_CTRL_2:
1275 case RT5663_DRC1_PRI_REG_1:
1276 case RT5663_DRC1_PRI_REG_2:
1277 case RT5663_DRC1_PRI_REG_3:
1278 case RT5663_DRC1_PRI_REG_4:
1279 case RT5663_DRC1_PRI_REG_5:
1280 case RT5663_DRC1_PRI_REG_6:
1281 case RT5663_DRC1_PRI_REG_7:
1282 case RT5663_DRC1_PRI_REG_8:
1283 case RT5663_ALC_PGA_CTL_1:
1284 case RT5663_ALC_PGA_CTL_2:
1285 case RT5663_ALC_PGA_CTL_3:
1286 case RT5663_ALC_PGA_CTL_4:
1287 case RT5663_ALC_PGA_CTL_5:
1288 case RT5663_ALC_PGA_CTL_6:
1289 case RT5663_ALC_PGA_CTL_7:
1290 case RT5663_ALC_PGA_CTL_8:
1291 case RT5663_ALC_PGA_REG_1:
1292 case RT5663_ALC_PGA_REG_2:
1293 case RT5663_ALC_PGA_REG_3:
1294 case RT5663_ADC_EQ_RECOV_1:
1295 case RT5663_ADC_EQ_RECOV_2:
1296 case RT5663_ADC_EQ_RECOV_3:
1297 case RT5663_ADC_EQ_RECOV_4:
1298 case RT5663_ADC_EQ_RECOV_5:
1299 case RT5663_ADC_EQ_RECOV_6:
1300 case RT5663_ADC_EQ_RECOV_7:
1301 case RT5663_ADC_EQ_RECOV_8:
1302 case RT5663_ADC_EQ_RECOV_9:
1303 case RT5663_ADC_EQ_RECOV_10:
1304 case RT5663_ADC_EQ_RECOV_11:
1305 case RT5663_ADC_EQ_RECOV_12:
1306 case RT5663_ADC_EQ_RECOV_13:
1307 case RT5663_VID_HIDDEN:
1308 case RT5663_VID_CUSTOMER:
1309 case RT5663_SCAN_MODE:
1310 case RT5663_I2C_BYPA:
1313 case RT5663_DEPOP_3:
1314 case RT5663_ASRC_11_2:
1315 case RT5663_INT_ST_2:
1316 case RT5663_GPIO_STA1:
1317 case RT5663_SIN_GEN_1:
1318 case RT5663_SIN_GEN_2:
1319 case RT5663_SIN_GEN_3:
1320 case RT5663_IL_CMD_PWRSAV1:
1321 case RT5663_IL_CMD_PWRSAV2:
1322 case RT5663_EM_JACK_TYPE_1:
1323 case RT5663_EM_JACK_TYPE_2:
1324 case RT5663_EM_JACK_TYPE_3:
1325 case RT5663_EM_JACK_TYPE_4:
1326 case RT5663_FAST_OFF_MICBIAS:
1327 case RT5663_ANA_BIAS_CUR_1:
1328 case RT5663_ANA_BIAS_CUR_2:
1329 case RT5663_BIAS_CUR_9:
1330 case RT5663_DUMMY_REG_4:
1331 case RT5663_VREF_RECMIX:
1332 case RT5663_CHARGE_PUMP_1_2:
1333 case RT5663_CHARGE_PUMP_1_3:
1334 case RT5663_CHARGE_PUMP_2:
1335 case RT5663_CHOP_DAC_R:
1336 case RT5663_DUMMY_CTL_DACLR:
1337 case RT5663_DUMMY_REG_5:
1338 case RT5663_SOFT_RAMP:
1339 case RT5663_TEST_MODE_1:
1340 case RT5663_STO_DRE_10:
1341 case RT5663_MIC_DECRO_1:
1342 case RT5663_MIC_DECRO_2:
1343 case RT5663_MIC_DECRO_3:
1344 case RT5663_MIC_DECRO_4:
1345 case RT5663_MIC_DECRO_5:
1346 case RT5663_MIC_DECRO_6:
1347 case RT5663_HP_DECRO_1:
1348 case RT5663_HP_DECRO_2:
1349 case RT5663_HP_DECRO_3:
1350 case RT5663_HP_DECRO_4:
1351 case RT5663_HP_DECOUP:
1352 case RT5663_HP_IMPSEN_MAP4:
1353 case RT5663_HP_IMPSEN_MAP5:
1354 case RT5663_HP_IMPSEN_MAP7:
1355 case RT5663_HP_CALIB_1:
1361 return rt5663_readable_register(dev, reg);
1365 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1366 static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1367 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1368 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1370 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1371 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1372 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1373 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1374 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1375 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1376 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1377 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1378 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1381 /* Interface data select */
1382 static const char * const rt5663_if1_adc_data_select[] = {
1383 "L/R", "R/L", "L/L", "R/R"
1386 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1387 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1389 static void rt5663_enable_push_button_irq(struct snd_soc_component *component,
1392 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1395 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1396 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1397 /* reset in-line command */
1398 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1399 RT5663_RESET_4BTN_INL_MASK,
1400 RT5663_RESET_4BTN_INL_RESET);
1401 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1402 RT5663_RESET_4BTN_INL_MASK,
1403 RT5663_RESET_4BTN_INL_NOR);
1404 switch (rt5663->codec_ver) {
1406 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1407 RT5663_V2_EN_IRQ_INLINE_MASK,
1408 RT5663_V2_EN_IRQ_INLINE_NOR);
1411 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1412 RT5663_EN_IRQ_INLINE_MASK,
1413 RT5663_EN_IRQ_INLINE_NOR);
1416 dev_err(component->dev, "Unknown CODEC Version\n");
1419 switch (rt5663->codec_ver) {
1421 snd_soc_component_update_bits(component, RT5663_IRQ_3,
1422 RT5663_V2_EN_IRQ_INLINE_MASK,
1423 RT5663_V2_EN_IRQ_INLINE_BYP);
1426 snd_soc_component_update_bits(component, RT5663_IRQ_2,
1427 RT5663_EN_IRQ_INLINE_MASK,
1428 RT5663_EN_IRQ_INLINE_BYP);
1431 dev_err(component->dev, "Unknown CODEC Version\n");
1433 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1434 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1435 /* reset in-line command */
1436 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1437 RT5663_RESET_4BTN_INL_MASK,
1438 RT5663_RESET_4BTN_INL_RESET);
1439 snd_soc_component_update_bits(component, RT5663_IL_CMD_6,
1440 RT5663_RESET_4BTN_INL_MASK,
1441 RT5663_RESET_4BTN_INL_NOR);
1446 * rt5663_v2_jack_detect - Detect headset.
1447 * @component: SoC audio component device.
1448 * @jack_insert: Jack insert or not.
1450 * Detect whether is headset or not when jack inserted.
1452 * Returns detect status.
1455 static int rt5663_v2_jack_detect(struct snd_soc_component *component, int jack_insert)
1457 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1458 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1459 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1461 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1463 snd_soc_component_write(component, RT5663_CBJ_TYPE_2, 0x8040);
1464 snd_soc_component_write(component, RT5663_CBJ_TYPE_3, 0x1484);
1466 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1467 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1468 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1469 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1470 snd_soc_dapm_sync(dapm);
1471 snd_soc_component_update_bits(component, RT5663_RC_CLK,
1472 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1473 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x8);
1476 msleep(sleep_time[i]);
1477 val = snd_soc_component_read32(component, RT5663_CBJ_TYPE_2) & 0x0003;
1478 if (val == 0x1 || val == 0x2 || val == 0x3)
1480 dev_dbg(component->dev, "%s: MX-0011 val=%x sleep %d\n",
1481 __func__, val, sleep_time[i]);
1484 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1488 rt5663->jack_type = SND_JACK_HEADSET;
1489 rt5663_enable_push_button_irq(component, true);
1492 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1493 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1494 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1495 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1496 snd_soc_dapm_sync(dapm);
1497 rt5663->jack_type = SND_JACK_HEADPHONE;
1501 snd_soc_component_update_bits(component, RT5663_RECMIX, 0x8, 0x0);
1503 if (rt5663->jack_type == SND_JACK_HEADSET) {
1504 rt5663_enable_push_button_irq(component, false);
1505 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1506 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1507 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1508 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1509 snd_soc_dapm_sync(dapm);
1511 rt5663->jack_type = 0;
1514 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1515 return rt5663->jack_type;
1519 * rt5663_jack_detect - Detect headset.
1520 * @component: SoC audio component device.
1521 * @jack_insert: Jack insert or not.
1523 * Detect whether is headset or not when jack inserted.
1525 * Returns detect status.
1527 static int rt5663_jack_detect(struct snd_soc_component *component, int jack_insert)
1529 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1532 dev_dbg(component->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1535 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
1536 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1537 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1538 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1539 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1540 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1541 snd_soc_component_update_bits(component, RT5663_DUMMY_1,
1542 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1543 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1544 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1545 snd_soc_component_update_bits(component, RT5663_CBJ_1,
1546 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1547 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1548 snd_soc_component_update_bits(component, RT5663_IL_CMD_2,
1549 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1550 /* BST1 power on for JD */
1551 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1552 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1553 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1554 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1555 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1556 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1557 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1558 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1559 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1560 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1561 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1562 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1563 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1564 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1566 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1567 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1568 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1569 snd_soc_component_update_bits(component, RT5663_AUTO_1MRC_CLK,
1570 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1571 snd_soc_component_update_bits(component, RT5663_IRQ_1,
1572 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1573 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1574 RT5663_EM_JD_MASK, RT5663_EM_JD_RST);
1575 snd_soc_component_update_bits(component, RT5663_EM_JACK_TYPE_1,
1576 RT5663_EM_JD_MASK, RT5663_EM_JD_NOR);
1579 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1581 usleep_range(10000, 10005);
1590 val = snd_soc_component_read32(component, RT5663_EM_JACK_TYPE_2) & 0x0003;
1591 dev_dbg(component->dev, "%s val = %d\n", __func__, val);
1593 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
1594 RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
1595 RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
1600 rt5663->jack_type = SND_JACK_HEADSET;
1601 rt5663_enable_push_button_irq(component, true);
1603 if (rt5663->pdata.impedance_sensing_num)
1606 if (rt5663->pdata.dc_offset_l_manual_mic) {
1607 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1608 rt5663->pdata.dc_offset_l_manual_mic >>
1610 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1611 rt5663->pdata.dc_offset_l_manual_mic &
1615 if (rt5663->pdata.dc_offset_r_manual_mic) {
1616 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1617 rt5663->pdata.dc_offset_r_manual_mic >>
1619 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1620 rt5663->pdata.dc_offset_r_manual_mic &
1625 rt5663->jack_type = SND_JACK_HEADPHONE;
1626 snd_soc_component_update_bits(component,
1628 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1629 RT5663_PWR_VREF2_MASK, 0);
1630 if (rt5663->pdata.impedance_sensing_num)
1633 if (rt5663->pdata.dc_offset_l_manual) {
1634 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
1635 rt5663->pdata.dc_offset_l_manual >> 16);
1636 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
1637 rt5663->pdata.dc_offset_l_manual &
1641 if (rt5663->pdata.dc_offset_r_manual) {
1642 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
1643 rt5663->pdata.dc_offset_r_manual >> 16);
1644 regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
1645 rt5663->pdata.dc_offset_r_manual &
1651 if (rt5663->jack_type == SND_JACK_HEADSET)
1652 rt5663_enable_push_button_irq(component, false);
1653 rt5663->jack_type = 0;
1654 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1655 RT5663_PWR_MB_MASK | RT5663_PWR_VREF1_MASK |
1656 RT5663_PWR_VREF2_MASK, 0);
1659 dev_dbg(component->dev, "jack_type = %d\n", rt5663->jack_type);
1660 return rt5663->jack_type;
1663 static int rt5663_impedance_sensing(struct snd_soc_component *component)
1665 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1666 unsigned int value, i, reg84, reg26, reg2fa, reg91, reg10, reg80;
1668 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1669 if (rt5663->imp_table[i].vol == 7)
1673 if (rt5663->jack_type == SND_JACK_HEADSET) {
1674 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1675 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1676 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1677 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1678 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1679 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1680 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1681 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1683 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1684 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1685 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1686 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1687 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1688 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1689 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1690 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1693 reg84 = snd_soc_component_read32(component, RT5663_ASRC_2);
1694 reg26 = snd_soc_component_read32(component, RT5663_STO1_ADC_MIXER);
1695 reg2fa = snd_soc_component_read32(component, RT5663_DUMMY_1);
1696 reg91 = snd_soc_component_read32(component, RT5663_HP_CHARGE_PUMP_1);
1697 reg10 = snd_soc_component_read32(component, RT5663_RECMIX);
1698 reg80 = snd_soc_component_read32(component, RT5663_GLB_CLK);
1700 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000, 0);
1701 snd_soc_component_write(component, RT5663_ASRC_2, 0);
1702 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, 0x4040);
1703 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1704 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
1705 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1706 RT5663_PWR_VREF1 | RT5663_PWR_VREF2);
1707 usleep_range(10000, 10005);
1708 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1709 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
1710 RT5663_PWR_FV1 | RT5663_PWR_FV2);
1711 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
1712 RT5663_SCLK_SRC_RCCLK);
1713 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1714 RT5663_DIG_25M_CLK_EN);
1715 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1, RT5663_I2S_PD1_MASK, 0);
1716 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
1717 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
1718 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, 0x1232);
1719 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0x0005);
1720 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
1721 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0x0030);
1722 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0x0003);
1723 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1724 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F,
1725 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F);
1726 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1727 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1728 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1730 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1731 RT5663_PWR_LDO_DACREF_ON | RT5663_PWR_ADC_L1 |
1734 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1735 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2,
1736 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2);
1738 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
1739 snd_soc_component_write(component, RT5663_STO_DAC_MIXER, 0);
1740 snd_soc_component_write(component, RT5663_BYPASS_STO_DAC, 0x000c);
1741 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
1742 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
1743 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x8088);
1744 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x3000);
1745 snd_soc_component_write(component, RT5663_ADDA_RST, 0xc000);
1746 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0x3320);
1747 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c9);
1748 snd_soc_component_write(component, RT5663_DUMMY_1, 0x004c);
1749 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7733);
1750 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
1751 snd_soc_component_write(component, RT5663_STO_DRE_9, 0x0007);
1752 snd_soc_component_write(component, RT5663_STO_DRE_10, 0x0007);
1753 snd_soc_component_write(component, RT5663_DUMMY_2, 0x02a4);
1754 snd_soc_component_write(component, RT5663_RECMIX, 0x0005);
1755 snd_soc_component_write(component, RT5663_HP_IMP_SEN_1, 0x4334);
1756 snd_soc_component_update_bits(component, RT5663_IRQ_3, 0x0004, 0x0004);
1757 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x2200);
1758 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x3000);
1759 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0x6200);
1761 for (i = 0; i < 100; i++) {
1763 if (snd_soc_component_read32(component, RT5663_INT_ST_1) & 0x2)
1767 value = snd_soc_component_read32(component, RT5663_HP_IMP_SEN_4);
1769 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0);
1770 snd_soc_component_write(component, RT5663_INT_ST_1, 0);
1771 snd_soc_component_write(component, RT5663_HP_LOGIC_1, 0);
1772 snd_soc_component_update_bits(component, RT5663_RC_CLK, RT5663_DIG_25M_CLK_MASK,
1773 RT5663_DIG_25M_CLK_DIS);
1774 snd_soc_component_write(component, RT5663_GLB_CLK, reg80);
1775 snd_soc_component_write(component, RT5663_RECMIX, reg10);
1776 snd_soc_component_write(component, RT5663_DUMMY_2, 0x00a4);
1777 snd_soc_component_write(component, RT5663_DUMMY_1, reg2fa);
1778 snd_soc_component_write(component, RT5663_HP_CALIB_2, 0x00c8);
1779 snd_soc_component_write(component, RT5663_STO1_HPF_ADJ1, 0xb320);
1780 snd_soc_component_write(component, RT5663_ADDA_RST, 0xe400);
1781 snd_soc_component_write(component, RT5663_CHOP_ADC, 0x2000);
1782 snd_soc_component_write(component, RT5663_HP_OUT_EN, 0x0008);
1783 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
1784 RT5663_PWR_RECMIX1 | RT5663_PWR_RECMIX2, 0);
1785 snd_soc_component_update_bits(component, RT5663_PWR_DIG_1,
1786 RT5663_PWR_DAC_L1 | RT5663_PWR_DAC_R1 |
1787 RT5663_PWR_LDO_DACREF_MASK | RT5663_PWR_ADC_L1 |
1788 RT5663_PWR_ADC_R1, 0);
1789 snd_soc_component_update_bits(component, RT5663_PWR_DIG_2,
1790 RT5663_PWR_ADC_S1F | RT5663_PWR_DAC_S1F, 0);
1791 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
1792 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
1793 snd_soc_component_write(component, RT5663_HP_LOGIC_2, 0);
1794 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_1, reg91);
1795 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
1796 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK, 0);
1797 snd_soc_component_write(component, RT5663_STO1_ADC_MIXER, reg26);
1798 snd_soc_component_write(component, RT5663_ASRC_2, reg84);
1800 for (i = 0; i < rt5663->pdata.impedance_sensing_num; i++) {
1801 if (value >= rt5663->imp_table[i].imp_min &&
1802 value <= rt5663->imp_table[i].imp_max)
1806 snd_soc_component_update_bits(component, RT5663_STO_DRE_9, RT5663_DRE_GAIN_HP_MASK,
1807 rt5663->imp_table[i].vol);
1808 snd_soc_component_update_bits(component, RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_MASK,
1809 rt5663->imp_table[i].vol);
1811 if (rt5663->jack_type == SND_JACK_HEADSET) {
1812 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1813 rt5663->imp_table[i].dc_offset_l_manual_mic >> 16);
1814 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1815 rt5663->imp_table[i].dc_offset_l_manual_mic & 0xffff);
1816 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1817 rt5663->imp_table[i].dc_offset_r_manual_mic >> 16);
1818 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1819 rt5663->imp_table[i].dc_offset_r_manual_mic & 0xffff);
1821 snd_soc_component_write(component, RT5663_MIC_DECRO_2,
1822 rt5663->imp_table[i].dc_offset_l_manual >> 16);
1823 snd_soc_component_write(component, RT5663_MIC_DECRO_3,
1824 rt5663->imp_table[i].dc_offset_l_manual & 0xffff);
1825 snd_soc_component_write(component, RT5663_MIC_DECRO_5,
1826 rt5663->imp_table[i].dc_offset_r_manual >> 16);
1827 snd_soc_component_write(component, RT5663_MIC_DECRO_6,
1828 rt5663->imp_table[i].dc_offset_r_manual & 0xffff);
1834 static int rt5663_button_detect(struct snd_soc_component *component)
1838 val = snd_soc_component_read32(component, RT5663_IL_CMD_5);
1839 dev_dbg(component->dev, "%s: val=0x%x\n", __func__, val);
1840 btn_type = val & 0xfff0;
1841 snd_soc_component_write(component, RT5663_IL_CMD_5, val);
1846 static irqreturn_t rt5663_irq(int irq, void *data)
1848 struct rt5663_priv *rt5663 = data;
1850 dev_dbg(regmap_get_device(rt5663->regmap), "%s IRQ queue work\n",
1853 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1854 msecs_to_jiffies(250));
1859 static int rt5663_set_jack_detect(struct snd_soc_component *component,
1860 struct snd_soc_jack *hs_jack, void *data)
1862 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1864 rt5663->hs_jack = hs_jack;
1866 rt5663_irq(0, rt5663);
1871 static bool rt5663_check_jd_status(struct snd_soc_component *component)
1873 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
1874 int val = snd_soc_component_read32(component, RT5663_INT_ST_1);
1876 dev_dbg(component->dev, "%s val=%x\n", __func__, val);
1879 switch (rt5663->codec_ver) {
1881 return !(val & 0x2000);
1883 return !(val & 0x1000);
1885 dev_err(component->dev, "Unknown CODEC Version\n");
1891 static void rt5663_jack_detect_work(struct work_struct *work)
1893 struct rt5663_priv *rt5663 =
1894 container_of(work, struct rt5663_priv, jack_detect_work.work);
1895 struct snd_soc_component *component = rt5663->component;
1896 int btn_type, report = 0;
1901 if (rt5663_check_jd_status(component)) {
1903 if (rt5663->jack_type == 0) {
1904 /* jack was out, report jack type */
1905 switch (rt5663->codec_ver) {
1907 report = rt5663_v2_jack_detect(
1908 rt5663->component, 1);
1911 report = rt5663_jack_detect(rt5663->component, 1);
1912 if (rt5663->pdata.impedance_sensing_num)
1913 rt5663_impedance_sensing(rt5663->component);
1916 dev_err(component->dev, "Unknown CODEC Version\n");
1919 /* Delay the jack insert report to avoid pop noise */
1922 /* jack is already in, report button event */
1923 report = SND_JACK_HEADSET;
1924 btn_type = rt5663_button_detect(rt5663->component);
1926 * rt5663 can report three kinds of button behavior,
1927 * one click, double click and hold. However,
1928 * currently we will report button pressed/released
1929 * event. So all the three button behaviors are
1930 * treated as button pressed.
1936 report |= SND_JACK_BTN_0;
1941 report |= SND_JACK_BTN_1;
1946 report |= SND_JACK_BTN_2;
1951 report |= SND_JACK_BTN_3;
1953 case 0x0000: /* unpressed */
1957 dev_err(rt5663->component->dev,
1958 "Unexpected button code 0x%04x\n",
1962 /* button release or spurious interrput*/
1963 if (btn_type == 0) {
1964 report = rt5663->jack_type;
1965 cancel_delayed_work_sync(
1966 &rt5663->jd_unplug_work);
1968 queue_delayed_work(system_wq,
1969 &rt5663->jd_unplug_work,
1970 msecs_to_jiffies(500));
1975 switch (rt5663->codec_ver) {
1977 report = rt5663_v2_jack_detect(rt5663->component, 0);
1980 report = rt5663_jack_detect(rt5663->component, 0);
1983 dev_err(component->dev, "Unknown CODEC Version\n");
1986 dev_dbg(component->dev, "%s jack report: 0x%04x\n", __func__, report);
1987 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1988 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1989 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1992 static void rt5663_jd_unplug_work(struct work_struct *work)
1994 struct rt5663_priv *rt5663 =
1995 container_of(work, struct rt5663_priv, jd_unplug_work.work);
1996 struct snd_soc_component *component = rt5663->component;
2001 if (!rt5663_check_jd_status(component)) {
2003 switch (rt5663->codec_ver) {
2005 rt5663_v2_jack_detect(rt5663->component, 0);
2008 rt5663_jack_detect(rt5663->component, 0);
2011 dev_err(component->dev, "Unknown CODEC Version\n");
2014 snd_soc_jack_report(rt5663->hs_jack, 0, SND_JACK_HEADSET |
2015 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
2016 SND_JACK_BTN_2 | SND_JACK_BTN_3);
2018 queue_delayed_work(system_wq, &rt5663->jd_unplug_work,
2019 msecs_to_jiffies(500));
2023 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
2024 /* DAC Digital Volume */
2025 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
2026 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
2027 87, 0, dac_vol_tlv),
2028 /* ADC Digital Volume Control */
2029 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
2030 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
2031 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
2032 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
2033 63, 0, adc_vol_tlv),
2036 static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
2037 /* Headphone Output Volume */
2038 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
2039 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
2040 rt5663_v2_hp_vol_tlv),
2041 /* Mic Boost Volume */
2042 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
2043 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
2046 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
2047 /* Mic Boost Volume*/
2048 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
2049 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
2050 /* Data Swap for Slot0/1 in ADCDAT1 */
2051 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
2054 static const struct snd_kcontrol_new rt5663_hpvol_controls[] = {
2055 /* Headphone Output Volume */
2056 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
2057 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
2061 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
2062 struct snd_soc_dapm_widget *sink)
2065 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2067 val = snd_soc_component_read32(component, RT5663_GLB_CLK);
2068 val &= RT5663_SCLK_SRC_MASK;
2069 if (val == RT5663_SCLK_SRC_PLL1)
2075 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
2076 struct snd_soc_dapm_widget *sink)
2078 unsigned int reg, shift, val;
2079 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2080 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2082 if (rt5663->codec_ver == CODEC_VER_1) {
2084 case RT5663_ADC_STO1_ASRC_SHIFT:
2085 reg = RT5663_ASRC_3;
2086 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
2088 case RT5663_DAC_STO1_ASRC_SHIFT:
2089 reg = RT5663_ASRC_2;
2090 shift = RT5663_DA_STO1_TRACK_SHIFT;
2097 case RT5663_ADC_STO1_ASRC_SHIFT:
2098 reg = RT5663_ASRC_2;
2099 shift = RT5663_AD_STO1_TRACK_SHIFT;
2101 case RT5663_DAC_STO1_ASRC_SHIFT:
2102 reg = RT5663_ASRC_2;
2103 shift = RT5663_DA_STO1_TRACK_SHIFT;
2110 val = (snd_soc_component_read32(component, reg) >> shift) & 0x7;
2118 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
2119 struct snd_soc_dapm_widget *sink)
2121 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
2122 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2123 int da_asrc_en, ad_asrc_en;
2125 da_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2126 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
2127 switch (rt5663->codec_ver) {
2129 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_3) &
2130 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
2133 ad_asrc_en = (snd_soc_component_read32(component, RT5663_ASRC_2) &
2134 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
2137 dev_err(component->dev, "Unknown CODEC Version\n");
2141 if (da_asrc_en || ad_asrc_en)
2142 if (rt5663->sysclk > rt5663->lrck * 384)
2145 dev_err(component->dev, "sysclk < 384 x fs, disable i2s asrc\n");
2151 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
2152 * @component: SoC audio component device.
2153 * @filter_mask: mask of filters.
2154 * @clk_src: clock source
2156 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
2157 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
2158 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
2159 * ASRC function will track i2s clock and generate a corresponding system clock
2160 * for codec. This function provides an API to select the clock source for a
2161 * set of filters specified by the mask. And the codec driver will turn on ASRC
2162 * for these filters if ASRC is selected as their clock source.
2164 int rt5663_sel_asrc_clk_src(struct snd_soc_component *component,
2165 unsigned int filter_mask, unsigned int clk_src)
2167 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2168 unsigned int asrc2_mask = 0;
2169 unsigned int asrc2_value = 0;
2170 unsigned int asrc3_mask = 0;
2171 unsigned int asrc3_value = 0;
2174 case RT5663_CLK_SEL_SYS:
2175 case RT5663_CLK_SEL_I2S1_ASRC:
2182 if (filter_mask & RT5663_DA_STEREO_FILTER) {
2183 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
2184 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
2187 if (filter_mask & RT5663_AD_STEREO_FILTER) {
2188 switch (rt5663->codec_ver) {
2190 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
2191 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
2194 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
2195 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
2198 dev_err(component->dev, "Unknown CODEC Version\n");
2203 snd_soc_component_update_bits(component, RT5663_ASRC_2, asrc2_mask,
2207 snd_soc_component_update_bits(component, RT5663_ASRC_3, asrc3_mask,
2212 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
2215 static const struct snd_kcontrol_new rt5663_recmix1l[] = {
2216 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
2217 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
2218 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
2219 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
2222 static const struct snd_kcontrol_new rt5663_recmix1r[] = {
2223 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
2224 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
2228 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
2229 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2230 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
2231 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2232 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
2235 static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
2236 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
2237 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
2238 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
2239 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
2242 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
2243 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
2244 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
2245 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
2246 RT5663_M_DAC1_L_SHIFT, 1, 1),
2249 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
2250 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
2251 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
2252 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
2253 RT5663_M_DAC1_R_SHIFT, 1, 1),
2256 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
2257 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
2258 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
2261 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
2262 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
2263 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
2267 static const struct snd_kcontrol_new rt5663_hpo_switch =
2268 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
2269 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
2271 /* Stereo ADC source */
2272 static const char * const rt5663_sto1_adc_src[] = {
2276 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
2277 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
2279 static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
2280 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
2282 static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
2283 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
2285 static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
2286 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
2288 /* RT5663: Analog DACL1 input source */
2289 static const char * const rt5663_alg_dacl_src[] = {
2290 "DAC L", "STO DAC MIXL"
2293 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2294 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2296 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2297 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2299 /* RT5663: Analog DACR1 input source */
2300 static const char * const rt5663_alg_dacr_src[] = {
2301 "DAC R", "STO DAC MIXR"
2304 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2305 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2307 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2308 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2310 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2311 struct snd_kcontrol *kcontrol, int event)
2313 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2314 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2317 case SND_SOC_DAPM_POST_PMU:
2318 if (rt5663->codec_ver == CODEC_VER_1) {
2319 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2320 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2321 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2322 RT5663_HP_SIG_SRC1_MASK,
2323 RT5663_HP_SIG_SRC1_SILENCE);
2325 snd_soc_component_update_bits(component,
2326 RT5663_DACREF_LDO, 0x3e0e, 0x3a0a);
2327 snd_soc_component_write(component, RT5663_DEPOP_2, 0x3003);
2328 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2329 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2330 snd_soc_component_write(component, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2331 snd_soc_component_write(component, RT5663_HP_BIAS, 0xabba);
2332 snd_soc_component_write(component, RT5663_CHARGE_PUMP_1, 0x2224);
2333 snd_soc_component_write(component, RT5663_ANA_BIAS_CUR_1, 0x7766);
2334 snd_soc_component_write(component, RT5663_HP_BIAS, 0xafaa);
2335 snd_soc_component_write(component, RT5663_CHARGE_PUMP_2, 0x7777);
2336 snd_soc_component_update_bits(component, RT5663_STO_DRE_1, 0x8000,
2338 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000,
2343 case SND_SOC_DAPM_PRE_PMD:
2344 if (rt5663->codec_ver == CODEC_VER_1) {
2345 snd_soc_component_update_bits(component, RT5663_HP_LOGIC_2,
2346 RT5663_HP_SIG_SRC1_MASK,
2347 RT5663_HP_SIG_SRC1_REG);
2349 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x3000, 0x0);
2350 snd_soc_component_update_bits(component, RT5663_HP_CHARGE_PUMP_1,
2351 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2352 snd_soc_component_update_bits(component,
2353 RT5663_DACREF_LDO, 0x3e0e, 0);
2364 static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
2365 struct snd_kcontrol *kcontrol, int event)
2367 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2368 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2371 case SND_SOC_DAPM_PRE_PMU:
2372 if (rt5663->codec_ver == CODEC_VER_0) {
2373 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030,
2375 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003,
2380 case SND_SOC_DAPM_POST_PMD:
2381 if (rt5663->codec_ver == CODEC_VER_0) {
2382 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0003, 0);
2383 snd_soc_component_update_bits(component, RT5663_DEPOP_1, 0x0030, 0);
2394 static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2395 struct snd_kcontrol *kcontrol, int event)
2397 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2400 case SND_SOC_DAPM_POST_PMU:
2401 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2402 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2403 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2406 case SND_SOC_DAPM_PRE_PMD:
2407 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_2,
2408 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2418 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2419 struct snd_kcontrol *kcontrol, int event)
2421 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2424 case SND_SOC_DAPM_POST_PMU:
2425 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0xff00);
2426 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0xfffc);
2429 case SND_SOC_DAPM_PRE_PMD:
2430 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_1, 0x0000);
2431 snd_soc_component_write(component, RT5663_PRE_DIV_GATING_2, 0x0000);
2441 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2442 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2446 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2447 RT5663_PWR_MB1_SHIFT, 0),
2448 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2449 RT5663_PWR_MB2_SHIFT, 0),
2452 SND_SOC_DAPM_INPUT("IN1P"),
2453 SND_SOC_DAPM_INPUT("IN1N"),
2455 /* REC Mixer Power */
2456 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2457 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2460 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2461 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2462 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2463 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2464 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2467 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2468 0, 0, rt5663_sto1_adc_l_mix,
2469 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2471 /* ADC Filter Power */
2472 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2473 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2475 /* Digital Interface */
2476 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2478 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2479 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2480 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2481 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2482 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2484 /* Audio Interface */
2485 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2486 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2488 /* DAC mixer before sound effect */
2489 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2490 ARRAY_SIZE(rt5663_adda_l_mix)),
2491 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2492 ARRAY_SIZE(rt5663_adda_r_mix)),
2493 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2497 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2498 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2499 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2500 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2501 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2502 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2505 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2506 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2507 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2508 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2509 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2510 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2513 SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
2514 rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2515 SND_SOC_DAPM_POST_PMD),
2516 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2517 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2520 SND_SOC_DAPM_OUTPUT("HPOL"),
2521 SND_SOC_DAPM_OUTPUT("HPOR"),
2524 static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2525 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2526 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2527 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2528 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2529 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2530 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2533 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2534 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2535 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2536 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2537 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2538 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2541 SND_SOC_DAPM_INPUT("IN2P"),
2542 SND_SOC_DAPM_INPUT("IN2N"),
2545 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2546 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2547 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2548 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2549 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2550 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2551 SND_SOC_DAPM_POST_PMU),
2554 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2555 ARRAY_SIZE(rt5663_recmix1l)),
2556 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2557 ARRAY_SIZE(rt5663_recmix1r)),
2558 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2559 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2562 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2563 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2564 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2568 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2570 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2572 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2573 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2574 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2576 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2577 &rt5663_sto1_adcl_mux),
2578 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2579 &rt5663_sto1_adcr_mux),
2582 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2583 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2585 /* Analog DAC Clock */
2586 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2587 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2590 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2591 &rt5663_hpo_switch),
2594 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2595 /* System Clock Pre Divider Gating */
2596 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2597 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2598 SND_SOC_DAPM_PRE_PMD),
2601 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2602 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2605 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2606 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2607 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2608 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2609 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2610 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2616 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2617 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2619 /* Analog DAC source */
2620 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2621 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2624 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2626 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2629 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2630 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2631 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2633 { "ADC L", NULL, "ADC L Power" },
2634 { "ADC L", NULL, "ADC Clock" },
2636 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2638 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2639 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2640 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2642 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2643 { "IF ADC", NULL, "IF1 ADC1" },
2644 { "AIFTX", NULL, "IF ADC" },
2645 { "AIFTX", NULL, "I2S" },
2647 { "AIFRX", NULL, "I2S" },
2648 { "IF DAC", NULL, "AIFRX" },
2649 { "IF1 DAC1 L", NULL, "IF DAC" },
2650 { "IF1 DAC1 R", NULL, "IF DAC" },
2652 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2653 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2654 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2655 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2656 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2657 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2658 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2660 { "DAC L1", NULL, "ADDA MIXL" },
2661 { "DAC R1", NULL, "ADDA MIXR" },
2663 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2664 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2665 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2666 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2667 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2668 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2670 { "HP Amp", NULL, "HP Charge Pump" },
2671 { "HP Amp", NULL, "DAC L" },
2672 { "HP Amp", NULL, "DAC R" },
2675 static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2676 { "MICBIAS1", NULL, "LDO2" },
2677 { "MICBIAS2", NULL, "LDO2" },
2679 { "BST1 CBJ", NULL, "IN1P" },
2680 { "BST1 CBJ", NULL, "IN1N" },
2681 { "BST1 CBJ", NULL, "CBJ Power" },
2683 { "BST2", NULL, "IN2P" },
2684 { "BST2", NULL, "IN2N" },
2685 { "BST2", NULL, "BST2 Power" },
2687 { "RECMIX1L", "BST2 Switch", "BST2" },
2688 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2689 { "RECMIX1L", NULL, "RECMIX1L Power" },
2690 { "RECMIX1R", "BST2 Switch", "BST2" },
2691 { "RECMIX1R", NULL, "RECMIX1R Power" },
2693 { "ADC L", NULL, "RECMIX1L" },
2694 { "ADC R", NULL, "RECMIX1R" },
2695 { "ADC R", NULL, "ADC R Power" },
2696 { "ADC R", NULL, "ADC Clock" },
2698 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2699 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2700 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2702 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2703 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2704 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2705 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2707 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2708 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2709 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2711 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2713 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2715 { "DAC L", NULL, "STO1 DAC MIXL" },
2716 { "DAC L", NULL, "LDO DAC" },
2717 { "DAC L", NULL, "DAC Clock" },
2718 { "DAC R", NULL, "STO1 DAC MIXR" },
2719 { "DAC R", NULL, "LDO DAC" },
2720 { "DAC R", NULL, "DAC Clock" },
2722 { "HPO Playback", "Switch", "HP Amp" },
2723 { "HPOL", NULL, "HPO Playback" },
2724 { "HPOR", NULL, "HPO Playback" },
2727 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2728 { "I2S", NULL, "Pre Div Power" },
2730 { "BST1", NULL, "IN1P" },
2731 { "BST1", NULL, "IN1N" },
2732 { "BST1", NULL, "RECMIX1L Power" },
2734 { "ADC L", NULL, "BST1" },
2736 { "STO1 ADC L1", NULL, "ADC L" },
2738 { "DAC L Mux", "DAC L", "DAC L1" },
2739 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2740 { "DAC R Mux", "DAC R", "DAC R1"},
2741 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2743 { "DAC L", NULL, "DAC L Mux" },
2744 { "DAC R", NULL, "DAC R Mux" },
2746 { "HPOL", NULL, "HP Amp" },
2747 { "HPOR", NULL, "HP Amp" },
2750 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2751 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2753 struct snd_soc_component *component = dai->component;
2754 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2755 unsigned int val_len = 0;
2758 rt5663->lrck = params_rate(params);
2760 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2761 rt5663->lrck, rt5663->sysclk);
2763 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2765 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
2766 rt5663->lrck, dai->id);
2770 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2772 switch (params_width(params)) {
2774 val_len = RT5663_I2S_DL_8;
2777 val_len = RT5663_I2S_DL_16;
2780 val_len = RT5663_I2S_DL_20;
2783 val_len = RT5663_I2S_DL_24;
2789 snd_soc_component_update_bits(component, RT5663_I2S1_SDP,
2790 RT5663_I2S_DL_MASK, val_len);
2792 snd_soc_component_update_bits(component, RT5663_ADDA_CLK_1,
2793 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2798 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2800 struct snd_soc_component *component = dai->component;
2801 unsigned int reg_val = 0;
2803 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2804 case SND_SOC_DAIFMT_CBM_CFM:
2806 case SND_SOC_DAIFMT_CBS_CFS:
2807 reg_val |= RT5663_I2S_MS_S;
2813 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2814 case SND_SOC_DAIFMT_NB_NF:
2816 case SND_SOC_DAIFMT_IB_NF:
2817 reg_val |= RT5663_I2S_BP_INV;
2823 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2824 case SND_SOC_DAIFMT_I2S:
2826 case SND_SOC_DAIFMT_LEFT_J:
2827 reg_val |= RT5663_I2S_DF_LEFT;
2829 case SND_SOC_DAIFMT_DSP_A:
2830 reg_val |= RT5663_I2S_DF_PCM_A;
2832 case SND_SOC_DAIFMT_DSP_B:
2833 reg_val |= RT5663_I2S_DF_PCM_B;
2839 snd_soc_component_update_bits(component, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2840 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2845 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2846 unsigned int freq, int dir)
2848 struct snd_soc_component *component = dai->component;
2849 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2850 unsigned int reg_val = 0;
2852 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2856 case RT5663_SCLK_S_MCLK:
2857 reg_val |= RT5663_SCLK_SRC_MCLK;
2859 case RT5663_SCLK_S_PLL1:
2860 reg_val |= RT5663_SCLK_SRC_PLL1;
2862 case RT5663_SCLK_S_RCCLK:
2863 reg_val |= RT5663_SCLK_SRC_RCCLK;
2866 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2869 snd_soc_component_update_bits(component, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2871 rt5663->sysclk = freq;
2872 rt5663->sysclk_src = clk_id;
2874 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2880 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2881 unsigned int freq_in, unsigned int freq_out)
2883 struct snd_soc_component *component = dai->component;
2884 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2885 struct rl6231_pll_code pll_code;
2887 int mask, shift, val;
2889 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2890 freq_out == rt5663->pll_out)
2893 if (!freq_in || !freq_out) {
2894 dev_dbg(component->dev, "PLL disabled\n");
2897 rt5663->pll_out = 0;
2898 snd_soc_component_update_bits(component, RT5663_GLB_CLK,
2899 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2903 switch (rt5663->codec_ver) {
2905 mask = RT5663_V2_PLL1_SRC_MASK;
2906 shift = RT5663_V2_PLL1_SRC_SHIFT;
2909 mask = RT5663_PLL1_SRC_MASK;
2910 shift = RT5663_PLL1_SRC_SHIFT;
2913 dev_err(component->dev, "Unknown CODEC Version\n");
2918 case RT5663_PLL1_S_MCLK:
2921 case RT5663_PLL1_S_BCLK1:
2925 dev_err(component->dev, "Unknown PLL source %d\n", source);
2928 snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift));
2930 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2932 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2936 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2937 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2940 snd_soc_component_write(component, RT5663_PLL_1,
2941 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2942 snd_soc_component_write(component, RT5663_PLL_2,
2943 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2944 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2946 rt5663->pll_in = freq_in;
2947 rt5663->pll_out = freq_out;
2948 rt5663->pll_src = source;
2953 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2954 unsigned int rx_mask, int slots, int slot_width)
2956 struct snd_soc_component *component = dai->component;
2957 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
2958 unsigned int val = 0, reg;
2960 if (rx_mask || tx_mask)
2961 val |= RT5663_TDM_MODE_TDM;
2965 val |= RT5663_TDM_IN_CH_4;
2966 val |= RT5663_TDM_OUT_CH_4;
2969 val |= RT5663_TDM_IN_CH_6;
2970 val |= RT5663_TDM_OUT_CH_6;
2973 val |= RT5663_TDM_IN_CH_8;
2974 val |= RT5663_TDM_OUT_CH_8;
2982 switch (slot_width) {
2984 val |= RT5663_TDM_IN_LEN_20;
2985 val |= RT5663_TDM_OUT_LEN_20;
2988 val |= RT5663_TDM_IN_LEN_24;
2989 val |= RT5663_TDM_OUT_LEN_24;
2992 val |= RT5663_TDM_IN_LEN_32;
2993 val |= RT5663_TDM_OUT_LEN_32;
3001 switch (rt5663->codec_ver) {
3009 dev_err(component->dev, "Unknown CODEC Version\n");
3013 snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK |
3014 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
3015 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
3020 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3022 struct snd_soc_component *component = dai->component;
3023 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3026 dev_dbg(component->dev, "%s ratio = %d\n", __func__, ratio);
3028 if (rt5663->codec_ver == CODEC_VER_1)
3035 snd_soc_component_update_bits(component, reg,
3036 RT5663_TDM_LENGTN_MASK,
3037 RT5663_TDM_LENGTN_16);
3040 snd_soc_component_update_bits(component, reg,
3041 RT5663_TDM_LENGTN_MASK,
3042 RT5663_TDM_LENGTN_20);
3045 snd_soc_component_update_bits(component, reg,
3046 RT5663_TDM_LENGTN_MASK,
3047 RT5663_TDM_LENGTN_24);
3050 snd_soc_component_update_bits(component, reg,
3051 RT5663_TDM_LENGTN_MASK,
3052 RT5663_TDM_LENGTN_32);
3055 dev_err(component->dev, "Invalid ratio!\n");
3062 static int rt5663_set_bias_level(struct snd_soc_component *component,
3063 enum snd_soc_bias_level level)
3065 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3068 case SND_SOC_BIAS_ON:
3069 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3070 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3071 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3074 case SND_SOC_BIAS_PREPARE:
3075 if (rt5663->codec_ver == CODEC_VER_1) {
3076 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3077 RT5663_DIG_GATE_CTRL_MASK,
3078 RT5663_DIG_GATE_CTRL_EN);
3079 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3080 RT5663_EN_ANA_CLK_DET_MASK |
3081 RT5663_PWR_CLK_DET_MASK,
3082 RT5663_EN_ANA_CLK_DET_AUTO |
3083 RT5663_PWR_CLK_DET_EN);
3087 case SND_SOC_BIAS_STANDBY:
3088 if (rt5663->codec_ver == CODEC_VER_1)
3089 snd_soc_component_update_bits(component, RT5663_DIG_MISC,
3090 RT5663_DIG_GATE_CTRL_MASK,
3091 RT5663_DIG_GATE_CTRL_DIS);
3092 snd_soc_component_update_bits(component, RT5663_PWR_ANLG_1,
3093 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3094 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
3095 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
3096 RT5663_PWR_VREF2 | RT5663_PWR_MB);
3097 usleep_range(10000, 10005);
3098 if (rt5663->codec_ver == CODEC_VER_1) {
3099 snd_soc_component_update_bits(component, RT5663_SIG_CLK_DET,
3100 RT5663_EN_ANA_CLK_DET_MASK |
3101 RT5663_PWR_CLK_DET_MASK,
3102 RT5663_EN_ANA_CLK_DET_DIS |
3103 RT5663_PWR_CLK_DET_DIS);
3107 case SND_SOC_BIAS_OFF:
3108 if (rt5663->jack_type != SND_JACK_HEADSET)
3109 snd_soc_component_update_bits(component,
3111 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
3112 RT5663_PWR_FV1 | RT5663_PWR_FV2 |
3113 RT5663_PWR_MB_MASK, 0);
3115 snd_soc_component_update_bits(component,
3117 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
3118 RT5663_PWR_FV1 | RT5663_PWR_FV2);
3128 static int rt5663_probe(struct snd_soc_component *component)
3130 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3131 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3133 rt5663->component = component;
3135 switch (rt5663->codec_ver) {
3137 snd_soc_dapm_new_controls(dapm,
3138 rt5663_v2_specific_dapm_widgets,
3139 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
3140 snd_soc_dapm_add_routes(dapm,
3141 rt5663_v2_specific_dapm_routes,
3142 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
3143 snd_soc_add_component_controls(component, rt5663_v2_specific_controls,
3144 ARRAY_SIZE(rt5663_v2_specific_controls));
3147 snd_soc_dapm_new_controls(dapm,
3148 rt5663_specific_dapm_widgets,
3149 ARRAY_SIZE(rt5663_specific_dapm_widgets));
3150 snd_soc_dapm_add_routes(dapm,
3151 rt5663_specific_dapm_routes,
3152 ARRAY_SIZE(rt5663_specific_dapm_routes));
3153 snd_soc_add_component_controls(component, rt5663_specific_controls,
3154 ARRAY_SIZE(rt5663_specific_controls));
3156 if (!rt5663->imp_table)
3157 snd_soc_add_component_controls(component, rt5663_hpvol_controls,
3158 ARRAY_SIZE(rt5663_hpvol_controls));
3165 static void rt5663_remove(struct snd_soc_component *component)
3167 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3169 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3173 static int rt5663_suspend(struct snd_soc_component *component)
3175 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3177 regcache_cache_only(rt5663->regmap, true);
3178 regcache_mark_dirty(rt5663->regmap);
3183 static int rt5663_resume(struct snd_soc_component *component)
3185 struct rt5663_priv *rt5663 = snd_soc_component_get_drvdata(component);
3187 regcache_cache_only(rt5663->regmap, false);
3188 regcache_sync(rt5663->regmap);
3190 rt5663_irq(0, rt5663);
3195 #define rt5663_suspend NULL
3196 #define rt5663_resume NULL
3199 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3200 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3201 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3203 static const struct snd_soc_dai_ops rt5663_aif_dai_ops = {
3204 .hw_params = rt5663_hw_params,
3205 .set_fmt = rt5663_set_dai_fmt,
3206 .set_sysclk = rt5663_set_dai_sysclk,
3207 .set_pll = rt5663_set_dai_pll,
3208 .set_tdm_slot = rt5663_set_tdm_slot,
3209 .set_bclk_ratio = rt5663_set_bclk_ratio,
3212 static struct snd_soc_dai_driver rt5663_dai[] = {
3214 .name = "rt5663-aif",
3217 .stream_name = "AIF Playback",
3220 .rates = RT5663_STEREO_RATES,
3221 .formats = RT5663_FORMATS,
3224 .stream_name = "AIF Capture",
3227 .rates = RT5663_STEREO_RATES,
3228 .formats = RT5663_FORMATS,
3230 .ops = &rt5663_aif_dai_ops,
3234 static const struct snd_soc_component_driver soc_component_dev_rt5663 = {
3235 .probe = rt5663_probe,
3236 .remove = rt5663_remove,
3237 .suspend = rt5663_suspend,
3238 .resume = rt5663_resume,
3239 .set_bias_level = rt5663_set_bias_level,
3240 .controls = rt5663_snd_controls,
3241 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
3242 .dapm_widgets = rt5663_dapm_widgets,
3243 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
3244 .dapm_routes = rt5663_dapm_routes,
3245 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
3246 .set_jack = rt5663_set_jack_detect,
3247 .use_pmdown_time = 1,
3249 .non_legacy_dai_naming = 1,
3252 static const struct regmap_config rt5663_v2_regmap = {
3255 .use_single_rw = true,
3256 .max_register = 0x07fa,
3257 .volatile_reg = rt5663_v2_volatile_register,
3258 .readable_reg = rt5663_v2_readable_register,
3259 .cache_type = REGCACHE_RBTREE,
3260 .reg_defaults = rt5663_v2_reg,
3261 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
3264 static const struct regmap_config rt5663_regmap = {
3267 .use_single_rw = true,
3268 .max_register = 0x03f3,
3269 .volatile_reg = rt5663_volatile_register,
3270 .readable_reg = rt5663_readable_register,
3271 .cache_type = REGCACHE_RBTREE,
3272 .reg_defaults = rt5663_reg,
3273 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
3276 static const struct regmap_config temp_regmap = {
3280 .use_single_rw = true,
3281 .max_register = 0x03f3,
3282 .cache_type = REGCACHE_NONE,
3285 static const struct i2c_device_id rt5663_i2c_id[] = {
3289 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
3291 #if defined(CONFIG_OF)
3292 static const struct of_device_id rt5663_of_match[] = {
3293 { .compatible = "realtek,rt5663", },
3296 MODULE_DEVICE_TABLE(of, rt5663_of_match);
3300 static const struct acpi_device_id rt5663_acpi_match[] = {
3304 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
3307 static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
3309 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3310 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
3311 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
3312 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
3313 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3314 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3315 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3316 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
3317 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
3318 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
3320 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
3321 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
3322 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
3326 static void rt5663_calibrate(struct rt5663_priv *rt5663)
3330 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
3332 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
3333 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
3334 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
3335 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
3336 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3337 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3338 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3339 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3340 regmap_write(rt5663->regmap, RT5663_VREFADJ_OP, 0x0f28);
3341 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3343 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3344 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3345 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
3346 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3347 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3348 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3349 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3350 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3351 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3352 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3356 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3357 if (!(value & 0x80))
3358 usleep_range(10000, 10005);
3366 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
3367 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3368 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
3369 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3370 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3371 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3372 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3373 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3374 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3375 regmap_write(rt5663->regmap, RT5663_DUMMY_2, 0x8089);
3376 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3378 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
3379 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3380 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
3381 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3382 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3383 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3384 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3385 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3386 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
3387 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3388 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3389 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3390 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3391 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3392 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3393 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3394 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
3395 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3396 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3397 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3398 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3399 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3400 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3404 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3406 usleep_range(10000, 10005);
3415 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3416 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3417 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3421 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3423 usleep_range(10000, 10005);
3432 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3433 usleep_range(10000, 10005);
3434 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3435 usleep_range(10000, 10005);
3436 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3437 usleep_range(10000, 10005);
3438 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3439 usleep_range(10000, 10005);
3440 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3441 usleep_range(10000, 10005);
3442 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3443 usleep_range(10000, 10005);
3446 static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
3451 device_property_read_u32(dev, "realtek,dc_offset_l_manual",
3452 &rt5663->pdata.dc_offset_l_manual);
3453 device_property_read_u32(dev, "realtek,dc_offset_r_manual",
3454 &rt5663->pdata.dc_offset_r_manual);
3455 device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
3456 &rt5663->pdata.dc_offset_l_manual_mic);
3457 device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
3458 &rt5663->pdata.dc_offset_r_manual_mic);
3459 device_property_read_u32(dev, "realtek,impedance_sensing_num",
3460 &rt5663->pdata.impedance_sensing_num);
3462 if (rt5663->pdata.impedance_sensing_num) {
3463 table_size = sizeof(struct impedance_mapping_table) *
3464 rt5663->pdata.impedance_sensing_num;
3465 rt5663->imp_table = devm_kzalloc(dev, table_size, GFP_KERNEL);
3466 if (!rt5663->imp_table)
3468 ret = device_property_read_u32_array(dev,
3469 "realtek,impedance_sensing_table",
3470 (u32 *)rt5663->imp_table, table_size);
3478 static int rt5663_i2c_probe(struct i2c_client *i2c,
3479 const struct i2c_device_id *id)
3481 struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
3482 struct rt5663_priv *rt5663;
3485 struct regmap *regmap;
3487 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3493 i2c_set_clientdata(i2c, rt5663);
3496 rt5663->pdata = *pdata;
3498 ret = rt5663_parse_dp(rt5663, &i2c->dev);
3503 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3504 if (IS_ERR(regmap)) {
3505 ret = PTR_ERR(regmap);
3506 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3511 ret = regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3512 if (ret || (val != RT5663_DEVICE_ID_2 && val != RT5663_DEVICE_ID_1)) {
3514 "Device with ID register %#x is not rt5663, retry one time.\n",
3517 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3521 case RT5663_DEVICE_ID_2:
3522 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3523 rt5663->codec_ver = CODEC_VER_1;
3525 case RT5663_DEVICE_ID_1:
3526 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3527 rt5663->codec_ver = CODEC_VER_0;
3531 "Device with ID register %#x is not rt5663\n",
3536 if (IS_ERR(rt5663->regmap)) {
3537 ret = PTR_ERR(rt5663->regmap);
3538 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3543 /* reset and calibrate */
3544 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3545 regcache_cache_bypass(rt5663->regmap, true);
3546 switch (rt5663->codec_ver) {
3548 rt5663_v2_calibrate(rt5663);
3551 rt5663_calibrate(rt5663);
3554 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3556 regcache_cache_bypass(rt5663->regmap, false);
3557 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3558 dev_dbg(&i2c->dev, "calibrate done\n");
3560 switch (rt5663->codec_ver) {
3564 ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
3565 ARRAY_SIZE(rt5663_patch_list));
3568 "Failed to apply regmap patch: %d\n", ret);
3571 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3575 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3576 RT5663_GP1_PIN_IRQ);
3577 /* 4btn inline command debounce */
3578 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3579 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3581 switch (rt5663->codec_ver) {
3583 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3585 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3586 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3587 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3588 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3589 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3590 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3591 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3593 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3594 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3595 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3596 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3597 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3598 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3599 /* Set GPIO4 and GPIO8 as input for combo jack */
3600 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3601 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3602 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3603 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3604 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3605 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3606 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3609 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3610 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3611 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3612 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
3613 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3614 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3615 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3616 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
3617 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3618 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3619 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3620 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
3621 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3622 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3623 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3624 RT5663_DATA_SWAP_ADCDAT1_MASK,
3625 RT5663_DATA_SWAP_ADCDAT1_LL);
3628 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3631 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3632 INIT_DELAYED_WORK(&rt5663->jd_unplug_work, rt5663_jd_unplug_work);
3635 ret = request_irq(i2c->irq, rt5663_irq,
3636 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3637 | IRQF_ONESHOT, "rt5663", rt5663);
3639 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3643 ret = devm_snd_soc_register_component(&i2c->dev,
3644 &soc_component_dev_rt5663,
3645 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3649 free_irq(i2c->irq, rt5663);
3655 static int rt5663_i2c_remove(struct i2c_client *i2c)
3657 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3660 free_irq(i2c->irq, rt5663);
3665 static void rt5663_i2c_shutdown(struct i2c_client *client)
3667 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3669 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3672 static struct i2c_driver rt5663_i2c_driver = {
3675 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3676 .of_match_table = of_match_ptr(rt5663_of_match),
3678 .probe = rt5663_i2c_probe,
3679 .remove = rt5663_i2c_remove,
3680 .shutdown = rt5663_i2c_shutdown,
3681 .id_table = rt5663_i2c_id,
3683 module_i2c_driver(rt5663_i2c_driver);
3685 MODULE_DESCRIPTION("ASoC RT5663 driver");
3686 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3687 MODULE_LICENSE("GPL v2");
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