sound/soc/codecs/rt5514.c

   1 /*
   2  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2015 Realtek Semiconductor Corp.
   5  * Author: Oder Chiou <oder_chiou@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/acpi.h>
  13 #include <linux/fs.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/regmap.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/firmware.h>
  23 #include <linux/gpio.h>
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc.h>
  28 #include <sound/soc-dapm.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include "rl6231.h"
  33 #include "rt5514.h"
  34 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
  35 #include "rt5514-spi.h"
  36 #endif
  37
  38 static const struct reg_sequence rt5514_i2c_patch[] = {
  39         {0x1800101c, 0x00000000},
  40         {0x18001100, 0x0000031f},
  41         {0x18001104, 0x00000007},
  42         {0x18001108, 0x00000000},
  43         {0x1800110c, 0x00000000},
  44         {0x18001110, 0x00000000},
  45         {0x18001114, 0x00000001},
  46         {0x18001118, 0x00000000},
  47         {0x18002f08, 0x00000006},
  48         {0x18002f00, 0x00055149},
  49         {0x18002f00, 0x0005514b},
  50         {0x18002f00, 0x00055149},
  51         {0xfafafafa, 0x00000001},
  52         {0x18002f10, 0x00000001},
  53         {0x18002f10, 0x00000000},
  54         {0x18002f10, 0x00000001},
  55         {0xfafafafa, 0x00000001},
  56         {0x18002000, 0x000010ec},
  57         {0xfafafafa, 0x00000000},
  58 };
  59
  60 static const struct reg_sequence rt5514_patch[] = {
  61         {RT5514_DIG_IO_CTRL,            0x00000040},
  62         {RT5514_CLK_CTRL1,              0x38020041},
  63         {RT5514_SRC_CTRL,               0x44000eee},
  64         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  65         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
  66         {RT5514_ASRC_IN_CTRL1,          0x00000003},
  67         {RT5514_DOWNFILTER0_CTRL3,      0x10000342},
  68         {RT5514_DOWNFILTER1_CTRL3,      0x10000342},
  69 };
  70
  71 static const struct reg_default rt5514_reg[] = {
  72         {RT5514_RESET,                  0x00000000},
  73         {RT5514_PWR_ANA1,               0x00808880},
  74         {RT5514_PWR_ANA2,               0x00220000},
  75         {RT5514_I2S_CTRL1,              0x00000330},
  76         {RT5514_I2S_CTRL2,              0x20000000},
  77         {RT5514_VAD_CTRL6,              0xc00007d2},
  78         {RT5514_EXT_VAD_CTRL,           0x80000080},
  79         {RT5514_DIG_IO_CTRL,            0x00000040},
  80         {RT5514_PAD_CTRL1,              0x00804000},
  81         {RT5514_DMIC_DATA_CTRL,         0x00000005},
  82         {RT5514_DIG_SOURCE_CTRL,        0x00000002},
  83         {RT5514_SRC_CTRL,               0x44000eee},
  84         {RT5514_DOWNFILTER2_CTRL1,      0x0000882f},
  85         {RT5514_PLL_SOURCE_CTRL,        0x00000004},
  86         {RT5514_CLK_CTRL1,              0x38020041},
  87         {RT5514_CLK_CTRL2,              0x00000000},
  88         {RT5514_PLL3_CALIB_CTRL1,       0x00400200},
  89         {RT5514_PLL3_CALIB_CTRL5,       0x40220012},
  90         {RT5514_DELAY_BUF_CTRL1,        0x7fff006a},
  91         {RT5514_DELAY_BUF_CTRL3,        0x00000000},
  92         {RT5514_ASRC_IN_CTRL1,          0x00000003},
  93         {RT5514_DOWNFILTER0_CTRL1,      0x00020c2f},
  94         {RT5514_DOWNFILTER0_CTRL2,      0x00020c2f},
  95         {RT5514_DOWNFILTER0_CTRL3,      0x10000342},
  96         {RT5514_DOWNFILTER1_CTRL1,      0x00020c2f},
  97         {RT5514_DOWNFILTER1_CTRL2,      0x00020c2f},
  98         {RT5514_DOWNFILTER1_CTRL3,      0x10000342},
  99         {RT5514_ANA_CTRL_LDO10,         0x00028604},
 100         {RT5514_ANA_CTRL_LDO18_16,      0x02000345},
 101         {RT5514_ANA_CTRL_ADC12,         0x0000a2a8},
 102         {RT5514_ANA_CTRL_ADC21,         0x00001180},
 103         {RT5514_ANA_CTRL_ADC22,         0x0000aaa8},
 104         {RT5514_ANA_CTRL_ADC23,         0x00151427},
 105         {RT5514_ANA_CTRL_MICBST,        0x00002000},
 106         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
 107         {RT5514_ANA_CTRL_INBUF,         0x00000143},
 108         {RT5514_ANA_CTRL_VREF,          0x00008d50},
 109         {RT5514_ANA_CTRL_PLL3,          0x0000000e},
 110         {RT5514_ANA_CTRL_PLL1_1,        0x00000000},
 111         {RT5514_ANA_CTRL_PLL1_2,        0x00030220},
 112         {RT5514_DMIC_LP_CTRL,           0x00000000},
 113         {RT5514_MISC_CTRL_DSP,          0x00000000},
 114         {RT5514_DSP_CTRL1,              0x00055149},
 115         {RT5514_DSP_CTRL3,              0x00000006},
 116         {RT5514_DSP_CTRL4,              0x00000001},
 117         {RT5514_VENDOR_ID1,             0x00000001},
 118         {RT5514_VENDOR_ID2,             0x10ec5514},
 119 };
 120
 121 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
 122 {
 123         /* Reset */
 124         regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
 125         /* LDO_I_limit */
 126         regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
 127         /* I2C bypass enable */
 128         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
 129         /* mini-core reset */
 130         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
 131         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
 132         /* I2C bypass disable */
 133         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
 134         /* PIN config */
 135         regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
 136         /* PLL3(QN)=RCOSC*(10+2) */
 137         regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
 138         /* PLL3 source=RCOSC, fsi=rt_clk */
 139         regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
 140         /* Power on RCOSC, pll3 */
 141         regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
 142         /* DSP clk source = pll3, ENABLE DSP clk */
 143         regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
 144         /* Enable DSP clk auto switch */
 145         regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
 146         /* Reduce DSP power */
 147         regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
 148 }
 149
 150 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
 151 {
 152         switch (reg) {
 153         case RT5514_VENDOR_ID1:
 154         case RT5514_VENDOR_ID2:
 155                 return true;
 156
 157         default:
 158                 return false;
 159         }
 160 }
 161
 162 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
 163 {
 164         switch (reg) {
 165         case RT5514_RESET:
 166         case RT5514_PWR_ANA1:
 167         case RT5514_PWR_ANA2:
 168         case RT5514_I2S_CTRL1:
 169         case RT5514_I2S_CTRL2:
 170         case RT5514_VAD_CTRL6:
 171         case RT5514_EXT_VAD_CTRL:
 172         case RT5514_DIG_IO_CTRL:
 173         case RT5514_PAD_CTRL1:
 174         case RT5514_DMIC_DATA_CTRL:
 175         case RT5514_DIG_SOURCE_CTRL:
 176         case RT5514_SRC_CTRL:
 177         case RT5514_DOWNFILTER2_CTRL1:
 178         case RT5514_PLL_SOURCE_CTRL:
 179         case RT5514_CLK_CTRL1:
 180         case RT5514_CLK_CTRL2:
 181         case RT5514_PLL3_CALIB_CTRL1:
 182         case RT5514_PLL3_CALIB_CTRL5:
 183         case RT5514_DELAY_BUF_CTRL1:
 184         case RT5514_DELAY_BUF_CTRL3:
 185         case RT5514_ASRC_IN_CTRL1:
 186         case RT5514_DOWNFILTER0_CTRL1:
 187         case RT5514_DOWNFILTER0_CTRL2:
 188         case RT5514_DOWNFILTER0_CTRL3:
 189         case RT5514_DOWNFILTER1_CTRL1:
 190         case RT5514_DOWNFILTER1_CTRL2:
 191         case RT5514_DOWNFILTER1_CTRL3:
 192         case RT5514_ANA_CTRL_LDO10:
 193         case RT5514_ANA_CTRL_LDO18_16:
 194         case RT5514_ANA_CTRL_ADC12:
 195         case RT5514_ANA_CTRL_ADC21:
 196         case RT5514_ANA_CTRL_ADC22:
 197         case RT5514_ANA_CTRL_ADC23:
 198         case RT5514_ANA_CTRL_MICBST:
 199         case RT5514_ANA_CTRL_ADCFED:
 200         case RT5514_ANA_CTRL_INBUF:
 201         case RT5514_ANA_CTRL_VREF:
 202         case RT5514_ANA_CTRL_PLL3:
 203         case RT5514_ANA_CTRL_PLL1_1:
 204         case RT5514_ANA_CTRL_PLL1_2:
 205         case RT5514_DMIC_LP_CTRL:
 206         case RT5514_MISC_CTRL_DSP:
 207         case RT5514_DSP_CTRL1:
 208         case RT5514_DSP_CTRL3:
 209         case RT5514_DSP_CTRL4:
 210         case RT5514_VENDOR_ID1:
 211         case RT5514_VENDOR_ID2:
 212                 return true;
 213
 214         default:
 215                 return false;
 216         }
 217 }
 218
 219 static bool rt5514_i2c_readable_register(struct device *dev,
 220         unsigned int reg)
 221 {
 222         switch (reg) {
 223         case RT5514_DSP_MAPPING | RT5514_RESET:
 224         case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
 225         case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
 226         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
 227         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
 228         case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
 229         case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
 230         case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
 231         case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
 232         case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
 233         case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
 234         case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
 235         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
 236         case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
 237         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
 238         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
 239         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
 240         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
 241         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
 242         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
 243         case RT5514_DSP_MAPPING | RT5514_ASRC_IN_CTRL1:
 244         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
 245         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
 246         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
 247         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
 248         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
 249         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
 250         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
 251         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
 252         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
 253         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
 254         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
 255         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
 256         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
 257         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
 258         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
 259         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
 260         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
 261         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
 262         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
 263         case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
 264         case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
 265         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
 266         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
 267         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
 268         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
 269         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
 270                 return true;
 271
 272         default:
 273                 return false;
 274         }
 275 }
 276
 277 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
 278 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 279         0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
 280         3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
 281         4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
 282         5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
 283         6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
 284         7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
 285         8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
 286 );
 287
 288 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 289
 290 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
 291                 struct snd_ctl_elem_value *ucontrol)
 292 {
 293         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 294         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 295
 296         ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
 297
 298         return 0;
 299 }
 300
 301 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
 302                 struct snd_ctl_elem_value *ucontrol)
 303 {
 304         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 305         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 306         struct snd_soc_codec *codec = rt5514->codec;
 307         const struct firmware *fw = NULL;
 308
 309         if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
 310                 return 0;
 311
 312         if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 313                 rt5514->dsp_enabled = ucontrol->value.integer.value[0];
 314
 315                 if (rt5514->dsp_enabled) {
 316                         rt5514_enable_dsp_prepare(rt5514);
 317
 318                         reject_firmware(&fw, RT5514_FIRMWARE1, codec->dev);
 319                         if (fw) {
 320 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 321                                 rt5514_spi_burst_write(0x4ff60000, fw->data,
 322                                         ((fw->size/8)+1)*8);
 323 #else
 324                                 dev_err(codec->dev, "There is no SPI driver for"
 325                                         " loading the firmware\n");
 326 #endif
 327                                 release_firmware(fw);
 328                                 fw = NULL;
 329                         }
 330
 331                         reject_firmware(&fw, RT5514_FIRMWARE2, codec->dev);
 332                         if (fw) {
 333 #if IS_ENABLED(CONFIG_SND_SOC_RT5514_SPI)
 334                                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
 335                                         ((fw->size/8)+1)*8);
 336 #else
 337                                 dev_err(codec->dev, "There is no SPI driver for"
 338                                         " loading the firmware\n");
 339 #endif
 340                                 release_firmware(fw);
 341                                 fw = NULL;
 342                         }
 343
 344                         /* DSP run */
 345                         regmap_write(rt5514->i2c_regmap, 0x18002f00,
 346                                 0x00055148);
 347                 } else {
 348                         regmap_multi_reg_write(rt5514->i2c_regmap,
 349                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 350                         regcache_mark_dirty(rt5514->regmap);
 351                         regcache_sync(rt5514->regmap);
 352                 }
 353         }
 354
 355         return 1;
 356 }
 357
 358 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
 359         SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
 360                 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
 361         SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
 362                 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 363                 adc_vol_tlv),
 364         SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
 365                 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 366                 adc_vol_tlv),
 367         SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
 368                 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
 369 };
 370
 371 /* ADC Mixer*/
 372 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
 373         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
 374                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 375         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
 376                 RT5514_AD_AD_MIX_BIT, 1, 1),
 377 };
 378
 379 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
 380         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
 381                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 382         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
 383                 RT5514_AD_AD_MIX_BIT, 1, 1),
 384 };
 385
 386 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
 387         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
 388                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 389         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
 390                 RT5514_AD_AD_MIX_BIT, 1, 1),
 391 };
 392
 393 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
 394         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
 395                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 396         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
 397                 RT5514_AD_AD_MIX_BIT, 1, 1),
 398 };
 399
 400 /* DMIC Source */
 401 static const char * const rt5514_dmic_src[] = {
 402         "DMIC1", "DMIC2"
 403 };
 404
 405 static SOC_ENUM_SINGLE_DECL(
 406         rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 407         RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 408
 409 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
 410         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
 411
 412 static SOC_ENUM_SINGLE_DECL(
 413         rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 414         RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 415
 416 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
 417         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
 418
 419 /**
 420  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
 421  *
 422  * @rate: base clock rate.
 423  *
 424  * Choose divider parameter that gives the highest possible DMIC frequency in
 425  * 1MHz - 3MHz range.
 426  */
 427 static int rt5514_calc_dmic_clk(struct snd_soc_codec *codec, int rate)
 428 {
 429         int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
 430         int i;
 431
 432         if (rate < 1000000 * div[0]) {
 433                 pr_warn("Base clock rate %d is too low\n", rate);
 434                 return -EINVAL;
 435         }
 436
 437         for (i = 0; i < ARRAY_SIZE(div); i++) {
 438                 /* find divider that gives DMIC frequency below 3.072MHz */
 439                 if (3072000 * div[i] >= rate)
 440                         return i;
 441         }
 442
 443         dev_warn(codec->dev, "Base clock rate %d is too high\n", rate);
 444         return -EINVAL;
 445 }
 446
 447 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
 448         struct snd_kcontrol *kcontrol, int event)
 449 {
 450         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 451         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 452         int idx;
 453
 454         idx = rt5514_calc_dmic_clk(codec, rt5514->sysclk);
 455         if (idx < 0)
 456                 dev_err(codec->dev, "Failed to set DMIC clock\n");
 457         else
 458                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 459                         RT5514_CLK_DMIC_OUT_SEL_MASK,
 460                         idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
 461
 462         if (rt5514->pdata.dmic_init_delay)
 463                 msleep(rt5514->pdata.dmic_init_delay);
 464
 465         return idx;
 466 }
 467
 468 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 469                          struct snd_soc_dapm_widget *sink)
 470 {
 471         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 472         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 473
 474         if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
 475                 return 1;
 476         else
 477                 return 0;
 478 }
 479
 480 static int rt5514_i2s_use_asrc(struct snd_soc_dapm_widget *source,
 481         struct snd_soc_dapm_widget *sink)
 482 {
 483         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 484         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 485
 486         return (rt5514->sysclk > rt5514->lrck * 384);
 487 }
 488
 489 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
 490         /* Input Lines */
 491         SND_SOC_DAPM_INPUT("DMIC1L"),
 492         SND_SOC_DAPM_INPUT("DMIC1R"),
 493         SND_SOC_DAPM_INPUT("DMIC2L"),
 494         SND_SOC_DAPM_INPUT("DMIC2R"),
 495
 496         SND_SOC_DAPM_INPUT("AMICL"),
 497         SND_SOC_DAPM_INPUT("AMICR"),
 498
 499         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 500         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 501
 502         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
 503                 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 504
 505         SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
 506                 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
 507
 508         SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
 509                 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
 510         SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
 511                 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
 512         SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
 513                 NULL, 0),
 514         SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
 515                 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
 516         SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
 517                 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
 518         SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
 519                 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
 520         SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
 521                 NULL, 0),
 522         SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
 523                 NULL, 0),
 524         SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
 525                 NULL, 0),
 526         SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 527
 528
 529         SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
 530                 NULL, 0),
 531         SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
 532                 NULL, 0),
 533         SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
 534                 NULL, 0),
 535         SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
 536                 NULL, 0),
 537         SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
 538                 0, NULL, 0),
 539         SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 540
 541         SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
 542                 NULL, 0),
 543         SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
 544                 NULL, 0),
 545         SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
 546                 NULL, 0),
 547         SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
 548                 NULL, 0),
 549         SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
 550                 0, NULL, 0),
 551         SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 552
 553         SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
 554                 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
 555         SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
 556                 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
 557         SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
 558                 NULL, 0),
 559         SND_SOC_DAPM_SUPPLY_S("ASRC AD1", 1, RT5514_CLK_CTRL2,
 560                 RT5514_CLK_AD0_ASRC_EN_BIT, 0, NULL, 0),
 561         SND_SOC_DAPM_SUPPLY_S("ASRC AD2", 1, RT5514_CLK_CTRL2,
 562                 RT5514_CLK_AD1_ASRC_EN_BIT, 0, NULL, 0),
 563
 564         /* ADC Mux */
 565         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 566                                 &rt5514_sto1_dmic_mux),
 567         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 568                                 &rt5514_sto2_dmic_mux),
 569
 570         /* ADC Mixer */
 571         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
 572                 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
 573         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
 574                 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
 575
 576         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 577                 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
 578         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 579                 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
 580         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 581                 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
 582         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 583                 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
 584
 585         SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
 586                 RT5514_AD_AD_MUTE_BIT, 1),
 587         SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
 588                 RT5514_AD_AD_MUTE_BIT, 1),
 589         SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
 590                 RT5514_AD_AD_MUTE_BIT, 1),
 591         SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
 592                 RT5514_AD_AD_MUTE_BIT, 1),
 593
 594         /* ADC PGA */
 595         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 596         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 597
 598         /* Audio Interface */
 599         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 600 };
 601
 602 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
 603         { "DMIC1", NULL, "DMIC1L" },
 604         { "DMIC1", NULL, "DMIC1R" },
 605         { "DMIC2", NULL, "DMIC2L" },
 606         { "DMIC2", NULL, "DMIC2R" },
 607
 608         { "DMIC1L", NULL, "DMIC CLK" },
 609         { "DMIC1R", NULL, "DMIC CLK" },
 610         { "DMIC2L", NULL, "DMIC CLK" },
 611         { "DMIC2R", NULL, "DMIC CLK" },
 612
 613         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 614         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 615
 616         { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
 617         { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
 618         { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
 619         { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
 620
 621         { "ADC Power", NULL, "LDO18 IN" },
 622         { "ADC Power", NULL, "LDO18 ADC" },
 623         { "ADC Power", NULL, "LDO21" },
 624         { "ADC Power", NULL, "BG LDO18 IN" },
 625         { "ADC Power", NULL, "BG LDO21" },
 626         { "ADC Power", NULL, "BG MBIAS" },
 627         { "ADC Power", NULL, "MBIAS" },
 628         { "ADC Power", NULL, "VREF2" },
 629         { "ADC Power", NULL, "VREF1" },
 630
 631         { "ADCL Power", NULL, "LDO16L" },
 632         { "ADCL Power", NULL, "ADC1L" },
 633         { "ADCL Power", NULL, "BSTL2" },
 634         { "ADCL Power", NULL, "BSTL" },
 635         { "ADCL Power", NULL, "ADCFEDL" },
 636
 637         { "ADCR Power", NULL, "LDO16R" },
 638         { "ADCR Power", NULL, "ADC1R" },
 639         { "ADCR Power", NULL, "BSTR2" },
 640         { "ADCR Power", NULL, "BSTR" },
 641         { "ADCR Power", NULL, "ADCFEDR" },
 642
 643         { "AMICL", NULL, "ADC CLK" },
 644         { "AMICL", NULL, "ADC Power" },
 645         { "AMICL", NULL, "ADCL Power" },
 646         { "AMICR", NULL, "ADC CLK" },
 647         { "AMICR", NULL, "ADC Power" },
 648         { "AMICR", NULL, "ADCR Power" },
 649
 650         { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
 651         { "PLL1", NULL, "PLL1 LDO" },
 652
 653         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 654         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 655
 656         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 657         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 658         { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
 659         { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 660         { "adc stereo1 filter", NULL, "ASRC AD1", rt5514_i2s_use_asrc },
 661
 662         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 663         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 664
 665         { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
 666         { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
 667         { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
 668         { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
 669
 670         { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
 671         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 672
 673         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 674         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 675         { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
 676         { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 677         { "adc stereo2 filter", NULL, "ASRC AD2", rt5514_i2s_use_asrc },
 678
 679         { "AIF1TX", NULL, "Stereo1 ADC MIX"},
 680         { "AIF1TX", NULL, "Stereo2 ADC MIX"},
 681 };
 682
 683 static int rt5514_hw_params(struct snd_pcm_substream *substream,
 684         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 685 {
 686         struct snd_soc_codec *codec = dai->codec;
 687         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 688         int pre_div, bclk_ms, frame_size;
 689         unsigned int val_len = 0;
 690
 691         rt5514->lrck = params_rate(params);
 692         pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
 693         if (pre_div < 0) {
 694                 dev_err(codec->dev, "Unsupported clock setting\n");
 695                 return -EINVAL;
 696         }
 697
 698         frame_size = snd_soc_params_to_frame_size(params);
 699         if (frame_size < 0) {
 700                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
 701                 return -EINVAL;
 702         }
 703
 704         bclk_ms = frame_size > 32;
 705         rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
 706
 707         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 708                 rt5514->bclk, rt5514->lrck);
 709         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 710                                 bclk_ms, pre_div, dai->id);
 711
 712         switch (params_format(params)) {
 713         case SNDRV_PCM_FORMAT_S16_LE:
 714                 break;
 715         case SNDRV_PCM_FORMAT_S20_3LE:
 716                 val_len = RT5514_I2S_DL_20;
 717                 break;
 718         case SNDRV_PCM_FORMAT_S24_LE:
 719                 val_len = RT5514_I2S_DL_24;
 720                 break;
 721         case SNDRV_PCM_FORMAT_S8:
 722                 val_len = RT5514_I2S_DL_8;
 723                 break;
 724         default:
 725                 return -EINVAL;
 726         }
 727
 728         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
 729                 val_len);
 730         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 731                 RT5514_CLK_AD_ANA1_SEL_MASK,
 732                 (pre_div + 1) << RT5514_CLK_AD_ANA1_SEL_SFT);
 733         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 734                 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
 735                 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
 736                 pre_div << RT5514_SEL_ADC_OSR_SFT);
 737
 738         return 0;
 739 }
 740
 741 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 742 {
 743         struct snd_soc_codec *codec = dai->codec;
 744         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 745         unsigned int reg_val = 0;
 746
 747         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 748         case SND_SOC_DAIFMT_NB_NF:
 749                 break;
 750
 751         case SND_SOC_DAIFMT_NB_IF:
 752                 reg_val |= RT5514_I2S_LR_INV;
 753                 break;
 754
 755         case SND_SOC_DAIFMT_IB_NF:
 756                 reg_val |= RT5514_I2S_BP_INV;
 757                 break;
 758
 759         case SND_SOC_DAIFMT_IB_IF:
 760                 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
 761                 break;
 762
 763         default:
 764                 return -EINVAL;
 765         }
 766
 767         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 768         case SND_SOC_DAIFMT_I2S:
 769                 break;
 770
 771         case SND_SOC_DAIFMT_LEFT_J:
 772                 reg_val |= RT5514_I2S_DF_LEFT;
 773                 break;
 774
 775         case SND_SOC_DAIFMT_DSP_A:
 776                 reg_val |= RT5514_I2S_DF_PCM_A;
 777                 break;
 778
 779         case SND_SOC_DAIFMT_DSP_B:
 780                 reg_val |= RT5514_I2S_DF_PCM_B;
 781                 break;
 782
 783         default:
 784                 return -EINVAL;
 785         }
 786
 787         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
 788                 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
 789                 reg_val);
 790
 791         return 0;
 792 }
 793
 794 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
 795                 int clk_id, unsigned int freq, int dir)
 796 {
 797         struct snd_soc_codec *codec = dai->codec;
 798         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 799         unsigned int reg_val = 0;
 800
 801         if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
 802                 return 0;
 803
 804         switch (clk_id) {
 805         case RT5514_SCLK_S_MCLK:
 806                 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
 807                 break;
 808
 809         case RT5514_SCLK_S_PLL1:
 810                 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
 811                 break;
 812
 813         default:
 814                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 815                 return -EINVAL;
 816         }
 817
 818         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 819                 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
 820
 821         rt5514->sysclk = freq;
 822         rt5514->sysclk_src = clk_id;
 823
 824         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 825
 826         return 0;
 827 }
 828
 829 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 830                         unsigned int freq_in, unsigned int freq_out)
 831 {
 832         struct snd_soc_codec *codec = dai->codec;
 833         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 834         struct rl6231_pll_code pll_code;
 835         int ret;
 836
 837         if (!freq_in || !freq_out) {
 838                 dev_dbg(codec->dev, "PLL disabled\n");
 839
 840                 rt5514->pll_in = 0;
 841                 rt5514->pll_out = 0;
 842                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 843                         RT5514_CLK_SYS_PRE_SEL_MASK,
 844                         RT5514_CLK_SYS_PRE_SEL_MCLK);
 845
 846                 return 0;
 847         }
 848
 849         if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
 850             freq_out == rt5514->pll_out)
 851                 return 0;
 852
 853         switch (source) {
 854         case RT5514_PLL1_S_MCLK:
 855                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 856                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
 857                 break;
 858
 859         case RT5514_PLL1_S_BCLK:
 860                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 861                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
 862                 break;
 863
 864         default:
 865                 dev_err(codec->dev, "Unknown PLL source %d\n", source);
 866                 return -EINVAL;
 867         }
 868
 869         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 870         if (ret < 0) {
 871                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
 872                 return ret;
 873         }
 874
 875         dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
 876                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 877                 pll_code.n_code, pll_code.k_code);
 878
 879         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
 880                 pll_code.k_code << RT5514_PLL_K_SFT |
 881                 pll_code.n_code << RT5514_PLL_N_SFT |
 882                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
 883         regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
 884                 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
 885
 886         rt5514->pll_in = freq_in;
 887         rt5514->pll_out = freq_out;
 888         rt5514->pll_src = source;
 889
 890         return 0;
 891 }
 892
 893 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 894                         unsigned int rx_mask, int slots, int slot_width)
 895 {
 896         struct snd_soc_codec *codec = dai->codec;
 897         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 898         unsigned int val = 0, val2 = 0;
 899
 900         if (rx_mask || tx_mask)
 901                 val |= RT5514_TDM_MODE;
 902
 903         switch (tx_mask) {
 904         case 0x3:
 905                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
 906                         RT5514_TDM_DOCKING_START_SLOT0;
 907                 break;
 908
 909         case 0x30:
 910                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH2 |
 911                         RT5514_TDM_DOCKING_START_SLOT4;
 912                 break;
 913
 914         case 0xf:
 915                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
 916                         RT5514_TDM_DOCKING_START_SLOT0;
 917                 break;
 918
 919         case 0xf0:
 920                 val2 |= RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH4 |
 921                         RT5514_TDM_DOCKING_START_SLOT4;
 922                 break;
 923
 924         default:
 925                 break;
 926         }
 927
 928
 929
 930         switch (slots) {
 931         case 4:
 932                 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
 933                 break;
 934
 935         case 6:
 936                 val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
 937                 break;
 938
 939         case 8:
 940                 val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
 941                 break;
 942
 943         case 2:
 944         default:
 945                 break;
 946         }
 947
 948         switch (slot_width) {
 949         case 20:
 950                 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
 951                 break;
 952
 953         case 24:
 954                 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
 955                 break;
 956
 957         case 25:
 958                 val |= RT5514_TDM_MODE2;
 959                 break;
 960
 961         case 32:
 962                 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
 963                 break;
 964
 965         case 16:
 966         default:
 967                 break;
 968         }
 969
 970         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
 971                 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
 972                 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
 973                 RT5514_TDM_MODE2, val);
 974
 975         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL2,
 976                 RT5514_TDM_DOCKING_MODE | RT5514_TDM_DOCKING_VALID_CH_MASK |
 977                 RT5514_TDM_DOCKING_START_MASK, val2);
 978
 979         return 0;
 980 }
 981
 982 static int rt5514_set_bias_level(struct snd_soc_codec *codec,
 983                         enum snd_soc_bias_level level)
 984 {
 985         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 986         int ret;
 987
 988         switch (level) {
 989         case SND_SOC_BIAS_PREPARE:
 990                 if (IS_ERR(rt5514->mclk))
 991                         break;
 992
 993                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
 994                         clk_disable_unprepare(rt5514->mclk);
 995                 } else {
 996                         ret = clk_prepare_enable(rt5514->mclk);
 997                         if (ret)
 998                                 return ret;
 999                 }
1000                 break;
1001
1002         case SND_SOC_BIAS_STANDBY:
1003                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1004                         /*
1005                          * If the DSP is enabled in start of recording, the DSP
1006                          * should be disabled, and sync back to normal recording
1007                          * settings to make sure recording properly.
1008                          */
1009                         if (rt5514->dsp_enabled) {
1010                                 rt5514->dsp_enabled = 0;
1011                                 regmap_multi_reg_write(rt5514->i2c_regmap,
1012                                         rt5514_i2c_patch,
1013                                         ARRAY_SIZE(rt5514_i2c_patch));
1014                                 regcache_mark_dirty(rt5514->regmap);
1015                                 regcache_sync(rt5514->regmap);
1016                         }
1017                 }
1018                 break;
1019
1020         default:
1021                 break;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int rt5514_probe(struct snd_soc_codec *codec)
1028 {
1029         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
1030
1031         rt5514->mclk = devm_clk_get(codec->dev, "mclk");
1032         if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
1033                 return -EPROBE_DEFER;
1034
1035         rt5514->codec = codec;
1036
1037         return 0;
1038 }
1039
1040 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
1041 {
1042         struct i2c_client *client = context;
1043         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1044
1045         regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1046
1047         return 0;
1048 }
1049
1050 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
1051 {
1052         struct i2c_client *client = context;
1053         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
1054
1055         regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
1056
1057         return 0;
1058 }
1059
1060 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1061 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1062                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1063
1064 static const struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1065         .hw_params = rt5514_hw_params,
1066         .set_fmt = rt5514_set_dai_fmt,
1067         .set_sysclk = rt5514_set_dai_sysclk,
1068         .set_pll = rt5514_set_dai_pll,
1069         .set_tdm_slot = rt5514_set_tdm_slot,
1070 };
1071
1072 static struct snd_soc_dai_driver rt5514_dai[] = {
1073         {
1074                 .name = "rt5514-aif1",
1075                 .id = 0,
1076                 .capture = {
1077                         .stream_name = "AIF1 Capture",
1078                         .channels_min = 1,
1079                         .channels_max = 4,
1080                         .rates = RT5514_STEREO_RATES,
1081                         .formats = RT5514_FORMATS,
1082                 },
1083                 .ops = &rt5514_aif_dai_ops,
1084         }
1085 };
1086
1087 static const struct snd_soc_codec_driver soc_codec_dev_rt5514 = {
1088         .probe = rt5514_probe,
1089         .idle_bias_off = true,
1090         .set_bias_level = rt5514_set_bias_level,
1091         .component_driver = {
1092                 .controls               = rt5514_snd_controls,
1093                 .num_controls           = ARRAY_SIZE(rt5514_snd_controls),
1094                 .dapm_widgets           = rt5514_dapm_widgets,
1095                 .num_dapm_widgets       = ARRAY_SIZE(rt5514_dapm_widgets),
1096                 .dapm_routes            = rt5514_dapm_routes,
1097                 .num_dapm_routes        = ARRAY_SIZE(rt5514_dapm_routes),
1098         },
1099 };
1100
1101 static const struct regmap_config rt5514_i2c_regmap = {
1102         .name = "i2c",
1103         .reg_bits = 32,
1104         .val_bits = 32,
1105
1106         .readable_reg = rt5514_i2c_readable_register,
1107
1108         .cache_type = REGCACHE_NONE,
1109 };
1110
1111 static const struct regmap_config rt5514_regmap = {
1112         .reg_bits = 16,
1113         .val_bits = 32,
1114
1115         .max_register = RT5514_VENDOR_ID2,
1116         .volatile_reg = rt5514_volatile_register,
1117         .readable_reg = rt5514_readable_register,
1118         .reg_read = rt5514_i2c_read,
1119         .reg_write = rt5514_i2c_write,
1120
1121         .cache_type = REGCACHE_RBTREE,
1122         .reg_defaults = rt5514_reg,
1123         .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1124         .use_single_rw = true,
1125 };
1126
1127 static const struct i2c_device_id rt5514_i2c_id[] = {
1128         { "rt5514", 0 },
1129         { }
1130 };
1131 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1132
1133 #if defined(CONFIG_OF)
1134 static const struct of_device_id rt5514_of_match[] = {
1135         { .compatible = "realtek,rt5514", },
1136         {},
1137 };
1138 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1139 #endif
1140
1141 #ifdef CONFIG_ACPI
1142 static const struct acpi_device_id rt5514_acpi_match[] = {
1143         { "10EC5514", 0},
1144         {},
1145 };
1146 MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
1147 #endif
1148
1149 static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
1150 {
1151         device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1152                 &rt5514->pdata.dmic_init_delay);
1153
1154         return 0;
1155 }
1156
1157 static __maybe_unused int rt5514_i2c_resume(struct device *dev)
1158 {
1159         struct rt5514_priv *rt5514 = dev_get_drvdata(dev);
1160         unsigned int val;
1161
1162         /*
1163          * Add a bogus read to avoid rt5514's confusion after s2r in case it
1164          * saw glitches on the i2c lines and thought the other side sent a
1165          * start bit.
1166          */
1167         regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1168
1169         return 0;
1170 }
1171
1172 static int rt5514_i2c_probe(struct i2c_client *i2c,
1173                     const struct i2c_device_id *id)
1174 {
1175         struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1176         struct rt5514_priv *rt5514;
1177         int ret;
1178         unsigned int val = ~0;
1179
1180         rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1181                                 GFP_KERNEL);
1182         if (rt5514 == NULL)
1183                 return -ENOMEM;
1184
1185         i2c_set_clientdata(i2c, rt5514);
1186
1187         if (pdata)
1188                 rt5514->pdata = *pdata;
1189         else if (i2c->dev.of_node)
1190                 rt5514_parse_dt(rt5514, &i2c->dev);
1191
1192         rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1193         if (IS_ERR(rt5514->i2c_regmap)) {
1194                 ret = PTR_ERR(rt5514->i2c_regmap);
1195                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1196                         ret);
1197                 return ret;
1198         }
1199
1200         rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1201         if (IS_ERR(rt5514->regmap)) {
1202                 ret = PTR_ERR(rt5514->regmap);
1203                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1204                         ret);
1205                 return ret;
1206         }
1207
1208         /*
1209          * The rt5514 can get confused if the i2c lines glitch together, as
1210          * can happen at bootup as regulators are turned off and on.  If it's
1211          * in this glitched state the first i2c read will fail, so we'll give
1212          * it one change to retry.
1213          */
1214         ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1215         if (ret || val != RT5514_DEVICE_ID)
1216                 ret = regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1217         if (ret || val != RT5514_DEVICE_ID) {
1218                 dev_err(&i2c->dev,
1219                         "Device with ID register %x is not rt5514\n", val);
1220                 return -ENODEV;
1221         }
1222
1223         ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1224                                     ARRAY_SIZE(rt5514_i2c_patch));
1225         if (ret != 0)
1226                 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1227                         ret);
1228
1229         ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1230                                     ARRAY_SIZE(rt5514_patch));
1231         if (ret != 0)
1232                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1233
1234         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5514,
1235                         rt5514_dai, ARRAY_SIZE(rt5514_dai));
1236 }
1237
1238 static int rt5514_i2c_remove(struct i2c_client *i2c)
1239 {
1240         snd_soc_unregister_codec(&i2c->dev);
1241
1242         return 0;
1243 }
1244
1245 static const struct dev_pm_ops rt5514_i2_pm_ops = {
1246         SET_SYSTEM_SLEEP_PM_OPS(NULL, rt5514_i2c_resume)
1247 };
1248
1249 static struct i2c_driver rt5514_i2c_driver = {
1250         .driver = {
1251                 .name = "rt5514",
1252                 .acpi_match_table = ACPI_PTR(rt5514_acpi_match),
1253                 .of_match_table = of_match_ptr(rt5514_of_match),
1254                 .pm = &rt5514_i2_pm_ops,
1255         },
1256         .probe = rt5514_i2c_probe,
1257         .remove   = rt5514_i2c_remove,
1258         .id_table = rt5514_i2c_id,
1259 };
1260 module_i2c_driver(rt5514_i2c_driver);
1261
1262 MODULE_DESCRIPTION("ASoC RT5514 driver");
1263 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1264 MODULE_LICENSE("GPL v2");