sound/soc/codecs/rt286.c

   1 /*
   2  * rt286.c  --  RT286 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2013 Realtek Semiconductor Corp.
   5  * Author: Bard Liao <bardliao@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/delay.h>
  16 #include <linux/pm.h>
  17 #include <linux/i2c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/dmi.h>
  21 #include <linux/acpi.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <sound/jack.h>
  30 #include <linux/workqueue.h>
  31 #include <sound/rt286.h>
  32
  33 #include "rl6347a.h"
  34 #include "rt286.h"
  35
  36 #define RT286_VENDOR_ID 0x10ec0286
  37 #define RT288_VENDOR_ID 0x10ec0288
  38
  39 struct rt286_priv {
  40         struct reg_default *index_cache;
  41         int index_cache_size;
  42         struct regmap *regmap;
  43         struct snd_soc_codec *codec;
  44         struct rt286_platform_data pdata;
  45         struct i2c_client *i2c;
  46         struct snd_soc_jack *jack;
  47         struct delayed_work jack_detect_work;
  48         int sys_clk;
  49         int clk_id;
  50 };
  51
  52 static const struct reg_default rt286_index_def[] = {
  53         { 0x01, 0xaaaa },
  54         { 0x02, 0x8aaa },
  55         { 0x03, 0x0002 },
  56         { 0x04, 0xaf01 },
  57         { 0x08, 0x000d },
  58         { 0x09, 0xd810 },
  59         { 0x0a, 0x0120 },
  60         { 0x0b, 0x0000 },
  61         { 0x0d, 0x2800 },
  62         { 0x0f, 0x0000 },
  63         { 0x19, 0x0a17 },
  64         { 0x20, 0x0020 },
  65         { 0x33, 0x0208 },
  66         { 0x49, 0x0004 },
  67         { 0x4f, 0x50e9 },
  68         { 0x50, 0x2000 },
  69         { 0x63, 0x2902 },
  70         { 0x67, 0x1111 },
  71         { 0x68, 0x1016 },
  72         { 0x69, 0x273f },
  73 };
  74 #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  75
  76 static const struct reg_default rt286_reg[] = {
  77         { 0x00170500, 0x00000400 },
  78         { 0x00220000, 0x00000031 },
  79         { 0x00239000, 0x0000007f },
  80         { 0x0023a000, 0x0000007f },
  81         { 0x00270500, 0x00000400 },
  82         { 0x00370500, 0x00000400 },
  83         { 0x00870500, 0x00000400 },
  84         { 0x00920000, 0x00000031 },
  85         { 0x00935000, 0x000000c3 },
  86         { 0x00936000, 0x000000c3 },
  87         { 0x00970500, 0x00000400 },
  88         { 0x00b37000, 0x00000097 },
  89         { 0x00b37200, 0x00000097 },
  90         { 0x00b37300, 0x00000097 },
  91         { 0x00c37000, 0x00000000 },
  92         { 0x00c37100, 0x00000080 },
  93         { 0x01270500, 0x00000400 },
  94         { 0x01370500, 0x00000400 },
  95         { 0x01371f00, 0x411111f0 },
  96         { 0x01439000, 0x00000080 },
  97         { 0x0143a000, 0x00000080 },
  98         { 0x01470700, 0x00000000 },
  99         { 0x01470500, 0x00000400 },
 100         { 0x01470c00, 0x00000000 },
 101         { 0x01470100, 0x00000000 },
 102         { 0x01837000, 0x00000000 },
 103         { 0x01870500, 0x00000400 },
 104         { 0x02050000, 0x00000000 },
 105         { 0x02139000, 0x00000080 },
 106         { 0x0213a000, 0x00000080 },
 107         { 0x02170100, 0x00000000 },
 108         { 0x02170500, 0x00000400 },
 109         { 0x02170700, 0x00000000 },
 110         { 0x02270100, 0x00000000 },
 111         { 0x02370100, 0x00000000 },
 112         { 0x01870700, 0x00000020 },
 113         { 0x00830000, 0x000000c3 },
 114         { 0x00930000, 0x000000c3 },
 115         { 0x01270700, 0x00000000 },
 116 };
 117
 118 static bool rt286_volatile_register(struct device *dev, unsigned int reg)
 119 {
 120         switch (reg) {
 121         case 0 ... 0xff:
 122         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 123         case RT286_GET_HP_SENSE:
 124         case RT286_GET_MIC1_SENSE:
 125         case RT286_PROC_COEF:
 126                 return true;
 127         default:
 128                 return false;
 129         }
 130
 131
 132 }
 133
 134 static bool rt286_readable_register(struct device *dev, unsigned int reg)
 135 {
 136         switch (reg) {
 137         case 0 ... 0xff:
 138         case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
 139         case RT286_GET_HP_SENSE:
 140         case RT286_GET_MIC1_SENSE:
 141         case RT286_SET_AUDIO_POWER:
 142         case RT286_SET_HPO_POWER:
 143         case RT286_SET_SPK_POWER:
 144         case RT286_SET_DMIC1_POWER:
 145         case RT286_SPK_MUX:
 146         case RT286_HPO_MUX:
 147         case RT286_ADC0_MUX:
 148         case RT286_ADC1_MUX:
 149         case RT286_SET_MIC1:
 150         case RT286_SET_PIN_HPO:
 151         case RT286_SET_PIN_SPK:
 152         case RT286_SET_PIN_DMIC1:
 153         case RT286_SPK_EAPD:
 154         case RT286_SET_AMP_GAIN_HPO:
 155         case RT286_SET_DMIC2_DEFAULT:
 156         case RT286_DACL_GAIN:
 157         case RT286_DACR_GAIN:
 158         case RT286_ADCL_GAIN:
 159         case RT286_ADCR_GAIN:
 160         case RT286_MIC_GAIN:
 161         case RT286_SPOL_GAIN:
 162         case RT286_SPOR_GAIN:
 163         case RT286_HPOL_GAIN:
 164         case RT286_HPOR_GAIN:
 165         case RT286_F_DAC_SWITCH:
 166         case RT286_F_RECMIX_SWITCH:
 167         case RT286_REC_MIC_SWITCH:
 168         case RT286_REC_I2S_SWITCH:
 169         case RT286_REC_LINE_SWITCH:
 170         case RT286_REC_BEEP_SWITCH:
 171         case RT286_DAC_FORMAT:
 172         case RT286_ADC_FORMAT:
 173         case RT286_COEF_INDEX:
 174         case RT286_PROC_COEF:
 175         case RT286_SET_AMP_GAIN_ADC_IN1:
 176         case RT286_SET_AMP_GAIN_ADC_IN2:
 177         case RT286_SET_GPIO_MASK:
 178         case RT286_SET_GPIO_DIRECTION:
 179         case RT286_SET_GPIO_DATA:
 180         case RT286_SET_POWER(RT286_DAC_OUT1):
 181         case RT286_SET_POWER(RT286_DAC_OUT2):
 182         case RT286_SET_POWER(RT286_ADC_IN1):
 183         case RT286_SET_POWER(RT286_ADC_IN2):
 184         case RT286_SET_POWER(RT286_DMIC2):
 185         case RT286_SET_POWER(RT286_MIC1):
 186                 return true;
 187         default:
 188                 return false;
 189         }
 190 }
 191
 192 #ifdef CONFIG_PM
 193 static void rt286_index_sync(struct snd_soc_codec *codec)
 194 {
 195         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 196         int i;
 197
 198         for (i = 0; i < INDEX_CACHE_SIZE; i++) {
 199                 snd_soc_write(codec, rt286->index_cache[i].reg,
 200                                   rt286->index_cache[i].def);
 201         }
 202 }
 203 #endif
 204
 205 static int rt286_support_power_controls[] = {
 206         RT286_DAC_OUT1,
 207         RT286_DAC_OUT2,
 208         RT286_ADC_IN1,
 209         RT286_ADC_IN2,
 210         RT286_MIC1,
 211         RT286_DMIC1,
 212         RT286_DMIC2,
 213         RT286_SPK_OUT,
 214         RT286_HP_OUT,
 215 };
 216 #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
 217
 218 static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
 219 {
 220         struct snd_soc_dapm_context *dapm;
 221         unsigned int val, buf;
 222
 223         *hp = false;
 224         *mic = false;
 225
 226         if (!rt286->codec)
 227                 return -EINVAL;
 228
 229         dapm = snd_soc_codec_get_dapm(rt286->codec);
 230
 231         if (rt286->pdata.cbj_en) {
 232                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 233                 *hp = buf & 0x80000000;
 234                 if (*hp) {
 235                         /* power on HV,VERF */
 236                         regmap_update_bits(rt286->regmap,
 237                                 RT286_DC_GAIN, 0x200, 0x200);
 238
 239                         snd_soc_dapm_force_enable_pin(dapm, "HV");
 240                         snd_soc_dapm_force_enable_pin(dapm, "VREF");
 241                         /* power LDO1 */
 242                         snd_soc_dapm_force_enable_pin(dapm, "LDO1");
 243                         snd_soc_dapm_sync(dapm);
 244
 245                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
 246                         msleep(50);
 247
 248                         regmap_update_bits(rt286->regmap,
 249                                 RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
 250                         msleep(300);
 251                         regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
 252
 253                         if (0x0070 == (val & 0x0070)) {
 254                                 *mic = true;
 255                         } else {
 256                                 regmap_update_bits(rt286->regmap,
 257                                         RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
 258                                 msleep(300);
 259                                 regmap_read(rt286->regmap,
 260                                         RT286_CBJ_CTRL2, &val);
 261                                 if (0x0070 == (val & 0x0070))
 262                                         *mic = true;
 263                                 else
 264                                         *mic = false;
 265                         }
 266                         regmap_update_bits(rt286->regmap,
 267                                 RT286_DC_GAIN, 0x200, 0x0);
 268
 269                 } else {
 270                         *mic = false;
 271                         regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
 272                         regmap_update_bits(rt286->regmap,
 273                                 RT286_CBJ_CTRL1, 0x0400, 0x0000);
 274                 }
 275         } else {
 276                 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
 277                 *hp = buf & 0x80000000;
 278                 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
 279                 *mic = buf & 0x80000000;
 280         }
 281
 282         snd_soc_dapm_disable_pin(dapm, "HV");
 283         snd_soc_dapm_disable_pin(dapm, "VREF");
 284         if (!*hp)
 285                 snd_soc_dapm_disable_pin(dapm, "LDO1");
 286         snd_soc_dapm_sync(dapm);
 287
 288         return 0;
 289 }
 290
 291 static void rt286_jack_detect_work(struct work_struct *work)
 292 {
 293         struct rt286_priv *rt286 =
 294                 container_of(work, struct rt286_priv, jack_detect_work.work);
 295         int status = 0;
 296         bool hp = false;
 297         bool mic = false;
 298
 299         rt286_jack_detect(rt286, &hp, &mic);
 300
 301         if (hp == true)
 302                 status |= SND_JACK_HEADPHONE;
 303
 304         if (mic == true)
 305                 status |= SND_JACK_MICROPHONE;
 306
 307         snd_soc_jack_report(rt286->jack, status,
 308                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 309 }
 310
 311 int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
 312 {
 313         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
 314         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 315
 316         rt286->jack = jack;
 317
 318         if (jack) {
 319                 /* enable IRQ */
 320                 if (rt286->jack->status & SND_JACK_HEADPHONE)
 321                         snd_soc_dapm_force_enable_pin(dapm, "LDO1");
 322                 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
 323                 /* Send an initial empty report */
 324                 snd_soc_jack_report(rt286->jack, rt286->jack->status,
 325                         SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 326         } else {
 327                 /* disable IRQ */
 328                 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
 329                 snd_soc_dapm_disable_pin(dapm, "LDO1");
 330         }
 331         snd_soc_dapm_sync(dapm);
 332
 333         return 0;
 334 }
 335 EXPORT_SYMBOL_GPL(rt286_mic_detect);
 336
 337 static int is_mclk_mode(struct snd_soc_dapm_widget *source,
 338                          struct snd_soc_dapm_widget *sink)
 339 {
 340         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 341         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 342
 343         if (rt286->clk_id == RT286_SCLK_S_MCLK)
 344                 return 1;
 345         else
 346                 return 0;
 347 }
 348
 349 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
 350 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
 351
 352 static const struct snd_kcontrol_new rt286_snd_controls[] = {
 353         SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
 354                             RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 355         SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
 356                             RT286_ADCR_GAIN, 7, 1, 1),
 357         SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
 358                             RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
 359         SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
 360                             0, 0x3, 0, mic_vol_tlv),
 361         SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
 362                             RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
 363 };
 364
 365 /* Digital Mixer */
 366 static const struct snd_kcontrol_new rt286_front_mix[] = {
 367         SOC_DAPM_SINGLE("DAC Switch",  RT286_F_DAC_SWITCH,
 368                         RT286_MUTE_SFT, 1, 1),
 369         SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
 370                         RT286_MUTE_SFT, 1, 1),
 371 };
 372
 373 /* Analog Input Mixer */
 374 static const struct snd_kcontrol_new rt286_rec_mix[] = {
 375         SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
 376                         RT286_MUTE_SFT, 1, 1),
 377         SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
 378                         RT286_MUTE_SFT, 1, 1),
 379         SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
 380                         RT286_MUTE_SFT, 1, 1),
 381         SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
 382                         RT286_MUTE_SFT, 1, 1),
 383 };
 384
 385 static const struct snd_kcontrol_new spo_enable_control =
 386         SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
 387                         RT286_SET_PIN_SFT, 1, 0);
 388
 389 static const struct snd_kcontrol_new hpol_enable_control =
 390         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
 391                         RT286_MUTE_SFT, 1, 1);
 392
 393 static const struct snd_kcontrol_new hpor_enable_control =
 394         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
 395                         RT286_MUTE_SFT, 1, 1);
 396
 397 /* ADC0 source */
 398 static const char * const rt286_adc_src[] = {
 399         "Mic", "RECMIX", "Dmic"
 400 };
 401
 402 static const int rt286_adc_values[] = {
 403         0, 4, 5,
 404 };
 405
 406 static SOC_VALUE_ENUM_SINGLE_DECL(
 407         rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
 408         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 409
 410 static const struct snd_kcontrol_new rt286_adc0_mux =
 411         SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
 412
 413 static SOC_VALUE_ENUM_SINGLE_DECL(
 414         rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
 415         RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
 416
 417 static const struct snd_kcontrol_new rt286_adc1_mux =
 418         SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
 419
 420 static const char * const rt286_dac_src[] = {
 421         "Front", "Surround"
 422 };
 423 /* HP-OUT source */
 424 static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
 425                                 0, rt286_dac_src);
 426
 427 static const struct snd_kcontrol_new rt286_hpo_mux =
 428 SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
 429
 430 /* SPK-OUT source */
 431 static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
 432                                 0, rt286_dac_src);
 433
 434 static const struct snd_kcontrol_new rt286_spo_mux =
 435 SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
 436
 437 static int rt286_spk_event(struct snd_soc_dapm_widget *w,
 438                             struct snd_kcontrol *kcontrol, int event)
 439 {
 440         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 441
 442         switch (event) {
 443         case SND_SOC_DAPM_POST_PMU:
 444                 snd_soc_write(codec,
 445                         RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
 446                 break;
 447         case SND_SOC_DAPM_PRE_PMD:
 448                 snd_soc_write(codec,
 449                         RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
 450                 break;
 451
 452         default:
 453                 return 0;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
 460                                   struct snd_kcontrol *kcontrol, int event)
 461 {
 462         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 463
 464         switch (event) {
 465         case SND_SOC_DAPM_POST_PMU:
 466                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
 467                 break;
 468         case SND_SOC_DAPM_PRE_PMD:
 469                 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
 470                 break;
 471         default:
 472                 return 0;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
 479                              struct snd_kcontrol *kcontrol, int event)
 480 {
 481         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 482
 483         switch (event) {
 484         case SND_SOC_DAPM_POST_PMU:
 485                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
 486                 break;
 487         case SND_SOC_DAPM_PRE_PMD:
 488                 snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
 489                 break;
 490         default:
 491                 return 0;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
 498                              struct snd_kcontrol *kcontrol, int event)
 499 {
 500         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 501
 502         switch (event) {
 503         case SND_SOC_DAPM_PRE_PMU:
 504                 snd_soc_update_bits(codec,
 505                         RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
 506                 snd_soc_update_bits(codec,
 507                         RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
 508                 break;
 509         case SND_SOC_DAPM_POST_PMD:
 510                 snd_soc_update_bits(codec,
 511                         RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
 512                 snd_soc_update_bits(codec,
 513                         RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
 514                 break;
 515         default:
 516                 return 0;
 517         }
 518
 519         return 0;
 520 }
 521
 522 static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
 523         SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
 524                 12, 1, NULL, 0),
 525         SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
 526                 0, 1, NULL, 0),
 527         SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
 528                 2, 0, NULL, 0),
 529         SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
 530                 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
 531                 SND_SOC_DAPM_POST_PMU),
 532         SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
 533                 5, 0, NULL, 0),
 534         SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
 535                 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
 536                 SND_SOC_DAPM_POST_PMD),
 537
 538         /* Input Lines */
 539         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
 540         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
 541         SND_SOC_DAPM_INPUT("MIC1"),
 542         SND_SOC_DAPM_INPUT("LINE1"),
 543         SND_SOC_DAPM_INPUT("Beep"),
 544
 545         /* DMIC */
 546         SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
 547                 NULL, 0, rt286_set_dmic1_event,
 548                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 549         SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
 550                 NULL, 0),
 551         SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
 552                 0, 0, NULL, 0),
 553
 554         /* REC Mixer */
 555         SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
 556                 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
 557
 558         /* ADCs */
 559         SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
 560         SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
 561
 562         /* ADC Mux */
 563         SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
 564                 &rt286_adc0_mux),
 565         SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
 566                 &rt286_adc1_mux),
 567
 568         /* Audio Interface */
 569         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
 570         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 571         SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
 572         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
 573
 574         /* Output Side */
 575         /* DACs */
 576         SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
 577         SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
 578
 579         /* Output Mux */
 580         SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
 581         SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
 582
 583         SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
 584                 RT286_SET_PIN_SFT, 0, NULL, 0),
 585
 586         /* Output Mixer */
 587         SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
 588                         rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
 589         SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
 590                         NULL, 0),
 591
 592         /* Output Pga */
 593         SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
 594                 &spo_enable_control, rt286_spk_event,
 595                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 596         SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
 597                 &hpol_enable_control),
 598         SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
 599                 &hpor_enable_control),
 600
 601         /* Output Lines */
 602         SND_SOC_DAPM_OUTPUT("SPOL"),
 603         SND_SOC_DAPM_OUTPUT("SPOR"),
 604         SND_SOC_DAPM_OUTPUT("HPO Pin"),
 605         SND_SOC_DAPM_OUTPUT("SPDIF"),
 606 };
 607
 608 static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
 609         {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
 610         {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
 611         {"Front", NULL, "MCLK MODE", is_mclk_mode},
 612         {"Surround", NULL, "MCLK MODE", is_mclk_mode},
 613
 614         {"HP Power", NULL, "LDO1"},
 615         {"HP Power", NULL, "LDO2"},
 616
 617         {"MIC1", NULL, "LDO1"},
 618         {"MIC1", NULL, "LDO2"},
 619         {"MIC1", NULL, "HV"},
 620         {"MIC1", NULL, "VREF"},
 621         {"MIC1", NULL, "MIC1 Input Buffer"},
 622
 623         {"SPO", NULL, "LDO1"},
 624         {"SPO", NULL, "LDO2"},
 625         {"SPO", NULL, "HV"},
 626         {"SPO", NULL, "VREF"},
 627
 628         {"DMIC1", NULL, "DMIC1 Pin"},
 629         {"DMIC2", NULL, "DMIC2 Pin"},
 630         {"DMIC1", NULL, "DMIC Receiver"},
 631         {"DMIC2", NULL, "DMIC Receiver"},
 632
 633         {"RECMIX", "Beep Switch", "Beep"},
 634         {"RECMIX", "Line1 Switch", "LINE1"},
 635         {"RECMIX", "Mic1 Switch", "MIC1"},
 636
 637         {"ADC 0 Mux", "Dmic", "DMIC1"},
 638         {"ADC 0 Mux", "RECMIX", "RECMIX"},
 639         {"ADC 0 Mux", "Mic", "MIC1"},
 640         {"ADC 1 Mux", "Dmic", "DMIC2"},
 641         {"ADC 1 Mux", "RECMIX", "RECMIX"},
 642         {"ADC 1 Mux", "Mic", "MIC1"},
 643
 644         {"ADC 0", NULL, "ADC 0 Mux"},
 645         {"ADC 1", NULL, "ADC 1 Mux"},
 646
 647         {"AIF1TX", NULL, "ADC 0"},
 648         {"AIF2TX", NULL, "ADC 1"},
 649
 650         {"DAC 0", NULL, "AIF1RX"},
 651         {"DAC 1", NULL, "AIF2RX"},
 652
 653         {"Front", "DAC Switch", "DAC 0"},
 654         {"Front", "RECMIX Switch", "RECMIX"},
 655
 656         {"Surround", NULL, "DAC 1"},
 657
 658         {"SPK Mux", "Front", "Front"},
 659         {"SPK Mux", "Surround", "Surround"},
 660
 661         {"HPO Mux", "Front", "Front"},
 662         {"HPO Mux", "Surround", "Surround"},
 663
 664         {"SPO", "Switch", "SPK Mux"},
 665         {"HPO L", "Switch", "HPO Mux"},
 666         {"HPO R", "Switch", "HPO Mux"},
 667         {"HPO L", NULL, "HP Power"},
 668         {"HPO R", NULL, "HP Power"},
 669
 670         {"SPOL", NULL, "SPO"},
 671         {"SPOR", NULL, "SPO"},
 672         {"HPO Pin", NULL, "HPO L"},
 673         {"HPO Pin", NULL, "HPO R"},
 674 };
 675
 676 static int rt286_hw_params(struct snd_pcm_substream *substream,
 677                             struct snd_pcm_hw_params *params,
 678                             struct snd_soc_dai *dai)
 679 {
 680         struct snd_soc_codec *codec = dai->codec;
 681         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 682         unsigned int val = 0;
 683         int d_len_code;
 684
 685         switch (params_rate(params)) {
 686         /* bit 14 0:48K 1:44.1K */
 687         case 44100:
 688                 val |= 0x4000;
 689                 break;
 690         case 48000:
 691                 break;
 692         default:
 693                 dev_err(codec->dev, "Unsupported sample rate %d\n",
 694                                         params_rate(params));
 695                 return -EINVAL;
 696         }
 697         switch (rt286->sys_clk) {
 698         case 12288000:
 699         case 24576000:
 700                 if (params_rate(params) != 48000) {
 701                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 702                                         params_rate(params), rt286->sys_clk);
 703                         return -EINVAL;
 704                 }
 705                 break;
 706         case 11289600:
 707         case 22579200:
 708                 if (params_rate(params) != 44100) {
 709                         dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
 710                                         params_rate(params), rt286->sys_clk);
 711                         return -EINVAL;
 712                 }
 713                 break;
 714         }
 715
 716         if (params_channels(params) <= 16) {
 717                 /* bit 3:0 Number of Channel */
 718                 val |= (params_channels(params) - 1);
 719         } else {
 720                 dev_err(codec->dev, "Unsupported channels %d\n",
 721                                         params_channels(params));
 722                 return -EINVAL;
 723         }
 724
 725         d_len_code = 0;
 726         switch (params_width(params)) {
 727         /* bit 6:4 Bits per Sample */
 728         case 16:
 729                 d_len_code = 0;
 730                 val |= (0x1 << 4);
 731                 break;
 732         case 32:
 733                 d_len_code = 2;
 734                 val |= (0x4 << 4);
 735                 break;
 736         case 20:
 737                 d_len_code = 1;
 738                 val |= (0x2 << 4);
 739                 break;
 740         case 24:
 741                 d_len_code = 2;
 742                 val |= (0x3 << 4);
 743                 break;
 744         case 8:
 745                 d_len_code = 3;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         snd_soc_update_bits(codec,
 752                 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
 753         dev_dbg(codec->dev, "format val = 0x%x\n", val);
 754
 755         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
 756         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
 757
 758         return 0;
 759 }
 760
 761 static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 762 {
 763         struct snd_soc_codec *codec = dai->codec;
 764
 765         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 766         case SND_SOC_DAIFMT_CBM_CFM:
 767                 snd_soc_update_bits(codec,
 768                         RT286_I2S_CTRL1, 0x800, 0x800);
 769                 break;
 770         case SND_SOC_DAIFMT_CBS_CFS:
 771                 snd_soc_update_bits(codec,
 772                         RT286_I2S_CTRL1, 0x800, 0x0);
 773                 break;
 774         default:
 775                 return -EINVAL;
 776         }
 777
 778         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 779         case SND_SOC_DAIFMT_I2S:
 780                 snd_soc_update_bits(codec,
 781                         RT286_I2S_CTRL1, 0x300, 0x0);
 782                 break;
 783         case SND_SOC_DAIFMT_LEFT_J:
 784                 snd_soc_update_bits(codec,
 785                         RT286_I2S_CTRL1, 0x300, 0x1 << 8);
 786                 break;
 787         case SND_SOC_DAIFMT_DSP_A:
 788                 snd_soc_update_bits(codec,
 789                         RT286_I2S_CTRL1, 0x300, 0x2 << 8);
 790                 break;
 791         case SND_SOC_DAIFMT_DSP_B:
 792                 snd_soc_update_bits(codec,
 793                         RT286_I2S_CTRL1, 0x300, 0x3 << 8);
 794                 break;
 795         default:
 796                 return -EINVAL;
 797         }
 798         /* bit 15 Stream Type 0:PCM 1:Non-PCM */
 799         snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
 800         snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
 801
 802         return 0;
 803 }
 804
 805 static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
 806                                 int clk_id, unsigned int freq, int dir)
 807 {
 808         struct snd_soc_codec *codec = dai->codec;
 809         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 810
 811         dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
 812
 813         if (RT286_SCLK_S_MCLK == clk_id) {
 814                 snd_soc_update_bits(codec,
 815                         RT286_I2S_CTRL2, 0x0100, 0x0);
 816                 snd_soc_update_bits(codec,
 817                         RT286_PLL_CTRL1, 0x20, 0x20);
 818         } else {
 819                 snd_soc_update_bits(codec,
 820                         RT286_I2S_CTRL2, 0x0100, 0x0100);
 821                 snd_soc_update_bits(codec,
 822                         RT286_PLL_CTRL, 0x4, 0x4);
 823                 snd_soc_update_bits(codec,
 824                         RT286_PLL_CTRL1, 0x20, 0x0);
 825         }
 826
 827         switch (freq) {
 828         case 19200000:
 829                 if (RT286_SCLK_S_MCLK == clk_id) {
 830                         dev_err(codec->dev, "Should not use MCLK\n");
 831                         return -EINVAL;
 832                 }
 833                 snd_soc_update_bits(codec,
 834                         RT286_I2S_CTRL2, 0x40, 0x40);
 835                 break;
 836         case 24000000:
 837                 if (RT286_SCLK_S_MCLK == clk_id) {
 838                         dev_err(codec->dev, "Should not use MCLK\n");
 839                         return -EINVAL;
 840                 }
 841                 snd_soc_update_bits(codec,
 842                         RT286_I2S_CTRL2, 0x40, 0x0);
 843                 break;
 844         case 12288000:
 845         case 11289600:
 846                 snd_soc_update_bits(codec,
 847                         RT286_I2S_CTRL2, 0x8, 0x0);
 848                 snd_soc_update_bits(codec,
 849                         RT286_CLK_DIV, 0xfc1e, 0x0004);
 850                 break;
 851         case 24576000:
 852         case 22579200:
 853                 snd_soc_update_bits(codec,
 854                         RT286_I2S_CTRL2, 0x8, 0x8);
 855                 snd_soc_update_bits(codec,
 856                         RT286_CLK_DIV, 0xfc1e, 0x5406);
 857                 break;
 858         default:
 859                 dev_err(codec->dev, "Unsupported system clock\n");
 860                 return -EINVAL;
 861         }
 862
 863         rt286->sys_clk = freq;
 864         rt286->clk_id = clk_id;
 865
 866         return 0;
 867 }
 868
 869 static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
 870 {
 871         struct snd_soc_codec *codec = dai->codec;
 872
 873         dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
 874         if (50 == ratio)
 875                 snd_soc_update_bits(codec,
 876                         RT286_I2S_CTRL1, 0x1000, 0x1000);
 877         else
 878                 snd_soc_update_bits(codec,
 879                         RT286_I2S_CTRL1, 0x1000, 0x0);
 880
 881
 882         return 0;
 883 }
 884
 885 static int rt286_set_bias_level(struct snd_soc_codec *codec,
 886                                  enum snd_soc_bias_level level)
 887 {
 888         switch (level) {
 889         case SND_SOC_BIAS_PREPARE:
 890                 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
 891                         snd_soc_write(codec,
 892                                 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
 893                         snd_soc_update_bits(codec,
 894                                 RT286_DC_GAIN, 0x200, 0x200);
 895                 }
 896                 break;
 897
 898         case SND_SOC_BIAS_ON:
 899                 mdelay(10);
 900                 snd_soc_update_bits(codec,
 901                         RT286_DC_GAIN, 0x200, 0x0);
 902
 903                 break;
 904
 905         case SND_SOC_BIAS_STANDBY:
 906                 snd_soc_write(codec,
 907                         RT286_SET_AUDIO_POWER, AC_PWRST_D3);
 908                 break;
 909
 910         default:
 911                 break;
 912         }
 913
 914         return 0;
 915 }
 916
 917 static irqreturn_t rt286_irq(int irq, void *data)
 918 {
 919         struct rt286_priv *rt286 = data;
 920         bool hp = false;
 921         bool mic = false;
 922         int status = 0;
 923
 924         rt286_jack_detect(rt286, &hp, &mic);
 925
 926         /* Clear IRQ */
 927         regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
 928
 929         if (hp == true)
 930                 status |= SND_JACK_HEADPHONE;
 931
 932         if (mic == true)
 933                 status |= SND_JACK_MICROPHONE;
 934
 935         snd_soc_jack_report(rt286->jack, status,
 936                 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
 937
 938         pm_wakeup_event(&rt286->i2c->dev, 300);
 939
 940         return IRQ_HANDLED;
 941 }
 942
 943 static int rt286_probe(struct snd_soc_codec *codec)
 944 {
 945         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 946
 947         rt286->codec = codec;
 948
 949         if (rt286->i2c->irq) {
 950                 regmap_update_bits(rt286->regmap,
 951                                         RT286_IRQ_CTRL, 0x2, 0x2);
 952
 953                 INIT_DELAYED_WORK(&rt286->jack_detect_work,
 954                                         rt286_jack_detect_work);
 955                 schedule_delayed_work(&rt286->jack_detect_work,
 956                                         msecs_to_jiffies(1250));
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int rt286_remove(struct snd_soc_codec *codec)
 963 {
 964         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 965
 966         cancel_delayed_work_sync(&rt286->jack_detect_work);
 967
 968         return 0;
 969 }
 970
 971 #ifdef CONFIG_PM
 972 static int rt286_suspend(struct snd_soc_codec *codec)
 973 {
 974         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 975
 976         regcache_cache_only(rt286->regmap, true);
 977         regcache_mark_dirty(rt286->regmap);
 978
 979         return 0;
 980 }
 981
 982 static int rt286_resume(struct snd_soc_codec *codec)
 983 {
 984         struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
 985
 986         regcache_cache_only(rt286->regmap, false);
 987         rt286_index_sync(codec);
 988         regcache_sync(rt286->regmap);
 989
 990         return 0;
 991 }
 992 #else
 993 #define rt286_suspend NULL
 994 #define rt286_resume NULL
 995 #endif
 996
 997 #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 998 #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 999                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1000
1001 static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1002         .hw_params = rt286_hw_params,
1003         .set_fmt = rt286_set_dai_fmt,
1004         .set_sysclk = rt286_set_dai_sysclk,
1005         .set_bclk_ratio = rt286_set_bclk_ratio,
1006 };
1007
1008 static struct snd_soc_dai_driver rt286_dai[] = {
1009         {
1010                 .name = "rt286-aif1",
1011                 .id = RT286_AIF1,
1012                 .playback = {
1013                         .stream_name = "AIF1 Playback",
1014                         .channels_min = 1,
1015                         .channels_max = 2,
1016                         .rates = RT286_STEREO_RATES,
1017                         .formats = RT286_FORMATS,
1018                 },
1019                 .capture = {
1020                         .stream_name = "AIF1 Capture",
1021                         .channels_min = 1,
1022                         .channels_max = 2,
1023                         .rates = RT286_STEREO_RATES,
1024                         .formats = RT286_FORMATS,
1025                 },
1026                 .ops = &rt286_aif_dai_ops,
1027                 .symmetric_rates = 1,
1028         },
1029         {
1030                 .name = "rt286-aif2",
1031                 .id = RT286_AIF2,
1032                 .playback = {
1033                         .stream_name = "AIF2 Playback",
1034                         .channels_min = 1,
1035                         .channels_max = 2,
1036                         .rates = RT286_STEREO_RATES,
1037                         .formats = RT286_FORMATS,
1038                 },
1039                 .capture = {
1040                         .stream_name = "AIF2 Capture",
1041                         .channels_min = 1,
1042                         .channels_max = 2,
1043                         .rates = RT286_STEREO_RATES,
1044                         .formats = RT286_FORMATS,
1045                 },
1046                 .ops = &rt286_aif_dai_ops,
1047                 .symmetric_rates = 1,
1048         },
1049
1050 };
1051
1052 static const struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1053         .probe = rt286_probe,
1054         .remove = rt286_remove,
1055         .suspend = rt286_suspend,
1056         .resume = rt286_resume,
1057         .set_bias_level = rt286_set_bias_level,
1058         .idle_bias_off = true,
1059         .component_driver = {
1060                 .controls               = rt286_snd_controls,
1061                 .num_controls           = ARRAY_SIZE(rt286_snd_controls),
1062                 .dapm_widgets           = rt286_dapm_widgets,
1063                 .num_dapm_widgets       = ARRAY_SIZE(rt286_dapm_widgets),
1064                 .dapm_routes            = rt286_dapm_routes,
1065                 .num_dapm_routes        = ARRAY_SIZE(rt286_dapm_routes),
1066         },
1067 };
1068
1069 static const struct regmap_config rt286_regmap = {
1070         .reg_bits = 32,
1071         .val_bits = 32,
1072         .max_register = 0x02370100,
1073         .volatile_reg = rt286_volatile_register,
1074         .readable_reg = rt286_readable_register,
1075         .reg_write = rl6347a_hw_write,
1076         .reg_read = rl6347a_hw_read,
1077         .cache_type = REGCACHE_RBTREE,
1078         .reg_defaults = rt286_reg,
1079         .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1080 };
1081
1082 static const struct i2c_device_id rt286_i2c_id[] = {
1083         {"rt286", 0},
1084         {"rt288", 0},
1085         {}
1086 };
1087 MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1088
1089 static const struct acpi_device_id rt286_acpi_match[] = {
1090         { "INT343A", 0 },
1091         {},
1092 };
1093 MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1094
1095 static const struct dmi_system_id force_combo_jack_table[] = {
1096         {
1097                 .ident = "Intel Wilson Beach",
1098                 .matches = {
1099                         DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1100                 }
1101         },
1102         {
1103                 .ident = "Intel Skylake RVP",
1104                 .matches = {
1105                         DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1106                 }
1107         },
1108         {
1109                 .ident = "Intel Kabylake RVP",
1110                 .matches = {
1111                         DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
1112                 }
1113         },
1114         {
1115                 .ident = "Thinkpad Helix 2nd",
1116                 .matches = {
1117                         DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1118                         DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
1119                 }
1120         },
1121
1122         { }
1123 };
1124
1125 static const struct dmi_system_id dmi_dell[] = {
1126         {
1127                 .ident = "Dell",
1128                 .matches = {
1129                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1130                 }
1131         },
1132         { }
1133 };
1134
1135 static int rt286_i2c_probe(struct i2c_client *i2c,
1136                            const struct i2c_device_id *id)
1137 {
1138         struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1139         struct rt286_priv *rt286;
1140         int i, ret, vendor_id;
1141
1142         rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1143                                 GFP_KERNEL);
1144         if (NULL == rt286)
1145                 return -ENOMEM;
1146
1147         rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1148         if (IS_ERR(rt286->regmap)) {
1149                 ret = PTR_ERR(rt286->regmap);
1150                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1151                         ret);
1152                 return ret;
1153         }
1154
1155         ret = regmap_read(rt286->regmap,
1156                 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id);
1157         if (ret != 0) {
1158                 dev_err(&i2c->dev, "I2C error %d\n", ret);
1159                 return ret;
1160         }
1161         if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) {
1162                 dev_err(&i2c->dev,
1163                         "Device with ID register %#x is not rt286\n",
1164                         vendor_id);
1165                 return -ENODEV;
1166         }
1167
1168         rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
1169                                           sizeof(rt286_index_def), GFP_KERNEL);
1170         if (!rt286->index_cache)
1171                 return -ENOMEM;
1172
1173         rt286->index_cache_size = INDEX_CACHE_SIZE;
1174         rt286->i2c = i2c;
1175         i2c_set_clientdata(i2c, rt286);
1176
1177         /* restore codec default */
1178         for (i = 0; i < INDEX_CACHE_SIZE; i++)
1179                 regmap_write(rt286->regmap, rt286->index_cache[i].reg,
1180                                 rt286->index_cache[i].def);
1181         for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
1182                 regmap_write(rt286->regmap, rt286_reg[i].reg,
1183                                 rt286_reg[i].def);
1184
1185         if (pdata)
1186                 rt286->pdata = *pdata;
1187
1188         if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) ||
1189                 dmi_check_system(force_combo_jack_table))
1190                 rt286->pdata.cbj_en = true;
1191
1192         regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1193
1194         for (i = 0; i < RT286_POWER_REG_LEN; i++)
1195                 regmap_write(rt286->regmap,
1196                         RT286_SET_POWER(rt286_support_power_controls[i]),
1197                         AC_PWRST_D1);
1198
1199         if (!rt286->pdata.cbj_en) {
1200                 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1201                 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1202                 regmap_update_bits(rt286->regmap,
1203                                         RT286_CBJ_CTRL1, 0xf000, 0xb000);
1204         } else {
1205                 regmap_update_bits(rt286->regmap,
1206                                         RT286_CBJ_CTRL1, 0xf000, 0x5000);
1207         }
1208
1209         mdelay(10);
1210
1211         if (!rt286->pdata.gpio2_en)
1212                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1213         else
1214                 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1215
1216         mdelay(10);
1217
1218         regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1219         /* Power down LDO, VREF */
1220         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
1221         regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
1222
1223         /* Set depop parameter */
1224         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1225         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1226         regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1227
1228         if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) {
1229                 regmap_update_bits(rt286->regmap,
1230                         RT286_SET_GPIO_MASK, 0x40, 0x40);
1231                 regmap_update_bits(rt286->regmap,
1232                         RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
1233                 regmap_update_bits(rt286->regmap,
1234                         RT286_SET_GPIO_DATA, 0x40, 0x40);
1235                 regmap_update_bits(rt286->regmap,
1236                         RT286_GPIO_CTRL, 0xc, 0x8);
1237         }
1238
1239         if (rt286->i2c->irq) {
1240                 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1241                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1242                 if (ret != 0) {
1243                         dev_err(&i2c->dev,
1244                                 "Failed to reguest IRQ: %d\n", ret);
1245                         return ret;
1246                 }
1247         }
1248
1249         ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1250                                      rt286_dai, ARRAY_SIZE(rt286_dai));
1251
1252         return ret;
1253 }
1254
1255 static int rt286_i2c_remove(struct i2c_client *i2c)
1256 {
1257         struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1258
1259         if (i2c->irq)
1260                 free_irq(i2c->irq, rt286);
1261         snd_soc_unregister_codec(&i2c->dev);
1262
1263         return 0;
1264 }
1265
1266
1267 static struct i2c_driver rt286_i2c_driver = {
1268         .driver = {
1269                    .name = "rt286",
1270                    .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1271                    },
1272         .probe = rt286_i2c_probe,
1273         .remove = rt286_i2c_remove,
1274         .id_table = rt286_i2c_id,
1275 };
1276
1277 module_i2c_driver(rt286_i2c_driver);
1278
1279 MODULE_DESCRIPTION("ASoC RT286 driver");
1280 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1281 MODULE_LICENSE("GPL");