1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
5 // Copyright 2019 Realtek Semiconductor Corp.
7 // Author: Jack Yu <jack.yu@realtek.com>
11 #include <linux/acpi.h>
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/rt1015.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/soc.h>
30 #include <sound/tlv.h>
35 static const struct rt1015_platform_data i2s_default_platform_data = {
36 .power_up_delay_ms = 50,
39 static const struct reg_default rt1015_reg[] = {
202 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
209 case RT1015_VENDOR_ID:
210 case RT1015_DEVICE_ID:
214 case RT1015_VBAT_TEST_OUT1:
215 case RT1015_VBAT_TEST_OUT2:
216 case RT1015_VBAT_PROT_ATT:
217 case RT1015_VBAT_DET_CODE:
218 case RT1015_SMART_BST_CTRL1:
219 case RT1015_SPK_DC_DETECT1:
220 case RT1015_SPK_DC_DETECT4:
221 case RT1015_SPK_DC_DETECT5:
222 case RT1015_DC_CALIB_CLSD1:
223 case RT1015_DC_CALIB_CLSD5:
224 case RT1015_DC_CALIB_CLSD6:
225 case RT1015_DC_CALIB_CLSD7:
226 case RT1015_DC_CALIB_CLSD8:
227 case RT1015_S_BST_TIMING_INTER1:
228 case RT1015_OSCK_STA:
229 case RT1015_MONO_DYNA_CTRL1:
230 case RT1015_MONO_DYNA_CTRL5:
238 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
254 case RT1015_CUSTOMER_ID:
255 case RT1015_PCODE_FWVER:
257 case RT1015_VENDOR_ID:
258 case RT1015_DEVICE_ID:
259 case RT1015_PAD_DRV1:
260 case RT1015_PAD_DRV2:
261 case RT1015_GAT_BOOST:
263 case RT1015_OSCK_STA:
270 case RT1015_TDM_MASTER:
271 case RT1015_TDM_TCON:
279 case RT1015_ANA_PROTECT1:
280 case RT1015_ANA_CTRL_SEQ1:
281 case RT1015_ANA_CTRL_SEQ2:
282 case RT1015_VBAT_DET_DEB:
283 case RT1015_VBAT_VOLT_DET1:
284 case RT1015_VBAT_VOLT_DET2:
285 case RT1015_VBAT_TEST_OUT1:
286 case RT1015_VBAT_TEST_OUT2:
287 case RT1015_VBAT_PROT_ATT:
288 case RT1015_VBAT_DET_CODE:
296 case RT1015_CLASSD_SEQ:
297 case RT1015_SMART_BST_CTRL1:
298 case RT1015_SMART_BST_CTRL2:
299 case RT1015_ANA_CTRL1:
300 case RT1015_ANA_CTRL2:
301 case RT1015_PWR_STATE_CTRL:
302 case RT1015_MONO_DYNA_CTRL:
303 case RT1015_MONO_DYNA_CTRL1:
304 case RT1015_MONO_DYNA_CTRL2:
305 case RT1015_MONO_DYNA_CTRL3:
306 case RT1015_MONO_DYNA_CTRL4:
307 case RT1015_MONO_DYNA_CTRL5:
309 case RT1015_SHORT_DETTOP1:
310 case RT1015_SHORT_DETTOP2:
311 case RT1015_SPK_DC_DETECT1:
312 case RT1015_SPK_DC_DETECT2:
313 case RT1015_SPK_DC_DETECT3:
314 case RT1015_SPK_DC_DETECT4:
315 case RT1015_SPK_DC_DETECT5:
316 case RT1015_BAT_RPO_STEP1:
317 case RT1015_BAT_RPO_STEP2:
318 case RT1015_BAT_RPO_STEP3:
319 case RT1015_BAT_RPO_STEP4:
320 case RT1015_BAT_RPO_STEP5:
321 case RT1015_BAT_RPO_STEP6:
322 case RT1015_BAT_RPO_STEP7:
323 case RT1015_BAT_RPO_STEP8:
324 case RT1015_BAT_RPO_STEP9:
325 case RT1015_BAT_RPO_STEP10:
326 case RT1015_BAT_RPO_STEP11:
327 case RT1015_BAT_RPO_STEP12:
328 case RT1015_SPREAD_SPEC1:
329 case RT1015_SPREAD_SPEC2:
330 case RT1015_PAD_STATUS:
331 case RT1015_PADS_PULLING_CTRL1:
332 case RT1015_PADS_DRIVING:
333 case RT1015_SYS_RST1:
334 case RT1015_SYS_RST2:
335 case RT1015_SYS_GATING1:
336 case RT1015_TEST_MODE1:
337 case RT1015_TEST_MODE2:
338 case RT1015_TIMING_CTRL1:
340 case RT1015_TEST_OUT1:
341 case RT1015_DC_CALIB_CLSD1:
342 case RT1015_DC_CALIB_CLSD2:
343 case RT1015_DC_CALIB_CLSD3:
344 case RT1015_DC_CALIB_CLSD4:
345 case RT1015_DC_CALIB_CLSD5:
346 case RT1015_DC_CALIB_CLSD6:
347 case RT1015_DC_CALIB_CLSD7:
348 case RT1015_DC_CALIB_CLSD8:
349 case RT1015_DC_CALIB_CLSD9:
350 case RT1015_DC_CALIB_CLSD10:
351 case RT1015_CLSD_INTERNAL1:
352 case RT1015_CLSD_INTERNAL2:
353 case RT1015_CLSD_INTERNAL3:
354 case RT1015_CLSD_INTERNAL4:
355 case RT1015_CLSD_INTERNAL5:
356 case RT1015_CLSD_INTERNAL6:
357 case RT1015_CLSD_INTERNAL7:
358 case RT1015_CLSD_INTERNAL8:
359 case RT1015_CLSD_INTERNAL9:
360 case RT1015_CLSD_OCP_CTRL:
366 case RT1015_VREF_LV1:
367 case RT1015_S_BST_TIMING_INTER1:
368 case RT1015_S_BST_TIMING_INTER2:
369 case RT1015_S_BST_TIMING_INTER3:
370 case RT1015_S_BST_TIMING_INTER4:
371 case RT1015_S_BST_TIMING_INTER5:
372 case RT1015_S_BST_TIMING_INTER6:
373 case RT1015_S_BST_TIMING_INTER7:
374 case RT1015_S_BST_TIMING_INTER8:
375 case RT1015_S_BST_TIMING_INTER9:
376 case RT1015_S_BST_TIMING_INTER10:
377 case RT1015_S_BST_TIMING_INTER11:
378 case RT1015_S_BST_TIMING_INTER12:
379 case RT1015_S_BST_TIMING_INTER13:
380 case RT1015_S_BST_TIMING_INTER14:
381 case RT1015_S_BST_TIMING_INTER15:
382 case RT1015_S_BST_TIMING_INTER16:
383 case RT1015_S_BST_TIMING_INTER17:
384 case RT1015_S_BST_TIMING_INTER18:
385 case RT1015_S_BST_TIMING_INTER19:
386 case RT1015_S_BST_TIMING_INTER20:
387 case RT1015_S_BST_TIMING_INTER21:
388 case RT1015_S_BST_TIMING_INTER22:
389 case RT1015_S_BST_TIMING_INTER23:
390 case RT1015_S_BST_TIMING_INTER24:
391 case RT1015_S_BST_TIMING_INTER25:
392 case RT1015_S_BST_TIMING_INTER26:
393 case RT1015_S_BST_TIMING_INTER27:
394 case RT1015_S_BST_TIMING_INTER28:
395 case RT1015_S_BST_TIMING_INTER29:
396 case RT1015_S_BST_TIMING_INTER30:
397 case RT1015_S_BST_TIMING_INTER31:
398 case RT1015_S_BST_TIMING_INTER32:
399 case RT1015_S_BST_TIMING_INTER33:
400 case RT1015_S_BST_TIMING_INTER34:
401 case RT1015_S_BST_TIMING_INTER35:
402 case RT1015_S_BST_TIMING_INTER36:
410 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
412 static const char * const rt1015_din_source_select[] = {
415 "Left + Right average",
418 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
419 rt1015_din_source_select);
421 static const char * const rt1015_boost_mode[] = {
422 "Bypass", "Adaptive", "Fixed Adaptive"
425 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
428 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
429 struct snd_ctl_elem_value *ucontrol)
431 struct snd_soc_component *component =
432 snd_soc_kcontrol_component(kcontrol);
433 struct rt1015_priv *rt1015 =
434 snd_soc_component_get_drvdata(component);
436 ucontrol->value.integer.value[0] = rt1015->boost_mode;
441 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
442 struct snd_ctl_elem_value *ucontrol)
444 struct snd_soc_component *component =
445 snd_soc_kcontrol_component(kcontrol);
446 struct rt1015_priv *rt1015 =
447 snd_soc_component_get_drvdata(component);
448 int boost_mode = ucontrol->value.integer.value[0];
450 switch (boost_mode) {
452 snd_soc_component_update_bits(component,
453 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
454 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
455 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
456 RT1015_BYPASS_SWRREG_BYPASS);
459 snd_soc_component_update_bits(component,
460 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
461 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
462 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
463 RT1015_BYPASS_SWRREG_PASS);
466 snd_soc_component_update_bits(component,
467 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
468 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
469 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
470 RT1015_BYPASS_SWRREG_PASS);
473 dev_err(component->dev, "Unknown boost control.\n");
477 rt1015->boost_mode = boost_mode;
482 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_value *ucontrol)
485 struct snd_soc_component *component =
486 snd_soc_kcontrol_component(kcontrol);
487 struct rt1015_priv *rt1015 =
488 snd_soc_component_get_drvdata(component);
490 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
495 static void rt1015_calibrate(struct rt1015_priv *rt1015)
497 struct snd_soc_component *component = rt1015->component;
498 struct regmap *regmap = rt1015->regmap;
500 snd_soc_dapm_mutex_lock(&component->dapm);
501 regcache_cache_bypass(regmap, true);
503 regmap_write(regmap, RT1015_CLK_DET, 0x0000);
504 regmap_write(regmap, RT1015_PWR4, 0x00B2);
505 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
507 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
509 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
511 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
512 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
513 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
515 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
516 regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
517 regmap_write(regmap, RT1015_CLK_DET, 0x8000);
519 regcache_cache_bypass(regmap, false);
520 regcache_mark_dirty(regmap);
521 regcache_sync(regmap);
522 snd_soc_dapm_mutex_unlock(&component->dapm);
525 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
526 struct snd_ctl_elem_value *ucontrol)
528 struct snd_soc_component *component =
529 snd_soc_kcontrol_component(kcontrol);
530 struct rt1015_priv *rt1015 =
531 snd_soc_component_get_drvdata(component);
533 if (rt1015->dac_is_used) {
534 dev_err(component->dev, "DAC is being used!\n");
538 rt1015->bypass_boost = ucontrol->value.integer.value[0];
539 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
540 !rt1015->cali_done) {
541 rt1015_calibrate(rt1015);
542 rt1015->cali_done = 1;
544 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
550 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
551 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
552 127, 0, dac_vol_tlv),
553 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
554 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
555 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
556 rt1015_boost_mode_get, rt1015_boost_mode_put),
557 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
558 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
559 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
562 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
563 struct snd_soc_dapm_widget *sink)
565 struct snd_soc_component *component =
566 snd_soc_dapm_to_component(source->dapm);
567 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
569 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
575 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
576 struct snd_kcontrol *kcontrol, int event)
578 struct snd_soc_component *component =
579 snd_soc_dapm_to_component(w->dapm);
580 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
583 case SND_SOC_DAPM_PRE_PMU:
584 rt1015->dac_is_used = 1;
585 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
586 snd_soc_component_write(component,
587 RT1015_SYS_RST1, 0x05f7);
588 snd_soc_component_write(component,
589 RT1015_SYS_RST2, 0x0b0a);
590 snd_soc_component_write(component,
591 RT1015_GAT_BOOST, 0xacfe);
592 snd_soc_component_write(component,
593 RT1015_PWR9, 0xaa00);
594 snd_soc_component_write(component,
595 RT1015_GAT_BOOST, 0xecfe);
597 snd_soc_component_write(component,
599 snd_soc_component_write(component,
600 RT1015_SYS_RST1, 0x05f7);
601 snd_soc_component_write(component,
602 RT1015_SYS_RST2, 0x0b0a);
603 snd_soc_component_write(component,
604 RT1015_PWR_STATE_CTRL, 0x008e);
608 case SND_SOC_DAPM_POST_PMD:
609 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
610 snd_soc_component_write(component,
611 RT1015_PWR9, 0xa800);
612 snd_soc_component_write(component,
613 RT1015_SYS_RST1, 0x05f5);
614 snd_soc_component_write(component,
615 RT1015_SYS_RST2, 0x0b9a);
617 snd_soc_component_write(component,
619 snd_soc_component_write(component,
620 RT1015_PWR_STATE_CTRL, 0x0088);
621 snd_soc_component_write(component,
622 RT1015_SYS_RST1, 0x05f5);
623 snd_soc_component_write(component,
624 RT1015_SYS_RST2, 0x0b9a);
626 rt1015->dac_is_used = 0;
635 static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
636 struct snd_kcontrol *kcontrol, int event)
638 struct snd_soc_component *component =
639 snd_soc_dapm_to_component(w->dapm);
640 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
641 unsigned int ret, ret2;
644 case SND_SOC_DAPM_PRE_PMU:
645 ret = snd_soc_component_read(component, RT1015_CLK_DET);
646 ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
647 if (!((ret >> 15) & 0x1)) {
648 snd_soc_component_update_bits(component, RT1015_CLK_DET,
649 RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
650 dev_dbg(component->dev, "BCLK Detection Enabled.\n");
652 if (!((ret2 >> 12) & 0x1)) {
653 snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
654 RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
655 dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
658 case SND_SOC_DAPM_POST_PMU:
659 msleep(rt1015->pdata.power_up_delay_ms);
667 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
668 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
670 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
671 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
672 r1015_dac_event, SND_SOC_DAPM_PRE_PMU |
673 SND_SOC_DAPM_POST_PMD),
674 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
675 rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
676 SND_SOC_DAPM_POST_PMU),
677 SND_SOC_DAPM_OUTPUT("SPO"),
680 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
681 { "DAC", NULL, "AIFRX" },
682 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
683 { "Amp Drv", NULL, "DAC" },
684 { "SPO", NULL, "Amp Drv" },
687 static int rt1015_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
690 struct snd_soc_component *component = dai->component;
691 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
692 int pre_div, frame_size, lrck;
693 unsigned int val_len = 0;
695 lrck = params_rate(params);
696 pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck);
698 dev_err(component->dev, "Unsupported clock rate\n");
702 frame_size = snd_soc_params_to_frame_size(params);
703 if (frame_size < 0) {
704 dev_err(component->dev, "Unsupported frame size: %d\n",
709 dev_dbg(component->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
711 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
712 lrck, pre_div, dai->id);
714 switch (params_width(params)) {
718 val_len = RT1015_I2S_DL_20;
721 val_len = RT1015_I2S_DL_24;
724 val_len = RT1015_I2S_DL_8;
730 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
731 RT1015_I2S_DL_MASK, val_len);
732 snd_soc_component_update_bits(component, RT1015_CLK2,
733 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
738 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
740 struct snd_soc_component *component = dai->component;
741 unsigned int reg_val = 0, reg_val2 = 0;
743 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
744 case SND_SOC_DAIFMT_CBM_CFM:
745 reg_val |= RT1015_TCON_TDM_MS_M;
747 case SND_SOC_DAIFMT_CBS_CFS:
748 reg_val |= RT1015_TCON_TDM_MS_S;
754 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
755 case SND_SOC_DAIFMT_NB_NF:
757 case SND_SOC_DAIFMT_IB_NF:
758 reg_val2 |= RT1015_TDM_INV_BCLK;
764 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
765 case SND_SOC_DAIFMT_I2S:
768 case SND_SOC_DAIFMT_LEFT_J:
769 reg_val |= RT1015_I2S_M_DF_LEFT;
772 case SND_SOC_DAIFMT_DSP_A:
773 reg_val |= RT1015_I2S_M_DF_PCM_A;
776 case SND_SOC_DAIFMT_DSP_B:
777 reg_val |= RT1015_I2S_M_DF_PCM_B;
784 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
785 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
787 snd_soc_component_update_bits(component, RT1015_TDM1_1,
788 RT1015_TDM_INV_BCLK_MASK, reg_val2);
793 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
794 int clk_id, int source, unsigned int freq, int dir)
796 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
797 unsigned int reg_val = 0;
799 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
803 case RT1015_SCLK_S_MCLK:
804 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
807 case RT1015_SCLK_S_PLL:
808 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
812 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
816 rt1015->sysclk = freq;
817 rt1015->sysclk_src = clk_id;
819 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
822 snd_soc_component_update_bits(component, RT1015_CLK2,
823 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
828 static int rt1015_set_component_pll(struct snd_soc_component *component,
829 int pll_id, int source, unsigned int freq_in,
830 unsigned int freq_out)
832 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
833 struct rl6231_pll_code pll_code;
836 if (!freq_in || !freq_out) {
837 dev_dbg(component->dev, "PLL disabled\n");
845 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
846 freq_out == rt1015->pll_out)
850 case RT1015_PLL_S_MCLK:
851 snd_soc_component_update_bits(component, RT1015_CLK2,
852 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
855 case RT1015_PLL_S_BCLK:
856 snd_soc_component_update_bits(component, RT1015_CLK2,
857 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
861 dev_err(component->dev, "Unknown PLL Source %d\n", source);
865 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
867 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
871 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
872 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
873 pll_code.n_code, pll_code.k_code);
875 snd_soc_component_write(component, RT1015_PLL1,
876 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
877 (pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
879 snd_soc_component_write(component, RT1015_PLL2,
882 rt1015->pll_in = freq_in;
883 rt1015->pll_out = freq_out;
884 rt1015->pll_src = source;
889 static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
890 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
892 struct snd_soc_component *component = dai->component;
893 unsigned int val = 0, rx_slotnum, tx_slotnum;
894 int ret = 0, first_bit;
898 val |= RT1015_I2S_TX_2CH;
901 val |= RT1015_I2S_TX_4CH;
904 val |= RT1015_I2S_TX_6CH;
907 val |= RT1015_I2S_TX_8CH;
914 switch (slot_width) {
916 val |= RT1015_I2S_CH_TX_LEN_16B;
919 val |= RT1015_I2S_CH_TX_LEN_20B;
922 val |= RT1015_I2S_CH_TX_LEN_24B;
925 val |= RT1015_I2S_CH_TX_LEN_32B;
932 /* Rx slot configuration */
933 rx_slotnum = hweight_long(rx_mask);
934 if (rx_slotnum != 1) {
936 dev_err(component->dev, "too many rx slots or zero slot\n");
940 /* This is an assumption that the system sends stereo audio to the amplifier typically.
941 * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
942 * The users could select the channel from L/R/L+R by "Mono LR Select" control.
944 first_bit = __ffs(rx_mask);
950 snd_soc_component_update_bits(component,
952 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
953 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
954 (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
955 ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
961 snd_soc_component_update_bits(component,
963 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
964 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
965 ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
966 (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
973 /* Tx slot configuration */
974 tx_slotnum = hweight_long(tx_mask);
977 dev_err(component->dev, "doesn't need to support tx slots\n");
981 snd_soc_component_update_bits(component, RT1015_TDM1_1,
982 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
983 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
989 static int rt1015_probe(struct snd_soc_component *component)
991 struct rt1015_priv *rt1015 =
992 snd_soc_component_get_drvdata(component);
994 rt1015->component = component;
999 static void rt1015_remove(struct snd_soc_component *component)
1001 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1003 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1006 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1007 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1008 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1010 static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1011 .hw_params = rt1015_hw_params,
1012 .set_fmt = rt1015_set_dai_fmt,
1013 .set_tdm_slot = rt1015_set_tdm_slot,
1016 static struct snd_soc_dai_driver rt1015_dai[] = {
1018 .name = "rt1015-aif",
1021 .stream_name = "AIF Playback",
1024 .rates = RT1015_STEREO_RATES,
1025 .formats = RT1015_FORMATS,
1027 .ops = &rt1015_aif_dai_ops,
1032 static int rt1015_suspend(struct snd_soc_component *component)
1034 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1036 regcache_cache_only(rt1015->regmap, true);
1037 regcache_mark_dirty(rt1015->regmap);
1042 static int rt1015_resume(struct snd_soc_component *component)
1044 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1046 regcache_cache_only(rt1015->regmap, false);
1047 regcache_sync(rt1015->regmap);
1049 if (rt1015->cali_done)
1050 rt1015_calibrate(rt1015);
1055 #define rt1015_suspend NULL
1056 #define rt1015_resume NULL
1059 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1060 .probe = rt1015_probe,
1061 .remove = rt1015_remove,
1062 .suspend = rt1015_suspend,
1063 .resume = rt1015_resume,
1064 .controls = rt1015_snd_controls,
1065 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1066 .dapm_widgets = rt1015_dapm_widgets,
1067 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1068 .dapm_routes = rt1015_dapm_routes,
1069 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1070 .set_sysclk = rt1015_set_component_sysclk,
1071 .set_pll = rt1015_set_component_pll,
1072 .use_pmdown_time = 1,
1074 .non_legacy_dai_naming = 1,
1077 static const struct regmap_config rt1015_regmap = {
1080 .max_register = RT1015_S_BST_TIMING_INTER36,
1081 .volatile_reg = rt1015_volatile_register,
1082 .readable_reg = rt1015_readable_register,
1083 .cache_type = REGCACHE_RBTREE,
1084 .reg_defaults = rt1015_reg,
1085 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1088 static const struct i2c_device_id rt1015_i2c_id[] = {
1092 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1094 #if defined(CONFIG_OF)
1095 static const struct of_device_id rt1015_of_match[] = {
1096 { .compatible = "realtek,rt1015", },
1099 MODULE_DEVICE_TABLE(of, rt1015_of_match);
1103 static const struct acpi_device_id rt1015_acpi_match[] = {
1107 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1110 static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1112 device_property_read_u32(dev, "realtek,power-up-delay-ms",
1113 &rt1015->pdata.power_up_delay_ms);
1116 static int rt1015_i2c_probe(struct i2c_client *i2c)
1118 struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
1119 struct rt1015_priv *rt1015;
1123 rt1015 = devm_kzalloc(&i2c->dev, sizeof(*rt1015), GFP_KERNEL);
1127 i2c_set_clientdata(i2c, rt1015);
1129 rt1015->pdata = i2s_default_platform_data;
1132 rt1015->pdata = *pdata;
1134 rt1015_parse_dt(rt1015, &i2c->dev);
1136 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1137 if (IS_ERR(rt1015->regmap)) {
1138 ret = PTR_ERR(rt1015->regmap);
1139 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1144 ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1147 "Failed to read device register: %d\n", ret);
1149 } else if ((val != RT1015_DEVICE_ID_VAL) &&
1150 (val != RT1015_DEVICE_ID_VAL2)) {
1152 "Device with ID register %x is not rt1015\n", val);
1156 return devm_snd_soc_register_component(&i2c->dev,
1157 &soc_component_dev_rt1015,
1158 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1161 static void rt1015_i2c_shutdown(struct i2c_client *client)
1163 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1165 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1168 static struct i2c_driver rt1015_i2c_driver = {
1171 .of_match_table = of_match_ptr(rt1015_of_match),
1172 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1174 .probe_new = rt1015_i2c_probe,
1175 .shutdown = rt1015_i2c_shutdown,
1176 .id_table = rt1015_i2c_id,
1178 module_i2c_driver(rt1015_i2c_driver);
1180 MODULE_DESCRIPTION("ASoC RT1015 driver");
1181 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1182 MODULE_LICENSE("GPL v2");