2 * Nuvoton NAU8825 audio codec driver
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
9 * Licensed under the GPL-2.
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21 #include <linux/semaphore.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
37 #define NAU_FREF_MAX 13500000
38 #define NAU_FVCO_MAX 124000000
39 #define NAU_FVCO_MIN 90000000
41 /* cross talk suppression detection */
42 #define LOG10_MAGIC 646456993
43 #define GAIN_AUGMENT 22500
44 #define SIDETONE_BASE 207000
47 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
48 int clk_id, unsigned int freq);
58 struct nau8825_fll_attr {
63 /* scaling for mclk from sysclk_src output */
64 static const struct nau8825_fll_attr mclk_src_scaling[] = {
80 /* ratio for input clk freq */
81 static const struct nau8825_fll_attr fll_ratio[] = {
91 static const struct nau8825_fll_attr fll_pre_scalar[] = {
98 static const struct reg_default nau8825_reg_defaults[] = {
99 { NAU8825_REG_ENA_CTRL, 0x00ff },
100 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
101 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
102 { NAU8825_REG_FLL1, 0x0 },
103 { NAU8825_REG_FLL2, 0x3126 },
104 { NAU8825_REG_FLL3, 0x0008 },
105 { NAU8825_REG_FLL4, 0x0010 },
106 { NAU8825_REG_FLL5, 0x0 },
107 { NAU8825_REG_FLL6, 0x6000 },
108 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
109 { NAU8825_REG_HSD_CTRL, 0x000c },
110 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
111 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
112 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
113 { NAU8825_REG_SAR_CTRL, 0x0015 },
114 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
115 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
116 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
117 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
118 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
119 { NAU8825_REG_GPIO34_CTRL, 0x0 },
120 { NAU8825_REG_GPIO12_CTRL, 0x0 },
121 { NAU8825_REG_TDM_CTRL, 0x0 },
122 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
123 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
124 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
125 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
126 { NAU8825_REG_BIQ_CTRL, 0x0 },
127 { NAU8825_REG_BIQ_COF1, 0x0 },
128 { NAU8825_REG_BIQ_COF2, 0x0 },
129 { NAU8825_REG_BIQ_COF3, 0x0 },
130 { NAU8825_REG_BIQ_COF4, 0x0 },
131 { NAU8825_REG_BIQ_COF5, 0x0 },
132 { NAU8825_REG_BIQ_COF6, 0x0 },
133 { NAU8825_REG_BIQ_COF7, 0x0 },
134 { NAU8825_REG_BIQ_COF8, 0x0 },
135 { NAU8825_REG_BIQ_COF9, 0x0 },
136 { NAU8825_REG_BIQ_COF10, 0x0 },
137 { NAU8825_REG_ADC_RATE, 0x0010 },
138 { NAU8825_REG_DAC_CTRL1, 0x0001 },
139 { NAU8825_REG_DAC_CTRL2, 0x0 },
140 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
141 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
142 { NAU8825_REG_MUTE_CTRL, 0x0 },
143 { NAU8825_REG_HSVOL_CTRL, 0x0 },
144 { NAU8825_REG_DACL_CTRL, 0x02cf },
145 { NAU8825_REG_DACR_CTRL, 0x00cf },
146 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
147 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
148 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
149 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
150 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
151 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
152 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
153 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
154 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
155 { NAU8825_REG_CLASSG_CTRL, 0x0 },
156 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
157 { NAU8825_REG_MISC_CTRL, 0x0 },
158 { NAU8825_REG_BIAS_ADJ, 0x0 },
159 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
160 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
161 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
162 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
163 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
164 { NAU8825_REG_RDAC, 0x0008 },
165 { NAU8825_REG_MIC_BIAS, 0x0006 },
166 { NAU8825_REG_BOOST, 0x0 },
167 { NAU8825_REG_FEPGA, 0x0 },
168 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
169 { NAU8825_REG_CHARGE_PUMP, 0x0 },
172 /* register backup table when cross talk detection */
173 static struct reg_default nau8825_xtalk_baktab[] = {
174 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
175 { NAU8825_REG_HSVOL_CTRL, 0 },
176 { NAU8825_REG_DACL_CTRL, 0 },
177 { NAU8825_REG_DACR_CTRL, 0 },
180 static const unsigned short logtable[256] = {
181 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
182 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
183 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
184 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
185 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
186 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
187 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
188 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
189 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
190 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
191 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
192 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
193 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
194 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
195 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
196 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
197 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
198 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
199 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
200 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
201 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
202 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
203 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
204 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
205 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
206 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
207 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
208 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
209 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
210 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
211 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
212 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
216 * nau8825_sema_acquire - acquire the semaphore of nau88l25
217 * @nau8825: component to register the codec private data with
218 * @timeout: how long in jiffies to wait before failure or zero to wait
221 * Attempts to acquire the semaphore with number of jiffies. If no more
222 * tasks are allowed to acquire the semaphore, calling this function will
223 * put the task to sleep. If the semaphore is not released within the
224 * specified number of jiffies, this function returns.
225 * Acquires the semaphore without jiffies. If no more tasks are allowed
226 * to acquire the semaphore, calling this function will put the task to
227 * sleep until the semaphore is released.
228 * If the semaphore is not released within the specified number of jiffies,
229 * this function returns -ETIME.
230 * If the sleep is interrupted by a signal, this function will return -EINTR.
231 * It returns 0 if the semaphore was acquired successfully.
233 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
238 ret = down_timeout(&nau8825->xtalk_sem, timeout);
240 dev_warn(nau8825->dev, "Acquire semaphone timeout\n");
242 ret = down_interruptible(&nau8825->xtalk_sem);
244 dev_warn(nau8825->dev, "Acquire semaphone fail\n");
251 * nau8825_sema_release - release the semaphore of nau88l25
252 * @nau8825: component to register the codec private data with
254 * Release the semaphore which may be called from any context and
255 * even by tasks which have never called down().
257 static inline void nau8825_sema_release(struct nau8825 *nau8825)
259 up(&nau8825->xtalk_sem);
263 * nau8825_sema_reset - reset the semaphore for nau88l25
264 * @nau8825: component to register the codec private data with
266 * Reset the counter of the semaphore. Call this function to restart
267 * a new round task management.
269 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
271 nau8825->xtalk_sem.count = 1;
275 * Ramp up the headphone volume change gradually to target level.
277 * @nau8825: component to register the codec private data with
278 * @vol_from: the volume to start up
279 * @vol_to: the target volume
280 * @step: the volume span to move on
282 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
283 * If the volume changes sharp, there is a pop noise heard in headphone. We
284 * provide the function to ramp up the volume up or down by delaying 10ms
287 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
288 unsigned int vol_from, unsigned int vol_to, unsigned int step)
290 unsigned int value, volume, ramp_up, from, to;
292 if (vol_from == vol_to || step == 0) {
294 } else if (vol_from < vol_to) {
303 /* only handle volume from 0dB to minimum -54dB */
304 if (to > NAU8825_HP_VOL_MIN)
305 to = NAU8825_HP_VOL_MIN;
307 for (volume = from; volume < to; volume += step) {
311 value = to - volume + from;
312 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
313 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
314 (value << NAU8825_HPL_VOL_SFT) | value);
315 usleep_range(10000, 10500);
321 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
322 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
323 (value << NAU8825_HPL_VOL_SFT) | value);
327 * Computes log10 of a value; the result is round off to 3 decimal. This func-
328 * tion takes reference to dvb-math. The source code locates as the following.
329 * Linux/drivers/media/dvb-core/dvb_math.c
331 * return log10(value) * 1000
333 static u32 nau8825_intlog10_dec3(u32 value)
335 u32 msb, logentry, significand, interpolation, log10val;
338 /* first detect the msb (count begins at 0) */
339 msb = fls(value) - 1;
341 * now we use a logtable after the following method:
343 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
344 * where x = msb and therefore 1 <= y < 2
345 * first y is determined by shifting the value left
346 * so that msb is bit 31
347 * 0x00231f56 -> 0x8C7D5800
348 * the result is y * 2^31 -> "significand"
349 * then the highest 9 bits are used for a table lookup
350 * the highest bit is discarded because it's always set
351 * the highest nine bits in our example are 100011000
352 * so we would use the entry 0x18
354 significand = value << (31 - msb);
355 logentry = (significand >> 23) & 0xff;
357 * last step we do is interpolation because of the
358 * limitations of the log table the error is that part of
359 * the significand which isn't used for lookup then we
360 * compute the ratio between the error and the next table entry
361 * and interpolate it between the log table entry used and the
362 * next one the biggest error possible is 0x7fffff
363 * (in our example it's 0x7D5800)
364 * needed value for next table entry is 0x800000
365 * so the interpolation is
366 * (error / 0x800000) * (logtable_next - logtable_current)
367 * in the implementation the division is moved to the end for
368 * better accuracy there is also an overflow correction if
369 * logtable_next is 256
371 interpolation = ((significand & 0x7fffff) *
372 ((logtable[(logentry + 1) & 0xff] -
373 logtable[logentry]) & 0xffff)) >> 15;
375 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
377 * log10(x) = log2(x) * log10(2)
379 log10val = (log2val * LOG10_MAGIC) >> 31;
381 * the result is round off to 3 decimal
383 return log10val / ((1 << 24) / 1000);
387 * computes cross talk suppression sidetone gain.
389 * @sig_org: orignal signal level
390 * @sig_cros: cross talk signal level
392 * The orignal and cross talk signal vlues need to be characterized.
393 * Once these values have been characterized, this sidetone value
394 * can be converted to decibel with the equation below.
395 * sidetone = 20 * log (original signal level / crosstalk signal level)
397 * return cross talk sidetone gain
399 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
403 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
408 sig_org = nau8825_intlog10_dec3(sig_org);
409 sig_cros = nau8825_intlog10_dec3(sig_cros);
410 if (sig_org >= sig_cros)
411 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
413 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
414 sidetone = SIDETONE_BASE - gain * 2;
420 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
424 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
425 if (nau8825_xtalk_baktab[index].reg == reg)
430 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
434 /* Backup some register values to backup table */
435 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
436 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
437 &nau8825_xtalk_baktab[i].def);
440 static void nau8825_xtalk_restore(struct nau8825 *nau8825)
444 /* Restore register values from backup table; When the driver restores
445 * the headphone volumem, it needs recover to original level gradually
446 * with 3dB per step for less pop noise.
448 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
449 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
450 /* Ramping up the volume change to reduce pop noise */
451 volume = nau8825_xtalk_baktab[i].def &
452 NAU8825_HPR_VOL_MASK;
453 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
456 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
457 nau8825_xtalk_baktab[i].def);
461 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
463 /* Enable power of DAC path */
464 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
465 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
466 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
467 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
468 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
469 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
470 /* Prevent startup click by letting charge pump to ramp up and
473 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
474 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
475 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
476 /* Enable clock sync of DAC and DAC clock */
477 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
478 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
479 NAU8825_RDAC_FS_BCLK_ENB,
480 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
481 /* Power up output driver with 2 stage */
482 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
483 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
484 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
485 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
486 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
487 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
488 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
489 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
490 /* HP outputs not shouted to ground */
491 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
492 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
493 /* Enable HP boost driver */
494 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
495 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
496 /* Enable class G compare path to supply 1.8V or 0.9V. */
497 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
498 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
499 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
502 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
504 /* Power up left ADC and raise 5dB than Vmid for Vref */
505 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
506 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
507 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
510 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
512 /* Recover FLL default value */
513 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
514 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
515 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
516 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
517 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
518 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
519 /* Enable internal VCO clock for detection signal generated */
520 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
521 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
522 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
524 /* Given specific clock frequency of internal clock to
527 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
528 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
529 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
530 NAU8825_FLL_RATIO_MASK, 0x10);
533 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
537 /* Backup those registers changed by cross talk detection */
538 nau8825_xtalk_backup(nau8825);
539 /* Config IIS as master to output signal by codec */
540 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
541 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
542 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
543 (0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
544 /* Ramp up headphone volume to 0dB to get better performance and
545 * avoid pop noise in headphone.
547 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
548 if (index != -EINVAL) {
549 volume = nau8825_xtalk_baktab[index].def &
550 NAU8825_HPR_VOL_MASK;
551 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
553 nau8825_xtalk_clock(nau8825);
554 nau8825_xtalk_prepare_dac(nau8825);
555 nau8825_xtalk_prepare_adc(nau8825);
556 /* Config channel path and digital gain */
557 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
558 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
559 NAU8825_DACL_CH_SEL_L | 0xab);
560 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
561 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
562 NAU8825_DACR_CH_SEL_R | 0xab);
563 /* Config cross talk parameters and generate the 23Hz sine wave with
564 * 1/16 full scale of signal level for impedance measurement.
566 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
567 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
568 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
569 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
570 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
571 /* RMS intrruption enable */
572 regmap_update_bits(nau8825->regmap,
573 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
574 /* Power up left and right DAC */
575 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
576 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
579 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
581 /* Disable HP boost driver */
582 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
583 NAU8825_HP_BOOST_DIS, 0);
584 /* HP outputs shouted to ground */
585 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
586 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
587 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
588 /* Power down left and right DAC */
589 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
590 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
591 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
592 /* Enable the TESTDAC and disable L/R HP impedance */
593 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
594 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
595 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
596 /* Power down output driver with 2 stage */
597 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
598 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
599 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
600 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
601 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
602 /* Disable clock sync of DAC and DAC clock */
603 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
604 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
605 /* Disable charge pump ramp up function and change bump */
606 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
607 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
608 /* Disable power of DAC path */
609 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
610 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
611 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
613 regmap_update_bits(nau8825->regmap,
614 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
617 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
619 /* Power down left ADC and restore voltage to Vmid */
620 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
621 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
624 static void nau8825_xtalk_clean(struct nau8825 *nau8825)
626 /* Enable internal VCO needed for interruptions */
627 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
628 nau8825_xtalk_clean_dac(nau8825);
629 nau8825_xtalk_clean_adc(nau8825);
630 /* Clear cross talk parameters and disable */
631 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
632 /* RMS intrruption disable */
633 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
634 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
635 /* Recover default value for IIS */
636 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
637 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
638 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
639 /* Restore value of specific register for cross talk */
640 nau8825_xtalk_restore(nau8825);
643 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
645 /* Apply ADC volume for better cross talk performance */
646 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
647 NAU8825_ADC_DIG_VOL_MASK, vol);
648 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
649 * Do it before sending signal in order to erase pop noise.
651 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
652 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
653 NAU8825_BIAS_TESTDACL_EN);
654 switch (nau8825->xtalk_state) {
655 case NAU8825_XTALK_HPR_R2L:
656 /* Enable right headphone impedance */
657 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
658 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
659 NAU8825_BIAS_HPR_IMP);
661 case NAU8825_XTALK_HPL_R2L:
662 /* Enable left headphone impedance */
663 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
664 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
665 NAU8825_BIAS_HPL_IMP);
671 /* Impedance measurement mode enable */
672 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
673 NAU8825_IMM_EN, NAU8825_IMM_EN);
676 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
678 /* Impedance measurement mode disable */
679 regmap_update_bits(nau8825->regmap,
680 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
683 /* The cross talk measurement function can reduce cross talk across the
684 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
685 * level to determine what cross talk reduction gain is. This system works by
686 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
687 * the PGA. The output of the PGA is then connected to an internal current
688 * sense which measures the attenuated 23Hz signal and passing the output to
689 * an ADC which converts the measurement to a binary code. With two separated
690 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
691 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
692 * Thus, the measurement function has four states to complete whole sequence.
693 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
694 * IMM stat to make JKR1(HPR) impedance measure.
695 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
696 * to HPL IMM state to make JKTIP(HPL) impedance measure.
697 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
698 * transfer to IMM state to determine suppression sidetone gain.
699 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
700 * and cross talk signal level. Apply this gain and then restore codec
701 * configuration. Then transfer to Done state for ending.
703 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
707 switch (nau8825->xtalk_state) {
708 case NAU8825_XTALK_PREPARE:
709 /* In prepare state, set up clock, intrruption, DAC path, ADC
710 * path and cross talk detection parameters for preparation.
712 nau8825_xtalk_prepare(nau8825);
714 /* Trigger right headphone impedance detection */
715 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
716 nau8825_xtalk_imm_start(nau8825, 0x00d2);
718 case NAU8825_XTALK_HPR_R2L:
719 /* In right headphone IMM state, read out right headphone
720 * impedance measure result, and then start up left side.
722 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
723 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
724 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
725 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
726 /* Disable then re-enable IMM mode to update */
727 nau8825_xtalk_imm_stop(nau8825);
728 /* Trigger left headphone impedance detection */
729 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
730 nau8825_xtalk_imm_start(nau8825, 0x00ff);
732 case NAU8825_XTALK_HPL_R2L:
733 /* In left headphone IMM state, read out left headphone
734 * impedance measure result, and delay some time to wait
735 * detection sine wave output finish. Then, we can calculate
736 * the cross talk suppresstion side tone according to the L/R
737 * headphone imedance.
739 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
740 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
741 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
742 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
743 nau8825_xtalk_imm_stop(nau8825);
745 nau8825->xtalk_state = NAU8825_XTALK_IMM;
747 case NAU8825_XTALK_IMM:
748 /* In impedance measure state, the orignal and cross talk
749 * signal level vlues are ready. The side tone gain is deter-
750 * mined with these signal level. After all, restore codec
753 sidetone = nau8825_xtalk_sidetone(
754 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
755 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
756 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
757 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
758 (sidetone << 8) | sidetone);
759 nau8825_xtalk_clean(nau8825);
760 nau8825->xtalk_state = NAU8825_XTALK_DONE;
767 static void nau8825_xtalk_work(struct work_struct *work)
769 struct nau8825 *nau8825 = container_of(
770 work, struct nau8825, xtalk_work);
772 nau8825_xtalk_measure(nau8825);
773 /* To determine the cross talk side tone gain when reach
774 * the impedance measure state.
776 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
777 nau8825_xtalk_measure(nau8825);
779 /* Delay jack report until cross talk detection process
780 * completed. It can avoid application to do playback
781 * preparation before cross talk detection is still working.
782 * Meanwhile, the protection of the cross talk detection
785 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
786 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
787 nau8825->xtalk_event_mask);
788 nau8825_sema_release(nau8825);
789 nau8825->xtalk_protect = false;
793 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
795 /* If the xtalk_protect is true, that means the process is still
796 * on going. The driver forces to cancel the cross talk task and
797 * restores the configuration to original status.
799 if (nau8825->xtalk_protect) {
800 cancel_work_sync(&nau8825->xtalk_work);
801 nau8825_xtalk_clean(nau8825);
803 /* Reset parameters for cross talk suppression function */
804 nau8825_sema_reset(nau8825);
805 nau8825->xtalk_state = NAU8825_XTALK_DONE;
806 nau8825->xtalk_protect = false;
809 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
812 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
813 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
814 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
815 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
816 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
817 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
818 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
819 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
820 case NAU8825_REG_MISC_CTRL:
821 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
822 case NAU8825_REG_BIAS_ADJ:
823 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
824 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
825 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
826 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
834 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
837 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
838 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
839 case NAU8825_REG_INTERRUPT_MASK:
840 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
841 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
842 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
843 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
844 case NAU8825_REG_IMM_MODE_CTRL:
845 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
846 case NAU8825_REG_MISC_CTRL:
847 case NAU8825_REG_BIAS_ADJ:
848 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
849 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
850 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
851 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
858 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
861 case NAU8825_REG_RESET:
862 case NAU8825_REG_IRQ_STATUS:
863 case NAU8825_REG_INT_CLR_KEY_STATUS:
864 case NAU8825_REG_IMM_RMS_L:
865 case NAU8825_REG_IMM_RMS_R:
866 case NAU8825_REG_I2C_DEVICE_ID:
867 case NAU8825_REG_SARDOUT_RAM_STATUS:
868 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
869 case NAU8825_REG_GENERAL_STATUS:
870 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
877 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
878 struct snd_kcontrol *kcontrol, int event)
880 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
881 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
884 case SND_SOC_DAPM_POST_PMU:
886 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
887 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
889 case SND_SOC_DAPM_POST_PMD:
891 regmap_update_bits(nau8825->regmap,
892 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
901 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
902 struct snd_kcontrol *kcontrol, int event)
904 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
905 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
908 case SND_SOC_DAPM_POST_PMU:
909 /* Prevent startup click by letting charge pump to ramp up */
911 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
912 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
914 case SND_SOC_DAPM_PRE_PMD:
915 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
916 NAU8825_JAMNODCLOW, 0);
925 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
926 struct snd_kcontrol *kcontrol, int event)
928 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
929 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
932 case SND_SOC_DAPM_PRE_PMU:
933 /* Disables the TESTDAC to let DAC signal pass through. */
934 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
935 NAU8825_BIAS_TESTDAC_EN, 0);
937 case SND_SOC_DAPM_POST_PMD:
938 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
939 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
948 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
949 struct snd_ctl_elem_value *ucontrol)
951 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
952 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
954 if (!component->regmap)
957 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
958 ucontrol->value.bytes.data, params->max);
962 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
963 struct snd_ctl_elem_value *ucontrol)
965 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
966 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
969 if (!component->regmap)
972 data = kmemdup(ucontrol->value.bytes.data,
973 params->max, GFP_KERNEL | GFP_DMA);
977 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
978 NAU8825_BIQ_WRT_EN, 0);
979 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
981 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
982 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
988 static const char * const nau8825_biq_path[] = {
992 static const struct soc_enum nau8825_biq_path_enum =
993 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
994 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
996 static const char * const nau8825_adc_decimation[] = {
997 "32", "64", "128", "256"
1000 static const struct soc_enum nau8825_adc_decimation_enum =
1001 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1002 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1004 static const char * const nau8825_dac_oversampl[] = {
1005 "64", "256", "128", "", "32"
1008 static const struct soc_enum nau8825_dac_oversampl_enum =
1009 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1010 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1012 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1013 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1014 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1015 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1016 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1018 static const struct snd_kcontrol_new nau8825_controls[] = {
1019 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1020 0, 0xff, 0, adc_vol_tlv),
1021 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1022 12, 8, 0x0f, 0, sidetone_vol_tlv),
1023 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1024 6, 0, 0x3f, 1, dac_vol_tlv),
1025 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1026 8, 37, 0, fepga_gain_tlv),
1027 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1028 0, 8, 0xff, 0, crosstalk_vol_tlv),
1030 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1031 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1032 /* programmable biquad filter */
1033 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1034 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1035 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1038 /* DAC Mux 0x33[9] and 0x34[9] */
1039 static const char * const nau8825_dac_src[] = {
1043 static SOC_ENUM_SINGLE_DECL(
1044 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1045 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1047 static SOC_ENUM_SINGLE_DECL(
1048 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1049 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1051 static const struct snd_kcontrol_new nau8825_dacl_mux =
1052 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1054 static const struct snd_kcontrol_new nau8825_dacr_mux =
1055 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1058 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1059 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1062 SND_SOC_DAPM_INPUT("MIC"),
1063 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1065 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1068 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1069 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1070 SND_SOC_DAPM_POST_PMD),
1071 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1072 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1075 /* ADC for button press detection. A dapm supply widget is used to
1076 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1079 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1080 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1082 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1083 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1084 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1085 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1087 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1088 NAU8825_ENABLE_DACR_SFT, 0),
1089 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1090 NAU8825_ENABLE_DACL_SFT, 0),
1091 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1093 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1094 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1096 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1097 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1098 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1099 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1101 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1102 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1103 SND_SOC_DAPM_PRE_PMD),
1105 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1106 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1107 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1108 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1109 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1110 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1111 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1112 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1113 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1114 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1115 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1116 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1118 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1119 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1120 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1121 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1122 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1123 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1125 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1126 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1127 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1128 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1129 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1131 /* High current HPOL/R boost driver */
1132 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1133 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1135 /* Class G operation control*/
1136 SND_SOC_DAPM_PGA_S("Class G", 10,
1137 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1139 SND_SOC_DAPM_OUTPUT("HPOL"),
1140 SND_SOC_DAPM_OUTPUT("HPOR"),
1143 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1144 {"Frontend PGA", NULL, "MIC"},
1145 {"ADC", NULL, "Frontend PGA"},
1146 {"ADC", NULL, "ADC Clock"},
1147 {"ADC", NULL, "ADC Power"},
1148 {"AIFTX", NULL, "ADC"},
1150 {"DDACL", NULL, "Playback"},
1151 {"DDACR", NULL, "Playback"},
1152 {"DDACL", NULL, "DDAC Clock"},
1153 {"DDACR", NULL, "DDAC Clock"},
1154 {"DACL Mux", "DACL", "DDACL"},
1155 {"DACL Mux", "DACR", "DDACR"},
1156 {"DACR Mux", "DACL", "DDACL"},
1157 {"DACR Mux", "DACR", "DDACR"},
1158 {"HP amp L", NULL, "DACL Mux"},
1159 {"HP amp R", NULL, "DACR Mux"},
1160 {"Charge Pump", NULL, "HP amp L"},
1161 {"Charge Pump", NULL, "HP amp R"},
1162 {"ADACL", NULL, "Charge Pump"},
1163 {"ADACR", NULL, "Charge Pump"},
1164 {"ADACL Clock", NULL, "ADACL"},
1165 {"ADACR Clock", NULL, "ADACR"},
1166 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1167 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1168 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1169 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1170 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1171 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1172 {"Output DACL", NULL, "Output Driver L Stage 3"},
1173 {"Output DACR", NULL, "Output Driver R Stage 3"},
1174 {"HPOL Pulldown", NULL, "Output DACL"},
1175 {"HPOR Pulldown", NULL, "Output DACR"},
1176 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1177 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1178 {"Class G", NULL, "HP Boost Driver"},
1179 {"HPOL", NULL, "Class G"},
1180 {"HPOR", NULL, "Class G"},
1183 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1184 struct snd_pcm_hw_params *params,
1185 struct snd_soc_dai *dai)
1187 struct snd_soc_codec *codec = dai->codec;
1188 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1189 unsigned int val_len = 0;
1191 nau8825_sema_acquire(nau8825, 2 * HZ);
1193 switch (params_width(params)) {
1195 val_len |= NAU8825_I2S_DL_16;
1198 val_len |= NAU8825_I2S_DL_20;
1201 val_len |= NAU8825_I2S_DL_24;
1204 val_len |= NAU8825_I2S_DL_32;
1210 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1211 NAU8825_I2S_DL_MASK, val_len);
1213 /* Release the semaphone. */
1214 nau8825_sema_release(nau8825);
1219 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1221 struct snd_soc_codec *codec = codec_dai->codec;
1222 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1223 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1225 nau8825_sema_acquire(nau8825, 2 * HZ);
1227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1228 case SND_SOC_DAIFMT_CBM_CFM:
1229 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1231 case SND_SOC_DAIFMT_CBS_CFS:
1237 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1238 case SND_SOC_DAIFMT_NB_NF:
1240 case SND_SOC_DAIFMT_IB_NF:
1241 ctrl1_val |= NAU8825_I2S_BP_INV;
1247 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1248 case SND_SOC_DAIFMT_I2S:
1249 ctrl1_val |= NAU8825_I2S_DF_I2S;
1251 case SND_SOC_DAIFMT_LEFT_J:
1252 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1254 case SND_SOC_DAIFMT_RIGHT_J:
1255 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1257 case SND_SOC_DAIFMT_DSP_A:
1258 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1260 case SND_SOC_DAIFMT_DSP_B:
1261 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1262 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1268 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1269 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1270 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1272 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1273 NAU8825_I2S_MS_MASK, ctrl2_val);
1275 /* Release the semaphone. */
1276 nau8825_sema_release(nau8825);
1281 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1282 .hw_params = nau8825_hw_params,
1283 .set_fmt = nau8825_set_dai_fmt,
1286 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1287 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1288 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1290 static struct snd_soc_dai_driver nau8825_dai = {
1291 .name = "nau8825-hifi",
1293 .stream_name = "Playback",
1296 .rates = NAU8825_RATES,
1297 .formats = NAU8825_FORMATS,
1300 .stream_name = "Capture",
1303 .rates = NAU8825_RATES,
1304 .formats = NAU8825_FORMATS,
1306 .ops = &nau8825_dai_ops,
1310 * nau8825_enable_jack_detect - Specify a jack for event reporting
1312 * @component: component to register the jack with
1313 * @jack: jack to use to report headset and button events on
1315 * After this function has been called the headset insert/remove and button
1316 * events will be routed to the given jack. Jack can be null to stop
1319 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1320 struct snd_soc_jack *jack)
1322 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1323 struct regmap *regmap = nau8825->regmap;
1325 nau8825->jack = jack;
1327 /* Ground HP Outputs[1:0], needed for headset auto detection
1328 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1330 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1331 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1332 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1336 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1339 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1341 bool active_high, is_high;
1344 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1345 active_high = jkdet & NAU8825_JACK_POLARITY;
1346 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1347 is_high = status & NAU8825_GPIO2JD1;
1348 /* return jack connection status according to jack insertion logic
1349 * active high or active low.
1351 return active_high == is_high;
1354 static void nau8825_restart_jack_detection(struct regmap *regmap)
1356 /* this will restart the entire jack detection process including MIC/GND
1357 * switching and create interrupts. We have to go from 0 to 1 and back
1360 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1361 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1362 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1363 NAU8825_JACK_DET_RESTART, 0);
1366 static void nau8825_int_status_clear_all(struct regmap *regmap)
1368 int active_irq, clear_irq, i;
1370 /* Reset the intrruption status from rightmost bit if the corres-
1371 * ponding irq event occurs.
1373 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1374 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1375 clear_irq = (0x1 << i);
1376 if (active_irq & clear_irq)
1377 regmap_write(regmap,
1378 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1382 static void nau8825_eject_jack(struct nau8825 *nau8825)
1384 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1385 struct regmap *regmap = nau8825->regmap;
1387 /* Force to cancel the cross talk detection process */
1388 nau8825_xtalk_cancel(nau8825);
1390 snd_soc_dapm_disable_pin(dapm, "SAR");
1391 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1392 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1393 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1394 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1395 /* ground HPL/HPR, MICGRND1/2 */
1396 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1398 snd_soc_dapm_sync(dapm);
1400 /* Clear all interruption status */
1401 nau8825_int_status_clear_all(regmap);
1403 /* Enable the insertion interruption, disable the ejection inter-
1404 * ruption, and then bypass de-bounce circuit.
1406 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1407 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1408 NAU8825_IRQ_EJECT_DIS);
1409 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1410 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1411 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1412 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1413 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1414 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1415 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1417 /* Disable ADC needed for interruptions at audo mode */
1418 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1419 NAU8825_ENABLE_ADC, 0);
1421 /* Close clock for jack type detection at manual mode */
1422 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1425 /* Enable audo mode interruptions with internal clock. */
1426 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1428 struct regmap *regmap = nau8825->regmap;
1430 /* Enable headset jack type detection complete interruption and
1431 * jack ejection interruption.
1433 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1434 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1436 /* Enable internal VCO needed for interruptions */
1437 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1439 /* Enable ADC needed for interruptions */
1440 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1441 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1443 /* Chip needs one FSCLK cycle in order to generate interruptions,
1444 * as we cannot guarantee one will be provided by the system. Turning
1445 * master mode on then off enables us to generate that FSCLK cycle
1446 * with a minimum of contention on the clock bus.
1448 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1449 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1450 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1451 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1453 /* Not bypass de-bounce circuit */
1454 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1455 NAU8825_JACK_DET_DB_BYPASS, 0);
1457 /* Unmask all interruptions */
1458 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1460 /* Restart the jack detection process at auto mode */
1461 nau8825_restart_jack_detection(regmap);
1464 static int nau8825_button_decode(int value)
1468 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1470 buttons |= SND_JACK_BTN_0;
1472 buttons |= SND_JACK_BTN_1;
1474 buttons |= SND_JACK_BTN_2;
1476 buttons |= SND_JACK_BTN_3;
1478 buttons |= SND_JACK_BTN_4;
1480 buttons |= SND_JACK_BTN_5;
1485 static int nau8825_jack_insert(struct nau8825 *nau8825)
1487 struct regmap *regmap = nau8825->regmap;
1488 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1489 int jack_status_reg, mic_detected;
1492 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1493 mic_detected = (jack_status_reg >> 10) & 3;
1494 /* The JKSLV and JKR2 all detected in high impedance headset */
1495 if (mic_detected == 0x3)
1496 nau8825->high_imped = true;
1498 nau8825->high_imped = false;
1500 switch (mic_detected) {
1503 type = SND_JACK_HEADPHONE;
1506 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1507 type = SND_JACK_HEADSET;
1509 /* Unground MICGND1 */
1510 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1512 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1513 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1514 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1515 NAU8825_MICBIAS_JKR2);
1516 /* Attach SARADC to MICGND1 */
1517 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1518 NAU8825_SAR_INPUT_MASK,
1519 NAU8825_SAR_INPUT_JKR2);
1521 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1522 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1523 snd_soc_dapm_sync(dapm);
1527 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1528 type = SND_JACK_HEADSET;
1530 /* Unground MICGND2 */
1531 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1533 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1534 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1535 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1536 NAU8825_MICBIAS_JKSLV);
1537 /* Attach SARADC to MICGND2 */
1538 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1539 NAU8825_SAR_INPUT_MASK,
1540 NAU8825_SAR_INPUT_JKSLV);
1542 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1543 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1544 snd_soc_dapm_sync(dapm);
1548 /* Leaving HPOL/R grounded after jack insert by default. They will be
1549 * ungrounded as part of the widget power up sequence at the beginning
1550 * of playback to reduce pop.
1555 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1556 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1558 static irqreturn_t nau8825_interrupt(int irq, void *data)
1560 struct nau8825 *nau8825 = (struct nau8825 *)data;
1561 struct regmap *regmap = nau8825->regmap;
1562 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1564 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1565 dev_err(nau8825->dev, "failed to read irq status\n");
1569 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1570 NAU8825_JACK_EJECTION_DETECTED) {
1572 nau8825_eject_jack(nau8825);
1573 event_mask |= SND_JACK_HEADSET;
1574 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1575 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1578 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1581 /* upper 8 bits of the register are for short pressed keys,
1582 * lower 8 bits - for long pressed buttons
1584 nau8825->button_pressed = nau8825_button_decode(
1587 event |= nau8825->button_pressed;
1588 event_mask |= NAU8825_BUTTONS;
1589 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1590 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1591 event_mask = NAU8825_BUTTONS;
1592 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1593 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1594 if (nau8825_is_jack_inserted(regmap)) {
1595 event |= nau8825_jack_insert(nau8825);
1596 if (!nau8825->high_imped) {
1597 /* Apply the cross talk suppression in the
1598 * headset without high impedance.
1600 if (!nau8825->xtalk_protect) {
1601 /* Raise protection for cross talk de-
1602 * tection if no protection before.
1603 * The driver has to cancel the pro-
1604 * cess and restore changes if process
1605 * is ongoing when ejection.
1608 nau8825->xtalk_protect = true;
1609 ret = nau8825_sema_acquire(nau8825, 0);
1611 nau8825->xtalk_protect = false;
1613 /* Startup cross talk detection process */
1614 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1615 schedule_work(&nau8825->xtalk_work);
1617 /* The cross talk suppression shouldn't apply
1618 * in the headset with high impedance. Thus,
1619 * relieve the protection raised before.
1621 if (nau8825->xtalk_protect) {
1622 nau8825_sema_release(nau8825);
1623 nau8825->xtalk_protect = false;
1627 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1628 nau8825_eject_jack(nau8825);
1631 event_mask |= SND_JACK_HEADSET;
1632 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1633 /* Record the interruption report event for driver to report
1634 * the event later. The jack report will delay until cross
1635 * talk detection process is done.
1637 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1638 nau8825->xtalk_event = event;
1639 nau8825->xtalk_event_mask = event_mask;
1641 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1642 schedule_work(&nau8825->xtalk_work);
1643 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1644 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1645 NAU8825_JACK_INSERTION_DETECTED) {
1646 /* One more step to check GPIO status directly. Thus, the
1647 * driver can confirm the real insertion interruption because
1648 * the intrruption at manual mode has bypassed debounce
1649 * circuit which can get rid of unstable status.
1651 if (nau8825_is_jack_inserted(regmap)) {
1652 /* Turn off insertion interruption at manual mode */
1653 regmap_update_bits(regmap,
1654 NAU8825_REG_INTERRUPT_DIS_CTRL,
1655 NAU8825_IRQ_INSERT_DIS,
1656 NAU8825_IRQ_INSERT_DIS);
1657 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1658 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1659 /* Enable interruption for jack type detection at audo
1660 * mode which can detect microphone and jack type.
1662 nau8825_setup_auto_irq(nau8825);
1667 clear_irq = active_irq;
1668 /* clears the rightmost interruption */
1669 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1671 /* Delay jack report until cross talk detection is done. It can avoid
1672 * application to do playback preparation when cross talk detection
1673 * process is still working. Otherwise, the resource like clock and
1674 * power will be issued by them at the same time and conflict happens.
1676 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1677 snd_soc_jack_report(nau8825->jack, event, event_mask);
1682 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1684 struct regmap *regmap = nau8825->regmap;
1686 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1687 NAU8825_SAR_TRACKING_GAIN_MASK,
1688 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1689 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1690 NAU8825_SAR_COMPARE_TIME_MASK,
1691 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1692 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1693 NAU8825_SAR_SAMPLING_TIME_MASK,
1694 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1696 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1697 NAU8825_KEYDET_LEVELS_NR_MASK,
1698 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1699 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1700 NAU8825_KEYDET_HYSTERESIS_MASK,
1701 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1702 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1703 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1704 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1706 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1707 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1708 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1709 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1710 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1711 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1712 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1713 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1715 /* Enable short press and release interruptions */
1716 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1717 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1721 static void nau8825_init_regs(struct nau8825 *nau8825)
1723 struct regmap *regmap = nau8825->regmap;
1725 /* Latch IIC LSB value */
1726 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1727 /* Enable Bias/Vmid */
1728 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1729 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1730 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1731 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1734 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1735 NAU8825_BIAS_VMID_SEL_MASK,
1736 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1737 /* Disable Boost Driver, Automatic Short circuit protection enable */
1738 regmap_update_bits(regmap, NAU8825_REG_BOOST,
1739 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1740 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1741 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1742 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1744 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1745 NAU8825_JKDET_OUTPUT_EN,
1746 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1747 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1748 NAU8825_JKDET_PULL_EN,
1749 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1750 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1751 NAU8825_JKDET_PULL_UP,
1752 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1753 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1754 NAU8825_JACK_POLARITY,
1755 /* jkdet_polarity - 1 is for active-low */
1756 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1758 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1759 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1760 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1761 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1762 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1763 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1765 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1766 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1768 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1769 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1771 if (nau8825->sar_threshold_num)
1772 nau8825_setup_buttons(nau8825);
1774 /* Default oversampling/decimations settings are unusable
1775 * (audible hiss). Set it to something better.
1777 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1778 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
1779 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1780 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
1781 /* Disable DACR/L power */
1782 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1783 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1784 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1785 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1786 * signal to avoid any glitches due to power up transients in both
1787 * the analog and digital DAC circuit.
1789 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1790 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1792 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1793 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1795 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1796 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1797 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1798 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1799 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1800 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1801 /* Class G timer 64ms */
1802 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1803 NAU8825_CLASSG_TIMER_MASK,
1804 0x20 << NAU8825_CLASSG_TIMER_SFT);
1805 /* DAC clock delay 2ns, VREF */
1806 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1807 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1808 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1809 (0x3 << NAU8825_RDAC_VREF_SFT));
1810 /* Config L/R channel */
1811 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1812 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1813 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1814 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1817 static const struct regmap_config nau8825_regmap_config = {
1818 .val_bits = NAU8825_REG_DATA_LEN,
1819 .reg_bits = NAU8825_REG_ADDR_LEN,
1821 .max_register = NAU8825_REG_MAX,
1822 .readable_reg = nau8825_readable_reg,
1823 .writeable_reg = nau8825_writeable_reg,
1824 .volatile_reg = nau8825_volatile_reg,
1826 .cache_type = REGCACHE_RBTREE,
1827 .reg_defaults = nau8825_reg_defaults,
1828 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1831 static int nau8825_codec_probe(struct snd_soc_codec *codec)
1833 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1834 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1836 nau8825->dapm = dapm;
1841 static int nau8825_codec_remove(struct snd_soc_codec *codec)
1843 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1845 /* Cancel and reset cross tak suppresstion detection funciton */
1846 nau8825_xtalk_cancel(nau8825);
1852 * nau8825_calc_fll_param - Calculate FLL parameters.
1853 * @fll_in: external clock provided to codec.
1854 * @fs: sampling rate.
1855 * @fll_param: Pointer to structure of FLL parameters.
1857 * Calculate FLL parameters to configure codec.
1859 * Returns 0 for success or negative error code.
1861 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1862 struct nau8825_fll *fll_param)
1865 unsigned int fref, i, fvco_sel;
1867 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1868 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1869 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1871 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1872 fref = fll_in / fll_pre_scalar[i].param;
1873 if (fref <= NAU_FREF_MAX)
1876 if (i == ARRAY_SIZE(fll_pre_scalar))
1878 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1880 /* Choose the FLL ratio based on FREF */
1881 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1882 if (fref >= fll_ratio[i].param)
1885 if (i == ARRAY_SIZE(fll_ratio))
1887 fll_param->ratio = fll_ratio[i].val;
1889 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1890 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1891 * guaranteed across the full range of operation.
1892 * FDCO = freq_out * 2 * mclk_src_scaling
1895 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1896 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1897 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1898 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1904 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1906 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1908 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1909 * input based on FDCO, FREF and FLL ratio.
1911 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1912 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1913 fll_param->fll_frac = fvco & 0xFFFF;
1917 static void nau8825_fll_apply(struct nau8825 *nau8825,
1918 struct nau8825_fll *fll_param)
1920 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1921 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
1922 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
1923 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1924 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1925 /* FLL 16-bit fractional input */
1926 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1927 /* FLL 10-bit integer input */
1928 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1929 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1930 /* FLL pre-scaler */
1931 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1932 NAU8825_FLL_REF_DIV_MASK,
1933 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
1934 /* select divided VCO input */
1935 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1936 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
1937 /* Disable free-running mode */
1938 regmap_update_bits(nau8825->regmap,
1939 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1940 if (fll_param->fll_frac) {
1941 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1942 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1943 NAU8825_FLL_FTR_SW_MASK,
1944 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1945 NAU8825_FLL_FTR_SW_FILTER);
1946 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1947 NAU8825_SDM_EN, NAU8825_SDM_EN);
1949 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1950 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1951 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
1952 regmap_update_bits(nau8825->regmap,
1953 NAU8825_REG_FLL6, NAU8825_SDM_EN, 0);
1957 /* freq_out must be 256*Fs in order to achieve the best performance */
1958 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1959 unsigned int freq_in, unsigned int freq_out)
1961 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1962 struct nau8825_fll fll_param;
1965 fs = freq_out / 256;
1966 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1968 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1971 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1972 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1973 fll_param.fll_int, fll_param.clk_ref_div);
1975 nau8825_fll_apply(nau8825, &fll_param);
1977 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1978 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1982 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
1986 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
1987 if (IS_ERR(nau8825->mclk)) {
1988 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
1992 if (!nau8825->mclk_freq) {
1993 ret = clk_prepare_enable(nau8825->mclk);
1995 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2000 if (nau8825->mclk_freq != freq) {
2001 freq = clk_round_rate(nau8825->mclk, freq);
2002 ret = clk_set_rate(nau8825->mclk, freq);
2004 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2007 nau8825->mclk_freq = freq;
2013 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2015 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2016 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2017 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2021 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2024 struct regmap *regmap = nau8825->regmap;
2028 case NAU8825_CLK_DIS:
2029 /* Clock provided externally and disable internal VCO clock */
2030 nau8825_configure_mclk_as_sysclk(regmap);
2031 if (nau8825->mclk_freq) {
2032 clk_disable_unprepare(nau8825->mclk);
2033 nau8825->mclk_freq = 0;
2037 case NAU8825_CLK_MCLK:
2038 /* Acquire the semaphone to synchronize the playback and
2039 * interrupt handler. In order to avoid the playback inter-
2040 * fered by cross talk process, the driver make the playback
2041 * preparation halted until cross talk process finish.
2043 nau8825_sema_acquire(nau8825, 2 * HZ);
2044 nau8825_configure_mclk_as_sysclk(regmap);
2045 /* MCLK not changed by clock tree */
2046 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2047 NAU8825_CLK_MCLK_SRC_MASK, 0);
2048 /* Release the semaphone. */
2049 nau8825_sema_release(nau8825);
2051 ret = nau8825_mclk_prepare(nau8825, freq);
2056 case NAU8825_CLK_INTERNAL:
2057 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2058 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2059 NAU8825_DCO_EN, NAU8825_DCO_EN);
2060 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2061 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2062 /* Decrease the VCO frequency for power saving */
2063 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2064 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2065 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2066 NAU8825_FLL_RATIO_MASK, 0x10);
2067 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2068 NAU8825_SDM_EN, NAU8825_SDM_EN);
2070 /* The clock turns off intentionally for power saving
2071 * when no headset connected.
2073 nau8825_configure_mclk_as_sysclk(regmap);
2074 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2076 if (nau8825->mclk_freq) {
2077 clk_disable_unprepare(nau8825->mclk);
2078 nau8825->mclk_freq = 0;
2082 case NAU8825_CLK_FLL_MCLK:
2083 /* Acquire the semaphone to synchronize the playback and
2084 * interrupt handler. In order to avoid the playback inter-
2085 * fered by cross talk process, the driver make the playback
2086 * preparation halted until cross talk process finish.
2088 nau8825_sema_acquire(nau8825, 2 * HZ);
2089 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2090 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
2091 /* Release the semaphone. */
2092 nau8825_sema_release(nau8825);
2094 ret = nau8825_mclk_prepare(nau8825, freq);
2099 case NAU8825_CLK_FLL_BLK:
2100 /* Acquire the semaphone to synchronize the playback and
2101 * interrupt handler. In order to avoid the playback inter-
2102 * fered by cross talk process, the driver make the playback
2103 * preparation halted until cross talk process finish.
2105 nau8825_sema_acquire(nau8825, 2 * HZ);
2106 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2107 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
2108 /* Release the semaphone. */
2109 nau8825_sema_release(nau8825);
2111 if (nau8825->mclk_freq) {
2112 clk_disable_unprepare(nau8825->mclk);
2113 nau8825->mclk_freq = 0;
2117 case NAU8825_CLK_FLL_FS:
2118 /* Acquire the semaphone to synchronize the playback and
2119 * interrupt handler. In order to avoid the playback inter-
2120 * fered by cross talk process, the driver make the playback
2121 * preparation halted until cross talk process finish.
2123 nau8825_sema_acquire(nau8825, 2 * HZ);
2124 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2125 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
2126 /* Release the semaphone. */
2127 nau8825_sema_release(nau8825);
2129 if (nau8825->mclk_freq) {
2130 clk_disable_unprepare(nau8825->mclk);
2131 nau8825->mclk_freq = 0;
2136 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2140 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2145 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2146 int source, unsigned int freq, int dir)
2148 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2150 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2153 static int nau8825_resume_setup(struct nau8825 *nau8825)
2155 struct regmap *regmap = nau8825->regmap;
2157 /* Close clock when jack type detection at manual mode */
2158 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2160 /* Clear all interruption status */
2161 nau8825_int_status_clear_all(regmap);
2163 /* Enable both insertion and ejection interruptions, and then
2164 * bypass de-bounce circuit.
2166 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2167 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2168 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2169 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2170 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2171 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2172 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2173 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2178 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2179 enum snd_soc_bias_level level)
2181 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2185 case SND_SOC_BIAS_ON:
2188 case SND_SOC_BIAS_PREPARE:
2191 case SND_SOC_BIAS_STANDBY:
2192 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2193 if (nau8825->mclk_freq) {
2194 ret = clk_prepare_enable(nau8825->mclk);
2196 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2200 /* Setup codec configuration after resume */
2201 nau8825_resume_setup(nau8825);
2205 case SND_SOC_BIAS_OFF:
2206 /* Cancel and reset cross talk detection funciton */
2207 nau8825_xtalk_cancel(nau8825);
2208 /* Turn off all interruptions before system shutdown. Keep the
2209 * interruption quiet before resume setup completes.
2211 regmap_write(nau8825->regmap,
2212 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2213 /* Disable ADC needed for interruptions at audo mode */
2214 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2215 NAU8825_ENABLE_ADC, 0);
2216 if (nau8825->mclk_freq)
2217 clk_disable_unprepare(nau8825->mclk);
2223 static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2225 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2227 disable_irq(nau8825->irq);
2228 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2229 regcache_cache_only(nau8825->regmap, true);
2230 regcache_mark_dirty(nau8825->regmap);
2235 static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2237 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2240 regcache_cache_only(nau8825->regmap, false);
2241 regcache_sync(nau8825->regmap);
2242 nau8825->xtalk_protect = true;
2243 ret = nau8825_sema_acquire(nau8825, 0);
2245 nau8825->xtalk_protect = false;
2246 enable_irq(nau8825->irq);
2251 static struct snd_soc_codec_driver nau8825_codec_driver = {
2252 .probe = nau8825_codec_probe,
2253 .remove = nau8825_codec_remove,
2254 .set_sysclk = nau8825_set_sysclk,
2255 .set_pll = nau8825_set_pll,
2256 .set_bias_level = nau8825_set_bias_level,
2257 .suspend_bias_off = true,
2258 .suspend = nau8825_suspend,
2259 .resume = nau8825_resume,
2261 .component_driver = {
2262 .controls = nau8825_controls,
2263 .num_controls = ARRAY_SIZE(nau8825_controls),
2264 .dapm_widgets = nau8825_dapm_widgets,
2265 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2266 .dapm_routes = nau8825_dapm_routes,
2267 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2271 static void nau8825_reset_chip(struct regmap *regmap)
2273 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2274 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2277 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2280 struct device *dev = nau8825->dev;
2282 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2283 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2284 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2285 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2286 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2287 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2289 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2290 for (i = 0; i < nau8825->sar_threshold_num; i++)
2291 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2292 nau8825->sar_threshold[i]);
2294 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2295 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2296 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2297 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2298 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2299 dev_dbg(dev, "jack-insert-debounce: %d\n",
2300 nau8825->jack_insert_debounce);
2301 dev_dbg(dev, "jack-eject-debounce: %d\n",
2302 nau8825->jack_eject_debounce);
2305 static int nau8825_read_device_properties(struct device *dev,
2306 struct nau8825 *nau8825) {
2308 nau8825->jkdet_enable = device_property_read_bool(dev,
2309 "nuvoton,jkdet-enable");
2310 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2311 "nuvoton,jkdet-pull-enable");
2312 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2313 "nuvoton,jkdet-pull-up");
2314 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2315 &nau8825->jkdet_polarity);
2316 device_property_read_u32(dev, "nuvoton,micbias-voltage",
2317 &nau8825->micbias_voltage);
2318 device_property_read_u32(dev, "nuvoton,vref-impedance",
2319 &nau8825->vref_impedance);
2320 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2321 &nau8825->sar_threshold_num);
2322 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2323 nau8825->sar_threshold, nau8825->sar_threshold_num);
2324 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2325 &nau8825->sar_hysteresis);
2326 device_property_read_u32(dev, "nuvoton,sar-voltage",
2327 &nau8825->sar_voltage);
2328 device_property_read_u32(dev, "nuvoton,sar-compare-time",
2329 &nau8825->sar_compare_time);
2330 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2331 &nau8825->sar_sampling_time);
2332 device_property_read_u32(dev, "nuvoton,short-key-debounce",
2333 &nau8825->key_debounce);
2334 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2335 &nau8825->jack_insert_debounce);
2336 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2337 &nau8825->jack_eject_debounce);
2339 nau8825->mclk = devm_clk_get(dev, "mclk");
2340 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2341 return -EPROBE_DEFER;
2342 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2343 /* The MCLK is managed externally or not used at all */
2344 nau8825->mclk = NULL;
2345 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2346 } else if (IS_ERR(nau8825->mclk)) {
2353 static int nau8825_setup_irq(struct nau8825 *nau8825)
2357 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2358 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2359 "nau8825", nau8825);
2362 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2370 static int nau8825_i2c_probe(struct i2c_client *i2c,
2371 const struct i2c_device_id *id)
2373 struct device *dev = &i2c->dev;
2374 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2378 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2381 ret = nau8825_read_device_properties(dev, nau8825);
2386 i2c_set_clientdata(i2c, nau8825);
2388 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2389 if (IS_ERR(nau8825->regmap))
2390 return PTR_ERR(nau8825->regmap);
2392 nau8825->irq = i2c->irq;
2393 /* Initiate parameters, semaphone and work queue which are needed in
2394 * cross talk suppression measurment function.
2396 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2397 nau8825->xtalk_protect = false;
2398 sema_init(&nau8825->xtalk_sem, 1);
2399 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2401 nau8825_print_device_properties(nau8825);
2403 nau8825_reset_chip(nau8825->regmap);
2404 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2406 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2410 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2411 NAU8825_SOFTWARE_ID_NAU8825) {
2412 dev_err(dev, "Not a NAU8825 chip\n");
2416 nau8825_init_regs(nau8825);
2419 nau8825_setup_irq(nau8825);
2421 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2425 static int nau8825_i2c_remove(struct i2c_client *client)
2427 snd_soc_unregister_codec(&client->dev);
2431 static const struct i2c_device_id nau8825_i2c_ids[] = {
2435 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2438 static const struct of_device_id nau8825_of_ids[] = {
2439 { .compatible = "nuvoton,nau8825", },
2442 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2446 static const struct acpi_device_id nau8825_acpi_match[] = {
2450 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2453 static struct i2c_driver nau8825_driver = {
2456 .of_match_table = of_match_ptr(nau8825_of_ids),
2457 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2459 .probe = nau8825_i2c_probe,
2460 .remove = nau8825_i2c_remove,
2461 .id_table = nau8825_i2c_ids,
2463 module_i2c_driver(nau8825_driver);
2465 MODULE_DESCRIPTION("ASoC nau8825 driver");
2466 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2467 MODULE_LICENSE("GPL");