1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Argus Lin <argus.lin@mediatek.com>
10 /*************Register Bit Define*************/
11 #define PMIC_ACCDET_IRQ_SHIFT 0
12 #define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
13 #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
14 #define PMIC_ACCDET_IRQ_CLR_SHIFT 8
15 #define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT 10
16 #define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT 11
17 #define PMIC_RG_INT_STATUS_ACCDET_SHIFT 5
18 #define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6
19 #define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7
20 #define PMIC_RG_EINT0CONFIGACCDET_SHIFT 11
21 #define PMIC_RG_EINT1CONFIGACCDET_SHIFT 0
22 #define PMIC_ACCDET_EINT0_INVERTER_SW_EN_SHIFT 6
23 #define PMIC_ACCDET_EINT1_INVERTER_SW_EN_SHIFT 8
24 #define PMIC_RG_MTEST_EN_SHIFT 8
25 #define PMIC_RG_MTEST_SEL_SHIFT 9
26 #define PMIC_ACCDET_EINT0_M_SW_EN_SHIFT 10
27 #define PMIC_ACCDET_EINT1_M_SW_EN_SHIFT 11
28 #define PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT 5
29 #define PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT 10
30 #define PMIC_ACCDET_DA_STABLE_SHIFT 0
31 #define PMIC_ACCDET_EINT0_EN_STABLE_SHIFT 1
32 #define PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT 2
33 #define PMIC_ACCDET_EINT1_EN_STABLE_SHIFT 6
34 #define PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT 7
35 #define PMIC_ACCDET_EINT_CTURBO_SEL_SHIFT 7
36 #define PMIC_ACCDET_EINT0_CTURBO_SW_SHIFT 7
37 #define PMIC_RG_EINTCOMPVTH_SHIFT 4
38 #define PMIC_RG_EINT0HIRENB_SHIFT 12
39 #define PMIC_RG_EINT0NOHYS_SHIFT 10
40 #define PMIC_ACCDET_SW_EN_SHIFT 0
41 #define PMIC_ACCDET_EINT0_MEM_IN_SHIFT 6
42 #define PMIC_ACCDET_MEM_IN_SHIFT 6
43 #define PMIC_ACCDET_EINT_DEBOUNCE0_SHIFT 0
44 #define PMIC_ACCDET_EINT_DEBOUNCE1_SHIFT 4
45 #define PMIC_ACCDET_EINT_DEBOUNCE2_SHIFT 8
46 #define PMIC_ACCDET_EINT_DEBOUNCE3_SHIFT 12
47 #define PMIC_RG_ACCDET2AUXSWEN_SHIFT 14
48 #define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 9
49 #define PMIC_AUDACCDETAUXADCSWCTRL_SW_SHIFT 10
50 #define PMIC_RG_EINT0CTURBO_SHIFT 5
51 #define PMIC_RG_EINT1CTURBO_SHIFT 13
52 #define PMIC_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT 12
53 #define PMIC_ACCDET_EINT_M_DETECT_EN_SHIFT 12
54 #define PMIC_ACCDET_EINT0_SW_EN_SHIFT 2
55 #define PMIC_ACCDET_EINT1_SW_EN_SHIFT 4
56 #define PMIC_ACCDET_EINT_CMPMOUT_SEL_SHIFT 12
57 #define PMIC_ACCDET_EINT_CMPMEN_SEL_SHIFT 6
58 #define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT 0
59 #define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT 4
60 #define PMIC_RG_EINT0EN_SHIFT 2
61 #define PMIC_RG_EINT1EN_SHIFT 10
62 #define PMIC_RG_NCP_PDDIS_EN_SHIFT 0
63 #define PMIC_RG_ACCDETSPARE_SHIFT 0
64 #define PMIC_RG_ACCDET_RST_SHIFT 1
65 #define PMIC_RG_AUDMICBIAS1HVEN_SHIFT 12
66 #define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4
67 #define PMIC_RG_ANALOGFDEN_SHIFT 12
68 #define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT 8
69 #define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2
70 #define PMIC_ACCDET_SEQ_INIT_SHIFT 1
71 #define PMIC_RG_EINTCOMPVTH_MASK 0xf
72 #define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x3
73 #define PMIC_ACCDET_EINT_DEBOUNCE0_MASK 0xf
74 #define PMIC_ACCDET_EINT_DEBOUNCE1_MASK 0xf
75 #define PMIC_ACCDET_EINT_DEBOUNCE2_MASK 0xf
76 #define PMIC_ACCDET_EINT_DEBOUNCE3_MASK 0xf
77 #define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
78 #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
80 /* AUDENC_ANA_CON16: */
81 #define RG_AUD_MICBIAS1_LOWP_EN BIT(PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT)
83 /* AUDENC_ANA_CON18: */
84 #define RG_ACCDET_MODE_ANA11_MODE1 (0x000f)
85 #define RG_ACCDET_MODE_ANA11_MODE2 (0x008f)
86 #define RG_ACCDET_MODE_ANA11_MODE6 (0x008f)
88 /* AUXADC_ADC5: Auxadc CH5 read data */
89 #define AUXADC_DATA_RDY_CH5 BIT(15)
90 #define AUXADC_DATA_PROCEED_CH5 BIT(15)
91 #define AUXADC_DATA_MASK (0x0fff)
93 /* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
94 #define AUXADC_RQST_CH5_SET BIT(5)
95 /* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
96 #define AUXADC_RQST_CH5_CLR BIT(5)
98 #define ACCDET_CALI_MASK0 (0xff)
99 #define ACCDET_CALI_MASK1 (0xff << 8)
100 #define ACCDET_CALI_MASK2 (0xff)
101 #define ACCDET_CALI_MASK3 (0xff << 8)
102 #define ACCDET_CALI_MASK4 (0xff)
104 #define ACCDET_EINT1_IRQ_CLR_B11 BIT(PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT)
105 #define ACCDET_EINT0_IRQ_CLR_B10 BIT(PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
106 #define ACCDET_EINT_IRQ_CLR_B10_11 (0x03 << \
107 PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
108 #define ACCDET_IRQ_CLR_B8 BIT(PMIC_ACCDET_IRQ_CLR_SHIFT)
110 #define ACCDET_EINT1_IRQ_B3 BIT(PMIC_ACCDET_EINT1_IRQ_SHIFT)
111 #define ACCDET_EINT0_IRQ_B2 BIT(PMIC_ACCDET_EINT0_IRQ_SHIFT)
112 #define ACCDET_EINT_IRQ_B2_B3 (0x03 << PMIC_ACCDET_EINT0_IRQ_SHIFT)
113 #define ACCDET_IRQ_B0 BIT(PMIC_ACCDET_IRQ_SHIFT)
115 /* ACCDET_CON25: RO, accdet FSM state,etc.*/
116 #define ACCDET_STATE_MEM_IN_OFFSET (PMIC_ACCDET_MEM_IN_SHIFT)
117 #define ACCDET_STATE_AB_MASK (0x03)
118 #define ACCDET_STATE_AB_00 (0x00)
119 #define ACCDET_STATE_AB_01 (0x01)
120 #define ACCDET_STATE_AB_10 (0x02)
121 #define ACCDET_STATE_AB_11 (0x03)
124 #define ACCDET_EINT0_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
125 (1 << PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \
126 (1 << PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \
127 (1 << PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT))
129 #define ACCDET_EINT1_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
130 (1 << PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \
131 (1 << PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \
132 (1 << PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT))
134 /* The following are used for mt6359.c */
135 /* MT6359_DCXO_CW12 */
136 #define RG_XO_AUDIO_EN_M_SFT 13
138 /* LDO_VAUD18_CON0 */
139 #define RG_LDO_VAUD18_EN_SFT 0
140 #define RG_LDO_VAUD18_EN_MASK 0x1
141 #define RG_LDO_VAUD18_EN_MASK_SFT (0x1 << 0)
143 /* AUD_TOP_CKPDN_CON0 */
144 #define RG_VOW13M_CK_PDN_SFT 13
145 #define RG_VOW13M_CK_PDN_MASK 0x1
146 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
147 #define RG_VOW32K_CK_PDN_SFT 12
148 #define RG_VOW32K_CK_PDN_MASK 0x1
149 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
150 #define RG_AUD_INTRP_CK_PDN_SFT 8
151 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
152 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
153 #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT 7
154 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
155 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
156 #define RG_AUDNCP_CK_PDN_SFT 6
157 #define RG_AUDNCP_CK_PDN_MASK 0x1
158 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
159 #define RG_ZCD13M_CK_PDN_SFT 5
160 #define RG_ZCD13M_CK_PDN_MASK 0x1
161 #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
162 #define RG_AUDIF_CK_PDN_SFT 2
163 #define RG_AUDIF_CK_PDN_MASK 0x1
164 #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
165 #define RG_AUD_CK_PDN_SFT 1
166 #define RG_AUD_CK_PDN_MASK 0x1
167 #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
168 #define RG_ACCDET_CK_PDN_SFT 0
169 #define RG_ACCDET_CK_PDN_MASK 0x1
170 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
172 /* AUD_TOP_CKPDN_CON0_SET */
173 #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0
174 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff
175 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)
177 /* AUD_TOP_CKPDN_CON0_CLR */
178 #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0
179 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff
180 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)
182 /* AUD_TOP_CKSEL_CON0 */
183 #define RG_AUDIF_CK_CKSEL_SFT 3
184 #define RG_AUDIF_CK_CKSEL_MASK 0x1
185 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
186 #define RG_AUD_CK_CKSEL_SFT 2
187 #define RG_AUD_CK_CKSEL_MASK 0x1
188 #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
190 /* AUD_TOP_CKSEL_CON0_SET */
191 #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0
192 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf
193 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)
195 /* AUD_TOP_CKSEL_CON0_CLR */
196 #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0
197 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf
198 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)
200 /* AUD_TOP_CKTST_CON0 */
201 #define RG_VOW13M_CK_TSTSEL_SFT 9
202 #define RG_VOW13M_CK_TSTSEL_MASK 0x1
203 #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
204 #define RG_VOW13M_CK_TST_DIS_SFT 8
205 #define RG_VOW13M_CK_TST_DIS_MASK 0x1
206 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
207 #define RG_AUD26M_CK_TSTSEL_SFT 4
208 #define RG_AUD26M_CK_TSTSEL_MASK 0x1
209 #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
210 #define RG_AUDIF_CK_TSTSEL_SFT 3
211 #define RG_AUDIF_CK_TSTSEL_MASK 0x1
212 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
213 #define RG_AUD_CK_TSTSEL_SFT 2
214 #define RG_AUD_CK_TSTSEL_MASK 0x1
215 #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
216 #define RG_AUD26M_CK_TST_DIS_SFT 0
217 #define RG_AUD26M_CK_TST_DIS_MASK 0x1
218 #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
220 /* AUD_TOP_CLK_HWEN_CON0 */
221 #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0
222 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
223 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
225 /* AUD_TOP_CLK_HWEN_CON0_SET */
226 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0
227 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff
228 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)
230 /* AUD_TOP_CLK_HWEN_CON0_CLR */
231 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0
232 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff
233 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)
235 /* AUD_TOP_RST_CON0 */
236 #define RG_AUDNCP_RST_SFT 3
237 #define RG_AUDNCP_RST_MASK 0x1
238 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
239 #define RG_ZCD_RST_SFT 2
240 #define RG_ZCD_RST_MASK 0x1
241 #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
242 #define RG_ACCDET_RST_SFT 1
243 #define RG_ACCDET_RST_MASK 0x1
244 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
245 #define RG_AUDIO_RST_SFT 0
246 #define RG_AUDIO_RST_MASK 0x1
247 #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
249 /* AUD_TOP_RST_CON0_SET */
250 #define RG_AUD_TOP_RST_CON0_SET_SFT 0
251 #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf
252 #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)
254 /* AUD_TOP_RST_CON0_CLR */
255 #define RG_AUD_TOP_RST_CON0_CLR_SFT 0
256 #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf
257 #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)
259 /* AUD_TOP_RST_BANK_CON0 */
260 #define BANK_AUDZCD_SWRST_SFT 2
261 #define BANK_AUDZCD_SWRST_MASK 0x1
262 #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
263 #define BANK_AUDIO_SWRST_SFT 1
264 #define BANK_AUDIO_SWRST_MASK 0x1
265 #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
266 #define BANK_ACCDET_SWRST_SFT 0
267 #define BANK_ACCDET_SWRST_MASK 0x1
268 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
271 #define AFE_UL_LR_SWAP_SFT 15
272 #define AFE_UL_LR_SWAP_MASK 0x1
273 #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
274 #define AFE_DL_LR_SWAP_SFT 14
275 #define AFE_DL_LR_SWAP_MASK 0x1
276 #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
278 #define AFE_ON_MASK 0x1
279 #define AFE_ON_MASK_SFT (0x1 << 0)
281 /* AFE_DL_SRC2_CON0_L */
282 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
283 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
284 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
286 /* AFE_UL_SRC_CON0_H */
287 #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11
288 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
289 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
290 #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8
291 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
292 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
293 #define C_TWO_DIGITAL_MIC_CTL_SFT 7
294 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
295 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
297 /* AFE_UL_SRC_CON0_L */
298 #define DMIC_LOW_POWER_MODE_CTL_SFT 14
299 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
300 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
301 #define DIGMIC_4P33M_SEL_CTL_SFT 6
302 #define DIGMIC_4P33M_SEL_CTL_MASK 0x1
303 #define DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
304 #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
305 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
306 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
307 #define UL_LOOP_BACK_MODE_CTL_SFT 2
308 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
309 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
310 #define UL_SDM_3_LEVEL_CTL_SFT 1
311 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
312 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
313 #define UL_SRC_ON_TMP_CTL_SFT 0
314 #define UL_SRC_ON_TMP_CTL_MASK 0x1
315 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
317 /* AFE_ADDA6_L_SRC_CON0_H */
318 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 11
319 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
320 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
321 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 8
322 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
323 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
324 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_SFT 7
325 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
326 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
328 /* AFE_ADDA6_UL_SRC_CON0_L */
329 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT 14
330 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
331 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
332 #define ADDA6_DIGMIC_4P33M_SEL_CTL_SFT 6
333 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK 0x1
334 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
335 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
336 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
337 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
338 #define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT 2
339 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x1
340 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
341 #define ADDA6_UL_SDM_3_LEVEL_CTL_SFT 1
342 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x1
343 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
344 #define ADDA6_UL_SRC_ON_TMP_CTL_SFT 0
345 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x1
346 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
349 #define ADDA6_MTKAIF_SINE_ON_SFT 4
350 #define ADDA6_MTKAIF_SINE_ON_MASK 0x1
351 #define ADDA6_MTKAIF_SINE_ON_MASK_SFT (0x1 << 4)
352 #define ADDA6_UL_SINE_ON_SFT 3
353 #define ADDA6_UL_SINE_ON_MASK 0x1
354 #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
355 #define MTKAIF_SINE_ON_SFT 2
356 #define MTKAIF_SINE_ON_MASK 0x1
357 #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
358 #define UL_SINE_ON_SFT 1
359 #define UL_SINE_ON_MASK 0x1
360 #define UL_SINE_ON_MASK_SFT (0x1 << 1)
361 #define DL_SINE_ON_SFT 0
362 #define DL_SINE_ON_MASK 0x1
363 #define DL_SINE_ON_MASK_SFT (0x1 << 0)
366 #define PDN_AFE_CTL_SFT 7
367 #define PDN_AFE_CTL_MASK 0x1
368 #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
369 #define PDN_DAC_CTL_SFT 6
370 #define PDN_DAC_CTL_MASK 0x1
371 #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
372 #define PDN_ADC_CTL_SFT 5
373 #define PDN_ADC_CTL_MASK 0x1
374 #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
375 #define PDN_ADDA6_ADC_CTL_SFT 4
376 #define PDN_ADDA6_ADC_CTL_MASK 0x1
377 #define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4)
378 #define PDN_I2S_DL_CTL_SFT 3
379 #define PDN_I2S_DL_CTL_MASK 0x1
380 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
381 #define PWR_CLK_DIS_CTL_SFT 2
382 #define PWR_CLK_DIS_CTL_MASK 0x1
383 #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
384 #define PDN_AFE_TESTMODEL_CTL_SFT 1
385 #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
386 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
387 #define PDN_RESERVED_SFT 0
388 #define PDN_RESERVED_MASK 0x1
389 #define PDN_RESERVED_MASK_SFT (0x1 << 0)
392 #define AUDIO_SYS_TOP_MON_SWAP_SFT 14
393 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
394 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
395 #define AUDIO_SYS_TOP_MON_SEL_SFT 8
396 #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f
397 #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)
398 #define AFE_MON_SEL_SFT 0
399 #define AFE_MON_SEL_MASK 0xff
400 #define AFE_MON_SEL_MASK_SFT (0xff << 0)
403 #define CCI_AUD_ANACK_SEL_SFT 15
404 #define CCI_AUD_ANACK_SEL_MASK 0x1
405 #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
406 #define CCI_AUDIO_FIFO_WPTR_SFT 12
407 #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
408 #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
409 #define CCI_SCRAMBLER_CG_EN_SFT 11
410 #define CCI_SCRAMBLER_CG_EN_MASK 0x1
411 #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
412 #define CCI_LCH_INV_SFT 10
413 #define CCI_LCH_INV_MASK 0x1
414 #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
415 #define CCI_RAND_EN_SFT 9
416 #define CCI_RAND_EN_MASK 0x1
417 #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
418 #define CCI_SPLT_SCRMB_CLK_ON_SFT 8
419 #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
420 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
421 #define CCI_SPLT_SCRMB_ON_SFT 7
422 #define CCI_SPLT_SCRMB_ON_MASK 0x1
423 #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
424 #define CCI_AUD_IDAC_TEST_EN_SFT 6
425 #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
426 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
427 #define CCI_ZERO_PAD_DISABLE_SFT 5
428 #define CCI_ZERO_PAD_DISABLE_MASK 0x1
429 #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
430 #define CCI_AUD_SPLIT_TEST_EN_SFT 4
431 #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
432 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
433 #define CCI_AUD_SDM_MUTEL_SFT 3
434 #define CCI_AUD_SDM_MUTEL_MASK 0x1
435 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
436 #define CCI_AUD_SDM_MUTER_SFT 2
437 #define CCI_AUD_SDM_MUTER_MASK 0x1
438 #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
439 #define CCI_AUD_SDM_7BIT_SEL_SFT 1
440 #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
441 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
442 #define CCI_SCRAMBLER_EN_SFT 0
443 #define CCI_SCRAMBLER_EN_MASK 0x1
444 #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
447 #define AUD_SDM_TEST_L_SFT 8
448 #define AUD_SDM_TEST_L_MASK 0xff
449 #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)
450 #define AUD_SDM_TEST_R_SFT 0
451 #define AUD_SDM_TEST_R_MASK 0xff
452 #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)
455 #define CCI_AUD_DAC_ANA_MUTE_SFT 7
456 #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
457 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
458 #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6
459 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
460 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
461 #define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4
462 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
463 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
464 #define CCI_AUDIO_FIFO_ENABLE_SFT 3
465 #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
466 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
467 #define CCI_ACD_MODE_SFT 2
468 #define CCI_ACD_MODE_MASK 0x1
469 #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
470 #define CCI_AFIFO_CLK_PWDB_SFT 1
471 #define CCI_AFIFO_CLK_PWDB_MASK 0x1
472 #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
473 #define CCI_ACD_FUNC_RSTB_SFT 0
474 #define CCI_ACD_FUNC_RSTB_MASK 0x1
475 #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
478 #define SDM_ANA13M_TESTCK_SEL_SFT 15
479 #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
480 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
481 #define SDM_ANA13M_TESTCK_SRC_SEL_SFT 12
482 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
483 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
484 #define SDM_TESTCK_SRC_SEL_SFT 8
485 #define SDM_TESTCK_SRC_SEL_MASK 0x7
486 #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
487 #define DIGMIC_TESTCK_SRC_SEL_SFT 4
488 #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
489 #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
490 #define DIGMIC_TESTCK_SEL_SFT 0
491 #define DIGMIC_TESTCK_SEL_MASK 0x1
492 #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
495 #define UL_FIFO_WCLK_INV_SFT 8
496 #define UL_FIFO_WCLK_INV_MASK 0x1
497 #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
498 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6
499 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
500 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
501 #define UL_FIFO_WDATA_TESTEN_SFT 5
502 #define UL_FIFO_WDATA_TESTEN_MASK 0x1
503 #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
504 #define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4
505 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
506 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
507 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
508 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
509 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
510 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
511 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
512 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
515 #define R_AUD_DAC_POS_LARGE_MONO_SFT 8
516 #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff
517 #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)
518 #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0
519 #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff
520 #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)
523 #define R_AUD_DAC_POS_SMALL_MONO_SFT 12
524 #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf
525 #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)
526 #define R_AUD_DAC_NEG_SMALL_MONO_SFT 8
527 #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf
528 #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)
529 #define R_AUD_DAC_POS_TINY_MONO_SFT 6
530 #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
531 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
532 #define R_AUD_DAC_NEG_TINY_MONO_SFT 4
533 #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
534 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
535 #define R_AUD_DAC_MONO_SEL_SFT 3
536 #define R_AUD_DAC_MONO_SEL_MASK 0x1
537 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
538 #define R_AUD_DAC_3TH_SEL_SFT 1
539 #define R_AUD_DAC_3TH_SEL_MASK 0x1
540 #define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1)
541 #define R_AUD_DAC_SW_RSTB_SFT 0
542 #define R_AUD_DAC_SW_RSTB_MASK 0x1
543 #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
546 #define UL2_DIGMIC_TESTCK_SRC_SEL_SFT 10
547 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
548 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 10)
549 #define UL2_DIGMIC_TESTCK_SEL_SFT 9
550 #define UL2_DIGMIC_TESTCK_SEL_MASK 0x1
551 #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 9)
552 #define UL2_FIFO_WCLK_INV_SFT 8
553 #define UL2_FIFO_WCLK_INV_MASK 0x1
554 #define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
555 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6
556 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
557 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
558 #define UL2_FIFO_WDATA_TESTEN_SFT 5
559 #define UL2_FIFO_WDATA_TESTEN_MASK 0x1
560 #define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
561 #define UL2_FIFO_WDATA_TESTSRC_SEL_SFT 4
562 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
563 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
564 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
565 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
566 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
567 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
568 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
569 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
572 #define SPLITTER2_DITHER_EN_SFT 9
573 #define SPLITTER2_DITHER_EN_MASK 0x1
574 #define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
575 #define SPLITTER1_DITHER_EN_SFT 8
576 #define SPLITTER1_DITHER_EN_MASK 0x1
577 #define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
578 #define SPLITTER2_DITHER_GAIN_SFT 4
579 #define SPLITTER2_DITHER_GAIN_MASK 0xf
580 #define SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)
581 #define SPLITTER1_DITHER_GAIN_SFT 0
582 #define SPLITTER1_DITHER_GAIN_MASK 0xf
583 #define SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)
586 #define CCI_AUD_ANACK_SEL_2ND_SFT 15
587 #define CCI_AUD_ANACK_SEL_2ND_MASK 0x1
588 #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 15)
589 #define CCI_AUDIO_FIFO_WPTR_2ND_SFT 12
590 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x7
591 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 12)
592 #define CCI_SCRAMBLER_CG_EN_2ND_SFT 11
593 #define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x1
594 #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 11)
595 #define CCI_LCH_INV_2ND_SFT 10
596 #define CCI_LCH_INV_2ND_MASK 0x1
597 #define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 10)
598 #define CCI_RAND_EN_2ND_SFT 9
599 #define CCI_RAND_EN_2ND_MASK 0x1
600 #define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 9)
601 #define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT 8
602 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x1
603 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 8)
604 #define CCI_SPLT_SCRMB_ON_2ND_SFT 7
605 #define CCI_SPLT_SCRMB_ON_2ND_MASK 0x1
606 #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7)
607 #define CCI_AUD_IDAC_TEST_EN_2ND_SFT 6
608 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x1
609 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6)
610 #define CCI_ZERO_PAD_DISABLE_2ND_SFT 5
611 #define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x1
612 #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5)
613 #define CCI_AUD_SPLIT_TEST_EN_2ND_SFT 4
614 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x1
615 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4)
616 #define CCI_AUD_SDM_MUTEL_2ND_SFT 3
617 #define CCI_AUD_SDM_MUTEL_2ND_MASK 0x1
618 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
619 #define CCI_AUD_SDM_MUTER_2ND_SFT 2
620 #define CCI_AUD_SDM_MUTER_2ND_MASK 0x1
621 #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2)
622 #define CCI_AUD_SDM_7BIT_SEL_2ND_SFT 1
623 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x1
624 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1)
625 #define CCI_SCRAMBLER_EN_2ND_SFT 0
626 #define CCI_SCRAMBLER_EN_2ND_MASK 0x1
627 #define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0)
629 /* AFUNC_AUD_CON10 */
630 #define AUD_SDM_TEST_L_2ND_SFT 8
631 #define AUD_SDM_TEST_L_2ND_MASK 0xff
632 #define AUD_SDM_TEST_L_2ND_MASK_SFT (0xff << 8)
633 #define AUD_SDM_TEST_R_2ND_SFT 0
634 #define AUD_SDM_TEST_R_2ND_MASK 0xff
635 #define AUD_SDM_TEST_R_2ND_MASK_SFT (0xff << 0)
637 /* AFUNC_AUD_CON11 */
638 #define CCI_AUD_DAC_ANA_MUTE_2ND_SFT 7
639 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x1
640 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7)
641 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT 6
642 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x1
643 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6)
644 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT 4
645 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x1
646 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4)
647 #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 3
648 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x1
649 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
650 #define CCI_ACD_MODE_2ND_SFT 2
651 #define CCI_ACD_MODE_2ND_MASK 0x1
652 #define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2)
653 #define CCI_AFIFO_CLK_PWDB_2ND_SFT 1
654 #define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x1
655 #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1)
656 #define CCI_ACD_FUNC_RSTB_2ND_SFT 0
657 #define CCI_ACD_FUNC_RSTB_2ND_MASK 0x1
658 #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0)
660 /* AFUNC_AUD_CON12 */
661 #define SPLITTER2_DITHER_EN_2ND_SFT 9
662 #define SPLITTER2_DITHER_EN_2ND_MASK 0x1
663 #define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 9)
664 #define SPLITTER1_DITHER_EN_2ND_SFT 8
665 #define SPLITTER1_DITHER_EN_2ND_MASK 0x1
666 #define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 8)
667 #define SPLITTER2_DITHER_GAIN_2ND_SFT 4
668 #define SPLITTER2_DITHER_GAIN_2ND_MASK 0xf
669 #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT (0xf << 4)
670 #define SPLITTER1_DITHER_GAIN_2ND_SFT 0
671 #define SPLITTER1_DITHER_GAIN_2ND_MASK 0xf
672 #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT (0xf << 0)
675 #define AUD_SCR_OUT_L_SFT 8
676 #define AUD_SCR_OUT_L_MASK 0xff
677 #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)
678 #define AUD_SCR_OUT_R_SFT 0
679 #define AUD_SCR_OUT_R_MASK 0xff
680 #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)
683 #define AUD_SCR_OUT_L_2ND_SFT 8
684 #define AUD_SCR_OUT_L_2ND_MASK 0xff
685 #define AUD_SCR_OUT_L_2ND_MASK_SFT (0xff << 8)
686 #define AUD_SCR_OUT_R_2ND_SFT 0
687 #define AUD_SCR_OUT_R_2ND_MASK 0xff
688 #define AUD_SCR_OUT_R_2ND_MASK_SFT (0xff << 0)
690 /* AUDRC_TUNE_MON0 */
691 #define ASYNC_TEST_OUT_BCK_SFT 15
692 #define ASYNC_TEST_OUT_BCK_MASK 0x1
693 #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
694 #define RGS_AUDRCTUNE1READ_SFT 8
695 #define RGS_AUDRCTUNE1READ_MASK 0x1f
696 #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)
697 #define RGS_AUDRCTUNE0READ_SFT 0
698 #define RGS_AUDRCTUNE0READ_MASK 0x1f
699 #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)
701 /* AFE_ADDA_MTKAIF_FIFO_CFG0 */
702 #define AFE_RESERVED_SFT 1
703 #define AFE_RESERVED_MASK 0x7fff
704 #define AFE_RESERVED_MASK_SFT (0x7fff << 1)
705 #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0
706 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
707 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
709 /* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */
710 #define MTKAIF_RXIF_WR_FULL_STATUS_SFT 1
711 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
712 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
713 #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0
714 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
715 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
717 /* AFE_ADDA_MTKAIF_MON0 */
718 #define MTKAIFTX_V3_SYNC_OUT_SFT 15
719 #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
720 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 15)
721 #define MTKAIFTX_V3_SDATA_OUT3_SFT 14
722 #define MTKAIFTX_V3_SDATA_OUT3_MASK 0x1
723 #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT (0x1 << 14)
724 #define MTKAIFTX_V3_SDATA_OUT2_SFT 13
725 #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
726 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
727 #define MTKAIFTX_V3_SDATA_OUT1_SFT 12
728 #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
729 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
730 #define MTKAIF_RXIF_FIFO_STATUS_SFT 0
731 #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff
732 #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)
734 /* AFE_ADDA_MTKAIF_MON1 */
735 #define MTKAIFRX_V3_SYNC_IN_SFT 15
736 #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
737 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 15)
738 #define MTKAIFRX_V3_SDATA_IN3_SFT 14
739 #define MTKAIFRX_V3_SDATA_IN3_MASK 0x1
740 #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT (0x1 << 14)
741 #define MTKAIFRX_V3_SDATA_IN2_SFT 13
742 #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
743 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
744 #define MTKAIFRX_V3_SDATA_IN1_SFT 12
745 #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
746 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
747 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 11
748 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
749 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
750 #define MTKAIF_RXIF_INVALID_FLAG_SFT 8
751 #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
752 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
753 #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0
754 #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff
755 #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)
757 /* AFE_ADDA_MTKAIF_MON2 */
758 #define MTKAIF_TXIF_IN_CH2_SFT 8
759 #define MTKAIF_TXIF_IN_CH2_MASK 0xff
760 #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
761 #define MTKAIF_TXIF_IN_CH1_SFT 0
762 #define MTKAIF_TXIF_IN_CH1_MASK 0xff
763 #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
765 /* AFE_ADDA6_MTKAIF_MON3 */
766 #define ADDA6_MTKAIF_TXIF_IN_CH2_SFT 8
767 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK 0xff
768 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
769 #define ADDA6_MTKAIF_TXIF_IN_CH1_SFT 0
770 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK 0xff
771 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
773 /* AFE_ADDA_MTKAIF_MON4 */
774 #define MTKAIF_RXIF_OUT_CH2_SFT 8
775 #define MTKAIF_RXIF_OUT_CH2_MASK 0xff
776 #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
777 #define MTKAIF_RXIF_OUT_CH1_SFT 0
778 #define MTKAIF_RXIF_OUT_CH1_MASK 0xff
779 #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
781 /* AFE_ADDA_MTKAIF_MON5 */
782 #define MTKAIF_RXIF_OUT_CH3_SFT 0
783 #define MTKAIF_RXIF_OUT_CH3_MASK 0xff
784 #define MTKAIF_RXIF_OUT_CH3_MASK_SFT (0xff << 0)
786 /* AFE_ADDA_MTKAIF_CFG0 */
787 #define RG_MTKAIF_RXIF_CLKINV_SFT 15
788 #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
789 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
790 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_SFT 9
791 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
792 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 9)
793 #define RG_MTKAIF_RXIF_PROTOCOL2_SFT 8
794 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
795 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
796 #define RG_MTKAIF_BYPASS_SRC_MODE_SFT 6
797 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
798 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
799 #define RG_MTKAIF_BYPASS_SRC_TEST_SFT 5
800 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
801 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
802 #define RG_MTKAIF_TXIF_PROTOCOL2_SFT 4
803 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
804 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
805 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT 3
806 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
807 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
808 #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 2
809 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
810 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
811 #define RG_MTKAIF_LOOPBACK_TEST2_SFT 1
812 #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
813 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
814 #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0
815 #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
816 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
818 /* AFE_ADDA_MTKAIF_RX_CFG0 */
819 #define RG_MTKAIF_RXIF_VOICE_MODE_SFT 12
820 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf
821 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)
822 #define RG_MTKAIF_RXIF_DATA_BIT_SFT 8
823 #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
824 #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
825 #define RG_MTKAIF_RXIF_FIFO_RSP_SFT 4
826 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
827 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
828 #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3
829 #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
830 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
831 #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0
832 #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
833 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
835 /* AFE_ADDA_MTKAIF_RX_CFG1 */
836 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 12
837 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
838 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
839 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 8
840 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
841 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
842 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 4
843 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf
844 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
845 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0
846 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf
847 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)
849 /* AFE_ADDA_MTKAIF_RX_CFG2 */
850 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_SFT 15
851 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK 0x1
852 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT (0x1 << 15)
853 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_SFT 14
854 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK 0x1
855 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 14)
856 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_SFT 13
857 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
858 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 13)
859 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 12
860 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
861 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
862 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0
863 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff
864 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)
866 /* AFE_ADDA_MTKAIF_RX_CFG3 */
867 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT 7
868 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
869 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
870 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4
871 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
872 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
873 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3
874 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
875 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
877 /* AFE_ADDA_MTKAIF_SYNCWORD_CFG0 */
878 #define RG_MTKAIF_RX_SYNC_WORD2_SFT 4
879 #define RG_MTKAIF_RX_SYNC_WORD2_MASK 0x7
880 #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT (0x7 << 4)
881 #define RG_MTKAIF_RX_SYNC_WORD1_SFT 0
882 #define RG_MTKAIF_RX_SYNC_WORD1_MASK 0x7
883 #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT (0x7 << 0)
885 /* AFE_ADDA_MTKAIF_SYNCWORD_CFG1 */
886 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_SFT 12
887 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK 0x7
888 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 12)
889 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_SFT 8
890 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK 0x7
891 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 8)
892 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_SFT 4
893 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK 0x7
894 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 4)
895 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT 0
896 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK 0x7
897 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 0)
900 #define SGEN_AMP_DIV_CH1_CTL_SFT 12
901 #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf
902 #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)
903 #define SGEN_DAC_EN_CTL_SFT 7
904 #define SGEN_DAC_EN_CTL_MASK 0x1
905 #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
906 #define SGEN_MUTE_SW_CTL_SFT 6
907 #define SGEN_MUTE_SW_CTL_MASK 0x1
908 #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
909 #define R_AUD_SDM_MUTE_L_SFT 5
910 #define R_AUD_SDM_MUTE_L_MASK 0x1
911 #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
912 #define R_AUD_SDM_MUTE_R_SFT 4
913 #define R_AUD_SDM_MUTE_R_MASK 0x1
914 #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
915 #define R_AUD_SDM_MUTE_L_2ND_SFT 3
916 #define R_AUD_SDM_MUTE_L_2ND_MASK 0x1
917 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
918 #define R_AUD_SDM_MUTE_R_2ND_SFT 2
919 #define R_AUD_SDM_MUTE_R_2ND_MASK 0x1
920 #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT (0x1 << 2)
923 #define C_SGEN_RCH_INV_5BIT_SFT 15
924 #define C_SGEN_RCH_INV_5BIT_MASK 0x1
925 #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
926 #define C_SGEN_RCH_INV_8BIT_SFT 14
927 #define C_SGEN_RCH_INV_8BIT_MASK 0x1
928 #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
929 #define SGEN_FREQ_DIV_CH1_CTL_SFT 0
930 #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f
931 #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)
933 /* AFE_ADC_ASYNC_FIFO_CFG */
934 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5
935 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
936 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
937 #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4
938 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
939 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
940 #define RG_AMIC_UL_ADC_CLK_SEL_SFT 1
941 #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
942 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
944 /* AFE_ADC_ASYNC_FIFO_CFG1 */
945 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT 5
946 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
947 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
948 #define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT 4
949 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x1
950 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
953 #define DCCLK_DIV_SFT 5
954 #define DCCLK_DIV_MASK 0x7ff
955 #define DCCLK_DIV_MASK_SFT (0x7ff << 5)
956 #define DCCLK_INV_SFT 4
957 #define DCCLK_INV_MASK 0x1
958 #define DCCLK_INV_MASK_SFT (0x1 << 4)
959 #define DCCLK_REF_CK_SEL_SFT 2
960 #define DCCLK_REF_CK_SEL_MASK 0x3
961 #define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)
962 #define DCCLK_PDN_SFT 1
963 #define DCCLK_PDN_MASK 0x1
964 #define DCCLK_PDN_MASK_SFT (0x1 << 1)
965 #define DCCLK_GEN_ON_SFT 0
966 #define DCCLK_GEN_ON_MASK 0x1
967 #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
970 #define RESYNC_SRC_SEL_SFT 10
971 #define RESYNC_SRC_SEL_MASK 0x3
972 #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
973 #define RESYNC_SRC_CK_INV_SFT 9
974 #define RESYNC_SRC_CK_INV_MASK 0x1
975 #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
976 #define DCCLK_RESYNC_BYPASS_SFT 8
977 #define DCCLK_RESYNC_BYPASS_MASK 0x1
978 #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
979 #define DCCLK_PHASE_SEL_SFT 4
980 #define DCCLK_PHASE_SEL_MASK 0xf
981 #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)
984 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 15
985 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
986 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
987 #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 8
988 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f
989 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)
990 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7
991 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
992 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
993 #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0
994 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f
995 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)
998 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT 7
999 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1
1000 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7)
1001 #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT 0
1002 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7f
1003 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT (0x7f << 0)
1005 /* AFE_AUD_PAD_TOP */
1006 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 12
1007 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
1008 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
1009 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 11
1010 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
1011 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
1012 #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 8
1013 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
1014 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
1016 /* AFE_AUD_PAD_TOP_MON */
1017 #define ADDA_AUD_PAD_TOP_MON_SFT 0
1018 #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff
1019 #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
1021 /* AFE_AUD_PAD_TOP_MON1 */
1022 #define ADDA_AUD_PAD_TOP_MON1_SFT 0
1023 #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff
1024 #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)
1026 /* AFE_AUD_PAD_TOP_MON2 */
1027 #define ADDA_AUD_PAD_TOP_MON2_SFT 0
1028 #define ADDA_AUD_PAD_TOP_MON2_MASK 0xffff
1029 #define ADDA_AUD_PAD_TOP_MON2_MASK_SFT (0xffff << 0)
1031 /* AFE_DL_NLE_CFG */
1032 #define NLE_RCH_HPGAIN_SEL_SFT 10
1033 #define NLE_RCH_HPGAIN_SEL_MASK 0x1
1034 #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
1035 #define NLE_RCH_CH_SEL_SFT 9
1036 #define NLE_RCH_CH_SEL_MASK 0x1
1037 #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
1038 #define NLE_RCH_ON_SFT 8
1039 #define NLE_RCH_ON_MASK 0x1
1040 #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
1041 #define NLE_LCH_HPGAIN_SEL_SFT 2
1042 #define NLE_LCH_HPGAIN_SEL_MASK 0x1
1043 #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
1044 #define NLE_LCH_CH_SEL_SFT 1
1045 #define NLE_LCH_CH_SEL_MASK 0x1
1046 #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
1047 #define NLE_LCH_ON_SFT 0
1048 #define NLE_LCH_ON_MASK 0x1
1049 #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
1051 /* AFE_DL_NLE_MON */
1052 #define NLE_MONITOR_SFT 0
1053 #define NLE_MONITOR_MASK 0x3fff
1054 #define NLE_MONITOR_MASK_SFT (0x3fff << 0)
1057 #define CK_CG_EN_MON_SFT 0
1058 #define CK_CG_EN_MON_MASK 0x3f
1059 #define CK_CG_EN_MON_MASK_SFT (0x3f << 0)
1061 /* AFE_MIC_ARRAY_CFG */
1062 #define RG_AMIC_ADC1_SOURCE_SEL_SFT 10
1063 #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3
1064 #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)
1065 #define RG_AMIC_ADC2_SOURCE_SEL_SFT 8
1066 #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3
1067 #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)
1068 #define RG_AMIC_ADC3_SOURCE_SEL_SFT 6
1069 #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3
1070 #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)
1071 #define RG_DMIC_ADC1_SOURCE_SEL_SFT 4
1072 #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3
1073 #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)
1074 #define RG_DMIC_ADC2_SOURCE_SEL_SFT 2
1075 #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3
1076 #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)
1077 #define RG_DMIC_ADC3_SOURCE_SEL_SFT 0
1078 #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3
1079 #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)
1082 #define RG_CHOP_DIV_SEL_SFT 4
1083 #define RG_CHOP_DIV_SEL_MASK 0x1f
1084 #define RG_CHOP_DIV_SEL_MASK_SFT (0x1f << 4)
1085 #define RG_CHOP_DIV_EN_SFT 0
1086 #define RG_CHOP_DIV_EN_MASK 0x1
1087 #define RG_CHOP_DIV_EN_MASK_SFT (0x1 << 0)
1089 /* AFE_MTKAIF_MUX_CFG */
1090 #define RG_ADDA6_EN_SEL_SFT 12
1091 #define RG_ADDA6_EN_SEL_MASK 0x1
1092 #define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 12)
1093 #define RG_ADDA6_CH2_SEL_SFT 10
1094 #define RG_ADDA6_CH2_SEL_MASK 0x3
1095 #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)
1096 #define RG_ADDA6_CH1_SEL_SFT 8
1097 #define RG_ADDA6_CH1_SEL_MASK 0x3
1098 #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)
1099 #define RG_ADDA_EN_SEL_SFT 4
1100 #define RG_ADDA_EN_SEL_MASK 0x1
1101 #define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4)
1102 #define RG_ADDA_CH2_SEL_SFT 2
1103 #define RG_ADDA_CH2_SEL_MASK 0x3
1104 #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)
1105 #define RG_ADDA_CH1_SEL_SFT 0
1106 #define RG_ADDA_CH1_SEL_MASK 0x3
1107 #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)
1109 /* AFE_PMIC_NEWIF_CFG3 */
1110 #define RG_UP8X_SYNC_WORD_SFT 0
1111 #define RG_UP8X_SYNC_WORD_MASK 0xffff
1112 #define RG_UP8X_SYNC_WORD_MASK_SFT (0xffff << 0)
1115 #define RG_NCP_CK1_VALID_CNT_SFT 9
1116 #define RG_NCP_CK1_VALID_CNT_MASK 0x7f
1117 #define RG_NCP_CK1_VALID_CNT_MASK_SFT (0x7f << 9)
1118 #define RG_NCP_ADITH_SFT 8
1119 #define RG_NCP_ADITH_MASK 0x1
1120 #define RG_NCP_ADITH_MASK_SFT (0x1 << 8)
1121 #define RG_NCP_DITHER_EN_SFT 7
1122 #define RG_NCP_DITHER_EN_MASK 0x1
1123 #define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7)
1124 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT 4
1125 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x7
1126 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4)
1127 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT 1
1128 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x7
1129 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1)
1130 #define RG_NCP_ON_SFT 0
1131 #define RG_NCP_ON_MASK 0x1
1132 #define RG_NCP_ON_MASK_SFT (0x1 << 0)
1135 #define RG_XY_VAL_CFG_EN_SFT 15
1136 #define RG_XY_VAL_CFG_EN_MASK 0x1
1137 #define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 15)
1138 #define RG_X_VAL_CFG_SFT 8
1139 #define RG_X_VAL_CFG_MASK 0x7f
1140 #define RG_X_VAL_CFG_MASK_SFT (0x7f << 8)
1141 #define RG_Y_VAL_CFG_SFT 0
1142 #define RG_Y_VAL_CFG_MASK 0x7f
1143 #define RG_Y_VAL_CFG_MASK_SFT (0x7f << 0)
1146 #define RG_NCP_NONCLK_SET_SFT 1
1147 #define RG_NCP_NONCLK_SET_MASK 0x1
1148 #define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1)
1149 #define RG_NCP_PDDIS_EN_SFT 0
1150 #define RG_NCP_PDDIS_EN_MASK 0x1
1151 #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
1153 /* AUDENC_ANA_CON0 */
1154 #define RG_AUDPREAMPLON_SFT 0
1155 #define RG_AUDPREAMPLON_MASK 0x1
1156 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1157 #define RG_AUDPREAMPLDCCEN_SFT 1
1158 #define RG_AUDPREAMPLDCCEN_MASK 0x1
1159 #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
1160 #define RG_AUDPREAMPLDCPRECHARGE_SFT 2
1161 #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
1162 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
1163 #define RG_AUDPREAMPLPGATEST_SFT 3
1164 #define RG_AUDPREAMPLPGATEST_MASK 0x1
1165 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
1166 #define RG_AUDPREAMPLVSCALE_SFT 4
1167 #define RG_AUDPREAMPLVSCALE_MASK 0x3
1168 #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
1169 #define RG_AUDPREAMPLINPUTSEL_SFT 6
1170 #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
1171 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
1172 #define RG_AUDPREAMPLGAIN_SFT 8
1173 #define RG_AUDPREAMPLGAIN_MASK 0x7
1174 #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
1175 #define RG_BULKL_VCM_EN_SFT 11
1176 #define RG_BULKL_VCM_EN_MASK 0x1
1177 #define RG_BULKL_VCM_EN_MASK_SFT (0x1 << 11)
1178 #define RG_AUDADCLPWRUP_SFT 12
1179 #define RG_AUDADCLPWRUP_MASK 0x1
1180 #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
1181 #define RG_AUDADCLINPUTSEL_SFT 13
1182 #define RG_AUDADCLINPUTSEL_MASK 0x3
1183 #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
1185 /* AUDENC_ANA_CON1 */
1186 #define RG_AUDPREAMPRON_SFT 0
1187 #define RG_AUDPREAMPRON_MASK 0x1
1188 #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
1189 #define RG_AUDPREAMPRDCCEN_SFT 1
1190 #define RG_AUDPREAMPRDCCEN_MASK 0x1
1191 #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
1192 #define RG_AUDPREAMPRDCPRECHARGE_SFT 2
1193 #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
1194 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
1195 #define RG_AUDPREAMPRPGATEST_SFT 3
1196 #define RG_AUDPREAMPRPGATEST_MASK 0x1
1197 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
1198 #define RG_AUDPREAMPRVSCALE_SFT 4
1199 #define RG_AUDPREAMPRVSCALE_MASK 0x3
1200 #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
1201 #define RG_AUDPREAMPRINPUTSEL_SFT 6
1202 #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
1203 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
1204 #define RG_AUDPREAMPRGAIN_SFT 8
1205 #define RG_AUDPREAMPRGAIN_MASK 0x7
1206 #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
1207 #define RG_BULKR_VCM_EN_SFT 11
1208 #define RG_BULKR_VCM_EN_MASK 0x1
1209 #define RG_BULKR_VCM_EN_MASK_SFT (0x1 << 11)
1210 #define RG_AUDADCRPWRUP_SFT 12
1211 #define RG_AUDADCRPWRUP_MASK 0x1
1212 #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
1213 #define RG_AUDADCRINPUTSEL_SFT 13
1214 #define RG_AUDADCRINPUTSEL_MASK 0x3
1215 #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
1217 /* AUDENC_ANA_CON2 */
1218 #define RG_AUDPREAMP3ON_SFT 0
1219 #define RG_AUDPREAMP3ON_MASK 0x1
1220 #define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0)
1221 #define RG_AUDPREAMP3DCCEN_SFT 1
1222 #define RG_AUDPREAMP3DCCEN_MASK 0x1
1223 #define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1)
1224 #define RG_AUDPREAMP3DCPRECHARGE_SFT 2
1225 #define RG_AUDPREAMP3DCPRECHARGE_MASK 0x1
1226 #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2)
1227 #define RG_AUDPREAMP3PGATEST_SFT 3
1228 #define RG_AUDPREAMP3PGATEST_MASK 0x1
1229 #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
1230 #define RG_AUDPREAMP3VSCALE_SFT 4
1231 #define RG_AUDPREAMP3VSCALE_MASK 0x3
1232 #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)
1233 #define RG_AUDPREAMP3INPUTSEL_SFT 6
1234 #define RG_AUDPREAMP3INPUTSEL_MASK 0x3
1235 #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)
1236 #define RG_AUDPREAMP3GAIN_SFT 8
1237 #define RG_AUDPREAMP3GAIN_MASK 0x7
1238 #define RG_AUDPREAMP3GAIN_MASK_SFT (0x7 << 8)
1239 #define RG_BULK3_VCM_EN_SFT 11
1240 #define RG_BULK3_VCM_EN_MASK 0x1
1241 #define RG_BULK3_VCM_EN_MASK_SFT (0x1 << 11)
1242 #define RG_AUDADC3PWRUP_SFT 12
1243 #define RG_AUDADC3PWRUP_MASK 0x1
1244 #define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 12)
1245 #define RG_AUDADC3INPUTSEL_SFT 13
1246 #define RG_AUDADC3INPUTSEL_MASK 0x3
1247 #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)
1249 /* AUDENC_ANA_CON3 */
1250 #define RG_AUDULHALFBIAS_SFT 0
1251 #define RG_AUDULHALFBIAS_MASK 0x1
1252 #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
1253 #define RG_AUDGLBVOWLPWEN_SFT 1
1254 #define RG_AUDGLBVOWLPWEN_MASK 0x1
1255 #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
1256 #define RG_AUDPREAMPLPEN_SFT 2
1257 #define RG_AUDPREAMPLPEN_MASK 0x1
1258 #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
1259 #define RG_AUDADC1STSTAGELPEN_SFT 3
1260 #define RG_AUDADC1STSTAGELPEN_MASK 0x1
1261 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1262 #define RG_AUDADC2NDSTAGELPEN_SFT 4
1263 #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
1264 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
1265 #define RG_AUDADCFLASHLPEN_SFT 5
1266 #define RG_AUDADCFLASHLPEN_MASK 0x1
1267 #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
1268 #define RG_AUDPREAMPIDDTEST_SFT 6
1269 #define RG_AUDPREAMPIDDTEST_MASK 0x3
1270 #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
1271 #define RG_AUDADC1STSTAGEIDDTEST_SFT 8
1272 #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
1273 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
1274 #define RG_AUDADC2NDSTAGEIDDTEST_SFT 10
1275 #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
1276 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
1277 #define RG_AUDADCREFBUFIDDTEST_SFT 12
1278 #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
1279 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
1280 #define RG_AUDADCFLASHIDDTEST_SFT 14
1281 #define RG_AUDADCFLASHIDDTEST_MASK 0x3
1282 #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
1284 /* AUDENC_ANA_CON4 */
1285 #define RG_AUDRULHALFBIAS_SFT 0
1286 #define RG_AUDRULHALFBIAS_MASK 0x1
1287 #define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0)
1288 #define RG_AUDGLBRVOWLPWEN_SFT 1
1289 #define RG_AUDGLBRVOWLPWEN_MASK 0x1
1290 #define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1)
1291 #define RG_AUDRPREAMPLPEN_SFT 2
1292 #define RG_AUDRPREAMPLPEN_MASK 0x1
1293 #define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2)
1294 #define RG_AUDRADC1STSTAGELPEN_SFT 3
1295 #define RG_AUDRADC1STSTAGELPEN_MASK 0x1
1296 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1297 #define RG_AUDRADC2NDSTAGELPEN_SFT 4
1298 #define RG_AUDRADC2NDSTAGELPEN_MASK 0x1
1299 #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
1300 #define RG_AUDRADCFLASHLPEN_SFT 5
1301 #define RG_AUDRADCFLASHLPEN_MASK 0x1
1302 #define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5)
1303 #define RG_AUDRPREAMPIDDTEST_SFT 6
1304 #define RG_AUDRPREAMPIDDTEST_MASK 0x3
1305 #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)
1306 #define RG_AUDRADC1STSTAGEIDDTEST_SFT 8
1307 #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3
1308 #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
1309 #define RG_AUDRADC2NDSTAGEIDDTEST_SFT 10
1310 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3
1311 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
1312 #define RG_AUDRADCREFBUFIDDTEST_SFT 12
1313 #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3
1314 #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
1315 #define RG_AUDRADCFLASHIDDTEST_SFT 14
1316 #define RG_AUDRADCFLASHIDDTEST_MASK 0x3
1317 #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
1319 /* AUDENC_ANA_CON5 */
1320 #define RG_AUDADCCLKRSTB_SFT 0
1321 #define RG_AUDADCCLKRSTB_MASK 0x1
1322 #define RG_AUDADCCLKRSTB_MASK_SFT (0x1 << 0)
1323 #define RG_AUDADCCLKSEL_SFT 1
1324 #define RG_AUDADCCLKSEL_MASK 0x3
1325 #define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)
1326 #define RG_AUDADCCLKSOURCE_SFT 3
1327 #define RG_AUDADCCLKSOURCE_MASK 0x3
1328 #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)
1329 #define RG_AUDADCCLKGENMODE_SFT 5
1330 #define RG_AUDADCCLKGENMODE_MASK 0x3
1331 #define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)
1332 #define RG_AUDPREAMP_ACCFS_SFT 7
1333 #define RG_AUDPREAMP_ACCFS_MASK 0x1
1334 #define RG_AUDPREAMP_ACCFS_MASK_SFT (0x1 << 7)
1335 #define RG_AUDPREAMPAAFEN_SFT 8
1336 #define RG_AUDPREAMPAAFEN_MASK 0x1
1337 #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
1338 #define RG_DCCVCMBUFLPMODSEL_SFT 9
1339 #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
1340 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
1341 #define RG_DCCVCMBUFLPSWEN_SFT 10
1342 #define RG_DCCVCMBUFLPSWEN_MASK 0x1
1343 #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
1344 #define RG_AUDSPAREPGA_SFT 11
1345 #define RG_AUDSPAREPGA_MASK 0x1f
1346 #define RG_AUDSPAREPGA_MASK_SFT (0x1f << 11)
1348 /* AUDENC_ANA_CON6 */
1349 #define RG_AUDADC1STSTAGESDENB_SFT 0
1350 #define RG_AUDADC1STSTAGESDENB_MASK 0x1
1351 #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
1352 #define RG_AUDADC2NDSTAGERESET_SFT 1
1353 #define RG_AUDADC2NDSTAGERESET_MASK 0x1
1354 #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
1355 #define RG_AUDADC3RDSTAGERESET_SFT 2
1356 #define RG_AUDADC3RDSTAGERESET_MASK 0x1
1357 #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
1358 #define RG_AUDADCFSRESET_SFT 3
1359 #define RG_AUDADCFSRESET_MASK 0x1
1360 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
1361 #define RG_AUDADCWIDECM_SFT 4
1362 #define RG_AUDADCWIDECM_MASK 0x1
1363 #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
1364 #define RG_AUDADCNOPATEST_SFT 5
1365 #define RG_AUDADCNOPATEST_MASK 0x1
1366 #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
1367 #define RG_AUDADCBYPASS_SFT 6
1368 #define RG_AUDADCBYPASS_MASK 0x1
1369 #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
1370 #define RG_AUDADCFFBYPASS_SFT 7
1371 #define RG_AUDADCFFBYPASS_MASK 0x1
1372 #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
1373 #define RG_AUDADCDACFBCURRENT_SFT 8
1374 #define RG_AUDADCDACFBCURRENT_MASK 0x1
1375 #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
1376 #define RG_AUDADCDACIDDTEST_SFT 9
1377 #define RG_AUDADCDACIDDTEST_MASK 0x3
1378 #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
1379 #define RG_AUDADCDACNRZ_SFT 11
1380 #define RG_AUDADCDACNRZ_MASK 0x1
1381 #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
1382 #define RG_AUDADCNODEM_SFT 12
1383 #define RG_AUDADCNODEM_MASK 0x1
1384 #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
1385 #define RG_AUDADCDACTEST_SFT 13
1386 #define RG_AUDADCDACTEST_MASK 0x1
1387 #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
1388 #define RG_AUDADCDAC0P25FS_SFT 14
1389 #define RG_AUDADCDAC0P25FS_MASK 0x1
1390 #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 14)
1391 #define RG_AUDADCRDAC0P25FS_SFT 15
1392 #define RG_AUDADCRDAC0P25FS_MASK 0x1
1393 #define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 15)
1395 /* AUDENC_ANA_CON7 */
1396 #define RG_AUDADCTESTDATA_SFT 0
1397 #define RG_AUDADCTESTDATA_MASK 0xffff
1398 #define RG_AUDADCTESTDATA_MASK_SFT (0xffff << 0)
1400 /* AUDENC_ANA_CON8 */
1401 #define RG_AUDRCTUNEL_SFT 0
1402 #define RG_AUDRCTUNEL_MASK 0x1f
1403 #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)
1404 #define RG_AUDRCTUNELSEL_SFT 5
1405 #define RG_AUDRCTUNELSEL_MASK 0x1
1406 #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
1407 #define RG_AUDRCTUNER_SFT 8
1408 #define RG_AUDRCTUNER_MASK 0x1f
1409 #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)
1410 #define RG_AUDRCTUNERSEL_SFT 13
1411 #define RG_AUDRCTUNERSEL_MASK 0x1
1412 #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
1414 /* AUDENC_ANA_CON9 */
1415 #define RG_AUD3CTUNEL_SFT 0
1416 #define RG_AUD3CTUNEL_MASK 0x1f
1417 #define RG_AUD3CTUNEL_MASK_SFT (0x1f << 0)
1418 #define RG_AUD3CTUNELSEL_SFT 5
1419 #define RG_AUD3CTUNELSEL_MASK 0x1
1420 #define RG_AUD3CTUNELSEL_MASK_SFT (0x1 << 5)
1421 #define RGS_AUDRCTUNE3READ_SFT 6
1422 #define RGS_AUDRCTUNE3READ_MASK 0x1f
1423 #define RGS_AUDRCTUNE3READ_MASK_SFT (0x1f << 6)
1424 #define RG_AUD3SPARE_SFT 11
1425 #define RG_AUD3SPARE_MASK 0x1f
1426 #define RG_AUD3SPARE_MASK_SFT (0x1f << 11)
1428 /* AUDENC_ANA_CON10 */
1429 #define RGS_AUDRCTUNELREAD_SFT 0
1430 #define RGS_AUDRCTUNELREAD_MASK 0x1f
1431 #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)
1432 #define RGS_AUDRCTUNERREAD_SFT 8
1433 #define RGS_AUDRCTUNERREAD_MASK 0x1f
1434 #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)
1436 /* AUDENC_ANA_CON11 */
1437 #define RG_AUDSPAREVA30_SFT 0
1438 #define RG_AUDSPAREVA30_MASK 0xff
1439 #define RG_AUDSPAREVA30_MASK_SFT (0xff << 0)
1440 #define RG_AUDSPAREVA18_SFT 8
1441 #define RG_AUDSPAREVA18_MASK 0xff
1442 #define RG_AUDSPAREVA18_MASK_SFT (0xff << 8)
1444 /* AUDENC_ANA_CON12 */
1445 #define RG_AUDPGA_DECAP_SFT 0
1446 #define RG_AUDPGA_DECAP_MASK 0x1
1447 #define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0)
1448 #define RG_AUDPGA_CAPRA_SFT 1
1449 #define RG_AUDPGA_CAPRA_MASK 0x1
1450 #define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1)
1451 #define RG_AUDPGA_ACCCMP_SFT 2
1452 #define RG_AUDPGA_ACCCMP_MASK 0x1
1453 #define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2)
1454 #define RG_AUDENC_SPARE2_SFT 3
1455 #define RG_AUDENC_SPARE2_MASK 0x1fff
1456 #define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)
1458 /* AUDENC_ANA_CON13 */
1459 #define RG_AUDDIGMICEN_SFT 0
1460 #define RG_AUDDIGMICEN_MASK 0x1
1461 #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
1462 #define RG_AUDDIGMICBIAS_SFT 1
1463 #define RG_AUDDIGMICBIAS_MASK 0x3
1464 #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
1465 #define RG_DMICHPCLKEN_SFT 3
1466 #define RG_DMICHPCLKEN_MASK 0x1
1467 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
1468 #define RG_AUDDIGMICPDUTY_SFT 4
1469 #define RG_AUDDIGMICPDUTY_MASK 0x3
1470 #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
1471 #define RG_AUDDIGMICNDUTY_SFT 6
1472 #define RG_AUDDIGMICNDUTY_MASK 0x3
1473 #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
1474 #define RG_DMICMONEN_SFT 8
1475 #define RG_DMICMONEN_MASK 0x1
1476 #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
1477 #define RG_DMICMONSEL_SFT 9
1478 #define RG_DMICMONSEL_MASK 0x7
1479 #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
1481 /* AUDENC_ANA_CON14 */
1482 #define RG_AUDDIGMIC1EN_SFT 0
1483 #define RG_AUDDIGMIC1EN_MASK 0x1
1484 #define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0)
1485 #define RG_AUDDIGMICBIAS1_SFT 1
1486 #define RG_AUDDIGMICBIAS1_MASK 0x3
1487 #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)
1488 #define RG_DMIC1HPCLKEN_SFT 3
1489 #define RG_DMIC1HPCLKEN_MASK 0x1
1490 #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
1491 #define RG_AUDDIGMIC1PDUTY_SFT 4
1492 #define RG_AUDDIGMIC1PDUTY_MASK 0x3
1493 #define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)
1494 #define RG_AUDDIGMIC1NDUTY_SFT 6
1495 #define RG_AUDDIGMIC1NDUTY_MASK 0x3
1496 #define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)
1497 #define RG_DMIC1MONEN_SFT 8
1498 #define RG_DMIC1MONEN_MASK 0x1
1499 #define RG_DMIC1MONEN_MASK_SFT (0x1 << 8)
1500 #define RG_DMIC1MONSEL_SFT 9
1501 #define RG_DMIC1MONSEL_MASK 0x7
1502 #define RG_DMIC1MONSEL_MASK_SFT (0x7 << 9)
1503 #define RG_AUDSPAREVMIC_SFT 12
1504 #define RG_AUDSPAREVMIC_MASK 0xf
1505 #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)
1507 /* AUDENC_ANA_CON15 */
1508 #define RG_AUDPWDBMICBIAS0_SFT 0
1509 #define RG_AUDPWDBMICBIAS0_MASK 0x1
1510 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1511 #define RG_AUDMICBIAS0BYPASSEN_SFT 1
1512 #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
1513 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
1514 #define RG_AUDMICBIAS0LOWPEN_SFT 2
1515 #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
1516 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
1517 #define RG_AUDPWDBMICBIAS3_SFT 3
1518 #define RG_AUDPWDBMICBIAS3_MASK 0x1
1519 #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
1520 #define RG_AUDMICBIAS0VREF_SFT 4
1521 #define RG_AUDMICBIAS0VREF_MASK 0x7
1522 #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
1523 #define RG_AUDMICBIAS0DCSW0P1EN_SFT 8
1524 #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
1525 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
1526 #define RG_AUDMICBIAS0DCSW0P2EN_SFT 9
1527 #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
1528 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
1529 #define RG_AUDMICBIAS0DCSW0NEN_SFT 10
1530 #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
1531 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
1532 #define RG_AUDMICBIAS0DCSW2P1EN_SFT 12
1533 #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
1534 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
1535 #define RG_AUDMICBIAS0DCSW2P2EN_SFT 13
1536 #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
1537 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
1538 #define RG_AUDMICBIAS0DCSW2NEN_SFT 14
1539 #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
1540 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
1542 /* AUDENC_ANA_CON16 */
1543 #define RG_AUDPWDBMICBIAS1_SFT 0
1544 #define RG_AUDPWDBMICBIAS1_MASK 0x1
1545 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
1546 #define RG_AUDMICBIAS1BYPASSEN_SFT 1
1547 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
1548 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
1549 #define RG_AUDMICBIAS1LOWPEN_SFT 2
1550 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
1551 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
1552 #define RG_AUDMICBIAS1VREF_SFT 4
1553 #define RG_AUDMICBIAS1VREF_MASK 0x7
1554 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
1555 #define RG_AUDMICBIAS1DCSW1PEN_SFT 8
1556 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
1557 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
1558 #define RG_AUDMICBIAS1DCSW1NEN_SFT 9
1559 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
1560 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
1561 #define RG_BANDGAPGEN_SFT 10
1562 #define RG_BANDGAPGEN_MASK 0x1
1563 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
1564 #define RG_AUDMICBIAS1HVEN_SFT 12
1565 #define RG_AUDMICBIAS1HVEN_MASK 0x1
1566 #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
1567 #define RG_AUDMICBIAS1HVVREF_SFT 13
1568 #define RG_AUDMICBIAS1HVVREF_MASK 0x1
1569 #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
1571 /* AUDENC_ANA_CON17 */
1572 #define RG_AUDPWDBMICBIAS2_SFT 0
1573 #define RG_AUDPWDBMICBIAS2_MASK 0x1
1574 #define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0)
1575 #define RG_AUDMICBIAS2BYPASSEN_SFT 1
1576 #define RG_AUDMICBIAS2BYPASSEN_MASK 0x1
1577 #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1)
1578 #define RG_AUDMICBIAS2LOWPEN_SFT 2
1579 #define RG_AUDMICBIAS2LOWPEN_MASK 0x1
1580 #define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2)
1581 #define RG_AUDMICBIAS2VREF_SFT 4
1582 #define RG_AUDMICBIAS2VREF_MASK 0x7
1583 #define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4)
1584 #define RG_AUDMICBIAS2DCSW3P1EN_SFT 8
1585 #define RG_AUDMICBIAS2DCSW3P1EN_MASK 0x1
1586 #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT (0x1 << 8)
1587 #define RG_AUDMICBIAS2DCSW3P2EN_SFT 9
1588 #define RG_AUDMICBIAS2DCSW3P2EN_MASK 0x1
1589 #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT (0x1 << 9)
1590 #define RG_AUDMICBIAS2DCSW3NEN_SFT 10
1591 #define RG_AUDMICBIAS2DCSW3NEN_MASK 0x1
1592 #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT (0x1 << 10)
1593 #define RG_AUDMICBIASSPARE_SFT 12
1594 #define RG_AUDMICBIASSPARE_MASK 0xf
1595 #define RG_AUDMICBIASSPARE_MASK_SFT (0xf << 12)
1597 /* AUDENC_ANA_CON18 */
1598 #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
1599 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
1600 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
1601 #define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1
1602 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
1603 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
1604 #define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2
1605 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
1606 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
1607 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
1608 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
1609 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
1610 #define RG_AUDACCDETVTHACAL_SFT 4
1611 #define RG_AUDACCDETVTHACAL_MASK 0x1
1612 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
1613 #define RG_AUDACCDETVTHBCAL_SFT 5
1614 #define RG_AUDACCDETVTHBCAL_MASK 0x1
1615 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
1616 #define RG_AUDACCDETTVDET_SFT 6
1617 #define RG_AUDACCDETTVDET_MASK 0x1
1618 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
1619 #define RG_ACCDETSEL_SFT 7
1620 #define RG_ACCDETSEL_MASK 0x1
1621 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
1622 #define RG_SWBUFMODSEL_SFT 8
1623 #define RG_SWBUFMODSEL_MASK 0x1
1624 #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
1625 #define RG_SWBUFSWEN_SFT 9
1626 #define RG_SWBUFSWEN_MASK 0x1
1627 #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
1628 #define RG_EINT0NOHYS_SFT 10
1629 #define RG_EINT0NOHYS_MASK 0x1
1630 #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
1631 #define RG_EINT0CONFIGACCDET_SFT 11
1632 #define RG_EINT0CONFIGACCDET_MASK 0x1
1633 #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
1634 #define RG_EINT0HIRENB_SFT 12
1635 #define RG_EINT0HIRENB_MASK 0x1
1636 #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
1637 #define RG_ACCDET2AUXRESBYPASS_SFT 13
1638 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
1639 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
1640 #define RG_ACCDET2AUXSWEN_SFT 14
1641 #define RG_ACCDET2AUXSWEN_MASK 0x1
1642 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
1643 #define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15
1644 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
1645 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
1647 /* AUDENC_ANA_CON19 */
1648 #define RG_EINT1CONFIGACCDET_SFT 0
1649 #define RG_EINT1CONFIGACCDET_MASK 0x1
1650 #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
1651 #define RG_EINT1HIRENB_SFT 1
1652 #define RG_EINT1HIRENB_MASK 0x1
1653 #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
1654 #define RG_EINT1NOHYS_SFT 2
1655 #define RG_EINT1NOHYS_MASK 0x1
1656 #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
1657 #define RG_EINTCOMPVTH_SFT 4
1658 #define RG_EINTCOMPVTH_MASK 0xf
1659 #define RG_EINTCOMPVTH_MASK_SFT (0xf << 4)
1660 #define RG_MTEST_EN_SFT 8
1661 #define RG_MTEST_EN_MASK 0x1
1662 #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
1663 #define RG_MTEST_SEL_SFT 9
1664 #define RG_MTEST_SEL_MASK 0x1
1665 #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
1666 #define RG_MTEST_CURRENT_SFT 10
1667 #define RG_MTEST_CURRENT_MASK 0x1
1668 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
1669 #define RG_ANALOGFDEN_SFT 12
1670 #define RG_ANALOGFDEN_MASK 0x1
1671 #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
1672 #define RG_FDVIN1PPULLLOW_SFT 13
1673 #define RG_FDVIN1PPULLLOW_MASK 0x1
1674 #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
1675 #define RG_FDEINT0TYPE_SFT 14
1676 #define RG_FDEINT0TYPE_MASK 0x1
1677 #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
1678 #define RG_FDEINT1TYPE_SFT 15
1679 #define RG_FDEINT1TYPE_MASK 0x1
1680 #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
1682 /* AUDENC_ANA_CON20 */
1683 #define RG_EINT0CMPEN_SFT 0
1684 #define RG_EINT0CMPEN_MASK 0x1
1685 #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
1686 #define RG_EINT0CMPMEN_SFT 1
1687 #define RG_EINT0CMPMEN_MASK 0x1
1688 #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
1689 #define RG_EINT0EN_SFT 2
1690 #define RG_EINT0EN_MASK 0x1
1691 #define RG_EINT0EN_MASK_SFT (0x1 << 2)
1692 #define RG_EINT0CEN_SFT 3
1693 #define RG_EINT0CEN_MASK 0x1
1694 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
1695 #define RG_EINT0INVEN_SFT 4
1696 #define RG_EINT0INVEN_MASK 0x1
1697 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
1698 #define RG_EINT0CTURBO_SFT 5
1699 #define RG_EINT0CTURBO_MASK 0x7
1700 #define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
1701 #define RG_EINT1CMPEN_SFT 8
1702 #define RG_EINT1CMPEN_MASK 0x1
1703 #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
1704 #define RG_EINT1CMPMEN_SFT 9
1705 #define RG_EINT1CMPMEN_MASK 0x1
1706 #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
1707 #define RG_EINT1EN_SFT 10
1708 #define RG_EINT1EN_MASK 0x1
1709 #define RG_EINT1EN_MASK_SFT (0x1 << 10)
1710 #define RG_EINT1CEN_SFT 11
1711 #define RG_EINT1CEN_MASK 0x1
1712 #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
1713 #define RG_EINT1INVEN_SFT 12
1714 #define RG_EINT1INVEN_MASK 0x1
1715 #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
1716 #define RG_EINT1CTURBO_SFT 13
1717 #define RG_EINT1CTURBO_MASK 0x7
1718 #define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
1720 /* AUDENC_ANA_CON21 */
1721 #define RG_ACCDETSPARE_SFT 0
1722 #define RG_ACCDETSPARE_MASK 0xffff
1723 #define RG_ACCDETSPARE_MASK_SFT (0xffff << 0)
1725 /* AUDENC_ANA_CON22 */
1726 #define RG_AUDENCSPAREVA30_SFT 0
1727 #define RG_AUDENCSPAREVA30_MASK 0xff
1728 #define RG_AUDENCSPAREVA30_MASK_SFT (0xff << 0)
1729 #define RG_AUDENCSPAREVA18_SFT 8
1730 #define RG_AUDENCSPAREVA18_MASK 0xff
1731 #define RG_AUDENCSPAREVA18_MASK_SFT (0xff << 8)
1733 /* AUDENC_ANA_CON23 */
1734 #define RG_CLKSQ_EN_SFT 0
1735 #define RG_CLKSQ_EN_MASK 0x1
1736 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1737 #define RG_CLKSQ_IN_SEL_TEST_SFT 1
1738 #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
1739 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
1740 #define RG_CM_REFGENSEL_SFT 2
1741 #define RG_CM_REFGENSEL_MASK 0x1
1742 #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
1743 #define RG_AUDIO_VOW_EN_SFT 3
1744 #define RG_AUDIO_VOW_EN_MASK 0x1
1745 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
1746 #define RG_CLKSQ_EN_VOW_SFT 4
1747 #define RG_CLKSQ_EN_VOW_MASK 0x1
1748 #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 4)
1749 #define RG_CLKAND_EN_VOW_SFT 5
1750 #define RG_CLKAND_EN_VOW_MASK 0x1
1751 #define RG_CLKAND_EN_VOW_MASK_SFT (0x1 << 5)
1752 #define RG_VOWCLK_SEL_EN_VOW_SFT 6
1753 #define RG_VOWCLK_SEL_EN_VOW_MASK 0x1
1754 #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT (0x1 << 6)
1755 #define RG_SPARE_VOW_SFT 7
1756 #define RG_SPARE_VOW_MASK 0x7
1757 #define RG_SPARE_VOW_MASK_SFT (0x7 << 7)
1759 /* AUDDEC_ANA_CON0 */
1760 #define RG_AUDDACLPWRUP_VAUDP32_SFT 0
1761 #define RG_AUDDACLPWRUP_VAUDP32_MASK 0x1
1762 #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
1763 #define RG_AUDDACRPWRUP_VAUDP32_SFT 1
1764 #define RG_AUDDACRPWRUP_VAUDP32_MASK 0x1
1765 #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
1766 #define RG_AUD_DAC_PWR_UP_VA32_SFT 2
1767 #define RG_AUD_DAC_PWR_UP_VA32_MASK 0x1
1768 #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT (0x1 << 2)
1769 #define RG_AUD_DAC_PWL_UP_VA32_SFT 3
1770 #define RG_AUD_DAC_PWL_UP_VA32_MASK 0x1
1771 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
1772 #define RG_AUDHPLPWRUP_VAUDP32_SFT 4
1773 #define RG_AUDHPLPWRUP_VAUDP32_MASK 0x1
1774 #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT (0x1 << 4)
1775 #define RG_AUDHPRPWRUP_VAUDP32_SFT 5
1776 #define RG_AUDHPRPWRUP_VAUDP32_MASK 0x1
1777 #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT (0x1 << 5)
1778 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_SFT 6
1779 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK 0x1
1780 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 6)
1781 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_SFT 7
1782 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK 0x1
1783 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 7)
1784 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT 8
1785 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x3
1786 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)
1787 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT 10
1788 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x3
1789 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)
1790 #define RG_AUDHPLSCDISABLE_VAUDP32_SFT 12
1791 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK 0x1
1792 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 12)
1793 #define RG_AUDHPRSCDISABLE_VAUDP32_SFT 13
1794 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK 0x1
1795 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT (0x1 << 13)
1796 #define RG_AUDHPLBSCCURRENT_VAUDP32_SFT 14
1797 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK 0x1
1798 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 14)
1799 #define RG_AUDHPRBSCCURRENT_VAUDP32_SFT 15
1800 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK 0x1
1801 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 15)
1803 /* AUDDEC_ANA_CON1 */
1804 #define RG_AUDHPLOUTPWRUP_VAUDP32_SFT 0
1805 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK 0x1
1806 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
1807 #define RG_AUDHPROUTPWRUP_VAUDP32_SFT 1
1808 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK 0x1
1809 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
1810 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_SFT 2
1811 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK 0x1
1812 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 2)
1813 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT 3
1814 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK 0x1
1815 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
1816 #define RG_HPLAUXFBRSW_EN_VAUDP32_SFT 4
1817 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK 0x1
1818 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 4)
1819 #define RG_HPRAUXFBRSW_EN_VAUDP32_SFT 5
1820 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK 0x1
1821 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 5)
1822 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_SFT 6
1823 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK 0x1
1824 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT (0x1 << 6)
1825 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_SFT 7
1826 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK 0x1
1827 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT (0x1 << 7)
1828 #define RG_HPLOUTSTGCTRL_VAUDP32_SFT 8
1829 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK 0x7
1830 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 8)
1831 #define RG_HPROUTSTGCTRL_VAUDP32_SFT 12
1832 #define RG_HPROUTSTGCTRL_VAUDP32_MASK 0x7
1833 #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 12)
1835 /* AUDDEC_ANA_CON2 */
1836 #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0
1837 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
1838 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
1839 #define RG_HPROUTPUTSTBENH_VAUDP32_SFT 4
1840 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
1841 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
1842 #define RG_AUDHPSTARTUP_VAUDP32_SFT 7
1843 #define RG_AUDHPSTARTUP_VAUDP32_MASK 0x1
1844 #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT (0x1 << 7)
1845 #define RG_AUDREFN_DERES_EN_VAUDP32_SFT 8
1846 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK 0x1
1847 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT (0x1 << 8)
1848 #define RG_HPINPUTSTBENH_VAUDP32_SFT 9
1849 #define RG_HPINPUTSTBENH_VAUDP32_MASK 0x1
1850 #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 9)
1851 #define RG_HPINPUTRESET0_VAUDP32_SFT 10
1852 #define RG_HPINPUTRESET0_VAUDP32_MASK 0x1
1853 #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
1854 #define RG_HPOUTPUTRESET0_VAUDP32_SFT 11
1855 #define RG_HPOUTPUTRESET0_VAUDP32_MASK 0x1
1856 #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 11)
1857 #define RG_HPPSHORT2VCM_VAUDP32_SFT 12
1858 #define RG_HPPSHORT2VCM_VAUDP32_MASK 0x7
1859 #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT (0x7 << 12)
1860 #define RG_AUDHPTRIM_EN_VAUDP32_SFT 15
1861 #define RG_AUDHPTRIM_EN_VAUDP32_MASK 0x1
1862 #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT (0x1 << 15)
1864 /* AUDDEC_ANA_CON3 */
1865 #define RG_AUDHPLTRIM_VAUDP32_SFT 0
1866 #define RG_AUDHPLTRIM_VAUDP32_MASK 0x1f
1867 #define RG_AUDHPLTRIM_VAUDP32_MASK_SFT (0x1f << 0)
1868 #define RG_AUDHPLFINETRIM_VAUDP32_SFT 5
1869 #define RG_AUDHPLFINETRIM_VAUDP32_MASK 0x7
1870 #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT (0x7 << 5)
1871 #define RG_AUDHPRTRIM_VAUDP32_SFT 8
1872 #define RG_AUDHPRTRIM_VAUDP32_MASK 0x1f
1873 #define RG_AUDHPRTRIM_VAUDP32_MASK_SFT (0x1f << 8)
1874 #define RG_AUDHPRFINETRIM_VAUDP32_SFT 13
1875 #define RG_AUDHPRFINETRIM_VAUDP32_MASK 0x7
1876 #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT (0x7 << 13)
1878 /* AUDDEC_ANA_CON4 */
1879 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT 0
1880 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK 0x7
1881 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT (0x7 << 0)
1882 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_SFT 4
1883 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK 0x7
1884 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 4)
1885 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_SFT 8
1886 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK 0x7
1887 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 8)
1888 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT 12
1889 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x3
1890 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)
1891 #define RG_AUDHPCOMP_EN_VAUDP32_SFT 15
1892 #define RG_AUDHPCOMP_EN_VAUDP32_MASK 0x1
1893 #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT (0x1 << 15)
1895 /* AUDDEC_ANA_CON5 */
1896 #define RG_AUDHPDECMGAINADJ_VAUDP32_SFT 0
1897 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK 0x7
1898 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT (0x7 << 0)
1899 #define RG_AUDHPDEDMGAINADJ_VAUDP32_SFT 4
1900 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK 0x7
1901 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT (0x7 << 4)
1903 /* AUDDEC_ANA_CON6 */
1904 #define RG_AUDHSPWRUP_VAUDP32_SFT 0
1905 #define RG_AUDHSPWRUP_VAUDP32_MASK 0x1
1906 #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
1907 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_SFT 1
1908 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK 0x1
1909 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
1910 #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT 2
1911 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x3
1912 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
1913 #define RG_AUDHSSCDISABLE_VAUDP32_SFT 4
1914 #define RG_AUDHSSCDISABLE_VAUDP32_MASK 0x1
1915 #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
1916 #define RG_AUDHSBSCCURRENT_VAUDP32_SFT 5
1917 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK 0x1
1918 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
1919 #define RG_AUDHSSTARTUP_VAUDP32_SFT 6
1920 #define RG_AUDHSSTARTUP_VAUDP32_MASK 0x1
1921 #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
1922 #define RG_HSOUTPUTSTBENH_VAUDP32_SFT 7
1923 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK 0x1
1924 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
1925 #define RG_HSINPUTSTBENH_VAUDP32_SFT 8
1926 #define RG_HSINPUTSTBENH_VAUDP32_MASK 0x1
1927 #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
1928 #define RG_HSINPUTRESET0_VAUDP32_SFT 9
1929 #define RG_HSINPUTRESET0_VAUDP32_MASK 0x1
1930 #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
1931 #define RG_HSOUTPUTRESET0_VAUDP32_SFT 10
1932 #define RG_HSOUTPUTRESET0_VAUDP32_MASK 0x1
1933 #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
1934 #define RG_HSOUT_SHORTVCM_VAUDP32_SFT 11
1935 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK 0x1
1936 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
1938 /* AUDDEC_ANA_CON7 */
1939 #define RG_AUDLOLPWRUP_VAUDP32_SFT 0
1940 #define RG_AUDLOLPWRUP_VAUDP32_MASK 0x1
1941 #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
1942 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_SFT 1
1943 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK 0x1
1944 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
1945 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT 2
1946 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x3
1947 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
1948 #define RG_AUDLOLSCDISABLE_VAUDP32_SFT 4
1949 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK 0x1
1950 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
1951 #define RG_AUDLOLBSCCURRENT_VAUDP32_SFT 5
1952 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK 0x1
1953 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
1954 #define RG_AUDLOSTARTUP_VAUDP32_SFT 6
1955 #define RG_AUDLOSTARTUP_VAUDP32_MASK 0x1
1956 #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
1957 #define RG_LOINPUTSTBENH_VAUDP32_SFT 7
1958 #define RG_LOINPUTSTBENH_VAUDP32_MASK 0x1
1959 #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
1960 #define RG_LOOUTPUTSTBENH_VAUDP32_SFT 8
1961 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK 0x1
1962 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
1963 #define RG_LOINPUTRESET0_VAUDP32_SFT 9
1964 #define RG_LOINPUTRESET0_VAUDP32_MASK 0x1
1965 #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
1966 #define RG_LOOUTPUTRESET0_VAUDP32_SFT 10
1967 #define RG_LOOUTPUTRESET0_VAUDP32_MASK 0x1
1968 #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
1969 #define RG_LOOUT_SHORTVCM_VAUDP32_SFT 11
1970 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK 0x1
1971 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
1972 #define RG_AUDDACTPWRUP_VAUDP32_SFT 12
1973 #define RG_AUDDACTPWRUP_VAUDP32_MASK 0x1
1974 #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT (0x1 << 12)
1975 #define RG_AUD_DAC_PWT_UP_VA32_SFT 13
1976 #define RG_AUD_DAC_PWT_UP_VA32_MASK 0x1
1977 #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT (0x1 << 13)
1979 /* AUDDEC_ANA_CON8 */
1980 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT 0
1981 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK 0xf
1982 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT (0xf << 0)
1983 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_SFT 4
1984 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x3
1985 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)
1986 #define RG_AUDTRIMBUF_EN_VAUDP32_SFT 6
1987 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK 0x1
1988 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT (0x1 << 6)
1989 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SFT 8
1990 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x3
1991 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)
1992 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SFT 10
1993 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x3
1994 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)
1995 #define RG_AUDHPSPKDET_EN_VAUDP32_SFT 12
1996 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK 0x1
1997 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT (0x1 << 12)
1999 /* AUDDEC_ANA_CON9 */
2000 #define RG_ABIDEC_RSVD0_VA32_SFT 0
2001 #define RG_ABIDEC_RSVD0_VA32_MASK 0xff
2002 #define RG_ABIDEC_RSVD0_VA32_MASK_SFT (0xff << 0)
2003 #define RG_ABIDEC_RSVD0_VAUDP32_SFT 8
2004 #define RG_ABIDEC_RSVD0_VAUDP32_MASK 0xff
2005 #define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT (0xff << 8)
2007 /* AUDDEC_ANA_CON10 */
2008 #define RG_ABIDEC_RSVD1_VAUDP32_SFT 0
2009 #define RG_ABIDEC_RSVD1_VAUDP32_MASK 0xff
2010 #define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT (0xff << 0)
2011 #define RG_ABIDEC_RSVD2_VAUDP32_SFT 8
2012 #define RG_ABIDEC_RSVD2_VAUDP32_MASK 0xff
2013 #define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT (0xff << 8)
2015 /* AUDDEC_ANA_CON11 */
2016 #define RG_AUDZCDMUXSEL_VAUDP32_SFT 0
2017 #define RG_AUDZCDMUXSEL_VAUDP32_MASK 0x7
2018 #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT (0x7 << 0)
2019 #define RG_AUDZCDCLKSEL_VAUDP32_SFT 3
2020 #define RG_AUDZCDCLKSEL_VAUDP32_MASK 0x1
2021 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
2022 #define RG_AUDBIASADJ_0_VAUDP32_SFT 7
2023 #define RG_AUDBIASADJ_0_VAUDP32_MASK 0x1ff
2024 #define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT (0x1ff << 7)
2026 /* AUDDEC_ANA_CON12 */
2027 #define RG_AUDBIASADJ_1_VAUDP32_SFT 0
2028 #define RG_AUDBIASADJ_1_VAUDP32_MASK 0xff
2029 #define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT (0xff << 0)
2030 #define RG_AUDIBIASPWRDN_VAUDP32_SFT 8
2031 #define RG_AUDIBIASPWRDN_VAUDP32_MASK 0x1
2032 #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT (0x1 << 8)
2034 /* AUDDEC_ANA_CON13 */
2035 #define RG_RSTB_DECODER_VA32_SFT 0
2036 #define RG_RSTB_DECODER_VA32_MASK 0x1
2037 #define RG_RSTB_DECODER_VA32_MASK_SFT (0x1 << 0)
2038 #define RG_SEL_DECODER_96K_VA32_SFT 1
2039 #define RG_SEL_DECODER_96K_VA32_MASK 0x1
2040 #define RG_SEL_DECODER_96K_VA32_MASK_SFT (0x1 << 1)
2041 #define RG_SEL_DELAY_VCORE_SFT 2
2042 #define RG_SEL_DELAY_VCORE_MASK 0x1
2043 #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
2044 #define RG_AUDGLB_PWRDN_VA32_SFT 4
2045 #define RG_AUDGLB_PWRDN_VA32_MASK 0x1
2046 #define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4)
2047 #define RG_AUDGLB_LP_VOW_EN_VA32_SFT 5
2048 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK 0x1
2049 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT (0x1 << 5)
2050 #define RG_AUDGLB_LP2_VOW_EN_VA32_SFT 6
2051 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK 0x1
2052 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT (0x1 << 6)
2054 /* AUDDEC_ANA_CON14 */
2055 #define RG_LCLDO_DEC_EN_VA32_SFT 0
2056 #define RG_LCLDO_DEC_EN_VA32_MASK 0x1
2057 #define RG_LCLDO_DEC_EN_VA32_MASK_SFT (0x1 << 0)
2058 #define RG_LCLDO_DEC_PDDIS_EN_VA18_SFT 1
2059 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK 0x1
2060 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
2061 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT 2
2062 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK 0x1
2063 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
2064 #define RG_NVREG_EN_VAUDP32_SFT 4
2065 #define RG_NVREG_EN_VAUDP32_MASK 0x1
2066 #define RG_NVREG_EN_VAUDP32_MASK_SFT (0x1 << 4)
2067 #define RG_NVREG_PULL0V_VAUDP32_SFT 5
2068 #define RG_NVREG_PULL0V_VAUDP32_MASK 0x1
2069 #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT (0x1 << 5)
2070 #define RG_AUDPMU_RSVD_VA18_SFT 8
2071 #define RG_AUDPMU_RSVD_VA18_MASK 0xff
2072 #define RG_AUDPMU_RSVD_VA18_MASK_SFT (0xff << 8)
2074 /* MT6359_ZCD_CON0 */
2075 #define RG_AUDZCDENABLE_SFT 0
2076 #define RG_AUDZCDENABLE_MASK 0x1
2077 #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
2078 #define RG_AUDZCDGAINSTEPTIME_SFT 1
2079 #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
2080 #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
2081 #define RG_AUDZCDGAINSTEPSIZE_SFT 4
2082 #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
2083 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
2084 #define RG_AUDZCDTIMEOUTMODESEL_SFT 6
2085 #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
2086 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)
2088 /* MT6359_ZCD_CON1 */
2089 #define RG_AUDLOLGAIN_SFT 0
2090 #define RG_AUDLOLGAIN_MASK 0x1f
2091 #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)
2092 #define RG_AUDLORGAIN_SFT 7
2093 #define RG_AUDLORGAIN_MASK 0x1f
2094 #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)
2096 /* MT6359_ZCD_CON2 */
2097 #define RG_AUDHPLGAIN_SFT 0
2098 #define RG_AUDHPLGAIN_MASK 0x1f
2099 #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)
2100 #define RG_AUDHPRGAIN_SFT 7
2101 #define RG_AUDHPRGAIN_MASK 0x1f
2102 #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)
2104 /* MT6359_ZCD_CON3 */
2105 #define RG_AUDHSGAIN_SFT 0
2106 #define RG_AUDHSGAIN_MASK 0x1f
2107 #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)
2109 /* MT6359_ZCD_CON4 */
2110 #define RG_AUDIVLGAIN_SFT 0
2111 #define RG_AUDIVLGAIN_MASK 0x7
2112 #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
2113 #define RG_AUDIVRGAIN_SFT 8
2114 #define RG_AUDIVRGAIN_MASK 0x7
2115 #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
2117 /* MT6359_ZCD_CON5 */
2118 #define RG_AUDINTGAIN1_SFT 0
2119 #define RG_AUDINTGAIN1_MASK 0x3f
2120 #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)
2121 #define RG_AUDINTGAIN2_SFT 8
2122 #define RG_AUDINTGAIN2_MASK 0x3f
2123 #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)
2125 /* audio register */
2126 #define MT6359_GPIO_DIR0 0x88
2127 #define MT6359_GPIO_DIR0_SET 0x8a
2128 #define MT6359_GPIO_DIR0_CLR 0x8c
2129 #define MT6359_GPIO_DIR1 0x8e
2130 #define MT6359_GPIO_DIR1_SET 0x90
2131 #define MT6359_GPIO_DIR1_CLR 0x92
2133 #define MT6359_DCXO_CW11 0x7a6
2134 #define MT6359_DCXO_CW12 0x7a8
2135 #define MT6359_LDO_VAUD18_CON0 0x1c98
2137 #define MT6359_GPIO_MODE0 0xcc
2138 #define MT6359_GPIO_MODE0_SET 0xce
2139 #define MT6359_GPIO_MODE0_CLR 0xd0
2140 #define MT6359_GPIO_MODE1 0xd2
2141 #define MT6359_GPIO_MODE1_SET 0xd4
2142 #define MT6359_GPIO_MODE1_CLR 0xd6
2143 #define MT6359_GPIO_MODE2 0xd8
2144 #define MT6359_GPIO_MODE2_SET 0xda
2145 #define MT6359_GPIO_MODE2_CLR 0xdc
2146 #define MT6359_GPIO_MODE3 0xde
2147 #define MT6359_GPIO_MODE3_SET 0xe0
2148 #define MT6359_GPIO_MODE3_CLR 0xe2
2149 #define MT6359_GPIO_MODE4 0xe4
2150 #define MT6359_GPIO_MODE4_SET 0xe6
2151 #define MT6359_GPIO_MODE4_CLR 0xe8
2153 #define MT6359_AUD_TOP_ID 0x2300
2154 #define MT6359_AUD_TOP_REV0 0x2302
2155 #define MT6359_AUD_TOP_DBI 0x2304
2156 #define MT6359_AUD_TOP_DXI 0x2306
2157 #define MT6359_AUD_TOP_CKPDN_TPM0 0x2308
2158 #define MT6359_AUD_TOP_CKPDN_TPM1 0x230a
2159 #define MT6359_AUD_TOP_CKPDN_CON0 0x230c
2160 #define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e
2161 #define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310
2162 #define MT6359_AUD_TOP_CKSEL_CON0 0x2312
2163 #define MT6359_AUD_TOP_CKSEL_CON0_SET 0x2314
2164 #define MT6359_AUD_TOP_CKSEL_CON0_CLR 0x2316
2165 #define MT6359_AUD_TOP_CKTST_CON0 0x2318
2166 #define MT6359_AUD_TOP_CLK_HWEN_CON0 0x231a
2167 #define MT6359_AUD_TOP_CLK_HWEN_CON0_SET 0x231c
2168 #define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR 0x231e
2169 #define MT6359_AUD_TOP_RST_CON0 0x2320
2170 #define MT6359_AUD_TOP_RST_CON0_SET 0x2322
2171 #define MT6359_AUD_TOP_RST_CON0_CLR 0x2324
2172 #define MT6359_AUD_TOP_RST_BANK_CON0 0x2326
2173 #define MT6359_AUD_TOP_INT_CON0 0x2328
2174 #define MT6359_AUD_TOP_INT_CON0_SET 0x232a
2175 #define MT6359_AUD_TOP_INT_CON0_CLR 0x232c
2176 #define MT6359_AUD_TOP_INT_MASK_CON0 0x232e
2177 #define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330
2178 #define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332
2179 #define MT6359_AUD_TOP_INT_STATUS0 0x2334
2180 #define MT6359_AUD_TOP_INT_RAW_STATUS0 0x2336
2181 #define MT6359_AUD_TOP_INT_MISC_CON0 0x2338
2182 #define MT6359_AUD_TOP_MON_CON0 0x233a
2183 #define MT6359_AUDIO_DIG_DSN_ID 0x2380
2184 #define MT6359_AUDIO_DIG_DSN_REV0 0x2382
2185 #define MT6359_AUDIO_DIG_DSN_DBI 0x2384
2186 #define MT6359_AUDIO_DIG_DSN_DXI 0x2386
2187 #define MT6359_AFE_UL_DL_CON0 0x2388
2188 #define MT6359_AFE_DL_SRC2_CON0_L 0x238a
2189 #define MT6359_AFE_UL_SRC_CON0_H 0x238c
2190 #define MT6359_AFE_UL_SRC_CON0_L 0x238e
2191 #define MT6359_AFE_ADDA6_L_SRC_CON0_H 0x2390
2192 #define MT6359_AFE_ADDA6_UL_SRC_CON0_L 0x2392
2193 #define MT6359_AFE_TOP_CON0 0x2394
2194 #define MT6359_AUDIO_TOP_CON0 0x2396
2195 #define MT6359_AFE_MON_DEBUG0 0x2398
2196 #define MT6359_AFUNC_AUD_CON0 0x239a
2197 #define MT6359_AFUNC_AUD_CON1 0x239c
2198 #define MT6359_AFUNC_AUD_CON2 0x239e
2199 #define MT6359_AFUNC_AUD_CON3 0x23a0
2200 #define MT6359_AFUNC_AUD_CON4 0x23a2
2201 #define MT6359_AFUNC_AUD_CON5 0x23a4
2202 #define MT6359_AFUNC_AUD_CON6 0x23a6
2203 #define MT6359_AFUNC_AUD_CON7 0x23a8
2204 #define MT6359_AFUNC_AUD_CON8 0x23aa
2205 #define MT6359_AFUNC_AUD_CON9 0x23ac
2206 #define MT6359_AFUNC_AUD_CON10 0x23ae
2207 #define MT6359_AFUNC_AUD_CON11 0x23b0
2208 #define MT6359_AFUNC_AUD_CON12 0x23b2
2209 #define MT6359_AFUNC_AUD_MON0 0x23b4
2210 #define MT6359_AFUNC_AUD_MON1 0x23b6
2211 #define MT6359_AUDRC_TUNE_MON0 0x23b8
2212 #define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0 0x23ba
2213 #define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x23bc
2214 #define MT6359_AFE_ADDA_MTKAIF_MON0 0x23be
2215 #define MT6359_AFE_ADDA_MTKAIF_MON1 0x23c0
2216 #define MT6359_AFE_ADDA_MTKAIF_MON2 0x23c2
2217 #define MT6359_AFE_ADDA6_MTKAIF_MON3 0x23c4
2218 #define MT6359_AFE_ADDA_MTKAIF_MON4 0x23c6
2219 #define MT6359_AFE_ADDA_MTKAIF_MON5 0x23c8
2220 #define MT6359_AFE_ADDA_MTKAIF_CFG0 0x23ca
2221 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG0 0x23cc
2222 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG1 0x23ce
2223 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG2 0x23d0
2224 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG3 0x23d2
2225 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0 0x23d4
2226 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1 0x23d6
2227 #define MT6359_AFE_SGEN_CFG0 0x23d8
2228 #define MT6359_AFE_SGEN_CFG1 0x23da
2229 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG 0x23dc
2230 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG1 0x23de
2231 #define MT6359_AFE_DCCLK_CFG0 0x23e0
2232 #define MT6359_AFE_DCCLK_CFG1 0x23e2
2233 #define MT6359_AUDIO_DIG_CFG 0x23e4
2234 #define MT6359_AUDIO_DIG_CFG1 0x23e6
2235 #define MT6359_AFE_AUD_PAD_TOP 0x23e8
2236 #define MT6359_AFE_AUD_PAD_TOP_MON 0x23ea
2237 #define MT6359_AFE_AUD_PAD_TOP_MON1 0x23ec
2238 #define MT6359_AFE_AUD_PAD_TOP_MON2 0x23ee
2239 #define MT6359_AFE_DL_NLE_CFG 0x23f0
2240 #define MT6359_AFE_DL_NLE_MON 0x23f2
2241 #define MT6359_AFE_CG_EN_MON 0x23f4
2242 #define MT6359_AFE_MIC_ARRAY_CFG 0x23f6
2243 #define MT6359_AFE_CHOP_CFG0 0x23f8
2244 #define MT6359_AFE_MTKAIF_MUX_CFG 0x23fa
2245 #define MT6359_AUDIO_DIG_2ND_DSN_ID 0x2400
2246 #define MT6359_AUDIO_DIG_2ND_DSN_REV0 0x2402
2247 #define MT6359_AUDIO_DIG_2ND_DSN_DBI 0x2404
2248 #define MT6359_AUDIO_DIG_2ND_DSN_DXI 0x2406
2249 #define MT6359_AFE_PMIC_NEWIF_CFG3 0x2408
2250 #define MT6359_AUDIO_DIG_3RD_DSN_ID 0x2480
2251 #define MT6359_AUDIO_DIG_3RD_DSN_REV0 0x2482
2252 #define MT6359_AUDIO_DIG_3RD_DSN_DBI 0x2484
2253 #define MT6359_AUDIO_DIG_3RD_DSN_DXI 0x2486
2254 #define MT6359_AFE_NCP_CFG0 0x24de
2255 #define MT6359_AFE_NCP_CFG1 0x24e0
2256 #define MT6359_AFE_NCP_CFG2 0x24e2
2257 #define MT6359_AUDENC_DSN_ID 0x2500
2258 #define MT6359_AUDENC_DSN_REV0 0x2502
2259 #define MT6359_AUDENC_DSN_DBI 0x2504
2260 #define MT6359_AUDENC_DSN_FPI 0x2506
2261 #define MT6359_AUDENC_ANA_CON0 0x2508
2262 #define MT6359_AUDENC_ANA_CON1 0x250a
2263 #define MT6359_AUDENC_ANA_CON2 0x250c
2264 #define MT6359_AUDENC_ANA_CON3 0x250e
2265 #define MT6359_AUDENC_ANA_CON4 0x2510
2266 #define MT6359_AUDENC_ANA_CON5 0x2512
2267 #define MT6359_AUDENC_ANA_CON6 0x2514
2268 #define MT6359_AUDENC_ANA_CON7 0x2516
2269 #define MT6359_AUDENC_ANA_CON8 0x2518
2270 #define MT6359_AUDENC_ANA_CON9 0x251a
2271 #define MT6359_AUDENC_ANA_CON10 0x251c
2272 #define MT6359_AUDENC_ANA_CON11 0x251e
2273 #define MT6359_AUDENC_ANA_CON12 0x2520
2274 #define MT6359_AUDENC_ANA_CON13 0x2522
2275 #define MT6359_AUDENC_ANA_CON14 0x2524
2276 #define MT6359_AUDENC_ANA_CON15 0x2526
2277 #define MT6359_AUDENC_ANA_CON16 0x2528
2278 #define MT6359_AUDENC_ANA_CON17 0x252a
2279 #define MT6359_AUDENC_ANA_CON18 0x252c
2280 #define MT6359_AUDENC_ANA_CON19 0x252e
2281 #define MT6359_AUDENC_ANA_CON20 0x2530
2282 #define MT6359_AUDENC_ANA_CON21 0x2532
2283 #define MT6359_AUDENC_ANA_CON22 0x2534
2284 #define MT6359_AUDENC_ANA_CON23 0x2536
2285 #define MT6359_AUDDEC_DSN_ID 0x2580
2286 #define MT6359_AUDDEC_DSN_REV0 0x2582
2287 #define MT6359_AUDDEC_DSN_DBI 0x2584
2288 #define MT6359_AUDDEC_DSN_FPI 0x2586
2289 #define MT6359_AUDDEC_ANA_CON0 0x2588
2290 #define MT6359_AUDDEC_ANA_CON1 0x258a
2291 #define MT6359_AUDDEC_ANA_CON2 0x258c
2292 #define MT6359_AUDDEC_ANA_CON3 0x258e
2293 #define MT6359_AUDDEC_ANA_CON4 0x2590
2294 #define MT6359_AUDDEC_ANA_CON5 0x2592
2295 #define MT6359_AUDDEC_ANA_CON6 0x2594
2296 #define MT6359_AUDDEC_ANA_CON7 0x2596
2297 #define MT6359_AUDDEC_ANA_CON8 0x2598
2298 #define MT6359_AUDDEC_ANA_CON9 0x259a
2299 #define MT6359_AUDDEC_ANA_CON10 0x259c
2300 #define MT6359_AUDDEC_ANA_CON11 0x259e
2301 #define MT6359_AUDDEC_ANA_CON12 0x25a0
2302 #define MT6359_AUDDEC_ANA_CON13 0x25a2
2303 #define MT6359_AUDDEC_ANA_CON14 0x25a4
2304 #define MT6359_AUDZCD_DSN_ID 0x2600
2305 #define MT6359_AUDZCD_DSN_REV0 0x2602
2306 #define MT6359_AUDZCD_DSN_DBI 0x2604
2307 #define MT6359_AUDZCD_DSN_FPI 0x2606
2308 #define MT6359_ZCD_CON0 0x2608
2309 #define MT6359_ZCD_CON1 0x260a
2310 #define MT6359_ZCD_CON2 0x260c
2311 #define MT6359_ZCD_CON3 0x260e
2312 #define MT6359_ZCD_CON4 0x2610
2313 #define MT6359_ZCD_CON5 0x2612
2314 #define MT6359_ACCDET_DSN_DIG_ID 0x2680
2315 #define MT6359_ACCDET_DSN_DIG_REV0 0x2682
2316 #define MT6359_ACCDET_DSN_DBI 0x2684
2317 #define MT6359_ACCDET_DSN_FPI 0x2686
2318 #define MT6359_ACCDET_CON0 0x2688
2319 #define MT6359_ACCDET_CON1 0x268a
2320 #define MT6359_ACCDET_CON2 0x268c
2321 #define MT6359_ACCDET_CON3 0x268e
2322 #define MT6359_ACCDET_CON4 0x2690
2323 #define MT6359_ACCDET_CON5 0x2692
2324 #define MT6359_ACCDET_CON6 0x2694
2325 #define MT6359_ACCDET_CON7 0x2696
2326 #define MT6359_ACCDET_CON8 0x2698
2327 #define MT6359_ACCDET_CON9 0x269a
2328 #define MT6359_ACCDET_CON10 0x269c
2329 #define MT6359_ACCDET_CON11 0x269e
2330 #define MT6359_ACCDET_CON12 0x26a0
2331 #define MT6359_ACCDET_CON13 0x26a2
2332 #define MT6359_ACCDET_CON14 0x26a4
2333 #define MT6359_ACCDET_CON15 0x26a6
2334 #define MT6359_ACCDET_CON16 0x26a8
2335 #define MT6359_ACCDET_CON17 0x26aa
2336 #define MT6359_ACCDET_CON18 0x26ac
2337 #define MT6359_ACCDET_CON19 0x26ae
2338 #define MT6359_ACCDET_CON20 0x26b0
2339 #define MT6359_ACCDET_CON21 0x26b2
2340 #define MT6359_ACCDET_CON22 0x26b4
2341 #define MT6359_ACCDET_CON23 0x26b6
2342 #define MT6359_ACCDET_CON24 0x26b8
2343 #define MT6359_ACCDET_CON25 0x26ba
2344 #define MT6359_ACCDET_CON26 0x26bc
2345 #define MT6359_ACCDET_CON27 0x26be
2346 #define MT6359_ACCDET_CON28 0x26c0
2347 #define MT6359_ACCDET_CON29 0x26c2
2348 #define MT6359_ACCDET_CON30 0x26c4
2349 #define MT6359_ACCDET_CON31 0x26c6
2350 #define MT6359_ACCDET_CON32 0x26c8
2351 #define MT6359_ACCDET_CON33 0x26ca
2352 #define MT6359_ACCDET_CON34 0x26cc
2353 #define MT6359_ACCDET_CON35 0x26ce
2354 #define MT6359_ACCDET_CON36 0x26d0
2355 #define MT6359_ACCDET_CON37 0x26d2
2356 #define MT6359_ACCDET_CON38 0x26d4
2357 #define MT6359_ACCDET_CON39 0x26d6
2358 #define MT6359_ACCDET_CON40 0x26d8
2359 #define MT6359_MAX_REGISTER MT6359_ZCD_CON5
2362 #define DRBIAS_MASK 0x7
2363 #define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
2364 #define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)
2365 #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
2366 #define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)
2367 #define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)
2368 #define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)
2369 #define IBIAS_MASK 0x3
2370 #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
2371 #define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)
2372 #define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)
2373 #define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)
2374 #define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)
2375 #define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)
2376 #define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)
2377 #define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)
2380 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
2381 #define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)
2382 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
2383 #define DL_GAIN_REG_MASK 0x0f9f
2386 #define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
2387 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
2388 .info = snd_soc_info_enum_double, \
2389 .get = xhandler_get, .put = xhandler_put, \
2390 .private_value = (unsigned long)&(xenum) }
2393 MT6359_MTKAIF_PROTOCOL_1 = 0,
2394 MT6359_MTKAIF_PROTOCOL_2,
2395 MT6359_MTKAIF_PROTOCOL_2_CLK_P2,
2399 MT6359_AIF_1 = 0, /* dl: hp, rcv, hp+lo */
2400 MT6359_AIF_2, /* dl: lo only */
2405 AUDIO_ANALOG_VOLUME_HSOUTL,
2406 AUDIO_ANALOG_VOLUME_HSOUTR,
2407 AUDIO_ANALOG_VOLUME_HPOUTL,
2408 AUDIO_ANALOG_VOLUME_HPOUTR,
2409 AUDIO_ANALOG_VOLUME_LINEOUTL,
2410 AUDIO_ANALOG_VOLUME_LINEOUTR,
2411 AUDIO_ANALOG_VOLUME_MICAMP1,
2412 AUDIO_ANALOG_VOLUME_MICAMP2,
2413 AUDIO_ANALOG_VOLUME_MICAMP3,
2414 AUDIO_ANALOG_VOLUME_TYPE_MAX
2418 MUX_MIC_TYPE_0, /* ain0, micbias 0 */
2419 MUX_MIC_TYPE_1, /* ain1, micbias 1 */
2420 MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */
2438 HP_GAIN_CTL_ZCD = 0,
2448 HP_MUX_HP_IMPEDANCE,
2455 RCV_MUX_VOICE_PLAYBACK,
2468 /* Supply widget subseq */
2472 SUPPLY_SEQ_LDO_VAUD18,
2474 SUPPLY_SEQ_HP_PULL_DOWN,
2476 SUPPLY_SEQ_ADC_CLKGEN,
2478 SUPPLY_SEQ_TOP_CK_LAST,
2480 SUPPLY_SEQ_MIC_BIAS,
2483 SUPPLY_SEQ_AUD_TOP_LAST,
2484 SUPPLY_SEQ_DL_SDM_FIFO_CLK,
2490 SUPPLY_SEQ_DL_ESD_RESIST,
2491 SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
2493 SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
2496 SUPPLY_SEQ_HP_ANA_TRIM,
2497 SUPPLY_SEQ_DL_IBIST,
2501 SUPPLY_SEQ_UL_MTKAIF,
2502 SUPPLY_SEQ_UL_SRC_DMIC,
2553 DL_GAIN_N_10DB = 18,
2554 DL_GAIN_N_22DB = 30,
2555 DL_GAIN_N_40DB = 0x1f,
2560 MIC_TYPE_MUX_IDLE = 0,
2564 MIC_TYPE_MUX_DCC_ECM_DIFF,
2565 MIC_TYPE_MUX_DCC_ECM_SINGLE,
2570 UL_SRC_MUX_AMIC = 0,
2576 MISO_MUX_UL1_CH1 = 0,
2584 DMIC_MUX_DMIC_DATA0 = 0,
2585 DMIC_MUX_DMIC_DATA1_L,
2586 DMIC_MUX_DMIC_DATA1_L_1,
2587 DMIC_MUX_DMIC_DATA1_R,
2594 ADC_MUX_PREAMPLIFIER,
2620 struct mt6359_priv {
2622 struct regmap *regmap;
2623 unsigned int dl_rate[MT6359_AIF_NUM];
2624 unsigned int ul_rate[MT6359_AIF_NUM];
2625 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
2626 unsigned int mux_select[MUX_NUM];
2627 unsigned int dmic_one_wire_mode;
2628 int dev_counter[DEVICE_NUM];
2631 int mtkaif_protocol;
2632 struct regulator *avdd_reg;
2635 #define CODEC_MT6359_NAME "mtk-codec-mt6359"
2636 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
2637 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
2638 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
2640 #endif/* end _MT6359_H_ */