sound/soc/codecs/msm8916-wcd-analog.c

   1 #include <linux/module.h>
   2 #include <linux/err.h>
   3 #include <linux/kernel.h>
   4 #include <linux/delay.h>
   5 #include <linux/regulator/consumer.h>
   6 #include <linux/types.h>
   7 #include <linux/clk.h>
   8 #include <linux/of.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/regmap.h>
  11 #include <sound/soc.h>
  12 #include <sound/pcm.h>
  13 #include <sound/pcm_params.h>
  14 #include <sound/tlv.h>
  15 #include <sound/jack.h>
  16
  17 #define CDC_D_REVISION1                 (0xf000)
  18 #define CDC_D_PERPH_SUBTYPE             (0xf005)
  19 #define CDC_D_INT_EN_SET                (0xf015)
  20 #define CDC_D_INT_EN_CLR                (0xf016)
  21 #define MBHC_SWITCH_INT                 BIT(7)
  22 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
  23 #define MBHC_BUTTON_PRESS_DET           BIT(5)
  24 #define MBHC_BUTTON_RELEASE_DET         BIT(4)
  25 #define CDC_D_CDC_RST_CTL               (0xf046)
  26 #define RST_CTL_DIG_SW_RST_N_MASK       BIT(7)
  27 #define RST_CTL_DIG_SW_RST_N_RESET      0
  28 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
  29
  30 #define CDC_D_CDC_TOP_CLK_CTL           (0xf048)
  31 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
  32 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE     BIT(2)
  33 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE   BIT(3)
  34
  35 #define CDC_D_CDC_ANA_CLK_CTL           (0xf049)
  36 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
  37 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN     BIT(0)
  38 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN     BIT(1)
  39 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK    BIT(4)
  40 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
  41 #define ANA_CLK_CTL_TXA_CLK25_EN        BIT(5)
  42
  43 #define CDC_D_CDC_DIG_CLK_CTL           (0xf04A)
  44 #define DIG_CLK_CTL_RXD1_CLK_EN         BIT(0)
  45 #define DIG_CLK_CTL_RXD2_CLK_EN         BIT(1)
  46 #define DIG_CLK_CTL_RXD3_CLK_EN         BIT(2)
  47 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK  BIT(3)
  48 #define DIG_CLK_CTL_D_MBHC_CLK_EN       BIT(3)
  49 #define DIG_CLK_CTL_TXD_CLK_EN          BIT(4)
  50 #define DIG_CLK_CTL_NCP_CLK_EN_MASK     BIT(6)
  51 #define DIG_CLK_CTL_NCP_CLK_EN          BIT(6)
  52 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
  53 #define DIG_CLK_CTL_RXD_PDM_CLK_EN      BIT(7)
  54
  55 #define CDC_D_CDC_CONN_TX1_CTL          (0xf050)
  56 #define CONN_TX1_SERIAL_TX1_MUX         GENMASK(1, 0)
  57 #define CONN_TX1_SERIAL_TX1_ADC_1       0x0
  58 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB   0x1
  59 #define CONN_TX1_SERIAL_TX1_ZERO        0x2
  60
  61 #define CDC_D_CDC_CONN_TX2_CTL          (0xf051)
  62 #define CONN_TX2_SERIAL_TX2_MUX         GENMASK(1, 0)
  63 #define CONN_TX2_SERIAL_TX2_ADC_2       0x0
  64 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB   0x1
  65 #define CONN_TX2_SERIAL_TX2_ZERO        0x2
  66 #define CDC_D_CDC_CONN_HPHR_DAC_CTL     (0xf052)
  67 #define CDC_D_CDC_CONN_RX1_CTL          (0xf053)
  68 #define CDC_D_CDC_CONN_RX2_CTL          (0xf054)
  69 #define CDC_D_CDC_CONN_RX3_CTL          (0xf055)
  70 #define CDC_D_CDC_CONN_RX_LB_CTL        (0xf056)
  71 #define CDC_D_SEC_ACCESS                (0xf0D0)
  72 #define CDC_D_PERPH_RESET_CTL3          (0xf0DA)
  73 #define CDC_D_PERPH_RESET_CTL4          (0xf0DB)
  74 #define CDC_A_REVISION1                 (0xf100)
  75 #define CDC_A_REVISION2                 (0xf101)
  76 #define CDC_A_REVISION3                 (0xf102)
  77 #define CDC_A_REVISION4                 (0xf103)
  78 #define CDC_A_PERPH_TYPE                (0xf104)
  79 #define CDC_A_PERPH_SUBTYPE             (0xf105)
  80 #define CDC_A_INT_RT_STS                (0xf110)
  81 #define CDC_A_INT_SET_TYPE              (0xf111)
  82 #define CDC_A_INT_POLARITY_HIGH         (0xf112)
  83 #define CDC_A_INT_POLARITY_LOW          (0xf113)
  84 #define CDC_A_INT_LATCHED_CLR           (0xf114)
  85 #define CDC_A_INT_EN_SET                (0xf115)
  86 #define CDC_A_INT_EN_CLR                (0xf116)
  87 #define CDC_A_INT_LATCHED_STS           (0xf118)
  88 #define CDC_A_INT_PENDING_STS           (0xf119)
  89 #define CDC_A_INT_MID_SEL               (0xf11A)
  90 #define CDC_A_INT_PRIORITY              (0xf11B)
  91 #define CDC_A_MICB_1_EN                 (0xf140)
  92 #define MICB_1_EN_MICB_ENABLE           BIT(7)
  93 #define MICB_1_EN_BYP_CAP_MASK          BIT(6)
  94 #define MICB_1_EN_NO_EXT_BYP_CAP        BIT(6)
  95 #define MICB_1_EN_EXT_BYP_CAP           0
  96 #define MICB_1_EN_PULL_DOWN_EN_MASK     BIT(5)
  97 #define MICB_1_EN_PULL_DOWN_EN_ENABLE   BIT(5)
  98 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
  99 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA     (0x4)
 100 #define MICB_1_EN_PULL_UP_EN_MASK       BIT(4)
 101 #define MICB_1_EN_TX3_GND_SEL_MASK      BIT(0)
 102 #define MICB_1_EN_TX3_GND_SEL_TX_GND    0
 103
 104 #define CDC_A_MICB_1_VAL                (0xf141)
 105 #define MICB_MIN_VAL 1600
 106 #define MICB_STEP_SIZE 50
 107 #define MICB_VOLTAGE_REGVAL(v)          (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
 108 #define MICB_1_VAL_MICB_OUT_VAL_MASK    GENMASK(7, 3)
 109 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V  ((0x16)  << 3)
 110 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V  ((0x4)  << 3)
 111 #define CDC_A_MICB_1_CTL                (0xf142)
 112
 113 #define MICB_1_CTL_CFILT_REF_SEL_MASK           BIT(1)
 114 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF        BIT(1)
 115 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK         BIT(5)
 116 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE       BIT(5)
 117 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK        BIT(6)
 118 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL     BIT(6)
 119
 120 #define CDC_A_MICB_1_INT_RBIAS                  (0xf143)
 121 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK        BIT(7)
 122 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE      BIT(7)
 123 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE     0
 124
 125 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK       BIT(6)
 126 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
 127 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND        0
 128
 129 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK        BIT(4)
 130 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE      BIT(4)
 131 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE     0
 132 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK       BIT(3)
 133 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
 134 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND        0
 135
 136 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK        BIT(1)
 137 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE      BIT(1)
 138 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE     0
 139 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK       BIT(0)
 140 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
 141 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND        0
 142
 143 #define CDC_A_MICB_2_EN                 (0xf144)
 144 #define CDC_A_MICB_2_EN_ENABLE          BIT(7)
 145 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK  BIT(5)
 146 #define CDC_A_MICB_2_PULL_DOWN_EN       BIT(5)
 147 #define CDC_A_TX_1_2_ATEST_CTL_2        (0xf145)
 148 #define CDC_A_MASTER_BIAS_CTL           (0xf146)
 149 #define CDC_A_MBHC_DET_CTL_1            (0xf147)
 150 #define CDC_A_MBHC_DET_CTL_L_DET_EN                     BIT(7)
 151 #define CDC_A_MBHC_DET_CTL_GND_DET_EN                   BIT(6)
 152 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION      BIT(5)
 153 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL        (0)
 154 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK           BIT(5)
 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT          (5)
 156 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO           BIT(4)
 157 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL         BIT(3)
 158 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK           GENMASK(4, 3)
 159 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN                 BIT(2)
 160 #define CDC_A_MBHC_DET_CTL_2            (0xf150)
 161 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0  (BIT(7) | BIT(6))
 162 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
 163 #define CDC_A_PLUG_TYPE_MASK                            GENMASK(4, 3)
 164 #define CDC_A_HPHL_PLUG_TYPE_NO                         BIT(4)
 165 #define CDC_A_GND_PLUG_TYPE_NO                          BIT(3)
 166 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK     BIT(0)
 167 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN          BIT(0)
 168 #define CDC_A_MBHC_FSM_CTL              (0xf151)
 169 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN                  BIT(7)
 170 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK             BIT(7)
 171 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA        (0x3 << 4)
 172 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK           GENMASK(6, 4)
 173 #define CDC_A_MBHC_DBNC_TIMER           (0xf152)
 174 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS           BIT(3)
 175 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS      (0x9 << 4)
 176 #define CDC_A_MBHC_BTN0_ZDET_CTL_0      (0xf153)
 177 #define CDC_A_MBHC_BTN1_ZDET_CTL_1      (0xf154)
 178 #define CDC_A_MBHC_BTN2_ZDET_CTL_2      (0xf155)
 179 #define CDC_A_MBHC_BTN3_CTL             (0xf156)
 180 #define CDC_A_MBHC_BTN4_CTL             (0xf157)
 181 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT  (2)
 182 #define CDC_A_MBHC_BTN_VREF_FINE_MASK   GENMASK(4, 2)
 183 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
 184 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
 185 #define CDC_A_MBHC_BTN_VREF_MASK        (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
 186                                         CDC_A_MBHC_BTN_VREF_FINE_MASK)
 187 #define CDC_A_MBHC_RESULT_1             (0xf158)
 188 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK     GENMASK(4, 0)
 189 #define CDC_A_TX_1_EN                   (0xf160)
 190 #define CDC_A_TX_2_EN                   (0xf161)
 191 #define CDC_A_TX_1_2_TEST_CTL_1         (0xf162)
 192 #define CDC_A_TX_1_2_TEST_CTL_2         (0xf163)
 193 #define CDC_A_TX_1_2_ATEST_CTL          (0xf164)
 194 #define CDC_A_TX_1_2_OPAMP_BIAS         (0xf165)
 195 #define CDC_A_TX_3_EN                   (0xf167)
 196 #define CDC_A_NCP_EN                    (0xf180)
 197 #define CDC_A_NCP_CLK                   (0xf181)
 198 #define CDC_A_NCP_FBCTRL                (0xf183)
 199 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK        BIT(5)
 200 #define CDC_A_NCP_FBCTRL_FB_CLK_INV             BIT(5)
 201 #define CDC_A_NCP_BIAS                  (0xf184)
 202 #define CDC_A_NCP_VCTRL                 (0xf185)
 203 #define CDC_A_NCP_TEST                  (0xf186)
 204 #define CDC_A_NCP_CLIM_ADDR             (0xf187)
 205 #define CDC_A_RX_CLOCK_DIVIDER          (0xf190)
 206 #define CDC_A_RX_COM_OCP_CTL            (0xf191)
 207 #define CDC_A_RX_COM_OCP_COUNT          (0xf192)
 208 #define CDC_A_RX_COM_BIAS_DAC           (0xf193)
 209 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK         BIT(7)
 210 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE       BIT(7)
 211 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK         BIT(0)
 212 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE       BIT(0)
 213
 214 #define CDC_A_RX_HPH_BIAS_PA            (0xf194)
 215 #define CDC_A_RX_HPH_BIAS_LDO_OCP       (0xf195)
 216 #define CDC_A_RX_HPH_BIAS_CNP           (0xf196)
 217 #define CDC_A_RX_HPH_CNP_EN             (0xf197)
 218 #define CDC_A_RX_HPH_L_PA_DAC_CTL       (0xf19B)
 219 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK     BIT(1)
 220 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET    BIT(1)
 221 #define CDC_A_RX_HPH_R_PA_DAC_CTL       (0xf19D)
 222 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET  BIT(1)
 223 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
 224
 225 #define CDC_A_RX_EAR_CTL                        (0xf19E)
 226 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK         BIT(0)
 227 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE       BIT(0)
 228
 229 #define CDC_A_SPKR_DAC_CTL              (0xf1B0)
 230 #define SPKR_DAC_CTL_DAC_RESET_MASK     BIT(4)
 231 #define SPKR_DAC_CTL_DAC_RESET_NORMAL   0
 232
 233 #define CDC_A_SPKR_DRV_CTL              (0xf1B2)
 234 #define SPKR_DRV_CTL_DEF_MASK           0xEF
 235 #define SPKR_DRV_CLASSD_PA_EN_MASK      BIT(7)
 236 #define SPKR_DRV_CLASSD_PA_EN_ENABLE    BIT(7)
 237 #define SPKR_DRV_CAL_EN                 BIT(6)
 238 #define SPKR_DRV_SETTLE_EN              BIT(5)
 239 #define SPKR_DRV_FW_EN                  BIT(3)
 240 #define SPKR_DRV_BOOST_SET              BIT(2)
 241 #define SPKR_DRV_CMFB_SET               BIT(1)
 242 #define SPKR_DRV_GAIN_SET               BIT(0)
 243 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
 244                 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
 245                 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
 246                 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
 247 #define CDC_A_SPKR_OCP_CTL              (0xf1B4)
 248 #define CDC_A_SPKR_PWRSTG_CTL           (0xf1B5)
 249 #define SPKR_PWRSTG_CTL_DAC_EN_MASK     BIT(0)
 250 #define SPKR_PWRSTG_CTL_DAC_EN          BIT(0)
 251 #define SPKR_PWRSTG_CTL_MASK            0xE0
 252 #define SPKR_PWRSTG_CTL_BBM_MASK        BIT(7)
 253 #define SPKR_PWRSTG_CTL_BBM_EN          BIT(7)
 254 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK  BIT(6)
 255 #define SPKR_PWRSTG_CTL_HBRDGE_EN       BIT(6)
 256 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK   BIT(5)
 257 #define SPKR_PWRSTG_CTL_CLAMP_EN        BIT(5)
 258
 259 #define CDC_A_SPKR_DRV_DBG              (0xf1B7)
 260 #define CDC_A_CURRENT_LIMIT             (0xf1C0)
 261 #define CDC_A_BOOST_EN_CTL              (0xf1C3)
 262 #define CDC_A_SLOPE_COMP_IP_ZERO        (0xf1C4)
 263 #define CDC_A_SEC_ACCESS                (0xf1D0)
 264 #define CDC_A_PERPH_RESET_CTL3          (0xf1DA)
 265 #define CDC_A_PERPH_RESET_CTL4          (0xf1DB)
 266
 267 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 268                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
 269 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 270                                     SNDRV_PCM_FMTBIT_S32_LE)
 271
 272 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 273                SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
 274 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
 275
 276 static const char * const supply_names[] = {
 277         "vdd-cdc-io",
 278         "vdd-cdc-tx-rx-cx",
 279 };
 280
 281 #define MBHC_MAX_BUTTONS        (5)
 282
 283 struct pm8916_wcd_analog_priv {
 284         u16 pmic_rev;
 285         u16 codec_version;
 286         bool    mbhc_btn_enabled;
 287         /* special event to detect accessory type */
 288         bool    mbhc_btn0_pressed;
 289         bool    detect_accessory_type;
 290         struct clk *mclk;
 291         struct snd_soc_codec *codec;
 292         struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
 293         struct snd_soc_jack *jack;
 294         bool hphl_jack_type_normally_open;
 295         bool gnd_jack_type_normally_open;
 296         /* Voltage threshold when internal current source of 100uA is used */
 297         u32 vref_btn_cs[MBHC_MAX_BUTTONS];
 298         /* Voltage threshold when microphone bias is ON */
 299         u32 vref_btn_micb[MBHC_MAX_BUTTONS];
 300         unsigned int micbias1_cap_mode;
 301         unsigned int micbias2_cap_mode;
 302         unsigned int micbias_mv;
 303 };
 304
 305 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
 306 static const char *const rdac2_mux_text[] = { "RX1", "RX2" };
 307 static const char *const hph_text[] = { "ZERO", "Switch", };
 308
 309 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
 310                                         ARRAY_SIZE(hph_text), hph_text);
 311
 312 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
 313 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
 314
 315 /* ADC2 MUX */
 316 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
 317                         ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
 318
 319 /* RDAC2 MUX */
 320 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
 321                         CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
 322
 323 static const struct snd_kcontrol_new spkr_switch[] = {
 324         SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
 325 };
 326
 327 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
 328                                         "RDAC2 MUX Mux", rdac2_mux_enum);
 329 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
 330                                         "ADC2 MUX Mux", adc2_enum);
 331
 332 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
 333 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
 334
 335 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
 336         SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
 337         SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
 338         SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
 339 };
 340
 341 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_codec *codec)
 342 {
 343         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 344
 345         snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
 346                             MICB_1_CTL_EXT_PRECHARG_EN_MASK |
 347                             MICB_1_CTL_INT_PRECHARG_BYP_MASK,
 348                             MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
 349                             | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
 350
 351         if (wcd->micbias_mv) {
 352                 snd_soc_update_bits(codec, CDC_A_MICB_1_VAL,
 353                                     MICB_1_VAL_MICB_OUT_VAL_MASK,
 354                                     MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
 355                 /*
 356                  * Special headset needs MICBIAS as 2.7V so wait for
 357                  * 50 msec for the MICBIAS to reach 2.7 volts.
 358                  */
 359                 if (wcd->micbias_mv >= 2700)
 360                         msleep(50);
 361         }
 362
 363         snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
 364                             MICB_1_CTL_EXT_PRECHARG_EN_MASK |
 365                             MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
 366
 367 }
 368
 369 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_codec
 370                                                  *codec, int event,
 371                                                  int reg, unsigned int cap_mode)
 372 {
 373         switch (event) {
 374         case SND_SOC_DAPM_POST_PMU:
 375                 pm8916_wcd_analog_micbias_enable(codec);
 376                 snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
 377                                     MICB_1_EN_BYP_CAP_MASK, cap_mode);
 378                 break;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_codec
 385                                                  *codec, int event,
 386                                                  int reg, u32 cap_mode)
 387 {
 388
 389         switch (event) {
 390         case SND_SOC_DAPM_PRE_PMU:
 391                 snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS,
 392                                     MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
 393                                     MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
 394                 snd_soc_update_bits(codec, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0);
 395                 snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
 396                                     MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
 397                                     MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
 398
 399                 break;
 400         case SND_SOC_DAPM_POST_PMU:
 401                 pm8916_wcd_analog_micbias_enable(codec);
 402                 snd_soc_update_bits(codec, CDC_A_MICB_1_EN,
 403                                     MICB_1_EN_BYP_CAP_MASK, cap_mode);
 404                 break;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int pm8916_wcd_analog_enable_micbias_ext1(struct
 411                                                   snd_soc_dapm_widget
 412                                                   *w, struct snd_kcontrol
 413                                                   *kcontrol, int event)
 414 {
 415         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 416         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 417
 418         return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg,
 419                                                      wcd->micbias1_cap_mode);
 420 }
 421
 422 static int pm8916_wcd_analog_enable_micbias_ext2(struct
 423                                                   snd_soc_dapm_widget
 424                                                   *w, struct snd_kcontrol
 425                                                   *kcontrol, int event)
 426 {
 427         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 428         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 429
 430         return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg,
 431                                                      wcd->micbias2_cap_mode);
 432
 433 }
 434
 435 static int pm8916_wcd_analog_enable_micbias_int1(struct
 436                                                   snd_soc_dapm_widget
 437                                                   *w, struct snd_kcontrol
 438                                                   *kcontrol, int event)
 439 {
 440         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 441         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 442
 443         return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg,
 444                                                      wcd->micbias1_cap_mode);
 445 }
 446
 447 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
 448 {
 449         struct snd_soc_codec *codec = wcd->codec;
 450         u32 plug_type = 0;
 451         u32 int_en_mask;
 452
 453         snd_soc_write(codec, CDC_A_MBHC_DET_CTL_1,
 454                       CDC_A_MBHC_DET_CTL_L_DET_EN |
 455                       CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
 456                       CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
 457                       CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
 458
 459         if (wcd->hphl_jack_type_normally_open)
 460                 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
 461
 462         if (wcd->gnd_jack_type_normally_open)
 463                 plug_type |= CDC_A_GND_PLUG_TYPE_NO;
 464
 465         snd_soc_write(codec, CDC_A_MBHC_DET_CTL_2,
 466                       CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
 467                       CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
 468                       plug_type |
 469                       CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
 470
 471
 472         snd_soc_write(codec, CDC_A_MBHC_DBNC_TIMER,
 473                       CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
 474                       CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
 475
 476         /* enable MBHC clock */
 477         snd_soc_update_bits(codec, CDC_D_CDC_DIG_CLK_CTL,
 478                             DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
 479                             DIG_CLK_CTL_D_MBHC_CLK_EN);
 480
 481         int_en_mask = MBHC_SWITCH_INT;
 482         if (wcd->mbhc_btn_enabled)
 483                 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
 484
 485         snd_soc_update_bits(codec, CDC_D_INT_EN_CLR, int_en_mask, 0);
 486         snd_soc_update_bits(codec, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
 487         wcd->mbhc_btn0_pressed = false;
 488         wcd->detect_accessory_type = true;
 489 }
 490
 491 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
 492                                       bool micbias2_enabled)
 493 {
 494         struct snd_soc_codec *codec = priv->codec;
 495         u32 coarse, fine, reg_val, reg_addr;
 496         int *vrefs, i;
 497
 498         if (!micbias2_enabled) { /* use internal 100uA Current source */
 499                 /* Enable internal 2.2k Internal Rbias Resistor */
 500                 snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS,
 501                                     MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
 502                                     MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
 503                 /* Remove pull down on MIC BIAS2 */
 504                 snd_soc_update_bits(codec, CDC_A_MICB_2_EN,
 505                                    CDC_A_MICB_2_PULL_DOWN_EN_MASK,
 506                                    0);
 507                 /* enable 100uA internal current source */
 508                 snd_soc_update_bits(codec, CDC_A_MBHC_FSM_CTL,
 509                                     CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
 510                                     CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
 511         }
 512         snd_soc_update_bits(codec, CDC_A_MBHC_FSM_CTL,
 513                         CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
 514                         CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
 515
 516         if (micbias2_enabled)
 517                 vrefs = &priv->vref_btn_micb[0];
 518         else
 519                 vrefs = &priv->vref_btn_cs[0];
 520
 521         /* program vref ranges for all the buttons */
 522         reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
 523         for (i = 0; i <  MBHC_MAX_BUTTONS; i++) {
 524                 /* split mv in to coarse parts of 100mv & fine parts of 12mv */
 525                 coarse = (vrefs[i] / 100);
 526                 fine = ((vrefs[i] % 100) / 12);
 527                 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
 528                          (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
 529                 snd_soc_update_bits(codec, reg_addr,
 530                                CDC_A_MBHC_BTN_VREF_MASK,
 531                                reg_val);
 532                 reg_addr++;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int pm8916_wcd_analog_enable_micbias_int2(struct
 539                                                   snd_soc_dapm_widget
 540                                                   *w, struct snd_kcontrol
 541                                                   *kcontrol, int event)
 542 {
 543         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 544         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 545
 546         switch (event) {
 547         case SND_SOC_DAPM_POST_PMU:
 548                 pm8916_mbhc_configure_bias(wcd, true);
 549                 break;
 550         case SND_SOC_DAPM_POST_PMD:
 551                 pm8916_mbhc_configure_bias(wcd, false);
 552                 break;
 553         }
 554
 555         return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg,
 556                                                      wcd->micbias2_cap_mode);
 557 }
 558
 559 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
 560                                          struct snd_kcontrol *kcontrol,
 561                                          int event)
 562 {
 563         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 564         u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
 565         u8 init_bit_shift;
 566
 567         if (w->reg == CDC_A_TX_1_EN)
 568                 init_bit_shift = 5;
 569         else
 570                 init_bit_shift = 4;
 571
 572         switch (event) {
 573         case SND_SOC_DAPM_PRE_PMU:
 574                 if (w->reg == CDC_A_TX_2_EN)
 575                         snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
 576                                             MICB_1_CTL_CFILT_REF_SEL_MASK,
 577                                             MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
 578                 /*
 579                  * Add delay of 10 ms to give sufficient time for the voltage
 580                  * to shoot up and settle so that the txfe init does not
 581                  * happen when the input voltage is changing too much.
 582                  */
 583                 usleep_range(10000, 10010);
 584                 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
 585                                     1 << init_bit_shift);
 586                 switch (w->reg) {
 587                 case CDC_A_TX_1_EN:
 588                         snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL,
 589                                             CONN_TX1_SERIAL_TX1_MUX,
 590                                             CONN_TX1_SERIAL_TX1_ADC_1);
 591                         break;
 592                 case CDC_A_TX_2_EN:
 593                 case CDC_A_TX_3_EN:
 594                         snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL,
 595                                             CONN_TX2_SERIAL_TX2_MUX,
 596                                             CONN_TX2_SERIAL_TX2_ADC_2);
 597                         break;
 598                 }
 599                 break;
 600         case SND_SOC_DAPM_POST_PMU:
 601                 /*
 602                  * Add delay of 12 ms before deasserting the init
 603                  * to reduce the tx pop
 604                  */
 605                 usleep_range(12000, 12010);
 606                 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
 607                 break;
 608         case SND_SOC_DAPM_POST_PMD:
 609                 switch (w->reg) {
 610                 case CDC_A_TX_1_EN:
 611                         snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL,
 612                                             CONN_TX1_SERIAL_TX1_MUX,
 613                                             CONN_TX1_SERIAL_TX1_ZERO);
 614                         break;
 615                 case CDC_A_TX_2_EN:
 616                         snd_soc_update_bits(codec, CDC_A_MICB_1_CTL,
 617                                             MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
 618                 case CDC_A_TX_3_EN:
 619                         snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL,
 620                                             CONN_TX2_SERIAL_TX2_MUX,
 621                                             CONN_TX2_SERIAL_TX2_ZERO);
 622                         break;
 623                 }
 624
 625
 626                 break;
 627         }
 628         return 0;
 629 }
 630
 631 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
 632                                             struct snd_kcontrol *kcontrol,
 633                                             int event)
 634 {
 635         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 636
 637         switch (event) {
 638         case SND_SOC_DAPM_PRE_PMU:
 639                 snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL,
 640                                     SPKR_PWRSTG_CTL_DAC_EN_MASK |
 641                                     SPKR_PWRSTG_CTL_BBM_MASK |
 642                                     SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
 643                                     SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
 644                                     SPKR_PWRSTG_CTL_DAC_EN|
 645                                     SPKR_PWRSTG_CTL_BBM_EN |
 646                                     SPKR_PWRSTG_CTL_HBRDGE_EN |
 647                                     SPKR_PWRSTG_CTL_CLAMP_EN);
 648
 649                 snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL,
 650                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
 651                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
 652                 break;
 653         case SND_SOC_DAPM_POST_PMU:
 654                 snd_soc_update_bits(codec, CDC_A_SPKR_DRV_CTL,
 655                                     SPKR_DRV_CTL_DEF_MASK,
 656                                     SPKR_DRV_CTL_DEF_VAL);
 657                 snd_soc_update_bits(codec, w->reg,
 658                                     SPKR_DRV_CLASSD_PA_EN_MASK,
 659                                     SPKR_DRV_CLASSD_PA_EN_ENABLE);
 660                 break;
 661         case SND_SOC_DAPM_POST_PMD:
 662                 snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL,
 663                                     SPKR_PWRSTG_CTL_DAC_EN_MASK|
 664                                     SPKR_PWRSTG_CTL_BBM_MASK |
 665                                     SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
 666                                     SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
 667
 668                 snd_soc_update_bits(codec, CDC_A_SPKR_DAC_CTL,
 669                                     SPKR_DAC_CTL_DAC_RESET_MASK,
 670                                     SPKR_DAC_CTL_DAC_RESET_NORMAL);
 671                 snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL,
 672                                     RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
 673                 break;
 674         }
 675         return 0;
 676 }
 677
 678 static const struct reg_default wcd_reg_defaults_2_0[] = {
 679         {CDC_A_RX_COM_OCP_CTL, 0xD1},
 680         {CDC_A_RX_COM_OCP_COUNT, 0xFF},
 681         {CDC_D_SEC_ACCESS, 0xA5},
 682         {CDC_D_PERPH_RESET_CTL3, 0x0F},
 683         {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
 684         {CDC_A_NCP_FBCTRL, 0x28},
 685         {CDC_A_SPKR_DRV_CTL, 0x69},
 686         {CDC_A_SPKR_DRV_DBG, 0x01},
 687         {CDC_A_BOOST_EN_CTL, 0x5F},
 688         {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
 689         {CDC_A_SEC_ACCESS, 0xA5},
 690         {CDC_A_PERPH_RESET_CTL3, 0x0F},
 691         {CDC_A_CURRENT_LIMIT, 0x82},
 692         {CDC_A_SPKR_DAC_CTL, 0x03},
 693         {CDC_A_SPKR_OCP_CTL, 0xE1},
 694         {CDC_A_MASTER_BIAS_CTL, 0x30},
 695 };
 696
 697 static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
 698 {
 699         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev);
 700         int err, reg;
 701
 702         err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
 703         if (err != 0) {
 704                 dev_err(codec->dev, "failed to enable regulators (%d)\n", err);
 705                 return err;
 706         }
 707
 708         snd_soc_codec_set_drvdata(codec, priv);
 709         priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
 710         priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
 711
 712         dev_info(codec->dev, "PMIC REV: %d\t CODEC Version: %d\n",
 713                  priv->pmic_rev, priv->codec_version);
 714
 715         snd_soc_write(codec, CDC_D_PERPH_RESET_CTL4, 0x01);
 716         snd_soc_write(codec, CDC_A_PERPH_RESET_CTL4, 0x01);
 717
 718         for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
 719                 snd_soc_write(codec, wcd_reg_defaults_2_0[reg].reg,
 720                               wcd_reg_defaults_2_0[reg].def);
 721
 722         priv->codec = codec;
 723
 724         snd_soc_update_bits(codec, CDC_D_CDC_RST_CTL,
 725                             RST_CTL_DIG_SW_RST_N_MASK,
 726                             RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
 727
 728         pm8916_wcd_setup_mbhc(priv);
 729
 730         return 0;
 731 }
 732
 733 static int pm8916_wcd_analog_remove(struct snd_soc_codec *codec)
 734 {
 735         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev);
 736
 737         snd_soc_update_bits(codec, CDC_D_CDC_RST_CTL,
 738                             RST_CTL_DIG_SW_RST_N_MASK, 0);
 739
 740         return regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
 741                                       priv->supplies);
 742 }
 743
 744 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
 745
 746         {"PDM_RX1", NULL, "PDM Playback"},
 747         {"PDM_RX2", NULL, "PDM Playback"},
 748         {"PDM_RX3", NULL, "PDM Playback"},
 749         {"PDM Capture", NULL, "PDM_TX"},
 750
 751         /* ADC Connections */
 752         {"PDM_TX", NULL, "ADC2"},
 753         {"PDM_TX", NULL, "ADC3"},
 754         {"ADC2", NULL, "ADC2 MUX"},
 755         {"ADC3", NULL, "ADC2 MUX"},
 756         {"ADC2 MUX", "INP2", "ADC2_INP2"},
 757         {"ADC2 MUX", "INP3", "ADC2_INP3"},
 758
 759         {"PDM_TX", NULL, "ADC1"},
 760         {"ADC1", NULL, "AMIC1"},
 761         {"ADC2_INP2", NULL, "AMIC2"},
 762         {"ADC2_INP3", NULL, "AMIC3"},
 763
 764         /* RDAC Connections */
 765         {"HPHR DAC", NULL, "RDAC2 MUX"},
 766         {"RDAC2 MUX", "RX1", "PDM_RX1"},
 767         {"RDAC2 MUX", "RX2", "PDM_RX2"},
 768         {"HPHL DAC", NULL, "PDM_RX1"},
 769         {"PDM_RX1", NULL, "RXD1_CLK"},
 770         {"PDM_RX2", NULL, "RXD2_CLK"},
 771         {"PDM_RX3", NULL, "RXD3_CLK"},
 772
 773         {"PDM_RX1", NULL, "RXD_PDM_CLK"},
 774         {"PDM_RX2", NULL, "RXD_PDM_CLK"},
 775         {"PDM_RX3", NULL, "RXD_PDM_CLK"},
 776
 777         {"ADC1", NULL, "TXD_CLK"},
 778         {"ADC2", NULL, "TXD_CLK"},
 779         {"ADC3", NULL, "TXD_CLK"},
 780
 781         {"ADC1", NULL, "TXA_CLK25"},
 782         {"ADC2", NULL, "TXA_CLK25"},
 783         {"ADC3", NULL, "TXA_CLK25"},
 784
 785         {"PDM_RX1", NULL, "A_MCLK2"},
 786         {"PDM_RX2", NULL, "A_MCLK2"},
 787         {"PDM_RX3", NULL, "A_MCLK2"},
 788
 789         {"PDM_TX", NULL, "A_MCLK2"},
 790         {"A_MCLK2", NULL, "A_MCLK"},
 791
 792         /* Headset (RX MIX1 and RX MIX2) */
 793         {"HEADPHONE", NULL, "HPHL PA"},
 794         {"HEADPHONE", NULL, "HPHR PA"},
 795
 796         {"HPHL PA", NULL, "EAR_HPHL_CLK"},
 797         {"HPHR PA", NULL, "EAR_HPHR_CLK"},
 798
 799         {"CP", NULL, "NCP_CLK"},
 800
 801         {"HPHL PA", NULL, "HPHL"},
 802         {"HPHR PA", NULL, "HPHR"},
 803         {"HPHL PA", NULL, "CP"},
 804         {"HPHL PA", NULL, "RX_BIAS"},
 805         {"HPHR PA", NULL, "CP"},
 806         {"HPHR PA", NULL, "RX_BIAS"},
 807         {"HPHL", "Switch", "HPHL DAC"},
 808         {"HPHR", "Switch", "HPHR DAC"},
 809
 810         {"RX_BIAS", NULL, "DAC_REF"},
 811
 812         {"SPK_OUT", NULL, "SPK PA"},
 813         {"SPK PA", NULL, "RX_BIAS"},
 814         {"SPK PA", NULL, "SPKR_CLK"},
 815         {"SPK PA", NULL, "SPK DAC"},
 816         {"SPK DAC", "Switch", "PDM_RX3"},
 817
 818         {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
 819         {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
 820         {"MIC BIAS External1", NULL, "INT_LDO_H"},
 821         {"MIC BIAS External2", NULL, "INT_LDO_H"},
 822         {"MIC BIAS Internal1", NULL, "vdd-micbias"},
 823         {"MIC BIAS Internal2", NULL, "vdd-micbias"},
 824         {"MIC BIAS External1", NULL, "vdd-micbias"},
 825         {"MIC BIAS External2", NULL, "vdd-micbias"},
 826 };
 827
 828 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
 829
 830         SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
 831         SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
 832         SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
 833         SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
 834
 835         SND_SOC_DAPM_INPUT("AMIC1"),
 836         SND_SOC_DAPM_INPUT("AMIC3"),
 837         SND_SOC_DAPM_INPUT("AMIC2"),
 838         SND_SOC_DAPM_OUTPUT("HEADPHONE"),
 839
 840         /* RX stuff */
 841         SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
 842
 843         SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
 844         SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
 845         SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
 846                            0),
 847         SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
 848         SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
 849         SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
 850                            0),
 851         SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
 852                            spkr_switch, ARRAY_SIZE(spkr_switch)),
 853
 854         /* Speaker */
 855         SND_SOC_DAPM_OUTPUT("SPK_OUT"),
 856         SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
 857                            6, 0, NULL, 0,
 858                            pm8916_wcd_analog_enable_spk_pa,
 859                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 860                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 861         SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
 862         SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
 863
 864         SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
 865         SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
 866
 867         /* TX */
 868         SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
 869                             pm8916_wcd_analog_enable_micbias_int1,
 870                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 871                             SND_SOC_DAPM_POST_PMD),
 872         SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
 873                             pm8916_wcd_analog_enable_micbias_int2,
 874                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 875                             SND_SOC_DAPM_POST_PMD),
 876
 877         SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
 878                             pm8916_wcd_analog_enable_micbias_ext1,
 879                             SND_SOC_DAPM_POST_PMU),
 880         SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
 881                             pm8916_wcd_analog_enable_micbias_ext2,
 882                             SND_SOC_DAPM_POST_PMU),
 883
 884         SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
 885                            pm8916_wcd_analog_enable_adc,
 886                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 887                            SND_SOC_DAPM_POST_PMD),
 888         SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
 889                            pm8916_wcd_analog_enable_adc,
 890                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 891                            SND_SOC_DAPM_POST_PMD),
 892         SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
 893                            pm8916_wcd_analog_enable_adc,
 894                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 895                            SND_SOC_DAPM_POST_PMD),
 896
 897         SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 898         SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 899
 900         SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
 901         SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
 902
 903         /* Analog path clocks */
 904         SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
 905                             0),
 906         SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
 907                             0),
 908         SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
 909         SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
 910
 911         /* Digital path clocks */
 912
 913         SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
 914         SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
 915         SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
 916
 917         SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
 918         SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
 919         SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
 920                             0),
 921
 922         /* System Clock source */
 923         SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
 924         /* TX ADC and RX DAC Clock source. */
 925         SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
 926 };
 927
 928 static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
 929                                       struct snd_soc_jack *jack,
 930                                       void *data)
 931 {
 932         struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec);
 933
 934         wcd->jack = jack;
 935
 936         return 0;
 937 }
 938
 939 static struct regmap *pm8916_get_regmap(struct device *dev)
 940 {
 941         return dev_get_regmap(dev->parent, NULL);
 942 }
 943
 944 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
 945 {
 946         struct pm8916_wcd_analog_priv *priv = arg;
 947
 948         if (priv->detect_accessory_type) {
 949                 struct snd_soc_codec *codec = priv->codec;
 950                 u32 val = snd_soc_read(codec, CDC_A_MBHC_RESULT_1);
 951
 952                 /* check if its BTN0 thats released */
 953                 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
 954                         priv->mbhc_btn0_pressed = false;
 955
 956         } else {
 957                 snd_soc_jack_report(priv->jack, 0, btn_mask);
 958         }
 959
 960         return IRQ_HANDLED;
 961 }
 962
 963 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
 964 {
 965         struct pm8916_wcd_analog_priv *priv = arg;
 966         struct snd_soc_codec *codec = priv->codec;
 967         u32 btn_result;
 968
 969         btn_result = snd_soc_read(codec, CDC_A_MBHC_RESULT_1) &
 970                                   CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
 971
 972         switch (btn_result) {
 973         case 0xf:
 974                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
 975                 break;
 976         case 0x7:
 977                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
 978                 break;
 979         case 0x3:
 980                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
 981                 break;
 982         case 0x1:
 983                 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
 984                 break;
 985         case 0x0:
 986                 /* handle BTN_0 specially for type detection */
 987                 if (priv->detect_accessory_type)
 988                         priv->mbhc_btn0_pressed = true;
 989                 else
 990                         snd_soc_jack_report(priv->jack,
 991                                             SND_JACK_BTN_0, btn_mask);
 992                 break;
 993         default:
 994                 dev_err(codec->dev,
 995                         "Unexpected button press result (%x)", btn_result);
 996                 break;
 997         }
 998
 999         return IRQ_HANDLED;
1000 }
1001
1002 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
1003 {
1004         struct pm8916_wcd_analog_priv *priv = arg;
1005         struct snd_soc_codec *codec = priv->codec;
1006         bool ins = false;
1007
1008         if (snd_soc_read(codec, CDC_A_MBHC_DET_CTL_1) &
1009                                 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
1010                 ins = true;
1011
1012         /* Set the detection type appropriately */
1013         snd_soc_update_bits(codec, CDC_A_MBHC_DET_CTL_1,
1014                             CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
1015                             (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
1016
1017
1018         if (ins) { /* hs insertion */
1019                 bool micbias_enabled = false;
1020
1021                 if (snd_soc_read(codec, CDC_A_MICB_2_EN) &
1022                                 CDC_A_MICB_2_EN_ENABLE)
1023                         micbias_enabled = true;
1024
1025                 pm8916_mbhc_configure_bias(priv, micbias_enabled);
1026
1027                 /*
1028                  * if only a btn0 press event is receive just before
1029                  * insert event then its a 3 pole headphone else if
1030                  * both press and release event received then its
1031                  * a headset.
1032                  */
1033                 if (priv->mbhc_btn0_pressed)
1034                         snd_soc_jack_report(priv->jack,
1035                                             SND_JACK_HEADPHONE, hs_jack_mask);
1036                 else
1037                         snd_soc_jack_report(priv->jack,
1038                                             SND_JACK_HEADSET, hs_jack_mask);
1039
1040                 priv->detect_accessory_type = false;
1041
1042         } else { /* removal */
1043                 snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
1044                 priv->detect_accessory_type = true;
1045                 priv->mbhc_btn0_pressed = false;
1046         }
1047
1048         return IRQ_HANDLED;
1049 }
1050
1051 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
1052         [0] = {
1053                .name = "pm8916_wcd_analog_pdm_rx",
1054                .id = 0,
1055                .playback = {
1056                             .stream_name = "PDM Playback",
1057                             .rates = MSM8916_WCD_ANALOG_RATES,
1058                             .formats = MSM8916_WCD_ANALOG_FORMATS,
1059                             .channels_min = 1,
1060                             .channels_max = 3,
1061                             },
1062                },
1063         [1] = {
1064                .name = "pm8916_wcd_analog_pdm_tx",
1065                .id = 1,
1066                .capture = {
1067                            .stream_name = "PDM Capture",
1068                            .rates = MSM8916_WCD_ANALOG_RATES,
1069                            .formats = MSM8916_WCD_ANALOG_FORMATS,
1070                            .channels_min = 1,
1071                            .channels_max = 4,
1072                            },
1073                },
1074 };
1075
1076 static const struct snd_soc_codec_driver pm8916_wcd_analog = {
1077         .probe = pm8916_wcd_analog_probe,
1078         .remove = pm8916_wcd_analog_remove,
1079         .set_jack = pm8916_wcd_analog_set_jack,
1080         .get_regmap = pm8916_get_regmap,
1081         .component_driver = {
1082                 .controls = pm8916_wcd_analog_snd_controls,
1083                 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
1084                 .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
1085                 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
1086                 .dapm_routes = pm8916_wcd_analog_audio_map,
1087                 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
1088         },
1089 };
1090
1091 static int pm8916_wcd_analog_parse_dt(struct device *dev,
1092                                        struct pm8916_wcd_analog_priv *priv)
1093 {
1094         int rval;
1095
1096         if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
1097                 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1098         else
1099                 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1100
1101         if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
1102                 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
1103         else
1104                 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
1105
1106         of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
1107                              &priv->micbias_mv);
1108
1109         if (of_property_read_bool(dev->of_node,
1110                                   "qcom,hphl-jack-type-normally-open"))
1111                 priv->hphl_jack_type_normally_open = true;
1112         else
1113                 priv->hphl_jack_type_normally_open = false;
1114
1115         if (of_property_read_bool(dev->of_node,
1116                                   "qcom,gnd-jack-type-normally-open"))
1117                 priv->gnd_jack_type_normally_open = true;
1118         else
1119                 priv->gnd_jack_type_normally_open = false;
1120
1121         priv->mbhc_btn_enabled = true;
1122         rval = of_property_read_u32_array(dev->of_node,
1123                                           "qcom,mbhc-vthreshold-low",
1124                                           &priv->vref_btn_cs[0],
1125                                           MBHC_MAX_BUTTONS);
1126         if (rval < 0) {
1127                 priv->mbhc_btn_enabled = false;
1128         } else {
1129                 rval = of_property_read_u32_array(dev->of_node,
1130                                                   "qcom,mbhc-vthreshold-high",
1131                                                   &priv->vref_btn_micb[0],
1132                                                   MBHC_MAX_BUTTONS);
1133                 if (rval < 0)
1134                         priv->mbhc_btn_enabled = false;
1135         }
1136
1137         if (!priv->mbhc_btn_enabled)
1138                 dev_err(dev,
1139                         "DT property missing, MBHC btn detection disabled\n");
1140
1141
1142         return 0;
1143 }
1144
1145 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
1146 {
1147         struct pm8916_wcd_analog_priv *priv;
1148         struct device *dev = &pdev->dev;
1149         int ret, i, irq;
1150
1151         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1152         if (!priv)
1153                 return -ENOMEM;
1154
1155         ret = pm8916_wcd_analog_parse_dt(dev, priv);
1156         if (ret < 0)
1157                 return ret;
1158
1159         priv->mclk = devm_clk_get(dev, "mclk");
1160         if (IS_ERR(priv->mclk)) {
1161                 dev_err(dev, "failed to get mclk\n");
1162                 return PTR_ERR(priv->mclk);
1163         }
1164
1165         for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1166                 priv->supplies[i].supply = supply_names[i];
1167
1168         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
1169                                     priv->supplies);
1170         if (ret) {
1171                 dev_err(dev, "Failed to get regulator supplies %d\n", ret);
1172                 return ret;
1173         }
1174
1175         ret = clk_prepare_enable(priv->mclk);
1176         if (ret < 0) {
1177                 dev_err(dev, "failed to enable mclk %d\n", ret);
1178                 return ret;
1179         }
1180
1181         irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
1182         if (irq < 0) {
1183                 dev_err(dev, "failed to get mbhc switch irq\n");
1184                 return irq;
1185         }
1186
1187         ret = devm_request_threaded_irq(dev, irq, NULL,
1188                                pm8916_mbhc_switch_irq_handler,
1189                                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1190                                IRQF_ONESHOT,
1191                                "mbhc switch irq", priv);
1192         if (ret)
1193                 dev_err(dev, "cannot request mbhc switch irq\n");
1194
1195         if (priv->mbhc_btn_enabled) {
1196                 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
1197                 if (irq < 0) {
1198                         dev_err(dev, "failed to get button press irq\n");
1199                         return irq;
1200                 }
1201
1202                 ret = devm_request_threaded_irq(dev, irq, NULL,
1203                                        mbhc_btn_press_irq_handler,
1204                                        IRQF_TRIGGER_RISING |
1205                                        IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1206                                        "mbhc btn press irq", priv);
1207                 if (ret)
1208                         dev_err(dev, "cannot request mbhc button press irq\n");
1209
1210                 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
1211                 if (irq < 0) {
1212                         dev_err(dev, "failed to get button release irq\n");
1213                         return irq;
1214                 }
1215
1216                 ret = devm_request_threaded_irq(dev, irq, NULL,
1217                                        mbhc_btn_release_irq_handler,
1218                                        IRQF_TRIGGER_RISING |
1219                                        IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1220                                        "mbhc btn release irq", priv);
1221                 if (ret)
1222                         dev_err(dev, "cannot request mbhc button release irq\n");
1223
1224         }
1225
1226         dev_set_drvdata(dev, priv);
1227
1228         return snd_soc_register_codec(dev, &pm8916_wcd_analog,
1229                                       pm8916_wcd_analog_dai,
1230                                       ARRAY_SIZE(pm8916_wcd_analog_dai));
1231 }
1232
1233 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
1234 {
1235         struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
1236
1237         snd_soc_unregister_codec(&pdev->dev);
1238         clk_disable_unprepare(priv->mclk);
1239
1240         return 0;
1241 }
1242
1243 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
1244         { .compatible = "qcom,pm8916-wcd-analog-codec", },
1245         { }
1246 };
1247
1248 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
1249
1250 static struct platform_driver pm8916_wcd_analog_spmi_driver = {
1251         .driver = {
1252                    .name = "qcom,pm8916-wcd-spmi-codec",
1253                    .of_match_table = pm8916_wcd_analog_spmi_match_table,
1254         },
1255         .probe = pm8916_wcd_analog_spmi_probe,
1256         .remove = pm8916_wcd_analog_spmi_remove,
1257 };
1258
1259 module_platform_driver(pm8916_wcd_analog_spmi_driver);
1260
1261 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1262 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
1263 MODULE_LICENSE("GPL v2");