sound/soc/codecs/max98373.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/i2c.h>
   6 #include <linux/module.h>
   7 #include <linux/regmap.h>
   8 #include <linux/slab.h>
   9 #include <linux/cdev.h>
  10 #include <sound/pcm.h>
  11 #include <sound/pcm_params.h>
  12 #include <sound/soc.h>
  13 #include <linux/gpio.h>
  14 #include <linux/of_gpio.h>
  15 #include <sound/tlv.h>
  16 #include "max98373.h"
  17
  18 static struct reg_default max98373_reg[] = {
  19         {MAX98373_R2000_SW_RESET, 0x00},
  20         {MAX98373_R2001_INT_RAW1, 0x00},
  21         {MAX98373_R2002_INT_RAW2, 0x00},
  22         {MAX98373_R2003_INT_RAW3, 0x00},
  23         {MAX98373_R2004_INT_STATE1, 0x00},
  24         {MAX98373_R2005_INT_STATE2, 0x00},
  25         {MAX98373_R2006_INT_STATE3, 0x00},
  26         {MAX98373_R2007_INT_FLAG1, 0x00},
  27         {MAX98373_R2008_INT_FLAG2, 0x00},
  28         {MAX98373_R2009_INT_FLAG3, 0x00},
  29         {MAX98373_R200A_INT_EN1, 0x00},
  30         {MAX98373_R200B_INT_EN2, 0x00},
  31         {MAX98373_R200C_INT_EN3, 0x00},
  32         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  33         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  34         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  35         {MAX98373_R2010_IRQ_CTRL, 0x00},
  36         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  37         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
  38         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
  39         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
  40         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
  41         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
  42         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
  43         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
  44         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
  45         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
  46         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
  47         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
  48         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
  49         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
  50         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
  51         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
  52         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
  53         {MAX98373_R202B_PCM_RX_EN, 0x00},
  54         {MAX98373_R202C_PCM_TX_EN, 0x00},
  55         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
  56         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
  57         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
  58         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
  59         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
  60         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
  61         {MAX98373_R2035_ICC_TX_EN, 0x00},
  62         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
  63         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
  64         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
  65         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
  66         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
  67         {MAX98373_R2041_AMP_CFG, 0x03},
  68         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
  69         {MAX98373_R2043_AMP_EN, 0x00},
  70         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
  71         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
  72         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
  73         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
  74         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
  75         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
  76         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
  77         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
  78         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
  79         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
  80         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
  81         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
  82         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
  83         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
  84         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
  85         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
  86         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
  87         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
  88         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
  89         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
  90         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
  91         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
  92         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
  93         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
  94         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
  95         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
  96         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
  97         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
  98         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
  99         {MAX98373_R20B5_BDE_EN, 0x00},
 100         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 101         {MAX98373_R20D1_DHT_CFG, 0x01},
 102         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 103         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 104         {MAX98373_R20D4_DHT_EN, 0x00},
 105         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 106         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 107         {MAX98373_R20E2_LIMITER_EN, 0x00},
 108         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 109         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 110         {MAX98373_R21FF_REV_ID, 0x42},
 111 };
 112
 113 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 114 {
 115         struct snd_soc_component *component = codec_dai->component;
 116         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 117         unsigned int format = 0;
 118         unsigned int invert = 0;
 119
 120         dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
 121
 122         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 123         case SND_SOC_DAIFMT_NB_NF:
 124                 break;
 125         case SND_SOC_DAIFMT_IB_NF:
 126                 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
 127                 break;
 128         default:
 129                 dev_err(component->dev, "DAI invert mode unsupported\n");
 130                 return -EINVAL;
 131         }
 132
 133         regmap_update_bits(max98373->regmap,
 134                 MAX98373_R2026_PCM_CLOCK_RATIO,
 135                 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
 136                 invert);
 137
 138         /* interface format */
 139         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 140         case SND_SOC_DAIFMT_I2S:
 141                 format = MAX98373_PCM_FORMAT_I2S;
 142                 break;
 143         case SND_SOC_DAIFMT_LEFT_J:
 144                 format = MAX98373_PCM_FORMAT_LJ;
 145                 break;
 146         case SND_SOC_DAIFMT_DSP_A:
 147                 format = MAX98373_PCM_FORMAT_TDM_MODE1;
 148                 break;
 149         case SND_SOC_DAIFMT_DSP_B:
 150                 format = MAX98373_PCM_FORMAT_TDM_MODE0;
 151                 break;
 152         default:
 153                 return -EINVAL;
 154         }
 155
 156         regmap_update_bits(max98373->regmap,
 157                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 158                 MAX98373_PCM_MODE_CFG_FORMAT_MASK,
 159                 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
 160
 161         return 0;
 162 }
 163
 164 /* BCLKs per LRCLK */
 165 static const int bclk_sel_table[] = {
 166         32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
 167 };
 168
 169 static int max98373_get_bclk_sel(int bclk)
 170 {
 171         int i;
 172         /* match BCLKs per LRCLK */
 173         for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
 174                 if (bclk_sel_table[i] == bclk)
 175                         return i + 2;
 176         }
 177         return 0;
 178 }
 179
 180 static int max98373_set_clock(struct snd_soc_component *component,
 181         struct snd_pcm_hw_params *params)
 182 {
 183         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 184         /* BCLK/LRCLK ratio calculation */
 185         int blr_clk_ratio = params_channels(params) * max98373->ch_size;
 186         int value;
 187
 188         if (!max98373->tdm_mode) {
 189                 /* BCLK configuration */
 190                 value = max98373_get_bclk_sel(blr_clk_ratio);
 191                 if (!value) {
 192                         dev_err(component->dev, "format unsupported %d\n",
 193                                 params_format(params));
 194                         return -EINVAL;
 195                 }
 196
 197                 regmap_update_bits(max98373->regmap,
 198                         MAX98373_R2026_PCM_CLOCK_RATIO,
 199                         MAX98373_PCM_CLK_SETUP_BSEL_MASK,
 200                         value);
 201         }
 202         return 0;
 203 }
 204
 205 static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
 206         struct snd_pcm_hw_params *params,
 207         struct snd_soc_dai *dai)
 208 {
 209         struct snd_soc_component *component = dai->component;
 210         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 211         unsigned int sampling_rate = 0;
 212         unsigned int chan_sz = 0;
 213
 214         /* pcm mode configuration */
 215         switch (snd_pcm_format_width(params_format(params))) {
 216         case 16:
 217                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 218                 break;
 219         case 24:
 220                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 221                 break;
 222         case 32:
 223                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 224                 break;
 225         default:
 226                 dev_err(component->dev, "format unsupported %d\n",
 227                         params_format(params));
 228                 goto err;
 229         }
 230
 231         max98373->ch_size = snd_pcm_format_width(params_format(params));
 232
 233         regmap_update_bits(max98373->regmap,
 234                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 235                 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 236
 237         dev_dbg(component->dev, "format supported %d",
 238                 params_format(params));
 239
 240         /* sampling rate configuration */
 241         switch (params_rate(params)) {
 242         case 8000:
 243                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 244                 break;
 245         case 11025:
 246                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 247                 break;
 248         case 12000:
 249                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 250                 break;
 251         case 16000:
 252                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 253                 break;
 254         case 22050:
 255                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 256                 break;
 257         case 24000:
 258                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 259                 break;
 260         case 32000:
 261                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 262                 break;
 263         case 44100:
 264                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 265                 break;
 266         case 48000:
 267                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 268                 break;
 269         default:
 270                 dev_err(component->dev, "rate %d not supported\n",
 271                         params_rate(params));
 272                 goto err;
 273         }
 274
 275         /* set DAI_SR to correct LRCLK frequency */
 276         regmap_update_bits(max98373->regmap,
 277                 MAX98373_R2027_PCM_SR_SETUP_1,
 278                 MAX98373_PCM_SR_SET1_SR_MASK,
 279                 sampling_rate);
 280         regmap_update_bits(max98373->regmap,
 281                 MAX98373_R2028_PCM_SR_SETUP_2,
 282                 MAX98373_PCM_SR_SET2_SR_MASK,
 283                 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 284
 285         /* set sampling rate of IV */
 286         if (max98373->interleave_mode &&
 287             sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
 288                 regmap_update_bits(max98373->regmap,
 289                         MAX98373_R2028_PCM_SR_SETUP_2,
 290                         MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 291                         sampling_rate - 3);
 292         else
 293                 regmap_update_bits(max98373->regmap,
 294                         MAX98373_R2028_PCM_SR_SETUP_2,
 295                         MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 296                         sampling_rate);
 297
 298         return max98373_set_clock(component, params);
 299 err:
 300         return -EINVAL;
 301 }
 302
 303 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
 304         unsigned int tx_mask, unsigned int rx_mask,
 305         int slots, int slot_width)
 306 {
 307         struct snd_soc_component *component = dai->component;
 308         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 309         int bsel = 0;
 310         unsigned int chan_sz = 0;
 311         unsigned int mask;
 312         int x, slot_found;
 313
 314         if (!tx_mask && !rx_mask && !slots && !slot_width)
 315                 max98373->tdm_mode = false;
 316         else
 317                 max98373->tdm_mode = true;
 318
 319         /* BCLK configuration */
 320         bsel = max98373_get_bclk_sel(slots * slot_width);
 321         if (bsel == 0) {
 322                 dev_err(component->dev, "BCLK %d not supported\n",
 323                         slots * slot_width);
 324                 return -EINVAL;
 325         }
 326
 327         regmap_update_bits(max98373->regmap,
 328                 MAX98373_R2026_PCM_CLOCK_RATIO,
 329                 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
 330                 bsel);
 331
 332         /* Channel size configuration */
 333         switch (slot_width) {
 334         case 16:
 335                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 336                 break;
 337         case 24:
 338                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 339                 break;
 340         case 32:
 341                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 342                 break;
 343         default:
 344                 dev_err(component->dev, "format unsupported %d\n",
 345                         slot_width);
 346                 return -EINVAL;
 347         }
 348
 349         regmap_update_bits(max98373->regmap,
 350                 MAX98373_R2024_PCM_DATA_FMT_CFG,
 351                 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 352
 353         /* Rx slot configuration */
 354         slot_found = 0;
 355         mask = rx_mask;
 356         for (x = 0 ; x < 16 ; x++, mask >>= 1) {
 357                 if (mask & 0x1) {
 358                         if (slot_found == 0)
 359                                 regmap_update_bits(max98373->regmap,
 360                                         MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 361                                         MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
 362                         else
 363                                 regmap_write(max98373->regmap,
 364                                         MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 365                                         x);
 366                         slot_found++;
 367                         if (slot_found > 1)
 368                                 break;
 369                 }
 370         }
 371
 372         /* Tx slot Hi-Z configuration */
 373         regmap_write(max98373->regmap,
 374                 MAX98373_R2020_PCM_TX_HIZ_EN_1,
 375                 ~tx_mask & 0xFF);
 376         regmap_write(max98373->regmap,
 377                 MAX98373_R2021_PCM_TX_HIZ_EN_2,
 378                 (~tx_mask & 0xFF00) >> 8);
 379
 380         return 0;
 381 }
 382
 383 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 384
 385 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 386         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 387
 388 static const struct snd_soc_dai_ops max98373_dai_ops = {
 389         .set_fmt = max98373_dai_set_fmt,
 390         .hw_params = max98373_dai_hw_params,
 391         .set_tdm_slot = max98373_dai_tdm_slot,
 392 };
 393
 394 static int max98373_dac_event(struct snd_soc_dapm_widget *w,
 395         struct snd_kcontrol *kcontrol, int event)
 396 {
 397         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 398         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 399
 400         switch (event) {
 401         case SND_SOC_DAPM_POST_PMU:
 402                 regmap_update_bits(max98373->regmap,
 403                         MAX98373_R20FF_GLOBAL_SHDN,
 404                         MAX98373_GLOBAL_EN_MASK, 1);
 405                 break;
 406         case SND_SOC_DAPM_POST_PMD:
 407                 regmap_update_bits(max98373->regmap,
 408                         MAX98373_R20FF_GLOBAL_SHDN,
 409                         MAX98373_GLOBAL_EN_MASK, 0);
 410                 max98373->tdm_mode = 0;
 411                 break;
 412         default:
 413                 return 0;
 414         }
 415         return 0;
 416 }
 417
 418 static const char * const max98373_switch_text[] = {
 419         "Left", "Right", "LeftRight"};
 420
 421 static const struct soc_enum dai_sel_enum =
 422         SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 423                 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
 424                 3, max98373_switch_text);
 425
 426 static const struct snd_kcontrol_new max98373_dai_controls =
 427         SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
 428
 429 static const struct snd_kcontrol_new max98373_vi_control =
 430         SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
 431
 432 static const struct snd_kcontrol_new max98373_spkfb_control =
 433         SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
 434
 435 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
 436 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
 437         MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
 438         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 439 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
 440         &max98373_dai_controls),
 441 SND_SOC_DAPM_OUTPUT("BE_OUT"),
 442 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
 443         MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
 444 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
 445         MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
 446 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
 447         SND_SOC_NOPM, 0, 0),
 448 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
 449         &max98373_vi_control),
 450 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
 451         &max98373_spkfb_control),
 452 SND_SOC_DAPM_SIGGEN("VMON"),
 453 SND_SOC_DAPM_SIGGEN("IMON"),
 454 SND_SOC_DAPM_SIGGEN("FBMON"),
 455 };
 456
 457 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
 458 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
 459         0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
 460         9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
 461 );
 462 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
 463         0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
 464 );
 465 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
 466         0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
 467         2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
 468 );
 469 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
 470         0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
 471 );
 472 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
 473         0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
 474         2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
 475         8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
 476         10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
 477         12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
 478         14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
 479 );
 480 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
 481         0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
 482 );
 483
 484 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
 485         0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
 486 );
 487
 488 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 489 {
 490         switch (reg) {
 491         case MAX98373_R2000_SW_RESET:
 492         case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
 493         case MAX98373_R2010_IRQ_CTRL:
 494         case MAX98373_R2014_THERM_WARN_THRESH
 495                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 496         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 497                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 498         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 499         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 500                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 501         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 502                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 503         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 504         case MAX98373_R2097_BDE_L1_THRESH
 505                 ... MAX98373_R209B_BDE_THRESH_HYST:
 506         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 507         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 508         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 509         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 510         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 511                 ... MAX98373_R20FF_GLOBAL_SHDN:
 512         case MAX98373_R21FF_REV_ID:
 513                 return true;
 514         default:
 515                 return false;
 516         }
 517 };
 518
 519 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 520 {
 521         switch (reg) {
 522         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 523         case MAX98373_R203E_AMP_PATH_GAIN:
 524         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 525         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 526         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 527         case MAX98373_R21FF_REV_ID:
 528                 return true;
 529         default:
 530                 return false;
 531         }
 532 }
 533
 534 static const char * const max98373_output_voltage_lvl_text[] = {
 535         "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
 536         "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
 537 };
 538
 539 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
 540                             MAX98373_R203E_AMP_PATH_GAIN, 0,
 541                             max98373_output_voltage_lvl_text);
 542
 543 static const char * const max98373_dht_attack_rate_text[] = {
 544         "17.5us", "35us", "70us", "140us",
 545         "280us", "560us", "1120us", "2240us"
 546 };
 547
 548 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
 549                             MAX98373_R20D2_DHT_ATTACK_CFG, 0,
 550                             max98373_dht_attack_rate_text);
 551
 552 static const char * const max98373_dht_release_rate_text[] = {
 553         "45ms", "225ms", "450ms", "1150ms",
 554         "2250ms", "3100ms", "4500ms", "6750ms"
 555 };
 556
 557 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
 558                             MAX98373_R20D3_DHT_RELEASE_CFG, 0,
 559                             max98373_dht_release_rate_text);
 560
 561 static const char * const max98373_limiter_attack_rate_text[] = {
 562         "10us", "20us", "40us", "80us",
 563         "160us", "320us", "640us", "1.28ms",
 564         "2.56ms", "5.12ms", "10.24ms", "20.48ms",
 565         "40.96ms", "81.92ms", "16.384ms", "32.768ms"
 566 };
 567
 568 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
 569                             MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
 570                             max98373_limiter_attack_rate_text);
 571
 572 static const char * const max98373_limiter_release_rate_text[] = {
 573         "40us", "80us", "160us", "320us",
 574         "640us", "1.28ms", "2.56ms", "5.120ms",
 575         "10.24ms", "20.48ms", "40.96ms", "81.92ms",
 576         "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
 577 };
 578
 579 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
 580                             MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
 581                             max98373_limiter_release_rate_text);
 582
 583 static const char * const max98373_ADC_samplerate_text[] = {
 584         "333kHz", "192kHz", "64kHz", "48kHz"
 585 };
 586
 587 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
 588                             MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
 589                             max98373_ADC_samplerate_text);
 590
 591 static const struct snd_kcontrol_new max98373_snd_controls[] = {
 592 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
 593         MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
 594 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
 595         MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
 596 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
 597         MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
 598 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
 599         MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
 600 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
 601         MAX98373_CLOCK_MON_SHIFT, 1, 0),
 602 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
 603         MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
 604 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
 605         MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
 606 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
 607         0, 0x7F, 0, max98373_digital_tlv),
 608 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
 609         MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
 610 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
 611         MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
 612 SOC_ENUM("Output Voltage", max98373_out_volt_enum),
 613 /* Dynamic Headroom Tracking */
 614 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
 615         MAX98373_DHT_EN_SHIFT, 1, 0),
 616 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
 617         MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
 618 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
 619         MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
 620 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
 621         MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
 622 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
 623         MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
 624 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
 625 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
 626 /* ADC configuration */
 627 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
 628 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
 629         MAX98373_FLT_EN_SHIFT, 1, 0),
 630 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
 631         MAX98373_FLT_EN_SHIFT, 1, 0),
 632 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
 633 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
 634 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
 635         0, 0x3, 0),
 636 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
 637         0, 0x3, 0),
 638 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
 639 /* Brownout Detection Engine */
 640 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
 641 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
 642         MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
 643 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
 644         MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
 645 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
 646 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
 647 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
 648 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
 649 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
 650 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
 651 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
 652 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
 653 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
 654 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
 655 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
 656         0, 0x3C, 0, max98373_bde_gain_tlv),
 657 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
 658         0, 0x3C, 0, max98373_bde_gain_tlv),
 659 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
 660         0, 0x3C, 0, max98373_bde_gain_tlv),
 661 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
 662         0, 0x3C, 0, max98373_bde_gain_tlv),
 663 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
 664         0, 0x3C, 0, max98373_bde_gain_tlv),
 665 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
 666         0, 0x3C, 0, max98373_bde_gain_tlv),
 667 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
 668         0, 0x3C, 0, max98373_bde_gain_tlv),
 669 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
 670         0, 0x3C, 0, max98373_bde_gain_tlv),
 671 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
 672         0, 0xF, 0, max98373_limiter_thresh_tlv),
 673 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
 674         0, 0xF, 0, max98373_limiter_thresh_tlv),
 675 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
 676         0, 0xF, 0, max98373_limiter_thresh_tlv),
 677 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
 678         0, 0xF, 0, max98373_limiter_thresh_tlv),
 679 /* Limiter */
 680 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
 681         MAX98373_LIMITER_EN_SHIFT, 1, 0),
 682 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
 683         MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
 684 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
 685         MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
 686 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
 687 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
 688 };
 689
 690 static const struct snd_soc_dapm_route max98373_audio_map[] = {
 691         /* Plabyack */
 692         {"DAI Sel Mux", "Left", "Amp Enable"},
 693         {"DAI Sel Mux", "Right", "Amp Enable"},
 694         {"DAI Sel Mux", "LeftRight", "Amp Enable"},
 695         {"BE_OUT", NULL, "DAI Sel Mux"},
 696         /* Capture */
 697         { "VI Sense", "Switch", "VMON" },
 698         { "VI Sense", "Switch", "IMON" },
 699         { "SpkFB Sense", "Switch", "FBMON" },
 700         { "Voltage Sense", NULL, "VI Sense" },
 701         { "Current Sense", NULL, "VI Sense" },
 702         { "Speaker FB Sense", NULL, "SpkFB Sense" },
 703 };
 704
 705 static struct snd_soc_dai_driver max98373_dai[] = {
 706         {
 707                 .name = "max98373-aif1",
 708                 .playback = {
 709                         .stream_name = "HiFi Playback",
 710                         .channels_min = 1,
 711                         .channels_max = 2,
 712                         .rates = MAX98373_RATES,
 713                         .formats = MAX98373_FORMATS,
 714                 },
 715                 .capture = {
 716                         .stream_name = "HiFi Capture",
 717                         .channels_min = 1,
 718                         .channels_max = 2,
 719                         .rates = MAX98373_RATES,
 720                         .formats = MAX98373_FORMATS,
 721                 },
 722                 .ops = &max98373_dai_ops,
 723         }
 724 };
 725
 726 static int max98373_probe(struct snd_soc_component *component)
 727 {
 728         struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
 729
 730         /* Software Reset */
 731         regmap_write(max98373->regmap,
 732                 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
 733         usleep_range(10000, 11000);
 734
 735         /* IV default slot configuration */
 736         regmap_write(max98373->regmap,
 737                 MAX98373_R2020_PCM_TX_HIZ_EN_1,
 738                 0xFF);
 739         regmap_write(max98373->regmap,
 740                 MAX98373_R2021_PCM_TX_HIZ_EN_2,
 741                 0xFF);
 742         /* L/R mix configuration */
 743         regmap_write(max98373->regmap,
 744                 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 745                 0x80);
 746         regmap_write(max98373->regmap,
 747                 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 748                 0x1);
 749         /* Set inital volume (0dB) */
 750         regmap_write(max98373->regmap,
 751                 MAX98373_R203D_AMP_DIG_VOL_CTRL,
 752                 0x00);
 753         regmap_write(max98373->regmap,
 754                 MAX98373_R203E_AMP_PATH_GAIN,
 755                 0x00);
 756         /* Enable DC blocker */
 757         regmap_write(max98373->regmap,
 758                 MAX98373_R203F_AMP_DSP_CFG,
 759                 0x3);
 760         /* Enable IMON VMON DC blocker */
 761         regmap_write(max98373->regmap,
 762                 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 763                 0x7);
 764         /* voltage, current slot configuration */
 765         regmap_write(max98373->regmap,
 766                 MAX98373_R2022_PCM_TX_SRC_1,
 767                 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 768                 max98373->v_slot) & 0xFF);
 769         if (max98373->v_slot < 8)
 770                 regmap_update_bits(max98373->regmap,
 771                         MAX98373_R2020_PCM_TX_HIZ_EN_1,
 772                         1 << max98373->v_slot, 0);
 773         else
 774                 regmap_update_bits(max98373->regmap,
 775                         MAX98373_R2021_PCM_TX_HIZ_EN_2,
 776                         1 << (max98373->v_slot - 8), 0);
 777
 778         if (max98373->i_slot < 8)
 779                 regmap_update_bits(max98373->regmap,
 780                         MAX98373_R2020_PCM_TX_HIZ_EN_1,
 781                         1 << max98373->i_slot, 0);
 782         else
 783                 regmap_update_bits(max98373->regmap,
 784                         MAX98373_R2021_PCM_TX_HIZ_EN_2,
 785                         1 << (max98373->i_slot - 8), 0);
 786
 787         /* speaker feedback slot configuration */
 788         regmap_write(max98373->regmap,
 789                 MAX98373_R2023_PCM_TX_SRC_2,
 790                 max98373->spkfb_slot & 0xFF);
 791
 792         /* Set interleave mode */
 793         if (max98373->interleave_mode)
 794                 regmap_update_bits(max98373->regmap,
 795                         MAX98373_R2024_PCM_DATA_FMT_CFG,
 796                         MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 797                         MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 798
 799         /* Speaker enable */
 800         regmap_update_bits(max98373->regmap,
 801                 MAX98373_R2043_AMP_EN,
 802                 MAX98373_SPK_EN_MASK, 1);
 803
 804         return 0;
 805 }
 806
 807 #ifdef CONFIG_PM_SLEEP
 808 static int max98373_suspend(struct device *dev)
 809 {
 810         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 811
 812         regcache_cache_only(max98373->regmap, true);
 813         regcache_mark_dirty(max98373->regmap);
 814         return 0;
 815 }
 816 static int max98373_resume(struct device *dev)
 817 {
 818         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 819
 820         regmap_write(max98373->regmap,
 821                 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
 822         usleep_range(10000, 11000);
 823         regcache_cache_only(max98373->regmap, false);
 824         regcache_sync(max98373->regmap);
 825         return 0;
 826 }
 827 #endif
 828
 829 static const struct dev_pm_ops max98373_pm = {
 830         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 831 };
 832
 833 static const struct snd_soc_component_driver soc_codec_dev_max98373 = {
 834         .probe                  = max98373_probe,
 835         .controls               = max98373_snd_controls,
 836         .num_controls           = ARRAY_SIZE(max98373_snd_controls),
 837         .dapm_widgets           = max98373_dapm_widgets,
 838         .num_dapm_widgets       = ARRAY_SIZE(max98373_dapm_widgets),
 839         .dapm_routes            = max98373_audio_map,
 840         .num_dapm_routes        = ARRAY_SIZE(max98373_audio_map),
 841         .idle_bias_on           = 1,
 842         .use_pmdown_time        = 1,
 843         .endianness             = 1,
 844         .non_legacy_dai_naming  = 1,
 845 };
 846
 847 static const struct regmap_config max98373_regmap = {
 848         .reg_bits = 16,
 849         .val_bits = 8,
 850         .max_register = MAX98373_R21FF_REV_ID,
 851         .reg_defaults  = max98373_reg,
 852         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 853         .readable_reg = max98373_readable_register,
 854         .volatile_reg = max98373_volatile_reg,
 855         .cache_type = REGCACHE_RBTREE,
 856 };
 857
 858 static void max98373_slot_config(struct i2c_client *i2c,
 859         struct max98373_priv *max98373)
 860 {
 861         int value;
 862         struct device *dev = &i2c->dev;
 863
 864         if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
 865                 max98373->v_slot = value & 0xF;
 866         else
 867                 max98373->v_slot = 0;
 868
 869         if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
 870                 max98373->i_slot = value & 0xF;
 871         else
 872                 max98373->i_slot = 1;
 873
 874         if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
 875                 max98373->spkfb_slot = value & 0xF;
 876         else
 877                 max98373->spkfb_slot = 2;
 878 }
 879
 880 static int max98373_i2c_probe(struct i2c_client *i2c,
 881         const struct i2c_device_id *id)
 882 {
 883
 884         int ret = 0;
 885         int reg = 0;
 886         struct max98373_priv *max98373 = NULL;
 887
 888         max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
 889
 890         if (!max98373) {
 891                 ret = -ENOMEM;
 892                 return ret;
 893         }
 894         i2c_set_clientdata(i2c, max98373);
 895
 896         /* update interleave mode info */
 897         if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
 898                 max98373->interleave_mode = 1;
 899         else
 900                 max98373->interleave_mode = 0;
 901
 902
 903         /* regmap initialization */
 904         max98373->regmap
 905                 = devm_regmap_init_i2c(i2c, &max98373_regmap);
 906         if (IS_ERR(max98373->regmap)) {
 907                 ret = PTR_ERR(max98373->regmap);
 908                 dev_err(&i2c->dev,
 909                         "Failed to allocate regmap: %d\n", ret);
 910                 return ret;
 911         }
 912
 913         /* Check Revision ID */
 914         ret = regmap_read(max98373->regmap,
 915                 MAX98373_R21FF_REV_ID, &reg);
 916         if (ret < 0) {
 917                 dev_err(&i2c->dev,
 918                         "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
 919                 return ret;
 920         }
 921         dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
 922
 923         /* voltage/current slot configuration */
 924         max98373_slot_config(i2c, max98373);
 925
 926         /* codec registeration */
 927         ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
 928                 max98373_dai, ARRAY_SIZE(max98373_dai));
 929         if (ret < 0)
 930                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
 931
 932         return ret;
 933 }
 934
 935 static const struct i2c_device_id max98373_i2c_id[] = {
 936         { "max98373", 0},
 937         { },
 938 };
 939
 940 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
 941
 942 #if defined(CONFIG_OF)
 943 static const struct of_device_id max98373_of_match[] = {
 944         { .compatible = "maxim,max98373", },
 945         { }
 946 };
 947 MODULE_DEVICE_TABLE(of, max98373_of_match);
 948 #endif
 949
 950 #ifdef CONFIG_ACPI
 951 static const struct acpi_device_id max98373_acpi_match[] = {
 952         { "MX98373", 0 },
 953         {},
 954 };
 955 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 956 #endif
 957
 958 static struct i2c_driver max98373_i2c_driver = {
 959         .driver = {
 960                 .name = "max98373",
 961                 .of_match_table = of_match_ptr(max98373_of_match),
 962                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 963                 .pm = &max98373_pm,
 964         },
 965         .probe = max98373_i2c_probe,
 966         .id_table = max98373_i2c_id,
 967 };
 968
 969 module_i2c_driver(max98373_i2c_driver)
 970
 971 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
 972 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
 973 MODULE_LICENSE("GPL");