sound/soc/codecs/max98373-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2020, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/delay.h>
   6 #include <linux/module.h>
   7 #include <linux/mod_devicetable.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/regmap.h>
  10 #include <linux/slab.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <sound/tlv.h>
  15 #include <linux/of.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include "max98373.h"
  20 #include "max98373-sdw.h"
  21
  22 struct sdw_stream_data {
  23         struct sdw_stream_runtime *sdw_stream;
  24 };
  25
  26 static struct reg_default max98373_reg[] = {
  27         {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
  28         {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
  29         {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
  30         {MAX98373_R0044_SCP_CTRL, 0x00},
  31         {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
  32         {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
  33         {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
  34         {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
  35         {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
  36         {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
  37         {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
  38         {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
  39         {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
  40         {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
  41         {MAX98373_R0100_DP1_INIT_STAT, 0x00},
  42         {MAX98373_R0101_DP1_INIT_MASK, 0x00},
  43         {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
  44         {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
  45         {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
  46         {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
  47         {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
  48         {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
  49         {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
  50         {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
  51         {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
  52         {MAX98373_R0126_DP1_HCTRL, 0x00},
  53         {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
  54         {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
  55         {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
  56         {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
  57         {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
  58         {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
  59         {MAX98373_R0136_DP1_HCTRL, 0x0136},
  60         {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
  61         {MAX98373_R0300_DP3_INIT_STAT, 0x00},
  62         {MAX98373_R0301_DP3_INIT_MASK, 0x00},
  63         {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
  64         {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
  65         {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
  66         {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
  67         {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
  68         {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
  69         {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
  70         {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
  71         {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
  72         {MAX98373_R0326_DP3_HCTRL, 0x00},
  73         {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
  74         {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
  75         {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
  76         {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
  77         {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
  78         {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
  79         {MAX98373_R0336_DP3_HCTRL, 0x00},
  80         {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
  81         {MAX98373_R2000_SW_RESET, 0x00},
  82         {MAX98373_R2001_INT_RAW1, 0x00},
  83         {MAX98373_R2002_INT_RAW2, 0x00},
  84         {MAX98373_R2003_INT_RAW3, 0x00},
  85         {MAX98373_R2004_INT_STATE1, 0x00},
  86         {MAX98373_R2005_INT_STATE2, 0x00},
  87         {MAX98373_R2006_INT_STATE3, 0x00},
  88         {MAX98373_R2007_INT_FLAG1, 0x00},
  89         {MAX98373_R2008_INT_FLAG2, 0x00},
  90         {MAX98373_R2009_INT_FLAG3, 0x00},
  91         {MAX98373_R200A_INT_EN1, 0x00},
  92         {MAX98373_R200B_INT_EN2, 0x00},
  93         {MAX98373_R200C_INT_EN3, 0x00},
  94         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  95         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  96         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  97         {MAX98373_R2010_IRQ_CTRL, 0x00},
  98         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  99         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
 100         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
 101         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
 102         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
 103         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
 104         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
 105         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
 106         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
 107         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
 108         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
 109         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
 110         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
 111         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
 112         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
 113         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
 114         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
 115         {MAX98373_R202B_PCM_RX_EN, 0x00},
 116         {MAX98373_R202C_PCM_TX_EN, 0x00},
 117         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
 118         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
 119         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
 120         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
 121         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
 122         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
 123         {MAX98373_R2035_ICC_TX_EN, 0x00},
 124         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
 125         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
 126         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
 127         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
 128         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
 129         {MAX98373_R2041_AMP_CFG, 0x03},
 130         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
 131         {MAX98373_R2043_AMP_EN, 0x00},
 132         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
 133         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
 134         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
 135         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
 136         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
 137         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
 138         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
 139         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
 140         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
 141         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
 142         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
 143         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
 144         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
 145         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
 146         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
 147         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
 148         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
 149         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
 150         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
 151         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
 152         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
 153         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
 154         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
 155         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
 156         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
 157         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
 158         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
 159         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
 160         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
 161         {MAX98373_R20B5_BDE_EN, 0x00},
 162         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 163         {MAX98373_R20D1_DHT_CFG, 0x01},
 164         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 165         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 166         {MAX98373_R20D4_DHT_EN, 0x00},
 167         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 168         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 169         {MAX98373_R20E2_LIMITER_EN, 0x00},
 170         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 171         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 172         {MAX98373_R21FF_REV_ID, 0x42},
 173 };
 174
 175 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 176 {
 177         switch (reg) {
 178         case MAX98373_R21FF_REV_ID:
 179         case MAX98373_R2010_IRQ_CTRL:
 180         /* SoundWire Control Port Registers */
 181         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 182         /* Soundwire Data Port 1 Registers */
 183         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 184         /* Soundwire Data Port 3 Registers */
 185         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 186         case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
 187         case MAX98373_R2014_THERM_WARN_THRESH
 188                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 189         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 190                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 191         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 192         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 193                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 194         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 195                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 196         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 197         case MAX98373_R2097_BDE_L1_THRESH
 198                 ... MAX98373_R209B_BDE_THRESH_HYST:
 199         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 200         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 201         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 202         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 203         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 204                 ... MAX98373_R20FF_GLOBAL_SHDN:
 205                 return true;
 206         default:
 207                 return false;
 208         }
 209 };
 210
 211 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 212 {
 213         switch (reg) {
 214         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 215         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 216         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 217         case MAX98373_R20FF_GLOBAL_SHDN:
 218         case MAX98373_R21FF_REV_ID:
 219         /* SoundWire Control Port Registers */
 220         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 221         /* Soundwire Data Port 1 Registers */
 222         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 223         /* Soundwire Data Port 3 Registers */
 224         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 225         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 226                 return true;
 227         default:
 228                 return false;
 229         }
 230 }
 231
 232 static const struct regmap_config max98373_sdw_regmap = {
 233         .reg_bits = 32,
 234         .val_bits = 8,
 235         .max_register = MAX98373_R21FF_REV_ID,
 236         .reg_defaults  = max98373_reg,
 237         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 238         .readable_reg = max98373_readable_register,
 239         .volatile_reg = max98373_volatile_reg,
 240         .cache_type = REGCACHE_RBTREE,
 241         .use_single_read = true,
 242         .use_single_write = true,
 243 };
 244
 245 /* Power management functions and structure */
 246 static __maybe_unused int max98373_suspend(struct device *dev)
 247 {
 248         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 249
 250         regcache_cache_only(max98373->regmap, true);
 251         regcache_mark_dirty(max98373->regmap);
 252         return 0;
 253 }
 254
 255 static __maybe_unused int max98373_resume(struct device *dev)
 256 {
 257         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 258         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 259         unsigned long time;
 260
 261         if (!max98373->first_hw_init)
 262                 return 0;
 263
 264         if (!slave->unattach_request)
 265                 goto regmap_sync;
 266
 267         time = wait_for_completion_timeout(&slave->initialization_complete,
 268                                            msecs_to_jiffies(2000));
 269         if (!time) {
 270                 dev_err(dev, "Initialization not complete, timed out\n");
 271                 return -ETIMEDOUT;
 272         }
 273
 274 regmap_sync:
 275         slave->unattach_request = 0;
 276         regcache_cache_only(max98373->regmap, false);
 277         regcache_sync(max98373->regmap);
 278
 279         return 0;
 280 }
 281
 282 static const struct dev_pm_ops max98373_pm = {
 283         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 284         SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
 285 };
 286
 287 static int max98373_read_prop(struct sdw_slave *slave)
 288 {
 289         struct sdw_slave_prop *prop = &slave->prop;
 290         int nval, i;
 291         u32 bit;
 292         unsigned long addr;
 293         struct sdw_dpn_prop *dpn;
 294
 295         prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
 296
 297         /* BITMAP: 00001000  Dataport 3 is active */
 298         prop->source_ports = BIT(3);
 299         /* BITMAP: 00000010  Dataport 1 is active */
 300         prop->sink_ports = BIT(1);
 301         prop->paging_support = true;
 302         prop->clk_stop_timeout = 20;
 303
 304         nval = hweight32(prop->source_ports);
 305         prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
 306                                           sizeof(*prop->src_dpn_prop),
 307                                           GFP_KERNEL);
 308         if (!prop->src_dpn_prop)
 309                 return -ENOMEM;
 310
 311         i = 0;
 312         dpn = prop->src_dpn_prop;
 313         addr = prop->source_ports;
 314         for_each_set_bit(bit, &addr, 32) {
 315                 dpn[i].num = bit;
 316                 dpn[i].type = SDW_DPN_FULL;
 317                 dpn[i].simple_ch_prep_sm = true;
 318                 dpn[i].ch_prep_timeout = 10;
 319                 i++;
 320         }
 321
 322         /* do this again for sink now */
 323         nval = hweight32(prop->sink_ports);
 324         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 325                                            sizeof(*prop->sink_dpn_prop),
 326                                            GFP_KERNEL);
 327         if (!prop->sink_dpn_prop)
 328                 return -ENOMEM;
 329
 330         i = 0;
 331         dpn = prop->sink_dpn_prop;
 332         addr = prop->sink_ports;
 333         for_each_set_bit(bit, &addr, 32) {
 334                 dpn[i].num = bit;
 335                 dpn[i].type = SDW_DPN_FULL;
 336                 dpn[i].simple_ch_prep_sm = true;
 337                 dpn[i].ch_prep_timeout = 10;
 338                 i++;
 339         }
 340
 341         /* set the timeout values */
 342         prop->clk_stop_timeout = 20;
 343
 344         return 0;
 345 }
 346
 347 static int max98373_io_init(struct sdw_slave *slave)
 348 {
 349         struct device *dev = &slave->dev;
 350         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 351
 352         if (max98373->first_hw_init) {
 353                 regcache_cache_only(max98373->regmap, false);
 354                 regcache_cache_bypass(max98373->regmap, true);
 355         }
 356
 357         /*
 358          * PM runtime is only enabled when a Slave reports as Attached
 359          */
 360         if (!max98373->first_hw_init) {
 361                 /* set autosuspend parameters */
 362                 pm_runtime_set_autosuspend_delay(dev, 3000);
 363                 pm_runtime_use_autosuspend(dev);
 364
 365                 /* update count of parent 'active' children */
 366                 pm_runtime_set_active(dev);
 367
 368                 /* make sure the device does not suspend immediately */
 369                 pm_runtime_mark_last_busy(dev);
 370
 371                 pm_runtime_enable(dev);
 372         }
 373
 374         pm_runtime_get_noresume(dev);
 375
 376         /* Software Reset */
 377         max98373_reset(max98373, dev);
 378
 379         /* Set soundwire mode */
 380         regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
 381         /* Enable ADC */
 382         regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
 383         /* Set default Soundwire clock */
 384         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
 385         /* Set default sampling rate for speaker and IVDAC */
 386         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 387         /* IV default slot configuration */
 388         regmap_write(max98373->regmap,
 389                      MAX98373_R2020_PCM_TX_HIZ_EN_1,
 390                      0xFF);
 391         regmap_write(max98373->regmap,
 392                      MAX98373_R2021_PCM_TX_HIZ_EN_2,
 393                      0xFF);
 394         /* L/R mix configuration */
 395         regmap_write(max98373->regmap,
 396                      MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 397                      0x80);
 398         regmap_write(max98373->regmap,
 399                      MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 400                      0x1);
 401         /* Enable DC blocker */
 402         regmap_write(max98373->regmap,
 403                      MAX98373_R203F_AMP_DSP_CFG,
 404                      0x3);
 405         /* Enable IMON VMON DC blocker */
 406         regmap_write(max98373->regmap,
 407                      MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 408                      0x7);
 409         /* voltage, current slot configuration */
 410         regmap_write(max98373->regmap,
 411                      MAX98373_R2022_PCM_TX_SRC_1,
 412                      (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 413                      max98373->v_slot) & 0xFF);
 414         if (max98373->v_slot < 8)
 415                 regmap_update_bits(max98373->regmap,
 416                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 417                                    1 << max98373->v_slot, 0);
 418         else
 419                 regmap_update_bits(max98373->regmap,
 420                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 421                                    1 << (max98373->v_slot - 8), 0);
 422
 423         if (max98373->i_slot < 8)
 424                 regmap_update_bits(max98373->regmap,
 425                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 426                                    1 << max98373->i_slot, 0);
 427         else
 428                 regmap_update_bits(max98373->regmap,
 429                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 430                                    1 << (max98373->i_slot - 8), 0);
 431
 432         /* speaker feedback slot configuration */
 433         regmap_write(max98373->regmap,
 434                      MAX98373_R2023_PCM_TX_SRC_2,
 435                      max98373->spkfb_slot & 0xFF);
 436
 437         /* Set interleave mode */
 438         if (max98373->interleave_mode)
 439                 regmap_update_bits(max98373->regmap,
 440                                    MAX98373_R2024_PCM_DATA_FMT_CFG,
 441                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 442                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 443
 444         /* Speaker enable */
 445         regmap_update_bits(max98373->regmap,
 446                            MAX98373_R2043_AMP_EN,
 447                            MAX98373_SPK_EN_MASK, 1);
 448
 449         regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
 450         regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
 451
 452         if (max98373->first_hw_init) {
 453                 regcache_cache_bypass(max98373->regmap, false);
 454                 regcache_mark_dirty(max98373->regmap);
 455         }
 456
 457         max98373->first_hw_init = true;
 458         max98373->hw_init = true;
 459
 460         pm_runtime_mark_last_busy(dev);
 461         pm_runtime_put_autosuspend(dev);
 462
 463         return 0;
 464 }
 465
 466 static int max98373_clock_calculate(struct sdw_slave *slave,
 467                                     unsigned int clk_freq)
 468 {
 469         int x, y;
 470         static const int max98373_clk_family[] = {
 471                 7680000, 8400000, 9600000, 11289600,
 472                 12000000, 12288000, 13000000
 473         };
 474
 475         for (x = 0; x < 4; x++)
 476                 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
 477                         if (clk_freq == (max98373_clk_family[y] >> x))
 478                                 return (x << 3) + y;
 479
 480         /* Set default clock (12.288 Mhz) if the value is not in the list */
 481         dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
 482                 clk_freq);
 483         return 0x5;
 484 }
 485
 486 static int max98373_clock_config(struct sdw_slave *slave,
 487                                  struct sdw_bus_params *params)
 488 {
 489         struct device *dev = &slave->dev;
 490         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 491         unsigned int clk_freq, value;
 492
 493         clk_freq = (params->curr_dr_freq >> 1);
 494
 495         /*
 496          *      Select the proper value for the register based on the
 497          *      requested clock. If the value is not in the list,
 498          *      use reasonable default - 12.288 Mhz
 499          */
 500         value = max98373_clock_calculate(slave, clk_freq);
 501
 502         /* SWCLK */
 503         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
 504
 505         /* The default Sampling Rate value for IV is 48KHz*/
 506         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 507
 508         return 0;
 509 }
 510
 511 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 512 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
 513
 514 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
 515                                       struct snd_pcm_hw_params *params,
 516                                       struct snd_soc_dai *dai)
 517 {
 518         struct snd_soc_component *component = dai->component;
 519         struct max98373_priv *max98373 =
 520                 snd_soc_component_get_drvdata(component);
 521
 522         struct sdw_stream_config stream_config;
 523         struct sdw_port_config port_config;
 524         enum sdw_data_direction direction;
 525         struct sdw_stream_data *stream;
 526         int ret, chan_sz, sampling_rate;
 527
 528         stream = snd_soc_dai_get_dma_data(dai, substream);
 529
 530         if (!stream)
 531                 return -EINVAL;
 532
 533         if (!max98373->slave)
 534                 return -EINVAL;
 535
 536         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 537                 direction = SDW_DATA_DIR_RX;
 538                 port_config.num = 1;
 539         } else {
 540                 direction = SDW_DATA_DIR_TX;
 541                 port_config.num = 3;
 542         }
 543
 544         stream_config.frame_rate = params_rate(params);
 545         stream_config.bps = snd_pcm_format_width(params_format(params));
 546         stream_config.direction = direction;
 547
 548         if (max98373->slot && direction == SDW_DATA_DIR_RX) {
 549                 stream_config.ch_count = max98373->slot;
 550                 port_config.ch_mask = max98373->rx_mask;
 551         } else {
 552                 /* only IV are supported by capture */
 553                 if (direction == SDW_DATA_DIR_TX)
 554                         stream_config.ch_count = 2;
 555                 else
 556                         stream_config.ch_count = params_channels(params);
 557
 558                 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
 559         }
 560
 561         ret = sdw_stream_add_slave(max98373->slave, &stream_config,
 562                                    &port_config, 1, stream->sdw_stream);
 563         if (ret) {
 564                 dev_err(dai->dev, "Unable to configure port\n");
 565                 return ret;
 566         }
 567
 568         if (params_channels(params) > 16) {
 569                 dev_err(component->dev, "Unsupported channels %d\n",
 570                         params_channels(params));
 571                 return -EINVAL;
 572         }
 573
 574         /* Channel size configuration */
 575         switch (snd_pcm_format_width(params_format(params))) {
 576         case 16:
 577                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 578                 break;
 579         case 24:
 580                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 581                 break;
 582         case 32:
 583                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 584                 break;
 585         default:
 586                 dev_err(component->dev, "Channel size unsupported %d\n",
 587                         params_format(params));
 588                 return -EINVAL;
 589         }
 590
 591         max98373->ch_size = snd_pcm_format_width(params_format(params));
 592
 593         regmap_update_bits(max98373->regmap,
 594                            MAX98373_R2024_PCM_DATA_FMT_CFG,
 595                            MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 596
 597         dev_dbg(component->dev, "Format supported %d", params_format(params));
 598
 599         /* Sampling rate configuration */
 600         switch (params_rate(params)) {
 601         case 8000:
 602                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 603                 break;
 604         case 11025:
 605                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 606                 break;
 607         case 12000:
 608                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 609                 break;
 610         case 16000:
 611                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 612                 break;
 613         case 22050:
 614                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 615                 break;
 616         case 24000:
 617                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 618                 break;
 619         case 32000:
 620                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 621                 break;
 622         case 44100:
 623                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 624                 break;
 625         case 48000:
 626                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 627                 break;
 628         case 88200:
 629                 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
 630                 break;
 631         case 96000:
 632                 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
 633                 break;
 634         default:
 635                 dev_err(component->dev, "Rate %d is not supported\n",
 636                         params_rate(params));
 637                 return -EINVAL;
 638         }
 639
 640         /* set correct sampling frequency */
 641         regmap_update_bits(max98373->regmap,
 642                            MAX98373_R2028_PCM_SR_SETUP_2,
 643                            MAX98373_PCM_SR_SET2_SR_MASK,
 644                            sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 645
 646         /* set sampling rate of IV */
 647         regmap_update_bits(max98373->regmap,
 648                            MAX98373_R2028_PCM_SR_SETUP_2,
 649                            MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 650                            sampling_rate);
 651
 652         return 0;
 653 }
 654
 655 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
 656                                 struct snd_soc_dai *dai)
 657 {
 658         struct snd_soc_component *component = dai->component;
 659         struct max98373_priv *max98373 =
 660                 snd_soc_component_get_drvdata(component);
 661         struct sdw_stream_data *stream =
 662                 snd_soc_dai_get_dma_data(dai, substream);
 663
 664         if (!max98373->slave)
 665                 return -EINVAL;
 666
 667         sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
 668         return 0;
 669 }
 670
 671 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
 672                                    void *sdw_stream, int direction)
 673 {
 674         struct sdw_stream_data *stream;
 675
 676         if (!sdw_stream)
 677                 return 0;
 678
 679         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 680         if (!stream)
 681                 return -ENOMEM;
 682
 683         stream->sdw_stream = sdw_stream;
 684
 685         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 686         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 687                 dai->playback_dma_data = stream;
 688         else
 689                 dai->capture_dma_data = stream;
 690
 691         return 0;
 692 }
 693
 694 static void max98373_shutdown(struct snd_pcm_substream *substream,
 695                               struct snd_soc_dai *dai)
 696 {
 697         struct sdw_stream_data *stream;
 698
 699         stream = snd_soc_dai_get_dma_data(dai, substream);
 700         snd_soc_dai_set_dma_data(dai, substream, NULL);
 701         kfree(stream);
 702 }
 703
 704 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 705                                      unsigned int tx_mask,
 706                                      unsigned int rx_mask,
 707                                      int slots, int slot_width)
 708 {
 709         struct snd_soc_component *component = dai->component;
 710         struct max98373_priv *max98373 =
 711                 snd_soc_component_get_drvdata(component);
 712
 713         /* tx_mask is unused since it's irrelevant for I/V feedback */
 714         if (tx_mask)
 715                 return -EINVAL;
 716
 717         if (!rx_mask && !slots && !slot_width)
 718                 max98373->tdm_mode = false;
 719         else
 720                 max98373->tdm_mode = true;
 721
 722         max98373->rx_mask = rx_mask;
 723         max98373->slot = slots;
 724
 725         return 0;
 726 }
 727
 728 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
 729         .hw_params = max98373_sdw_dai_hw_params,
 730         .hw_free = max98373_pcm_hw_free,
 731         .set_stream = max98373_set_sdw_stream,
 732         .shutdown = max98373_shutdown,
 733         .set_tdm_slot = max98373_sdw_set_tdm_slot,
 734 };
 735
 736 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
 737         {
 738                 .name = "max98373-aif1",
 739                 .playback = {
 740                         .stream_name = "HiFi Playback",
 741                         .channels_min = 1,
 742                         .channels_max = 2,
 743                         .rates = MAX98373_RATES,
 744                         .formats = MAX98373_FORMATS,
 745                 },
 746                 .capture = {
 747                         .stream_name = "HiFi Capture",
 748                         .channels_min = 1,
 749                         .channels_max = 2,
 750                         .rates = MAX98373_RATES,
 751                         .formats = MAX98373_FORMATS,
 752                 },
 753                 .ops = &max98373_dai_sdw_ops,
 754         }
 755 };
 756
 757 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
 758 {
 759         struct max98373_priv *max98373;
 760         int ret;
 761         struct device *dev = &slave->dev;
 762
 763         /*  Allocate and assign private driver data structure  */
 764         max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
 765         if (!max98373)
 766                 return -ENOMEM;
 767
 768         dev_set_drvdata(dev, max98373);
 769         max98373->regmap = regmap;
 770         max98373->slave = slave;
 771
 772         /* Read voltage and slot configuration */
 773         max98373_slot_config(dev, max98373);
 774
 775         max98373->hw_init = false;
 776         max98373->first_hw_init = false;
 777
 778         /* codec registration  */
 779         ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
 780                                               max98373_sdw_dai,
 781                                               ARRAY_SIZE(max98373_sdw_dai));
 782         if (ret < 0)
 783                 dev_err(dev, "Failed to register codec: %d\n", ret);
 784
 785         return ret;
 786 }
 787
 788 static int max98373_update_status(struct sdw_slave *slave,
 789                                   enum sdw_slave_status status)
 790 {
 791         struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
 792
 793         if (status == SDW_SLAVE_UNATTACHED)
 794                 max98373->hw_init = false;
 795
 796         /*
 797          * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
 798          */
 799         if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
 800                 return 0;
 801
 802         /* perform I/O transfers required for Slave initialization */
 803         return max98373_io_init(slave);
 804 }
 805
 806 static int max98373_bus_config(struct sdw_slave *slave,
 807                                struct sdw_bus_params *params)
 808 {
 809         int ret;
 810
 811         ret = max98373_clock_config(slave, params);
 812         if (ret < 0)
 813                 dev_err(&slave->dev, "Invalid clk config");
 814
 815         return ret;
 816 }
 817
 818 /*
 819  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 820  * port_prep are not defined for now
 821  */
 822 static struct sdw_slave_ops max98373_slave_ops = {
 823         .read_prop = max98373_read_prop,
 824         .update_status = max98373_update_status,
 825         .bus_config = max98373_bus_config,
 826 };
 827
 828 static int max98373_sdw_probe(struct sdw_slave *slave,
 829                               const struct sdw_device_id *id)
 830 {
 831         struct regmap *regmap;
 832
 833         /* Regmap Initialization */
 834         regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
 835         if (IS_ERR(regmap))
 836                 return PTR_ERR(regmap);
 837
 838         return max98373_init(slave, regmap);
 839 }
 840
 841 #if defined(CONFIG_OF)
 842 static const struct of_device_id max98373_of_match[] = {
 843         { .compatible = "maxim,max98373", },
 844         {},
 845 };
 846 MODULE_DEVICE_TABLE(of, max98373_of_match);
 847 #endif
 848
 849 #ifdef CONFIG_ACPI
 850 static const struct acpi_device_id max98373_acpi_match[] = {
 851         { "MX98373", 0 },
 852         {},
 853 };
 854 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 855 #endif
 856
 857 static const struct sdw_device_id max98373_id[] = {
 858         SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
 859         {},
 860 };
 861 MODULE_DEVICE_TABLE(sdw, max98373_id);
 862
 863 static struct sdw_driver max98373_sdw_driver = {
 864         .driver = {
 865                 .name = "max98373",
 866                 .owner = THIS_MODULE,
 867                 .of_match_table = of_match_ptr(max98373_of_match),
 868                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 869                 .pm = &max98373_pm,
 870         },
 871         .probe = max98373_sdw_probe,
 872         .remove = NULL,
 873         .ops = &max98373_slave_ops,
 874         .id_table = max98373_id,
 875 };
 876
 877 module_sdw_driver(max98373_sdw_driver);
 878
 879 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
 880 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
 881 MODULE_LICENSE("GPL v2");