sound/soc/codecs/lpass-rx-macro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/init.h>
   6 #include <linux/io.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/clk.h>
  10 #include <sound/soc.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc-dapm.h>
  14 #include <sound/tlv.h>
  15 #include <linux/of_clk.h>
  16 #include <linux/clk-provider.h>
  17
  18 #include "lpass-macro-common.h"
  19
  20 #define CDC_RX_TOP_TOP_CFG0             (0x0000)
  21 #define CDC_RX_TOP_SWR_CTRL             (0x0008)
  22 #define CDC_RX_TOP_DEBUG                (0x000C)
  23 #define CDC_RX_TOP_DEBUG_BUS            (0x0010)
  24 #define CDC_RX_TOP_DEBUG_EN0            (0x0014)
  25 #define CDC_RX_TOP_DEBUG_EN1            (0x0018)
  26 #define CDC_RX_TOP_DEBUG_EN2            (0x001C)
  27 #define CDC_RX_TOP_HPHL_COMP_WR_LSB     (0x0020)
  28 #define CDC_RX_TOP_HPHL_COMP_WR_MSB     (0x0024)
  29 #define CDC_RX_TOP_HPHL_COMP_LUT        (0x0028)
  30 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK  BIT(7)
  31 #define CDC_RX_TOP_HPHL_COMP_RD_LSB     (0x002C)
  32 #define CDC_RX_TOP_HPHL_COMP_RD_MSB     (0x0030)
  33 #define CDC_RX_TOP_HPHR_COMP_WR_LSB     (0x0034)
  34 #define CDC_RX_TOP_HPHR_COMP_WR_MSB     (0x0038)
  35 #define CDC_RX_TOP_HPHR_COMP_LUT        (0x003C)
  36 #define CDC_RX_TOP_HPHR_COMP_RD_LSB     (0x0040)
  37 #define CDC_RX_TOP_HPHR_COMP_RD_MSB     (0x0044)
  38 #define CDC_RX_TOP_DSD0_DEBUG_CFG0      (0x0070)
  39 #define CDC_RX_TOP_DSD0_DEBUG_CFG1      (0x0074)
  40 #define CDC_RX_TOP_DSD0_DEBUG_CFG2      (0x0078)
  41 #define CDC_RX_TOP_DSD0_DEBUG_CFG3      (0x007C)
  42 #define CDC_RX_TOP_DSD1_DEBUG_CFG0      (0x0080)
  43 #define CDC_RX_TOP_DSD1_DEBUG_CFG1      (0x0084)
  44 #define CDC_RX_TOP_DSD1_DEBUG_CFG2      (0x0088)
  45 #define CDC_RX_TOP_DSD1_DEBUG_CFG3      (0x008C)
  46 #define CDC_RX_TOP_RX_I2S_CTL           (0x0090)
  47 #define CDC_RX_TOP_TX_I2S2_CTL          (0x0094)
  48 #define CDC_RX_TOP_I2S_CLK              (0x0098)
  49 #define CDC_RX_TOP_I2S_RESET            (0x009C)
  50 #define CDC_RX_TOP_I2S_MUX              (0x00A0)
  51 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL        (0x0100)
  52 #define CDC_RX_CLK_MCLK_EN_MASK         BIT(0)
  53 #define CDC_RX_CLK_MCLK_ENABLE          BIT(0)
  54 #define CDC_RX_CLK_MCLK2_EN_MASK        BIT(1)
  55 #define CDC_RX_CLK_MCLK2_ENABLE         BIT(1)
  56 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL      (0x0104)
  57 #define CDC_RX_FS_MCLK_CNT_EN_MASK      BIT(0)
  58 #define CDC_RX_FS_MCLK_CNT_ENABLE       BIT(0)
  59 #define CDC_RX_FS_MCLK_CNT_CLR_MASK     BIT(1)
  60 #define CDC_RX_FS_MCLK_CNT_CLR          BIT(1)
  61 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
  62 #define CDC_RX_SWR_CLK_EN_MASK          BIT(0)
  63 #define CDC_RX_SWR_RESET_MASK           BIT(1)
  64 #define CDC_RX_SWR_RESET                BIT(1)
  65 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
  66 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL  (0x0110)
  67 #define CDC_RX_SOFTCLIP_CRC             (0x0140)
  68 #define CDC_RX_SOFTCLIP_CLK_EN_MASK     BIT(0)
  69 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL   (0x0144)
  70 #define CDC_RX_SOFTCLIP_EN_MASK         BIT(0)
  71 #define CDC_RX_INP_MUX_RX_INT0_CFG0     (0x0180)
  72 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
  73 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)
  74 #define CDC_RX_INP_MUX_RX_INT0_CFG1     (0x0184)
  75 #define CDC_RX_INTX_2_SEL_MASK          GENMASK(3, 0)
  76 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)
  77 #define CDC_RX_INP_MUX_RX_INT1_CFG0     (0x0188)
  78 #define CDC_RX_INP_MUX_RX_INT1_CFG1     (0x018C)
  79 #define CDC_RX_INP_MUX_RX_INT2_CFG0     (0x0190)
  80 #define CDC_RX_INP_MUX_RX_INT2_CFG1     (0x0194)
  81 #define CDC_RX_INP_MUX_RX_MIX_CFG4      (0x0198)
  82 #define CDC_RX_INP_MUX_RX_MIX_CFG5      (0x019C)
  83 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0        (0x01A0)
  84 #define CDC_RX_CLSH_CRC                 (0x0200)
  85 #define CDC_RX_CLSH_CLK_EN_MASK         BIT(0)
  86 #define CDC_RX_CLSH_DLY_CTRL            (0x0204)
  87 #define CDC_RX_CLSH_DECAY_CTRL          (0x0208)
  88 #define CDC_RX_CLSH_DECAY_RATE_MASK     GENMASK(2, 0)
  89 #define CDC_RX_CLSH_HPH_V_PA            (0x020C)
  90 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK   GENMASK(5, 0)
  91 #define CDC_RX_CLSH_EAR_V_PA            (0x0210)
  92 #define CDC_RX_CLSH_HPH_V_HD            (0x0214)
  93 #define CDC_RX_CLSH_EAR_V_HD            (0x0218)
  94 #define CDC_RX_CLSH_K1_MSB              (0x021C)
  95 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK   GENMASK(3, 0)
  96 #define CDC_RX_CLSH_K1_LSB              (0x0220)
  97 #define CDC_RX_CLSH_K2_MSB              (0x0224)
  98 #define CDC_RX_CLSH_K2_LSB              (0x0228)
  99 #define CDC_RX_CLSH_IDLE_CTRL           (0x022C)
 100 #define CDC_RX_CLSH_IDLE_HPH            (0x0230)
 101 #define CDC_RX_CLSH_IDLE_EAR            (0x0234)
 102 #define CDC_RX_CLSH_TEST0               (0x0238)
 103 #define CDC_RX_CLSH_TEST1               (0x023C)
 104 #define CDC_RX_CLSH_OVR_VREF            (0x0240)
 105 #define CDC_RX_CLSH_CLSG_CTL            (0x0244)
 106 #define CDC_RX_CLSH_CLSG_CFG1           (0x0248)
 107 #define CDC_RX_CLSH_CLSG_CFG2           (0x024C)
 108 #define CDC_RX_BCL_VBAT_PATH_CTL        (0x0280)
 109 #define CDC_RX_BCL_VBAT_CFG             (0x0284)
 110 #define CDC_RX_BCL_VBAT_ADC_CAL1        (0x0288)
 111 #define CDC_RX_BCL_VBAT_ADC_CAL2        (0x028C)
 112 #define CDC_RX_BCL_VBAT_ADC_CAL3        (0x0290)
 113 #define CDC_RX_BCL_VBAT_PK_EST1         (0x0294)
 114 #define CDC_RX_BCL_VBAT_PK_EST2         (0x0298)
 115 #define CDC_RX_BCL_VBAT_PK_EST3         (0x029C)
 116 #define CDC_RX_BCL_VBAT_RF_PROC1        (0x02A0)
 117 #define CDC_RX_BCL_VBAT_RF_PROC2        (0x02A4)
 118 #define CDC_RX_BCL_VBAT_TAC1            (0x02A8)
 119 #define CDC_RX_BCL_VBAT_TAC2            (0x02AC)
 120 #define CDC_RX_BCL_VBAT_TAC3            (0x02B0)
 121 #define CDC_RX_BCL_VBAT_TAC4            (0x02B4)
 122 #define CDC_RX_BCL_VBAT_GAIN_UPD1       (0x02B8)
 123 #define CDC_RX_BCL_VBAT_GAIN_UPD2       (0x02BC)
 124 #define CDC_RX_BCL_VBAT_GAIN_UPD3       (0x02C0)
 125 #define CDC_RX_BCL_VBAT_GAIN_UPD4       (0x02C4)
 126 #define CDC_RX_BCL_VBAT_GAIN_UPD5       (0x02C8)
 127 #define CDC_RX_BCL_VBAT_DEBUG1          (0x02CC)
 128 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON    (0x02D0)
 129 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL    (0x02D4)
 130 #define CDC_RX_BCL_VBAT_BAN             (0x02D8)
 131 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1   (0x02DC)
 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2   (0x02E0)
 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3   (0x02E4)
 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4   (0x02E8)
 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5   (0x02EC)
 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6   (0x02F0)
 137 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7   (0x02F4)
 138 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8   (0x02F8)
 139 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9   (0x02FC)
 140 #define CDC_RX_BCL_VBAT_ATTN1           (0x0300)
 141 #define CDC_RX_BCL_VBAT_ATTN2           (0x0304)
 142 #define CDC_RX_BCL_VBAT_ATTN3           (0x0308)
 143 #define CDC_RX_BCL_VBAT_DECODE_CTL1     (0x030C)
 144 #define CDC_RX_BCL_VBAT_DECODE_CTL2     (0x0310)
 145 #define CDC_RX_BCL_VBAT_DECODE_CFG1     (0x0314)
 146 #define CDC_RX_BCL_VBAT_DECODE_CFG2     (0x0318)
 147 #define CDC_RX_BCL_VBAT_DECODE_CFG3     (0x031C)
 148 #define CDC_RX_BCL_VBAT_DECODE_CFG4     (0x0320)
 149 #define CDC_RX_BCL_VBAT_DECODE_ST       (0x0324)
 150 #define CDC_RX_INTR_CTRL_CFG            (0x0340)
 151 #define CDC_RX_INTR_CTRL_CLR_COMMIT     (0x0344)
 152 #define CDC_RX_INTR_CTRL_PIN1_MASK0     (0x0360)
 153 #define CDC_RX_INTR_CTRL_PIN1_STATUS0   (0x0368)
 154 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0    (0x0370)
 155 #define CDC_RX_INTR_CTRL_PIN2_MASK0     (0x0380)
 156 #define CDC_RX_INTR_CTRL_PIN2_STATUS0   (0x0388)
 157 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0    (0x0390)
 158 #define CDC_RX_INTR_CTRL_LEVEL0         (0x03C0)
 159 #define CDC_RX_INTR_CTRL_BYPASS0        (0x03C8)
 160 #define CDC_RX_INTR_CTRL_SET0           (0x03D0)
 161 #define CDC_RX_RXn_RX_PATH_CTL(n)       (0x0400 + 0x80 * n)
 162 #define CDC_RX_RX0_RX_PATH_CTL          (0x0400)
 163 #define CDC_RX_PATH_RESET_EN_MASK       BIT(6)
 164 #define CDC_RX_PATH_CLK_EN_MASK         BIT(5)
 165 #define CDC_RX_PATH_CLK_ENABLE          BIT(5)
 166 #define CDC_RX_PATH_PGA_MUTE_MASK       BIT(4)
 167 #define CDC_RX_PATH_PGA_MUTE_ENABLE     BIT(4)
 168 #define CDC_RX_PATH_PCM_RATE_MASK       GENMASK(3, 0)
 169 #define CDC_RX_RXn_RX_PATH_CFG0(n)      (0x0404 + 0x80 * n)
 170 #define CDC_RX_RXn_COMP_EN_MASK         BIT(1)
 171 #define CDC_RX_RX0_RX_PATH_CFG0         (0x0404)
 172 #define CDC_RX_RXn_CLSH_EN_MASK         BIT(6)
 173 #define CDC_RX_DLY_ZN_EN_MASK           BIT(3)
 174 #define CDC_RX_DLY_ZN_ENABLE            BIT(3)
 175 #define CDC_RX_RXn_HD2_EN_MASK          BIT(2)
 176 #define CDC_RX_RXn_RX_PATH_CFG1(n)      (0x0408 + 0x80 * n)
 177 #define CDC_RX_RXn_SIDETONE_EN_MASK     BIT(4)
 178 #define CDC_RX_RX0_RX_PATH_CFG1         (0x0408)
 179 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK   BIT(1)
 180 #define CDC_RX_RXn_RX_PATH_CFG2(n)      (0x040C + 0x80 * n)
 181 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK    GENMASK(1, 0)
 182 #define CDC_RX_RX0_RX_PATH_CFG2         (0x040C)
 183 #define CDC_RX_RXn_RX_PATH_CFG3(n)      (0x0410 + 0x80 * n)
 184 #define CDC_RX_RX0_RX_PATH_CFG3         (0x0410)
 185 #define CDC_RX_DC_COEFF_SEL_MASK        GENMASK(1, 0)
 186 #define CDC_RX_DC_COEFF_SEL_TWO         0x2
 187 #define CDC_RX_RXn_RX_VOL_CTL(n)        (0x0414 + 0x80 * n)
 188 #define CDC_RX_RX0_RX_VOL_CTL           (0x0414)
 189 #define CDC_RX_RXn_RX_PATH_MIX_CTL(n)   (0x0418 + 0x80 * n)
 190 #define CDC_RX_RXn_MIX_PCM_RATE_MASK    GENMASK(3, 0)
 191 #define CDC_RX_RXn_MIX_RESET_MASK       BIT(6)
 192 #define CDC_RX_RXn_MIX_RESET            BIT(6)
 193 #define CDC_RX_RXn_MIX_CLK_EN_MASK      BIT(5)
 194 #define CDC_RX_RX0_RX_PATH_MIX_CTL      (0x0418)
 195 #define CDC_RX_RX0_RX_PATH_MIX_CFG      (0x041C)
 196 #define CDC_RX_RXn_RX_VOL_MIX_CTL(n)    (0x0420 + 0x80 * n)
 197 #define CDC_RX_RX0_RX_VOL_MIX_CTL       (0x0420)
 198 #define CDC_RX_RX0_RX_PATH_SEC1         (0x0424)
 199 #define CDC_RX_RX0_RX_PATH_SEC2         (0x0428)
 200 #define CDC_RX_RX0_RX_PATH_SEC3         (0x042C)
 201 #define CDC_RX_RX0_RX_PATH_SEC4         (0x0430)
 202 #define CDC_RX_RX0_RX_PATH_SEC7         (0x0434)
 203 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK   GENMASK(2, 0)
 204 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
 205 #define CDC_RX_RX0_RX_PATH_MIX_SEC0     (0x0438)
 206 #define CDC_RX_RX0_RX_PATH_MIX_SEC1     (0x043C)
 207 #define CDC_RX_RXn_RX_PATH_DSM_CTL(n)   (0x0440 + 0x80 * n)
 208 #define CDC_RX_RXn_DSM_CLK_EN_MASK      BIT(0)
 209 #define CDC_RX_RX0_RX_PATH_DSM_CTL      (0x0440)
 210 #define CDC_RX_RX0_RX_PATH_DSM_DATA1    (0x0444)
 211 #define CDC_RX_RX0_RX_PATH_DSM_DATA2    (0x0448)
 212 #define CDC_RX_RX0_RX_PATH_DSM_DATA3    (0x044C)
 213 #define CDC_RX_RX0_RX_PATH_DSM_DATA4    (0x0450)
 214 #define CDC_RX_RX0_RX_PATH_DSM_DATA5    (0x0454)
 215 #define CDC_RX_RX0_RX_PATH_DSM_DATA6    (0x0458)
 216 #define CDC_RX_RX1_RX_PATH_CTL          (0x0480)
 217 #define CDC_RX_RX1_RX_PATH_CFG0         (0x0484)
 218 #define CDC_RX_RX1_RX_PATH_CFG1         (0x0488)
 219 #define CDC_RX_RX1_RX_PATH_CFG2         (0x048C)
 220 #define CDC_RX_RX1_RX_PATH_CFG3         (0x0490)
 221 #define CDC_RX_RX1_RX_VOL_CTL           (0x0494)
 222 #define CDC_RX_RX1_RX_PATH_MIX_CTL      (0x0498)
 223 #define CDC_RX_RX1_RX_PATH_MIX_CFG      (0x049C)
 224 #define CDC_RX_RX1_RX_VOL_MIX_CTL       (0x04A0)
 225 #define CDC_RX_RX1_RX_PATH_SEC1         (0x04A4)
 226 #define CDC_RX_RX1_RX_PATH_SEC2         (0x04A8)
 227 #define CDC_RX_RX1_RX_PATH_SEC3         (0x04AC)
 228 #define CDC_RX_RXn_HD2_ALPHA_MASK       GENMASK(5, 2)
 229 #define CDC_RX_RX1_RX_PATH_SEC4         (0x04B0)
 230 #define CDC_RX_RX1_RX_PATH_SEC7         (0x04B4)
 231 #define CDC_RX_RX1_RX_PATH_MIX_SEC0     (0x04B8)
 232 #define CDC_RX_RX1_RX_PATH_MIX_SEC1     (0x04BC)
 233 #define CDC_RX_RX1_RX_PATH_DSM_CTL      (0x04C0)
 234 #define CDC_RX_RX1_RX_PATH_DSM_DATA1    (0x04C4)
 235 #define CDC_RX_RX1_RX_PATH_DSM_DATA2    (0x04C8)
 236 #define CDC_RX_RX1_RX_PATH_DSM_DATA3    (0x04CC)
 237 #define CDC_RX_RX1_RX_PATH_DSM_DATA4    (0x04D0)
 238 #define CDC_RX_RX1_RX_PATH_DSM_DATA5    (0x04D4)
 239 #define CDC_RX_RX1_RX_PATH_DSM_DATA6    (0x04D8)
 240 #define CDC_RX_RX2_RX_PATH_CTL          (0x0500)
 241 #define CDC_RX_RX2_RX_PATH_CFG0         (0x0504)
 242 #define CDC_RX_RX2_CLSH_EN_MASK         BIT(4)
 243 #define CDC_RX_RX2_DLY_Z_EN_MASK        BIT(3)
 244 #define CDC_RX_RX2_RX_PATH_CFG1         (0x0508)
 245 #define CDC_RX_RX2_RX_PATH_CFG2         (0x050C)
 246 #define CDC_RX_RX2_RX_PATH_CFG3         (0x0510)
 247 #define CDC_RX_RX2_RX_VOL_CTL           (0x0514)
 248 #define CDC_RX_RX2_RX_PATH_MIX_CTL      (0x0518)
 249 #define CDC_RX_RX2_RX_PATH_MIX_CFG      (0x051C)
 250 #define CDC_RX_RX2_RX_VOL_MIX_CTL       (0x0520)
 251 #define CDC_RX_RX2_RX_PATH_SEC0         (0x0524)
 252 #define CDC_RX_RX2_RX_PATH_SEC1         (0x0528)
 253 #define CDC_RX_RX2_RX_PATH_SEC2         (0x052C)
 254 #define CDC_RX_RX2_RX_PATH_SEC3         (0x0530)
 255 #define CDC_RX_RX2_RX_PATH_SEC4         (0x0534)
 256 #define CDC_RX_RX2_RX_PATH_SEC5         (0x0538)
 257 #define CDC_RX_RX2_RX_PATH_SEC6         (0x053C)
 258 #define CDC_RX_RX2_RX_PATH_SEC7         (0x0540)
 259 #define CDC_RX_RX2_RX_PATH_MIX_SEC0     (0x0544)
 260 #define CDC_RX_RX2_RX_PATH_MIX_SEC1     (0x0548)
 261 #define CDC_RX_RX2_RX_PATH_DSM_CTL      (0x054C)
 262 #define CDC_RX_IDLE_DETECT_PATH_CTL     (0x0780)
 263 #define CDC_RX_IDLE_DETECT_CFG0         (0x0784)
 264 #define CDC_RX_IDLE_DETECT_CFG1         (0x0788)
 265 #define CDC_RX_IDLE_DETECT_CFG2         (0x078C)
 266 #define CDC_RX_IDLE_DETECT_CFG3         (0x0790)
 267 #define CDC_RX_COMPANDERn_CTL0(n)       (0x0800 + 0x40 * n)
 268 #define CDC_RX_COMPANDERn_CLK_EN_MASK   BIT(0)
 269 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)
 270 #define CDC_RX_COMPANDERn_HALT_MASK     BIT(2)
 271 #define CDC_RX_COMPANDER0_CTL0          (0x0800)
 272 #define CDC_RX_COMPANDER0_CTL1          (0x0804)
 273 #define CDC_RX_COMPANDER0_CTL2          (0x0808)
 274 #define CDC_RX_COMPANDER0_CTL3          (0x080C)
 275 #define CDC_RX_COMPANDER0_CTL4          (0x0810)
 276 #define CDC_RX_COMPANDER0_CTL5          (0x0814)
 277 #define CDC_RX_COMPANDER0_CTL6          (0x0818)
 278 #define CDC_RX_COMPANDER0_CTL7          (0x081C)
 279 #define CDC_RX_COMPANDER1_CTL0          (0x0840)
 280 #define CDC_RX_COMPANDER1_CTL1          (0x0844)
 281 #define CDC_RX_COMPANDER1_CTL2          (0x0848)
 282 #define CDC_RX_COMPANDER1_CTL3          (0x084C)
 283 #define CDC_RX_COMPANDER1_CTL4          (0x0850)
 284 #define CDC_RX_COMPANDER1_CTL5          (0x0854)
 285 #define CDC_RX_COMPANDER1_CTL6          (0x0858)
 286 #define CDC_RX_COMPANDER1_CTL7          (0x085C)
 287 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)
 288 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL       (0x0A00)
 289 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL    (0x0A04)
 290 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL    (0x0A08)
 291 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL    (0x0A0C)
 292 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL    (0x0A10)
 293 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL    (0x0A14)
 294 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL    (0x0A18)
 295 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL    (0x0A1C)
 296 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL    (0x0A20)
 297 #define CDC_RX_SIDETONE_IIR0_IIR_CTL            (0x0A24)
 298 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
 299 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL    (0x0A2C)
 300 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL    (0x0A30)
 301 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL       (0x0A80)
 302 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL    (0x0A84)
 303 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL    (0x0A88)
 304 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL    (0x0A8C)
 305 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL    (0x0A90)
 306 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL    (0x0A94)
 307 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL    (0x0A98)
 308 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL    (0x0A9C)
 309 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL    (0x0AA0)
 310 #define CDC_RX_SIDETONE_IIR1_IIR_CTL            (0x0AA4)
 311 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
 312 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL    (0x0AAC)
 313 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL    (0x0AB0)
 314 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0        (0x0B00)
 315 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1        (0x0B04)
 316 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2        (0x0B08)
 317 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3        (0x0B0C)
 318 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0        (0x0B10)
 319 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1        (0x0B14)
 320 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2        (0x0B18)
 321 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3        (0x0B1C)
 322 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL    (0x0B40)
 323 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1   (0x0B44)
 324 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL    (0x0B50)
 325 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1   (0x0B54)
 326 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL    (0x0C00)
 327 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0        (0x0C04)
 328 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL    (0x0C40)
 329 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0        (0x0C44)
 330 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL    (0x0C80)
 331 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0        (0x0C84)
 332 #define CDC_RX_EC_ASRC0_CLK_RST_CTL             (0x0D00)
 333 #define CDC_RX_EC_ASRC0_CTL0                    (0x0D04)
 334 #define CDC_RX_EC_ASRC0_CTL1                    (0x0D08)
 335 #define CDC_RX_EC_ASRC0_FIFO_CTL                (0x0D0C)
 336 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB    (0x0D10)
 337 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB    (0x0D14)
 338 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB    (0x0D18)
 339 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB    (0x0D1C)
 340 #define CDC_RX_EC_ASRC0_STATUS_FIFO             (0x0D20)
 341 #define CDC_RX_EC_ASRC1_CLK_RST_CTL             (0x0D40)
 342 #define CDC_RX_EC_ASRC1_CTL0                    (0x0D44)
 343 #define CDC_RX_EC_ASRC1_CTL1                    (0x0D48)
 344 #define CDC_RX_EC_ASRC1_FIFO_CTL                (0x0D4C)
 345 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB    (0x0D50)
 346 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB    (0x0D54)
 347 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB    (0x0D58)
 348 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB    (0x0D5C)
 349 #define CDC_RX_EC_ASRC1_STATUS_FIFO             (0x0D60)
 350 #define CDC_RX_EC_ASRC2_CLK_RST_CTL             (0x0D80)
 351 #define CDC_RX_EC_ASRC2_CTL0                    (0x0D84)
 352 #define CDC_RX_EC_ASRC2_CTL1                    (0x0D88)
 353 #define CDC_RX_EC_ASRC2_FIFO_CTL                (0x0D8C)
 354 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB    (0x0D90)
 355 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB    (0x0D94)
 356 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB    (0x0D98)
 357 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB    (0x0D9C)
 358 #define CDC_RX_EC_ASRC2_STATUS_FIFO             (0x0DA0)
 359 #define CDC_RX_DSD0_PATH_CTL                    (0x0F00)
 360 #define CDC_RX_DSD0_CFG0                        (0x0F04)
 361 #define CDC_RX_DSD0_CFG1                        (0x0F08)
 362 #define CDC_RX_DSD0_CFG2                        (0x0F0C)
 363 #define CDC_RX_DSD1_PATH_CTL                    (0x0F80)
 364 #define CDC_RX_DSD1_CFG0                        (0x0F84)
 365 #define CDC_RX_DSD1_CFG1                        (0x0F88)
 366 #define CDC_RX_DSD1_CFG2                        (0x0F8C)
 367 #define RX_MAX_OFFSET                           (0x0F8C)
 368
 369 #define MCLK_FREQ               9600000
 370
 371 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 372                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 373                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 374                         SNDRV_PCM_RATE_384000)
 375 /* Fractional Rates */
 376 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
 377                                 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
 378
 379 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 380                 SNDRV_PCM_FMTBIT_S24_LE |\
 381                 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 382
 383 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 384                         SNDRV_PCM_RATE_48000)
 385 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 386                 SNDRV_PCM_FMTBIT_S24_LE |\
 387                 SNDRV_PCM_FMTBIT_S24_3LE)
 388
 389 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2
 390
 391 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0
 392 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f
 393 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f
 394
 395 #define COMP_MAX_COEFF 25
 396 #define RX_NUM_CLKS_MAX 5
 397
 398 struct comp_coeff_val {
 399         u8 lsb;
 400         u8 msb;
 401 };
 402
 403 enum {
 404         HPH_ULP,
 405         HPH_LOHIFI,
 406         HPH_MODE_MAX,
 407 };
 408
 409 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
 410         {
 411                 {0x40, 0x00},
 412                 {0x4C, 0x00},
 413                 {0x5A, 0x00},
 414                 {0x6B, 0x00},
 415                 {0x7F, 0x00},
 416                 {0x97, 0x00},
 417                 {0xB3, 0x00},
 418                 {0xD5, 0x00},
 419                 {0xFD, 0x00},
 420                 {0x2D, 0x01},
 421                 {0x66, 0x01},
 422                 {0xA7, 0x01},
 423                 {0xF8, 0x01},
 424                 {0x57, 0x02},
 425                 {0xC7, 0x02},
 426                 {0x4B, 0x03},
 427                 {0xE9, 0x03},
 428                 {0xA3, 0x04},
 429                 {0x7D, 0x05},
 430                 {0x90, 0x06},
 431                 {0xD1, 0x07},
 432                 {0x49, 0x09},
 433                 {0x00, 0x0B},
 434                 {0x01, 0x0D},
 435                 {0x59, 0x0F},
 436         },
 437         {
 438                 {0x40, 0x00},
 439                 {0x4C, 0x00},
 440                 {0x5A, 0x00},
 441                 {0x6B, 0x00},
 442                 {0x80, 0x00},
 443                 {0x98, 0x00},
 444                 {0xB4, 0x00},
 445                 {0xD5, 0x00},
 446                 {0xFE, 0x00},
 447                 {0x2E, 0x01},
 448                 {0x66, 0x01},
 449                 {0xA9, 0x01},
 450                 {0xF8, 0x01},
 451                 {0x56, 0x02},
 452                 {0xC4, 0x02},
 453                 {0x4F, 0x03},
 454                 {0xF0, 0x03},
 455                 {0xAE, 0x04},
 456                 {0x8B, 0x05},
 457                 {0x8E, 0x06},
 458                 {0xBC, 0x07},
 459                 {0x56, 0x09},
 460                 {0x0F, 0x0B},
 461                 {0x13, 0x0D},
 462                 {0x6F, 0x0F},
 463         },
 464 };
 465
 466 struct rx_macro_reg_mask_val {
 467         u16 reg;
 468         u8 mask;
 469         u8 val;
 470 };
 471
 472 enum {
 473         INTERP_HPHL,
 474         INTERP_HPHR,
 475         INTERP_AUX,
 476         INTERP_MAX
 477 };
 478
 479 enum {
 480         RX_MACRO_RX0,
 481         RX_MACRO_RX1,
 482         RX_MACRO_RX2,
 483         RX_MACRO_RX3,
 484         RX_MACRO_RX4,
 485         RX_MACRO_RX5,
 486         RX_MACRO_PORTS_MAX
 487 };
 488
 489 enum {
 490         RX_MACRO_COMP1, /* HPH_L */
 491         RX_MACRO_COMP2, /* HPH_R */
 492         RX_MACRO_COMP_MAX
 493 };
 494
 495 enum {
 496         RX_MACRO_EC0_MUX = 0,
 497         RX_MACRO_EC1_MUX,
 498         RX_MACRO_EC2_MUX,
 499         RX_MACRO_EC_MUX_MAX,
 500 };
 501
 502 enum {
 503         INTn_1_INP_SEL_ZERO = 0,
 504         INTn_1_INP_SEL_DEC0,
 505         INTn_1_INP_SEL_DEC1,
 506         INTn_1_INP_SEL_IIR0,
 507         INTn_1_INP_SEL_IIR1,
 508         INTn_1_INP_SEL_RX0,
 509         INTn_1_INP_SEL_RX1,
 510         INTn_1_INP_SEL_RX2,
 511         INTn_1_INP_SEL_RX3,
 512         INTn_1_INP_SEL_RX4,
 513         INTn_1_INP_SEL_RX5,
 514 };
 515
 516 enum {
 517         INTn_2_INP_SEL_ZERO = 0,
 518         INTn_2_INP_SEL_RX0,
 519         INTn_2_INP_SEL_RX1,
 520         INTn_2_INP_SEL_RX2,
 521         INTn_2_INP_SEL_RX3,
 522         INTn_2_INP_SEL_RX4,
 523         INTn_2_INP_SEL_RX5,
 524 };
 525
 526 enum {
 527         INTERP_MAIN_PATH,
 528         INTERP_MIX_PATH,
 529 };
 530
 531 /* Codec supports 2 IIR filters */
 532 enum {
 533         IIR0 = 0,
 534         IIR1,
 535         IIR_MAX,
 536 };
 537
 538 /* Each IIR has 5 Filter Stages */
 539 enum {
 540         BAND1 = 0,
 541         BAND2,
 542         BAND3,
 543         BAND4,
 544         BAND5,
 545         BAND_MAX,
 546 };
 547
 548 #define RX_MACRO_IIR_FILTER_SIZE        (sizeof(u32) * BAND_MAX)
 549
 550 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
 551 { \
 552         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 553         .info = rx_macro_iir_filter_info, \
 554         .get = rx_macro_get_iir_band_audio_mixer, \
 555         .put = rx_macro_put_iir_band_audio_mixer, \
 556         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 557                 .iir_idx = iidx, \
 558                 .band_idx = bidx, \
 559                 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
 560         } \
 561 }
 562
 563 struct interp_sample_rate {
 564         int sample_rate;
 565         int rate_val;
 566 };
 567
 568 static struct interp_sample_rate sr_val_tbl[] = {
 569         {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
 570         {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
 571         {176400, 0xB}, {352800, 0xC},
 572 };
 573
 574 enum {
 575         RX_MACRO_AIF_INVALID = 0,
 576         RX_MACRO_AIF1_PB,
 577         RX_MACRO_AIF2_PB,
 578         RX_MACRO_AIF3_PB,
 579         RX_MACRO_AIF4_PB,
 580         RX_MACRO_AIF_ECHO,
 581         RX_MACRO_MAX_DAIS,
 582 };
 583
 584 enum {
 585         RX_MACRO_AIF1_CAP = 0,
 586         RX_MACRO_AIF2_CAP,
 587         RX_MACRO_AIF3_CAP,
 588         RX_MACRO_MAX_AIF_CAP_DAIS
 589 };
 590
 591 struct rx_macro {
 592         struct device *dev;
 593         int comp_enabled[RX_MACRO_COMP_MAX];
 594         /* Main path clock users count */
 595         int main_clk_users[INTERP_MAX];
 596         int rx_port_value[RX_MACRO_PORTS_MAX];
 597         u16 prim_int_users[INTERP_MAX];
 598         int rx_mclk_users;
 599         bool reset_swr;
 600         int clsh_users;
 601         int rx_mclk_cnt;
 602         bool is_ear_mode_on;
 603         bool hph_pwr_mode;
 604         bool hph_hd2_mode;
 605         struct snd_soc_component *component;
 606         unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
 607         unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
 608         u16 bit_width[RX_MACRO_MAX_DAIS];
 609         int is_softclip_on;
 610         int is_aux_hpf_on;
 611         int softclip_clk_users;
 612         struct lpass_macro *pds;
 613         struct regmap *regmap;
 614         struct clk *mclk;
 615         struct clk *npl;
 616         struct clk *macro;
 617         struct clk *dcodec;
 618         struct clk *fsgen;
 619         struct clk_hw hw;
 620 };
 621 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
 622
 623 struct wcd_iir_filter_ctl {
 624         unsigned int iir_idx;
 625         unsigned int band_idx;
 626         struct soc_bytes_ext bytes_ext;
 627 };
 628
 629 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 630
 631 static const char * const rx_int_mix_mux_text[] = {
 632         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 633 };
 634
 635 static const char * const rx_prim_mix_text[] = {
 636         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 637         "RX3", "RX4", "RX5"
 638 };
 639
 640 static const char * const rx_sidetone_mix_text[] = {
 641         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 642 };
 643
 644 static const char * const iir_inp_mux_text[] = {
 645         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
 646         "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 647 };
 648
 649 static const char * const rx_int_dem_inp_mux_text[] = {
 650         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 651 };
 652
 653 static const char * const rx_int0_1_interp_mux_text[] = {
 654         "ZERO", "RX INT0_1 MIX1",
 655 };
 656
 657 static const char * const rx_int1_1_interp_mux_text[] = {
 658         "ZERO", "RX INT1_1 MIX1",
 659 };
 660
 661 static const char * const rx_int2_1_interp_mux_text[] = {
 662         "ZERO", "RX INT2_1 MIX1",
 663 };
 664
 665 static const char * const rx_int0_2_interp_mux_text[] = {
 666         "ZERO", "RX INT0_2 MUX",
 667 };
 668
 669 static const char * const rx_int1_2_interp_mux_text[] = {
 670         "ZERO", "RX INT1_2 MUX",
 671 };
 672
 673 static const char * const rx_int2_2_interp_mux_text[] = {
 674         "ZERO", "RX INT2_2 MUX",
 675 };
 676
 677 static const char *const rx_macro_mux_text[] = {
 678         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
 679 };
 680
 681 static const char *const rx_macro_hph_pwr_mode_text[] = {
 682         "ULP", "LOHIFI"
 683 };
 684
 685 static const char * const rx_echo_mux_text[] = {
 686         "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
 687 };
 688
 689 static const struct soc_enum rx_macro_hph_pwr_mode_enum =
 690                 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
 691 static const struct soc_enum rx_mix_tx2_mux_enum =
 692                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
 693 static const struct soc_enum rx_mix_tx1_mux_enum =
 694                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
 695 static const struct soc_enum rx_mix_tx0_mux_enum =
 696                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
 697
 698 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
 699                             rx_int_mix_mux_text);
 700 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
 701                             rx_int_mix_mux_text);
 702 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
 703                             rx_int_mix_mux_text);
 704
 705 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
 706                             rx_prim_mix_text);
 707 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
 708                             rx_prim_mix_text);
 709 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
 710                             rx_prim_mix_text);
 711 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
 712                             rx_prim_mix_text);
 713 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
 714                             rx_prim_mix_text);
 715 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
 716                             rx_prim_mix_text);
 717 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
 718                             rx_prim_mix_text);
 719 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
 720                             rx_prim_mix_text);
 721 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
 722                             rx_prim_mix_text);
 723
 724 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
 725                             rx_sidetone_mix_text);
 726 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
 727                             rx_sidetone_mix_text);
 728 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
 729                             rx_sidetone_mix_text);
 730 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
 731                             iir_inp_mux_text);
 732 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
 733                             iir_inp_mux_text);
 734 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
 735                             iir_inp_mux_text);
 736 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
 737                             iir_inp_mux_text);
 738 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
 739                             iir_inp_mux_text);
 740 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
 741                             iir_inp_mux_text);
 742 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
 743                             iir_inp_mux_text);
 744 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
 745                             iir_inp_mux_text);
 746
 747 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
 748                             rx_int0_1_interp_mux_text);
 749 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
 750                             rx_int1_1_interp_mux_text);
 751 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
 752                             rx_int2_1_interp_mux_text);
 753 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
 754                             rx_int0_2_interp_mux_text);
 755 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
 756                             rx_int1_2_interp_mux_text);
 757 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
 758                             rx_int2_2_interp_mux_text);
 759 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
 760                             rx_int_dem_inp_mux_text);
 761 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
 762                             rx_int_dem_inp_mux_text);
 763
 764 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 765 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 766 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 767 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 768 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 769 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 770
 771 static const struct snd_kcontrol_new rx_mix_tx1_mux =
 772                 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
 773 static const struct snd_kcontrol_new rx_mix_tx2_mux =
 774                 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
 775 static const struct snd_kcontrol_new rx_int0_2_mux =
 776                 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
 777 static const struct snd_kcontrol_new rx_int1_2_mux =
 778                 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
 779 static const struct snd_kcontrol_new rx_int2_2_mux =
 780                 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
 781 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
 782                 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
 783 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
 784                 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
 785 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
 786                 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
 787 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
 788                 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
 789 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
 790                 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
 791 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
 792                 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
 793 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
 794                 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
 795 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
 796                 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
 797 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
 798                 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
 799 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
 800                 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
 801 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
 802                 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
 803 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
 804                 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
 805 static const struct snd_kcontrol_new iir0_inp0_mux =
 806                 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
 807 static const struct snd_kcontrol_new iir0_inp1_mux =
 808                 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
 809 static const struct snd_kcontrol_new iir0_inp2_mux =
 810                 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
 811 static const struct snd_kcontrol_new iir0_inp3_mux =
 812                 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
 813 static const struct snd_kcontrol_new iir1_inp0_mux =
 814                 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
 815 static const struct snd_kcontrol_new iir1_inp1_mux =
 816                 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
 817 static const struct snd_kcontrol_new iir1_inp2_mux =
 818                 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
 819 static const struct snd_kcontrol_new iir1_inp3_mux =
 820                 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
 821 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
 822                 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
 823 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
 824                 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
 825 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
 826                 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
 827 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
 828                 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
 829 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
 830                 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
 831 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
 832                 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
 833 static const struct snd_kcontrol_new rx_mix_tx0_mux =
 834                 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
 835
 836 static const struct reg_default rx_defaults[] = {
 837         /* RX Macro */
 838         { CDC_RX_TOP_TOP_CFG0, 0x00 },
 839         { CDC_RX_TOP_SWR_CTRL, 0x00 },
 840         { CDC_RX_TOP_DEBUG, 0x00 },
 841         { CDC_RX_TOP_DEBUG_BUS, 0x00 },
 842         { CDC_RX_TOP_DEBUG_EN0, 0x00 },
 843         { CDC_RX_TOP_DEBUG_EN1, 0x00 },
 844         { CDC_RX_TOP_DEBUG_EN2, 0x00 },
 845         { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
 846         { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
 847         { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
 848         { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
 849         { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
 850         { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
 851         { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
 852         { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
 853         { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
 854         { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
 855         { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
 856         { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
 857         { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
 858         { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
 859         { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
 860         { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
 861         { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
 862         { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
 863         { CDC_RX_TOP_RX_I2S_CTL, 0x0C },
 864         { CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
 865         { CDC_RX_TOP_I2S_CLK, 0x0C },
 866         { CDC_RX_TOP_I2S_RESET, 0x00 },
 867         { CDC_RX_TOP_I2S_MUX, 0x00 },
 868         { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
 869         { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
 870         { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
 871         { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
 872         { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
 873         { CDC_RX_SOFTCLIP_CRC, 0x00 },
 874         { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
 875         { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
 876         { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
 877         { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
 878         { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
 879         { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
 880         { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
 881         { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
 882         { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
 883         { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
 884         { CDC_RX_CLSH_CRC, 0x00 },
 885         { CDC_RX_CLSH_DLY_CTRL, 0x03 },
 886         { CDC_RX_CLSH_DECAY_CTRL, 0x02 },
 887         { CDC_RX_CLSH_HPH_V_PA, 0x1C },
 888         { CDC_RX_CLSH_EAR_V_PA, 0x39 },
 889         { CDC_RX_CLSH_HPH_V_HD, 0x0C },
 890         { CDC_RX_CLSH_EAR_V_HD, 0x0C },
 891         { CDC_RX_CLSH_K1_MSB, 0x01 },
 892         { CDC_RX_CLSH_K1_LSB, 0x00 },
 893         { CDC_RX_CLSH_K2_MSB, 0x00 },
 894         { CDC_RX_CLSH_K2_LSB, 0x80 },
 895         { CDC_RX_CLSH_IDLE_CTRL, 0x00 },
 896         { CDC_RX_CLSH_IDLE_HPH, 0x00 },
 897         { CDC_RX_CLSH_IDLE_EAR, 0x00 },
 898         { CDC_RX_CLSH_TEST0, 0x07 },
 899         { CDC_RX_CLSH_TEST1, 0x00 },
 900         { CDC_RX_CLSH_OVR_VREF, 0x00 },
 901         { CDC_RX_CLSH_CLSG_CTL, 0x02 },
 902         { CDC_RX_CLSH_CLSG_CFG1, 0x9A },
 903         { CDC_RX_CLSH_CLSG_CFG2, 0x10 },
 904         { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
 905         { CDC_RX_BCL_VBAT_CFG, 0x10 },
 906         { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
 907         { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
 908         { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
 909         { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
 910         { CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
 911         { CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
 912         { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
 913         { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 },
 914         { CDC_RX_BCL_VBAT_TAC1, 0x00 },
 915         { CDC_RX_BCL_VBAT_TAC2, 0x18 },
 916         { CDC_RX_BCL_VBAT_TAC3, 0x18 },
 917         { CDC_RX_BCL_VBAT_TAC4, 0x03 },
 918         { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
 919         { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
 920         { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
 921         { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
 922         { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
 923         { CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
 924         { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
 925         { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
 926         { CDC_RX_BCL_VBAT_BAN, 0x0C },
 927         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
 928         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
 929         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
 930         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
 931         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
 932         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
 933         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
 934         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
 935         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
 936         { CDC_RX_BCL_VBAT_ATTN1, 0x04 },
 937         { CDC_RX_BCL_VBAT_ATTN2, 0x08 },
 938         { CDC_RX_BCL_VBAT_ATTN3, 0x0C },
 939         { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
 940         { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
 941         { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
 942         { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
 943         { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
 944         { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
 945         { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
 946         { CDC_RX_INTR_CTRL_CFG, 0x00 },
 947         { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
 948         { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
 949         { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
 950         { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
 951         { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
 952         { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
 953         { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
 954         { CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
 955         { CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
 956         { CDC_RX_INTR_CTRL_SET0, 0x00 },
 957         { CDC_RX_RX0_RX_PATH_CTL, 0x04 },
 958         { CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
 959         { CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
 960         { CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
 961         { CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
 962         { CDC_RX_RX0_RX_VOL_CTL, 0x00 },
 963         { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
 964         { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
 965         { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
 966         { CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
 967         { CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
 968         { CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
 969         { CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
 970         { CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
 971         { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
 972         { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
 973         { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
 974         { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
 975         { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
 976         { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
 977         { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
 978         { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
 979         { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
 980         { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
 981         { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
 982         { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
 983         { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
 984         { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
 985         { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
 986         { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
 987         { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
 988         { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
 989         { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
 990         { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
 991         { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
 992         { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
 993         { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
 994         { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
 995         { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
 996         { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
 997         { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
 998         { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
 999         { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
1000         { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1001         { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1002         { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1003         { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
1004         { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
1005         { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
1006         { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1007         { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1008         { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1009         { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1010         { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1011         { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1012         { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1013         { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1014         { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1015         { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1016         { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1017         { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1018         { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1019         { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1020         { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1021         { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1022         { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1023         { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1024         { CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1025         { CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1026         { CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1027         { CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1028         { CDC_RX_COMPANDER0_CTL0, 0x60 },
1029         { CDC_RX_COMPANDER0_CTL1, 0xDB },
1030         { CDC_RX_COMPANDER0_CTL2, 0xFF },
1031         { CDC_RX_COMPANDER0_CTL3, 0x35 },
1032         { CDC_RX_COMPANDER0_CTL4, 0xFF },
1033         { CDC_RX_COMPANDER0_CTL5, 0x00 },
1034         { CDC_RX_COMPANDER0_CTL6, 0x01 },
1035         { CDC_RX_COMPANDER0_CTL7, 0x28 },
1036         { CDC_RX_COMPANDER1_CTL0, 0x60 },
1037         { CDC_RX_COMPANDER1_CTL1, 0xDB },
1038         { CDC_RX_COMPANDER1_CTL2, 0xFF },
1039         { CDC_RX_COMPANDER1_CTL3, 0x35 },
1040         { CDC_RX_COMPANDER1_CTL4, 0xFF },
1041         { CDC_RX_COMPANDER1_CTL5, 0x00 },
1042         { CDC_RX_COMPANDER1_CTL6, 0x01 },
1043         { CDC_RX_COMPANDER1_CTL7, 0x28 },
1044         { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1045         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1046         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1047         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1048         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1049         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1050         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1051         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1052         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1053         { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1054         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1055         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1056         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1057         { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1058         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1059         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1060         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1061         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1062         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1063         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1064         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1065         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1066         { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1067         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1068         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1069         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1070         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1071         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1072         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1073         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1074         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1075         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1076         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1077         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1078         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1079         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1080         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1081         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1082         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1083         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1084         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1085         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1086         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1087         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1088         { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1089         { CDC_RX_EC_ASRC0_CTL0, 0x00 },
1090         { CDC_RX_EC_ASRC0_CTL1, 0x00 },
1091         { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1092         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1093         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1094         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1095         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1096         { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1097         { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1098         { CDC_RX_EC_ASRC1_CTL0, 0x00 },
1099         { CDC_RX_EC_ASRC1_CTL1, 0x00 },
1100         { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1101         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1102         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1103         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1104         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1105         { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1106         { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1107         { CDC_RX_EC_ASRC2_CTL0, 0x00 },
1108         { CDC_RX_EC_ASRC2_CTL1, 0x00 },
1109         { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1110         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1111         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1112         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1113         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1114         { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1115         { CDC_RX_DSD0_PATH_CTL, 0x00 },
1116         { CDC_RX_DSD0_CFG0, 0x00 },
1117         { CDC_RX_DSD0_CFG1, 0x62 },
1118         { CDC_RX_DSD0_CFG2, 0x96 },
1119         { CDC_RX_DSD1_PATH_CTL, 0x00 },
1120         { CDC_RX_DSD1_CFG0, 0x00 },
1121         { CDC_RX_DSD1_CFG1, 0x62 },
1122         { CDC_RX_DSD1_CFG2, 0x96 },
1123 };
1124
1125 static bool rx_is_wronly_register(struct device *dev,
1126                                         unsigned int reg)
1127 {
1128         switch (reg) {
1129         case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
1130         case CDC_RX_INTR_CTRL_CLR_COMMIT:
1131         case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
1132         case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
1133                 return true;
1134         }
1135
1136         return false;
1137 }
1138
1139 static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
1140 {
1141         /* Update volatile list for rx/tx macros */
1142         switch (reg) {
1143         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1144         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1145         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1146         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1147         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1148         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1149         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1150         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1151         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1152         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1153         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1154         case CDC_RX_BCL_VBAT_DECODE_ST:
1155         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1156         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1157         case CDC_RX_COMPANDER0_CTL6:
1158         case CDC_RX_COMPANDER1_CTL6:
1159         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1160         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1161         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1162         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1163         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1164         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1165         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1166         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1167         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1168         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1169         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1170         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1171         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1172         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1173         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1174                 return true;
1175         }
1176         return false;
1177 }
1178
1179 static bool rx_is_rw_register(struct device *dev, unsigned int reg)
1180 {
1181         switch (reg) {
1182         case CDC_RX_TOP_TOP_CFG0:
1183         case CDC_RX_TOP_SWR_CTRL:
1184         case CDC_RX_TOP_DEBUG:
1185         case CDC_RX_TOP_DEBUG_BUS:
1186         case CDC_RX_TOP_DEBUG_EN0:
1187         case CDC_RX_TOP_DEBUG_EN1:
1188         case CDC_RX_TOP_DEBUG_EN2:
1189         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1190         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1191         case CDC_RX_TOP_HPHL_COMP_LUT:
1192         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1193         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1194         case CDC_RX_TOP_HPHR_COMP_LUT:
1195         case CDC_RX_TOP_DSD0_DEBUG_CFG0:
1196         case CDC_RX_TOP_DSD0_DEBUG_CFG1:
1197         case CDC_RX_TOP_DSD0_DEBUG_CFG3:
1198         case CDC_RX_TOP_DSD1_DEBUG_CFG0:
1199         case CDC_RX_TOP_DSD1_DEBUG_CFG1:
1200         case CDC_RX_TOP_DSD1_DEBUG_CFG3:
1201         case CDC_RX_TOP_RX_I2S_CTL:
1202         case CDC_RX_TOP_TX_I2S2_CTL:
1203         case CDC_RX_TOP_I2S_CLK:
1204         case CDC_RX_TOP_I2S_RESET:
1205         case CDC_RX_TOP_I2S_MUX:
1206         case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
1207         case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
1208         case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
1209         case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
1210         case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
1211         case CDC_RX_SOFTCLIP_CRC:
1212         case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
1213         case CDC_RX_INP_MUX_RX_INT0_CFG0:
1214         case CDC_RX_INP_MUX_RX_INT0_CFG1:
1215         case CDC_RX_INP_MUX_RX_INT1_CFG0:
1216         case CDC_RX_INP_MUX_RX_INT1_CFG1:
1217         case CDC_RX_INP_MUX_RX_INT2_CFG0:
1218         case CDC_RX_INP_MUX_RX_INT2_CFG1:
1219         case CDC_RX_INP_MUX_RX_MIX_CFG4:
1220         case CDC_RX_INP_MUX_RX_MIX_CFG5:
1221         case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
1222         case CDC_RX_CLSH_CRC:
1223         case CDC_RX_CLSH_DLY_CTRL:
1224         case CDC_RX_CLSH_DECAY_CTRL:
1225         case CDC_RX_CLSH_HPH_V_PA:
1226         case CDC_RX_CLSH_EAR_V_PA:
1227         case CDC_RX_CLSH_HPH_V_HD:
1228         case CDC_RX_CLSH_EAR_V_HD:
1229         case CDC_RX_CLSH_K1_MSB:
1230         case CDC_RX_CLSH_K1_LSB:
1231         case CDC_RX_CLSH_K2_MSB:
1232         case CDC_RX_CLSH_K2_LSB:
1233         case CDC_RX_CLSH_IDLE_CTRL:
1234         case CDC_RX_CLSH_IDLE_HPH:
1235         case CDC_RX_CLSH_IDLE_EAR:
1236         case CDC_RX_CLSH_TEST0:
1237         case CDC_RX_CLSH_TEST1:
1238         case CDC_RX_CLSH_OVR_VREF:
1239         case CDC_RX_CLSH_CLSG_CTL:
1240         case CDC_RX_CLSH_CLSG_CFG1:
1241         case CDC_RX_CLSH_CLSG_CFG2:
1242         case CDC_RX_BCL_VBAT_PATH_CTL:
1243         case CDC_RX_BCL_VBAT_CFG:
1244         case CDC_RX_BCL_VBAT_ADC_CAL1:
1245         case CDC_RX_BCL_VBAT_ADC_CAL2:
1246         case CDC_RX_BCL_VBAT_ADC_CAL3:
1247         case CDC_RX_BCL_VBAT_PK_EST1:
1248         case CDC_RX_BCL_VBAT_PK_EST2:
1249         case CDC_RX_BCL_VBAT_PK_EST3:
1250         case CDC_RX_BCL_VBAT_RF_PROC1:
1251         case CDC_RX_BCL_VBAT_RF_PROC2:
1252         case CDC_RX_BCL_VBAT_TAC1:
1253         case CDC_RX_BCL_VBAT_TAC2:
1254         case CDC_RX_BCL_VBAT_TAC3:
1255         case CDC_RX_BCL_VBAT_TAC4:
1256         case CDC_RX_BCL_VBAT_GAIN_UPD1:
1257         case CDC_RX_BCL_VBAT_GAIN_UPD2:
1258         case CDC_RX_BCL_VBAT_GAIN_UPD3:
1259         case CDC_RX_BCL_VBAT_GAIN_UPD4:
1260         case CDC_RX_BCL_VBAT_GAIN_UPD5:
1261         case CDC_RX_BCL_VBAT_DEBUG1:
1262         case CDC_RX_BCL_VBAT_BAN:
1263         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
1264         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
1265         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
1266         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
1267         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
1268         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
1269         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
1270         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
1271         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
1272         case CDC_RX_BCL_VBAT_ATTN1:
1273         case CDC_RX_BCL_VBAT_ATTN2:
1274         case CDC_RX_BCL_VBAT_ATTN3:
1275         case CDC_RX_BCL_VBAT_DECODE_CTL1:
1276         case CDC_RX_BCL_VBAT_DECODE_CTL2:
1277         case CDC_RX_BCL_VBAT_DECODE_CFG1:
1278         case CDC_RX_BCL_VBAT_DECODE_CFG2:
1279         case CDC_RX_BCL_VBAT_DECODE_CFG3:
1280         case CDC_RX_BCL_VBAT_DECODE_CFG4:
1281         case CDC_RX_INTR_CTRL_CFG:
1282         case CDC_RX_INTR_CTRL_PIN1_MASK0:
1283         case CDC_RX_INTR_CTRL_PIN2_MASK0:
1284         case CDC_RX_INTR_CTRL_LEVEL0:
1285         case CDC_RX_INTR_CTRL_BYPASS0:
1286         case CDC_RX_INTR_CTRL_SET0:
1287         case CDC_RX_RX0_RX_PATH_CTL:
1288         case CDC_RX_RX0_RX_PATH_CFG0:
1289         case CDC_RX_RX0_RX_PATH_CFG1:
1290         case CDC_RX_RX0_RX_PATH_CFG2:
1291         case CDC_RX_RX0_RX_PATH_CFG3:
1292         case CDC_RX_RX0_RX_VOL_CTL:
1293         case CDC_RX_RX0_RX_PATH_MIX_CTL:
1294         case CDC_RX_RX0_RX_PATH_MIX_CFG:
1295         case CDC_RX_RX0_RX_VOL_MIX_CTL:
1296         case CDC_RX_RX0_RX_PATH_SEC1:
1297         case CDC_RX_RX0_RX_PATH_SEC2:
1298         case CDC_RX_RX0_RX_PATH_SEC3:
1299         case CDC_RX_RX0_RX_PATH_SEC4:
1300         case CDC_RX_RX0_RX_PATH_SEC7:
1301         case CDC_RX_RX0_RX_PATH_MIX_SEC0:
1302         case CDC_RX_RX0_RX_PATH_MIX_SEC1:
1303         case CDC_RX_RX0_RX_PATH_DSM_CTL:
1304         case CDC_RX_RX0_RX_PATH_DSM_DATA1:
1305         case CDC_RX_RX0_RX_PATH_DSM_DATA2:
1306         case CDC_RX_RX0_RX_PATH_DSM_DATA3:
1307         case CDC_RX_RX0_RX_PATH_DSM_DATA4:
1308         case CDC_RX_RX0_RX_PATH_DSM_DATA5:
1309         case CDC_RX_RX0_RX_PATH_DSM_DATA6:
1310         case CDC_RX_RX1_RX_PATH_CTL:
1311         case CDC_RX_RX1_RX_PATH_CFG0:
1312         case CDC_RX_RX1_RX_PATH_CFG1:
1313         case CDC_RX_RX1_RX_PATH_CFG2:
1314         case CDC_RX_RX1_RX_PATH_CFG3:
1315         case CDC_RX_RX1_RX_VOL_CTL:
1316         case CDC_RX_RX1_RX_PATH_MIX_CTL:
1317         case CDC_RX_RX1_RX_PATH_MIX_CFG:
1318         case CDC_RX_RX1_RX_VOL_MIX_CTL:
1319         case CDC_RX_RX1_RX_PATH_SEC1:
1320         case CDC_RX_RX1_RX_PATH_SEC2:
1321         case CDC_RX_RX1_RX_PATH_SEC3:
1322         case CDC_RX_RX1_RX_PATH_SEC4:
1323         case CDC_RX_RX1_RX_PATH_SEC7:
1324         case CDC_RX_RX1_RX_PATH_MIX_SEC0:
1325         case CDC_RX_RX1_RX_PATH_MIX_SEC1:
1326         case CDC_RX_RX1_RX_PATH_DSM_CTL:
1327         case CDC_RX_RX1_RX_PATH_DSM_DATA1:
1328         case CDC_RX_RX1_RX_PATH_DSM_DATA2:
1329         case CDC_RX_RX1_RX_PATH_DSM_DATA3:
1330         case CDC_RX_RX1_RX_PATH_DSM_DATA4:
1331         case CDC_RX_RX1_RX_PATH_DSM_DATA5:
1332         case CDC_RX_RX1_RX_PATH_DSM_DATA6:
1333         case CDC_RX_RX2_RX_PATH_CTL:
1334         case CDC_RX_RX2_RX_PATH_CFG0:
1335         case CDC_RX_RX2_RX_PATH_CFG1:
1336         case CDC_RX_RX2_RX_PATH_CFG2:
1337         case CDC_RX_RX2_RX_PATH_CFG3:
1338         case CDC_RX_RX2_RX_VOL_CTL:
1339         case CDC_RX_RX2_RX_PATH_MIX_CTL:
1340         case CDC_RX_RX2_RX_PATH_MIX_CFG:
1341         case CDC_RX_RX2_RX_VOL_MIX_CTL:
1342         case CDC_RX_RX2_RX_PATH_SEC0:
1343         case CDC_RX_RX2_RX_PATH_SEC1:
1344         case CDC_RX_RX2_RX_PATH_SEC2:
1345         case CDC_RX_RX2_RX_PATH_SEC3:
1346         case CDC_RX_RX2_RX_PATH_SEC4:
1347         case CDC_RX_RX2_RX_PATH_SEC5:
1348         case CDC_RX_RX2_RX_PATH_SEC6:
1349         case CDC_RX_RX2_RX_PATH_SEC7:
1350         case CDC_RX_RX2_RX_PATH_MIX_SEC0:
1351         case CDC_RX_RX2_RX_PATH_MIX_SEC1:
1352         case CDC_RX_RX2_RX_PATH_DSM_CTL:
1353         case CDC_RX_IDLE_DETECT_PATH_CTL:
1354         case CDC_RX_IDLE_DETECT_CFG0:
1355         case CDC_RX_IDLE_DETECT_CFG1:
1356         case CDC_RX_IDLE_DETECT_CFG2:
1357         case CDC_RX_IDLE_DETECT_CFG3:
1358         case CDC_RX_COMPANDER0_CTL0:
1359         case CDC_RX_COMPANDER0_CTL1:
1360         case CDC_RX_COMPANDER0_CTL2:
1361         case CDC_RX_COMPANDER0_CTL3:
1362         case CDC_RX_COMPANDER0_CTL4:
1363         case CDC_RX_COMPANDER0_CTL5:
1364         case CDC_RX_COMPANDER0_CTL7:
1365         case CDC_RX_COMPANDER1_CTL0:
1366         case CDC_RX_COMPANDER1_CTL1:
1367         case CDC_RX_COMPANDER1_CTL2:
1368         case CDC_RX_COMPANDER1_CTL3:
1369         case CDC_RX_COMPANDER1_CTL4:
1370         case CDC_RX_COMPANDER1_CTL5:
1371         case CDC_RX_COMPANDER1_CTL7:
1372         case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
1373         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
1374         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
1375         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
1376         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
1377         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
1378         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
1379         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
1380         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
1381         case CDC_RX_SIDETONE_IIR0_IIR_CTL:
1382         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
1383         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
1384         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
1385         case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
1386         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
1387         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
1388         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
1389         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
1390         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
1391         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
1392         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
1393         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
1394         case CDC_RX_SIDETONE_IIR1_IIR_CTL:
1395         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
1396         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
1397         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
1398         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
1399         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
1400         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
1401         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
1402         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
1403         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
1404         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
1405         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
1406         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
1407         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
1408         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
1409         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
1410         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
1411         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
1412         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
1413         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
1414         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
1415         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
1416         case CDC_RX_EC_ASRC0_CLK_RST_CTL:
1417         case CDC_RX_EC_ASRC0_CTL0:
1418         case CDC_RX_EC_ASRC0_CTL1:
1419         case CDC_RX_EC_ASRC0_FIFO_CTL:
1420         case CDC_RX_EC_ASRC1_CLK_RST_CTL:
1421         case CDC_RX_EC_ASRC1_CTL0:
1422         case CDC_RX_EC_ASRC1_CTL1:
1423         case CDC_RX_EC_ASRC1_FIFO_CTL:
1424         case CDC_RX_EC_ASRC2_CLK_RST_CTL:
1425         case CDC_RX_EC_ASRC2_CTL0:
1426         case CDC_RX_EC_ASRC2_CTL1:
1427         case CDC_RX_EC_ASRC2_FIFO_CTL:
1428         case CDC_RX_DSD0_PATH_CTL:
1429         case CDC_RX_DSD0_CFG0:
1430         case CDC_RX_DSD0_CFG1:
1431         case CDC_RX_DSD0_CFG2:
1432         case CDC_RX_DSD1_PATH_CTL:
1433         case CDC_RX_DSD1_CFG0:
1434         case CDC_RX_DSD1_CFG1:
1435         case CDC_RX_DSD1_CFG2:
1436                 return true;
1437         }
1438
1439         return false;
1440 }
1441
1442 static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
1443 {
1444         bool ret;
1445
1446         ret = rx_is_rw_register(dev, reg);
1447         if (!ret)
1448                 return rx_is_wronly_register(dev, reg);
1449
1450         return ret;
1451 }
1452
1453 static bool rx_is_readable_register(struct device *dev, unsigned int reg)
1454 {
1455         switch (reg) {
1456         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1457         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1458         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1459         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1460         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1461         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1462         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1463         case CDC_RX_BCL_VBAT_DECODE_ST:
1464         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1465         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1466         case CDC_RX_COMPANDER0_CTL6:
1467         case CDC_RX_COMPANDER1_CTL6:
1468         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1469         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1470         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1471         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1472         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1473         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1474         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1475         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1476         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1477         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1478         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1479         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1480         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1481         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1482         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1483                 return true;
1484         }
1485
1486         return rx_is_rw_register(dev, reg);
1487 }
1488
1489 static const struct regmap_config rx_regmap_config = {
1490         .name = "rx_macro",
1491         .reg_bits = 16,
1492         .val_bits = 32, /* 8 but with 32 bit read/write */
1493         .reg_stride = 4,
1494         .cache_type = REGCACHE_FLAT,
1495         .reg_defaults = rx_defaults,
1496         .num_reg_defaults = ARRAY_SIZE(rx_defaults),
1497         .max_register = RX_MAX_OFFSET,
1498         .writeable_reg = rx_is_writeable_register,
1499         .volatile_reg = rx_is_volatile_register,
1500         .readable_reg = rx_is_readable_register,
1501 };
1502
1503 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
1504                                         struct snd_ctl_elem_value *ucontrol)
1505 {
1506         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1507         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1508         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1509         unsigned short look_ahead_dly_reg;
1510         unsigned int val;
1511
1512         val = ucontrol->value.enumerated.item[0];
1513
1514         if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
1515                 look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
1516         else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
1517                 look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
1518
1519         /* Set Look Ahead Delay */
1520         if (val)
1521                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1522                                               CDC_RX_DLY_ZN_EN_MASK,
1523                                               CDC_RX_DLY_ZN_ENABLE);
1524         else
1525                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1526                                               CDC_RX_DLY_ZN_EN_MASK, 0);
1527         /* Set DEM INP Select */
1528         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1529 }
1530
1531 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1532                 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
1533                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1534 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1535                 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
1536                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1537
1538 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1539                                                int rate_reg_val, u32 sample_rate)
1540 {
1541
1542         u8 int_1_mix1_inp;
1543         u32 j, port;
1544         u16 int_mux_cfg0, int_mux_cfg1;
1545         u16 int_fs_reg;
1546         u8 inp0_sel, inp1_sel, inp2_sel;
1547         struct snd_soc_component *component = dai->component;
1548         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1549
1550         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1551                 int_1_mix1_inp = port;
1552                 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
1553                 /*
1554                  * Loop through all interpolator MUX inputs and find out
1555                  * to which interpolator input, the rx port
1556                  * is connected
1557                  */
1558                 for (j = 0; j < INTERP_MAX; j++) {
1559                         int_mux_cfg1 = int_mux_cfg0 + 4;
1560
1561                         inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1562                                                                 CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1563                         inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1564                                                                 CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1565                         inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1566                                                                 CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1567
1568                         if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1569                             (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1570                             (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1571                                 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
1572                                 /* sample_rate is in Hz */
1573                                 snd_soc_component_update_bits(component, int_fs_reg,
1574                                                               CDC_RX_PATH_PCM_RATE_MASK,
1575                                                               rate_reg_val);
1576                         }
1577                         int_mux_cfg0 += 8;
1578                 }
1579         }
1580
1581         return 0;
1582 }
1583
1584 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1585                                               int rate_reg_val, u32 sample_rate)
1586 {
1587
1588         u8 int_2_inp;
1589         u32 j, port;
1590         u16 int_mux_cfg1, int_fs_reg;
1591         u8 int_mux_cfg1_val;
1592         struct snd_soc_component *component = dai->component;
1593         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1594
1595         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1596                 int_2_inp = port;
1597
1598                 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
1599                 for (j = 0; j < INTERP_MAX; j++) {
1600                         int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1601                                                                         CDC_RX_INTX_2_SEL_MASK);
1602
1603                         if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1604                                 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1605                                 snd_soc_component_update_bits(component, int_fs_reg,
1606                                                               CDC_RX_RXn_MIX_PCM_RATE_MASK,
1607                                                               rate_reg_val);
1608                         }
1609                         int_mux_cfg1 += 8;
1610                 }
1611         }
1612         return 0;
1613 }
1614
1615 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1616                                           u32 sample_rate)
1617 {
1618         int rate_val = 0;
1619         int i, ret;
1620
1621         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
1622                 if (sample_rate == sr_val_tbl[i].sample_rate)
1623                         rate_val = sr_val_tbl[i].rate_val;
1624
1625         ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate);
1626         if (ret)
1627                 return ret;
1628
1629         ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate);
1630
1631         return ret;
1632 }
1633
1634 static int rx_macro_hw_params(struct snd_pcm_substream *substream,
1635                               struct snd_pcm_hw_params *params,
1636                               struct snd_soc_dai *dai)
1637 {
1638         struct snd_soc_component *component = dai->component;
1639         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1640         int ret;
1641
1642         switch (substream->stream) {
1643         case SNDRV_PCM_STREAM_PLAYBACK:
1644                 ret = rx_macro_set_interpolator_rate(dai, params_rate(params));
1645                 if (ret) {
1646                         dev_err(component->dev, "%s: cannot set sample rate: %u\n",
1647                                 __func__, params_rate(params));
1648                         return ret;
1649                 }
1650                 rx->bit_width[dai->id] = params_width(params);
1651                 break;
1652         default:
1653                 break;
1654         }
1655         return 0;
1656 }
1657
1658 static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
1659                                     unsigned int *tx_num, unsigned int *tx_slot,
1660                                     unsigned int *rx_num, unsigned int *rx_slot)
1661 {
1662         struct snd_soc_component *component = dai->component;
1663         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1664         u16 val, mask = 0, cnt = 0, temp;
1665
1666         switch (dai->id) {
1667         case RX_MACRO_AIF1_PB:
1668         case RX_MACRO_AIF2_PB:
1669         case RX_MACRO_AIF3_PB:
1670         case RX_MACRO_AIF4_PB:
1671                 for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
1672                          RX_MACRO_PORTS_MAX) {
1673                         mask |= (1 << temp);
1674                         if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
1675                                 break;
1676                 }
1677                 /*
1678                  * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
1679                  * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
1680                  * CDC_DMA_RX_2 port drives RX4     -- ch_mask 0x1
1681                  * CDC_DMA_RX_3 port drives RX5     -- ch_mask 0x1
1682                  * AIFn can pair to any CDC_DMA_RX_n port.
1683                  * In general, below convention is used::
1684                  * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
1685                  * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
1686                  */
1687                 if (mask & 0x0C)
1688                         mask = mask >> 2;
1689                 if ((mask & 0x10) || (mask & 0x20))
1690                         mask = 0x1;
1691                 *rx_slot = mask;
1692                 *rx_num = rx->active_ch_cnt[dai->id];
1693                 break;
1694         case RX_MACRO_AIF_ECHO:
1695                 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4);
1696                 if (val & RX_MACRO_EC_MIX_TX0_MASK) {
1697                         mask |= 0x1;
1698                         cnt++;
1699                 }
1700                 if (val & RX_MACRO_EC_MIX_TX1_MASK) {
1701                         mask |= 0x2;
1702                         cnt++;
1703                 }
1704                 val = snd_soc_component_read(component,
1705                         CDC_RX_INP_MUX_RX_MIX_CFG5);
1706                 if (val & RX_MACRO_EC_MIX_TX2_MASK) {
1707                         mask |= 0x4;
1708                         cnt++;
1709                 }
1710                 *tx_slot = mask;
1711                 *tx_num = cnt;
1712                 break;
1713         default:
1714                 dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1715                 break;
1716         }
1717         return 0;
1718 }
1719
1720 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1721 {
1722         struct snd_soc_component *component = dai->component;
1723         uint16_t j, reg, mix_reg, dsm_reg;
1724         u16 int_mux_cfg0, int_mux_cfg1;
1725         u8 int_mux_cfg0_val, int_mux_cfg1_val;
1726
1727         switch (dai->id) {
1728         case RX_MACRO_AIF1_PB:
1729         case RX_MACRO_AIF2_PB:
1730         case RX_MACRO_AIF3_PB:
1731         case RX_MACRO_AIF4_PB:
1732                 for (j = 0; j < INTERP_MAX; j++) {
1733                         reg = CDC_RX_RXn_RX_PATH_CTL(j);
1734                         mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1735                         dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
1736
1737                         if (mute) {
1738                                 snd_soc_component_update_bits(component, reg,
1739                                                               CDC_RX_PATH_PGA_MUTE_MASK,
1740                                                               CDC_RX_PATH_PGA_MUTE_ENABLE);
1741                                 snd_soc_component_update_bits(component, mix_reg,
1742                                                               CDC_RX_PATH_PGA_MUTE_MASK,
1743                                                               CDC_RX_PATH_PGA_MUTE_ENABLE);
1744                         } else {
1745                                 snd_soc_component_update_bits(component, reg,
1746                                                               CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1747                                 snd_soc_component_update_bits(component, mix_reg,
1748                                                               CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1749                         }
1750
1751                         if (j == INTERP_AUX)
1752                                 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1753
1754                         int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1755                         int_mux_cfg1 = int_mux_cfg0 + 4;
1756                         int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1757                         int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1758
1759                         if (snd_soc_component_read(component, dsm_reg) & 0x01) {
1760                                 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
1761                                         snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1762                                 if (int_mux_cfg1_val & 0x0F) {
1763                                         snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1764                                         snd_soc_component_update_bits(component, mix_reg, 0x20,
1765                                                                       0x20);
1766                                 }
1767                         }
1768                 }
1769                 break;
1770         default:
1771                 break;
1772         }
1773         return 0;
1774 }
1775
1776 static const struct snd_soc_dai_ops rx_macro_dai_ops = {
1777         .hw_params = rx_macro_hw_params,
1778         .get_channel_map = rx_macro_get_channel_map,
1779         .mute_stream = rx_macro_digital_mute,
1780 };
1781
1782 static struct snd_soc_dai_driver rx_macro_dai[] = {
1783         {
1784                 .name = "rx_macro_rx1",
1785                 .id = RX_MACRO_AIF1_PB,
1786                 .playback = {
1787                         .stream_name = "RX_MACRO_AIF1 Playback",
1788                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1789                         .formats = RX_MACRO_FORMATS,
1790                         .rate_max = 384000,
1791                         .rate_min = 8000,
1792                         .channels_min = 1,
1793                         .channels_max = 2,
1794                 },
1795                 .ops = &rx_macro_dai_ops,
1796         },
1797         {
1798                 .name = "rx_macro_rx2",
1799                 .id = RX_MACRO_AIF2_PB,
1800                 .playback = {
1801                         .stream_name = "RX_MACRO_AIF2 Playback",
1802                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1803                         .formats = RX_MACRO_FORMATS,
1804                         .rate_max = 384000,
1805                         .rate_min = 8000,
1806                         .channels_min = 1,
1807                         .channels_max = 2,
1808                 },
1809                 .ops = &rx_macro_dai_ops,
1810         },
1811         {
1812                 .name = "rx_macro_rx3",
1813                 .id = RX_MACRO_AIF3_PB,
1814                 .playback = {
1815                         .stream_name = "RX_MACRO_AIF3 Playback",
1816                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1817                         .formats = RX_MACRO_FORMATS,
1818                         .rate_max = 384000,
1819                         .rate_min = 8000,
1820                         .channels_min = 1,
1821                         .channels_max = 2,
1822                 },
1823                 .ops = &rx_macro_dai_ops,
1824         },
1825         {
1826                 .name = "rx_macro_rx4",
1827                 .id = RX_MACRO_AIF4_PB,
1828                 .playback = {
1829                         .stream_name = "RX_MACRO_AIF4 Playback",
1830                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1831                         .formats = RX_MACRO_FORMATS,
1832                         .rate_max = 384000,
1833                         .rate_min = 8000,
1834                         .channels_min = 1,
1835                         .channels_max = 2,
1836                 },
1837                 .ops = &rx_macro_dai_ops,
1838         },
1839         {
1840                 .name = "rx_macro_echo",
1841                 .id = RX_MACRO_AIF_ECHO,
1842                 .capture = {
1843                         .stream_name = "RX_AIF_ECHO Capture",
1844                         .rates = RX_MACRO_ECHO_RATES,
1845                         .formats = RX_MACRO_ECHO_FORMATS,
1846                         .rate_max = 48000,
1847                         .rate_min = 8000,
1848                         .channels_min = 1,
1849                         .channels_max = 3,
1850                 },
1851                 .ops = &rx_macro_dai_ops,
1852         },
1853 };
1854
1855 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
1856 {
1857         struct regmap *regmap = rx->regmap;
1858
1859         if (mclk_enable) {
1860                 if (rx->rx_mclk_users == 0) {
1861                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1862                                            CDC_RX_CLK_MCLK_EN_MASK |
1863                                            CDC_RX_CLK_MCLK2_EN_MASK,
1864                                            CDC_RX_CLK_MCLK_ENABLE |
1865                                            CDC_RX_CLK_MCLK2_ENABLE);
1866                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1867                                            CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
1868                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1869                                            CDC_RX_FS_MCLK_CNT_EN_MASK,
1870                                            CDC_RX_FS_MCLK_CNT_ENABLE);
1871                         regcache_mark_dirty(regmap);
1872                         regcache_sync(regmap);
1873                 }
1874                 rx->rx_mclk_users++;
1875         } else {
1876                 if (rx->rx_mclk_users <= 0) {
1877                         dev_err(rx->dev, "%s: clock already disabled\n", __func__);
1878                         rx->rx_mclk_users = 0;
1879                         return;
1880                 }
1881                 rx->rx_mclk_users--;
1882                 if (rx->rx_mclk_users == 0) {
1883                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1884                                            CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0);
1885                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1886                                            CDC_RX_FS_MCLK_CNT_CLR_MASK,
1887                                            CDC_RX_FS_MCLK_CNT_CLR);
1888                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1889                                            CDC_RX_CLK_MCLK_EN_MASK |
1890                                            CDC_RX_CLK_MCLK2_EN_MASK, 0x0);
1891                 }
1892         }
1893 }
1894
1895 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
1896                                struct snd_kcontrol *kcontrol, int event)
1897 {
1898         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1899         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1900         int ret = 0;
1901
1902         switch (event) {
1903         case SND_SOC_DAPM_PRE_PMU:
1904                 rx_macro_mclk_enable(rx, true);
1905                 break;
1906         case SND_SOC_DAPM_POST_PMD:
1907                 rx_macro_mclk_enable(rx, false);
1908                 break;
1909         default:
1910                 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
1911                 ret = -EINVAL;
1912         }
1913         return ret;
1914 }
1915
1916 static bool rx_macro_adie_lb(struct snd_soc_component *component,
1917                              int interp_idx)
1918 {
1919         u16 int_mux_cfg0, int_mux_cfg1;
1920         u8 int_n_inp0, int_n_inp1, int_n_inp2;
1921
1922         int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1923         int_mux_cfg1 = int_mux_cfg0 + 4;
1924
1925         int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1926                                                   CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1927         int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1928                                                   CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1929         int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1930                                                   CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1931
1932         if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1933                 int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
1934                 int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
1935                 int_n_inp0 == INTn_1_INP_SEL_IIR1)
1936                 return true;
1937
1938         if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1939                 int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
1940                 int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
1941                 int_n_inp1 == INTn_1_INP_SEL_IIR1)
1942                 return true;
1943
1944         if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1945                 int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
1946                 int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
1947                 int_n_inp2 == INTn_1_INP_SEL_IIR1)
1948                 return true;
1949
1950         return false;
1951 }
1952
1953 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
1954                                       int event, int interp_idx);
1955 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1956                                         struct snd_kcontrol *kcontrol,
1957                                         int event)
1958 {
1959         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1960         u16 gain_reg, reg;
1961
1962         reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
1963         gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
1964
1965         switch (event) {
1966         case SND_SOC_DAPM_PRE_PMU:
1967                 rx_macro_enable_interp_clk(component, event, w->shift);
1968                 if (rx_macro_adie_lb(component, w->shift))
1969                         snd_soc_component_update_bits(component, reg,
1970                                                       CDC_RX_PATH_CLK_EN_MASK,
1971                                                       CDC_RX_PATH_CLK_ENABLE);
1972                 break;
1973         case SND_SOC_DAPM_POST_PMU:
1974                 snd_soc_component_write(component, gain_reg,
1975                         snd_soc_component_read(component, gain_reg));
1976                 break;
1977         case SND_SOC_DAPM_POST_PMD:
1978                 rx_macro_enable_interp_clk(component, event, w->shift);
1979                 break;
1980         }
1981
1982         return 0;
1983 }
1984
1985 static int rx_macro_config_compander(struct snd_soc_component *component,
1986                                 struct rx_macro *rx,
1987                                 int comp, int event)
1988 {
1989         u8 pcm_rate, val;
1990
1991         /* AUX does not have compander */
1992         if (comp == INTERP_AUX)
1993                 return 0;
1994
1995         pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
1996         if (pcm_rate < 0x06)
1997                 val = 0x03;
1998         else if (pcm_rate < 0x08)
1999                 val = 0x01;
2000         else if (pcm_rate < 0x0B)
2001                 val = 0x02;
2002         else
2003                 val = 0x00;
2004
2005         if (SND_SOC_DAPM_EVENT_ON(event))
2006                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2007                                               CDC_RX_DC_COEFF_SEL_MASK, val);
2008
2009         if (SND_SOC_DAPM_EVENT_OFF(event))
2010                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2011                                               CDC_RX_DC_COEFF_SEL_MASK, 0x3);
2012         if (!rx->comp_enabled[comp])
2013                 return 0;
2014
2015         if (SND_SOC_DAPM_EVENT_ON(event)) {
2016                 /* Enable Compander Clock */
2017                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2018                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1);
2019                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2020                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
2021                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2022                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
2023                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2024                                               CDC_RX_RXn_COMP_EN_MASK, 0x1);
2025         }
2026
2027         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2028                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2029                                               CDC_RX_COMPANDERn_HALT_MASK, 0x1);
2030                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2031                                               CDC_RX_RXn_COMP_EN_MASK, 0x0);
2032                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2033                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
2034                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2035                                               CDC_RX_COMPANDERn_HALT_MASK, 0x0);
2036         }
2037
2038         return 0;
2039 }
2040
2041 static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
2042                                          struct rx_macro *rx,
2043                                          int comp, int event)
2044 {
2045         u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
2046         int i;
2047         int hph_pwr_mode;
2048
2049         /* AUX does not have compander */
2050         if (comp == INTERP_AUX)
2051                 return 0;
2052
2053         if (!rx->comp_enabled[comp])
2054                 return 0;
2055
2056         if (comp == INTERP_HPHL) {
2057                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
2058                 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
2059         } else if (comp == INTERP_HPHR) {
2060                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
2061                 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
2062         } else {
2063                 /* compander coefficients are loaded only for hph path */
2064                 return 0;
2065         }
2066
2067         hph_pwr_mode = rx->hph_pwr_mode;
2068
2069         if (SND_SOC_DAPM_EVENT_ON(event)) {
2070                 /* Load Compander Coeff */
2071                 for (i = 0; i < COMP_MAX_COEFF; i++) {
2072                         snd_soc_component_write(component, comp_coeff_lsb_reg,
2073                                         comp_coeff_table[hph_pwr_mode][i].lsb);
2074                         snd_soc_component_write(component, comp_coeff_msb_reg,
2075                                         comp_coeff_table[hph_pwr_mode][i].msb);
2076                 }
2077         }
2078
2079         return 0;
2080 }
2081
2082 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
2083                                          struct rx_macro *rx, bool enable)
2084 {
2085         if (enable) {
2086                 if (rx->softclip_clk_users == 0)
2087                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2088                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 1);
2089                 rx->softclip_clk_users++;
2090         } else {
2091                 rx->softclip_clk_users--;
2092                 if (rx->softclip_clk_users == 0)
2093                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2094                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 0);
2095         }
2096 }
2097
2098 static int rx_macro_config_softclip(struct snd_soc_component *component,
2099                                     struct rx_macro *rx, int event)
2100 {
2101
2102         if (!rx->is_softclip_on)
2103                 return 0;
2104
2105         if (SND_SOC_DAPM_EVENT_ON(event)) {
2106                 /* Enable Softclip clock */
2107                 rx_macro_enable_softclip_clk(component, rx, true);
2108                 /* Enable Softclip control */
2109                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2110                                              CDC_RX_SOFTCLIP_EN_MASK, 0x01);
2111         }
2112
2113         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2114                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2115                                              CDC_RX_SOFTCLIP_EN_MASK, 0x0);
2116                 rx_macro_enable_softclip_clk(component, rx, false);
2117         }
2118
2119         return 0;
2120 }
2121
2122 static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
2123                                    struct rx_macro *rx, int event)
2124 {
2125         if (SND_SOC_DAPM_EVENT_ON(event)) {
2126                 /* Update Aux HPF control */
2127                 if (!rx->is_aux_hpf_on)
2128                         snd_soc_component_update_bits(component,
2129                                 CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
2130         }
2131
2132         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2133                 /* Reset to default (HPF=ON) */
2134                 snd_soc_component_update_bits(component,
2135                         CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
2136         }
2137
2138         return 0;
2139 }
2140
2141 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
2142 {
2143         if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
2144                 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC,
2145                                              CDC_RX_CLSH_CLK_EN_MASK, enable);
2146         if (rx->clsh_users < 0)
2147                 rx->clsh_users = 0;
2148 }
2149
2150 static int rx_macro_config_classh(struct snd_soc_component *component,
2151                                 struct rx_macro *rx,
2152                                 int interp_n, int event)
2153 {
2154         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2155                 rx_macro_enable_clsh_block(rx, false);
2156                 return 0;
2157         }
2158
2159         if (!SND_SOC_DAPM_EVENT_ON(event))
2160                 return 0;
2161
2162         rx_macro_enable_clsh_block(rx, true);
2163         if (interp_n == INTERP_HPHL ||
2164                 interp_n == INTERP_HPHR) {
2165                 /*
2166                  * These K1 values depend on the Headphone Impedance
2167                  * For now it is assumed to be 16 ohm
2168                  */
2169                 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0);
2170                 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
2171                                               CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0);
2172         }
2173         switch (interp_n) {
2174         case INTERP_HPHL:
2175                 if (rx->is_ear_mode_on)
2176                         snd_soc_component_update_bits(component,
2177                                 CDC_RX_CLSH_HPH_V_PA,
2178                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2179                 else
2180                         snd_soc_component_update_bits(component,
2181                                 CDC_RX_CLSH_HPH_V_PA,
2182                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2183                 snd_soc_component_update_bits(component,
2184                                 CDC_RX_CLSH_DECAY_CTRL,
2185                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2186                 snd_soc_component_write_field(component,
2187                                 CDC_RX_RX0_RX_PATH_CFG0,
2188                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2189                 break;
2190         case INTERP_HPHR:
2191                 if (rx->is_ear_mode_on)
2192                         snd_soc_component_update_bits(component,
2193                                 CDC_RX_CLSH_HPH_V_PA,
2194                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2195                 else
2196                         snd_soc_component_update_bits(component,
2197                                 CDC_RX_CLSH_HPH_V_PA,
2198                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2199                 snd_soc_component_update_bits(component,
2200                                 CDC_RX_CLSH_DECAY_CTRL,
2201                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2202                 snd_soc_component_write_field(component,
2203                                 CDC_RX_RX1_RX_PATH_CFG0,
2204                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2205                 break;
2206         case INTERP_AUX:
2207                 snd_soc_component_update_bits(component,
2208                                 CDC_RX_RX2_RX_PATH_CFG0,
2209                                 CDC_RX_RX2_DLY_Z_EN_MASK, 1);
2210                 snd_soc_component_write_field(component,
2211                                 CDC_RX_RX2_RX_PATH_CFG0,
2212                                 CDC_RX_RX2_CLSH_EN_MASK, 1);
2213                 break;
2214         }
2215
2216         return 0;
2217 }
2218
2219 static void rx_macro_hd2_control(struct snd_soc_component *component,
2220                                  u16 interp_idx, int event)
2221 {
2222         u16 hd2_scale_reg, hd2_enable_reg;
2223
2224         switch (interp_idx) {
2225         case INTERP_HPHL:
2226                 hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
2227                 hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
2228                 break;
2229         case INTERP_HPHR:
2230                 hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
2231                 hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
2232                 break;
2233         }
2234
2235         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2236                 snd_soc_component_update_bits(component, hd2_scale_reg,
2237                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14);
2238                 snd_soc_component_write_field(component, hd2_enable_reg,
2239                                               CDC_RX_RXn_HD2_EN_MASK, 1);
2240         }
2241
2242         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2243                 snd_soc_component_write_field(component, hd2_enable_reg,
2244                                               CDC_RX_RXn_HD2_EN_MASK, 0);
2245                 snd_soc_component_update_bits(component, hd2_scale_reg,
2246                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0);
2247         }
2248 }
2249
2250 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
2251                                struct snd_ctl_elem_value *ucontrol)
2252 {
2253         struct snd_soc_component *component =
2254                                 snd_soc_kcontrol_component(kcontrol);
2255         int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2256         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2257
2258         ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
2259         return 0;
2260 }
2261
2262 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
2263                                struct snd_ctl_elem_value *ucontrol)
2264 {
2265         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2266         int comp = ((struct soc_mixer_control *)  kcontrol->private_value)->shift;
2267         int value = ucontrol->value.integer.value[0];
2268         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2269
2270         rx->comp_enabled[comp] = value;
2271
2272         return 0;
2273 }
2274
2275 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
2276                           struct snd_ctl_elem_value *ucontrol)
2277 {
2278         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2279         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2280         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2281
2282         ucontrol->value.enumerated.item[0] =
2283                         rx->rx_port_value[widget->shift];
2284         return 0;
2285 }
2286
2287 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
2288                             struct snd_ctl_elem_value *ucontrol)
2289 {
2290         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2291         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2292         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2293         struct snd_soc_dapm_update *update = NULL;
2294         u32 rx_port_value = ucontrol->value.enumerated.item[0];
2295         u32 aif_rst;
2296         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2297
2298         aif_rst = rx->rx_port_value[widget->shift];
2299         if (!rx_port_value) {
2300                 if (aif_rst == 0) {
2301                         dev_err(component->dev, "%s:AIF reset already\n", __func__);
2302                         return 0;
2303                 }
2304                 if (aif_rst > RX_MACRO_AIF4_PB) {
2305                         dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2306                         return 0;
2307                 }
2308         }
2309         rx->rx_port_value[widget->shift] = rx_port_value;
2310
2311         switch (rx_port_value) {
2312         case 0:
2313                 if (rx->active_ch_cnt[aif_rst]) {
2314                         clear_bit(widget->shift,
2315                                 &rx->active_ch_mask[aif_rst]);
2316                         rx->active_ch_cnt[aif_rst]--;
2317                 }
2318                 break;
2319         case 1:
2320         case 2:
2321         case 3:
2322         case 4:
2323                 set_bit(widget->shift,
2324                         &rx->active_ch_mask[rx_port_value]);
2325                 rx->active_ch_cnt[rx_port_value]++;
2326                 break;
2327         default:
2328                 dev_err(component->dev,
2329                         "%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
2330                         __func__, rx_port_value);
2331                 goto err;
2332         }
2333
2334         snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2335                                         rx_port_value, e, update);
2336         return 0;
2337 err:
2338         return -EINVAL;
2339 }
2340
2341 static const struct snd_kcontrol_new rx_macro_rx0_mux =
2342                 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
2343                   rx_macro_mux_get, rx_macro_mux_put);
2344 static const struct snd_kcontrol_new rx_macro_rx1_mux =
2345                 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
2346                   rx_macro_mux_get, rx_macro_mux_put);
2347 static const struct snd_kcontrol_new rx_macro_rx2_mux =
2348                 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
2349                   rx_macro_mux_get, rx_macro_mux_put);
2350 static const struct snd_kcontrol_new rx_macro_rx3_mux =
2351                 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
2352                   rx_macro_mux_get, rx_macro_mux_put);
2353 static const struct snd_kcontrol_new rx_macro_rx4_mux =
2354                 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
2355                   rx_macro_mux_get, rx_macro_mux_put);
2356 static const struct snd_kcontrol_new rx_macro_rx5_mux =
2357                 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
2358                   rx_macro_mux_get, rx_macro_mux_put);
2359
2360 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
2361                                struct snd_ctl_elem_value *ucontrol)
2362 {
2363         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2364         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2365
2366         ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
2367         return 0;
2368 }
2369
2370 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
2371                                struct snd_ctl_elem_value *ucontrol)
2372 {
2373         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2374         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2375
2376         rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
2377         return 0;
2378 }
2379
2380 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2381                                struct snd_ctl_elem_value *ucontrol)
2382 {
2383         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2384         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2385
2386         ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
2387         return 0;
2388 }
2389
2390 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2391                                struct snd_ctl_elem_value *ucontrol)
2392 {
2393         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2394         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2395
2396         rx->hph_hd2_mode = ucontrol->value.integer.value[0];
2397         return 0;
2398 }
2399
2400 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2401                                struct snd_ctl_elem_value *ucontrol)
2402 {
2403         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2404         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2405
2406         ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode;
2407         return 0;
2408 }
2409
2410 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2411                                struct snd_ctl_elem_value *ucontrol)
2412 {
2413         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2414         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2415
2416         rx->hph_pwr_mode = ucontrol->value.enumerated.item[0];
2417         return 0;
2418 }
2419
2420 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2421                                           struct snd_ctl_elem_value *ucontrol)
2422 {
2423         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2424         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2425
2426         ucontrol->value.integer.value[0] = rx->is_softclip_on;
2427
2428         return 0;
2429 }
2430
2431 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2432                                           struct snd_ctl_elem_value *ucontrol)
2433 {
2434         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2435         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2436
2437         rx->is_softclip_on = ucontrol->value.integer.value[0];
2438
2439         return 0;
2440 }
2441
2442 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
2443                                           struct snd_ctl_elem_value *ucontrol)
2444 {
2445         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2446         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2447
2448         ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
2449
2450         return 0;
2451 }
2452
2453 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
2454                                           struct snd_ctl_elem_value *ucontrol)
2455 {
2456         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2457         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2458
2459         rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
2460
2461         return 0;
2462 }
2463
2464 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
2465                                         struct rx_macro *rx,
2466                                         u16 interp_idx, int event)
2467 {
2468         u16 hph_lut_bypass_reg;
2469         u16 hph_comp_ctrl7;
2470
2471         switch (interp_idx) {
2472         case INTERP_HPHL:
2473                 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
2474                 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
2475                 break;
2476         case INTERP_HPHR:
2477                 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
2478                 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
2479                 break;
2480         default:
2481                 return -EINVAL;
2482         }
2483
2484         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2485                 if (interp_idx == INTERP_HPHL) {
2486                         if (rx->is_ear_mode_on)
2487                                 snd_soc_component_write_field(component,
2488                                         CDC_RX_RX0_RX_PATH_CFG1,
2489                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
2490                         else
2491                                 snd_soc_component_write_field(component,
2492                                         hph_lut_bypass_reg,
2493                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2494                 } else {
2495                         snd_soc_component_write_field(component, hph_lut_bypass_reg,
2496                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2497                 }
2498                 if (rx->hph_pwr_mode)
2499                         snd_soc_component_write_field(component, hph_comp_ctrl7,
2500                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0);
2501         }
2502
2503         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2504                 snd_soc_component_write_field(component,
2505                                         CDC_RX_RX0_RX_PATH_CFG1,
2506                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
2507                 snd_soc_component_update_bits(component, hph_lut_bypass_reg,
2508                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
2509                 snd_soc_component_write_field(component, hph_comp_ctrl7,
2510                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1);
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2517                                       int event, int interp_idx)
2518 {
2519         u16 main_reg, dsm_reg, rx_cfg2_reg;
2520         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2521
2522         main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
2523         dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
2524         if (interp_idx == INTERP_AUX)
2525                 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
2526         rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
2527
2528         if (SND_SOC_DAPM_EVENT_ON(event)) {
2529                 if (rx->main_clk_users[interp_idx] == 0) {
2530                         /* Main path PGA mute enable */
2531                         snd_soc_component_write_field(component, main_reg,
2532                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2533                         snd_soc_component_write_field(component, dsm_reg,
2534                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1);
2535                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2536                                         CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03);
2537                         rx_macro_load_compander_coeff(component, rx, interp_idx, event);
2538                         if (rx->hph_hd2_mode)
2539                                 rx_macro_hd2_control(component, interp_idx, event);
2540                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2541                         rx_macro_config_compander(component, rx, interp_idx, event);
2542                         if (interp_idx == INTERP_AUX) {
2543                                 rx_macro_config_softclip(component, rx, event);
2544                                 rx_macro_config_aux_hpf(component, rx, event);
2545                         }
2546                         rx_macro_config_classh(component, rx, interp_idx, event);
2547                 }
2548                 rx->main_clk_users[interp_idx]++;
2549         }
2550
2551         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2552                 rx->main_clk_users[interp_idx]--;
2553                 if (rx->main_clk_users[interp_idx] <= 0) {
2554                         rx->main_clk_users[interp_idx] = 0;
2555                         /* Main path PGA mute enable */
2556                         snd_soc_component_write_field(component, main_reg,
2557                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2558                         /* Clk Disable */
2559                         snd_soc_component_write_field(component, dsm_reg,
2560                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0);
2561                         snd_soc_component_write_field(component, main_reg,
2562                                                       CDC_RX_PATH_CLK_EN_MASK, 0);
2563                         /* Reset enable and disable */
2564                         snd_soc_component_write_field(component, main_reg,
2565                                                       CDC_RX_PATH_RESET_EN_MASK, 1);
2566                         snd_soc_component_write_field(component, main_reg,
2567                                                       CDC_RX_PATH_RESET_EN_MASK, 0);
2568                         /* Reset rate to 48K*/
2569                         snd_soc_component_update_bits(component, main_reg,
2570                                                       CDC_RX_PATH_PCM_RATE_MASK,
2571                                                       0x04);
2572                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2573                                                       CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00);
2574                         rx_macro_config_classh(component, rx, interp_idx, event);
2575                         rx_macro_config_compander(component, rx, interp_idx, event);
2576                         if (interp_idx ==  INTERP_AUX) {
2577                                 rx_macro_config_softclip(component, rx, event);
2578                                 rx_macro_config_aux_hpf(component, rx, event);
2579                         }
2580                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2581                         if (rx->hph_hd2_mode)
2582                                 rx_macro_hd2_control(component, interp_idx, event);
2583                 }
2584         }
2585
2586         return rx->main_clk_users[interp_idx];
2587 }
2588
2589 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
2590                                     struct snd_kcontrol *kcontrol, int event)
2591 {
2592         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2593         u16 gain_reg, mix_reg;
2594
2595         gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
2596         mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
2597
2598         switch (event) {
2599         case SND_SOC_DAPM_PRE_PMU:
2600                 rx_macro_enable_interp_clk(component, event, w->shift);
2601                 break;
2602         case SND_SOC_DAPM_POST_PMU:
2603                 snd_soc_component_write(component, gain_reg,
2604                                         snd_soc_component_read(component, gain_reg));
2605                 break;
2606         case SND_SOC_DAPM_POST_PMD:
2607                 /* Clk Disable */
2608                 snd_soc_component_update_bits(component, mix_reg,
2609                                               CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00);
2610                 rx_macro_enable_interp_clk(component, event, w->shift);
2611                 /* Reset enable and disable */
2612                 snd_soc_component_update_bits(component, mix_reg,
2613                                               CDC_RX_RXn_MIX_RESET_MASK,
2614                                               CDC_RX_RXn_MIX_RESET);
2615                 snd_soc_component_update_bits(component, mix_reg,
2616                                               CDC_RX_RXn_MIX_RESET_MASK, 0x00);
2617                 break;
2618         }
2619
2620         return 0;
2621 }
2622
2623 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
2624                                        struct snd_kcontrol *kcontrol, int event)
2625 {
2626         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2627
2628         switch (event) {
2629         case SND_SOC_DAPM_PRE_PMU:
2630                 rx_macro_enable_interp_clk(component, event, w->shift);
2631                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2632                                               CDC_RX_RXn_SIDETONE_EN_MASK, 1);
2633                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
2634                                               CDC_RX_PATH_CLK_EN_MASK, 1);
2635                 break;
2636         case SND_SOC_DAPM_POST_PMD:
2637                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2638                                               CDC_RX_RXn_SIDETONE_EN_MASK, 0);
2639                 rx_macro_enable_interp_clk(component, event, w->shift);
2640                 break;
2641         default:
2642                 break;
2643         }
2644         return 0;
2645 }
2646
2647 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
2648                                  struct snd_kcontrol *kcontrol, int event)
2649 {
2650         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2651
2652         switch (event) {
2653         case SND_SOC_DAPM_POST_PMU: /* fall through */
2654         case SND_SOC_DAPM_PRE_PMD:
2655                 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2656                         snd_soc_component_write(component,
2657                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
2658                         snd_soc_component_read(component,
2659                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
2660                         snd_soc_component_write(component,
2661                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
2662                         snd_soc_component_read(component,
2663                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
2664                         snd_soc_component_write(component,
2665                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
2666                         snd_soc_component_read(component,
2667                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
2668                         snd_soc_component_write(component,
2669                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
2670                         snd_soc_component_read(component,
2671                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
2672                 } else {
2673                         snd_soc_component_write(component,
2674                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
2675                         snd_soc_component_read(component,
2676                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
2677                         snd_soc_component_write(component,
2678                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
2679                         snd_soc_component_read(component,
2680                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
2681                         snd_soc_component_write(component,
2682                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
2683                         snd_soc_component_read(component,
2684                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
2685                         snd_soc_component_write(component,
2686                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
2687                         snd_soc_component_read(component,
2688                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
2689                 }
2690                 break;
2691         }
2692         return 0;
2693 }
2694
2695 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2696                                    int iir_idx, int band_idx, int coeff_idx)
2697 {
2698         u32 value;
2699         int reg, b2_reg;
2700
2701         /* Address does not automatically update if reading */
2702         reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2703         b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2704
2705         snd_soc_component_write(component, reg,
2706                                 ((band_idx * BAND_MAX + coeff_idx) *
2707                                  sizeof(uint32_t)) & 0x7F);
2708
2709         value = snd_soc_component_read(component, b2_reg);
2710         snd_soc_component_write(component, reg,
2711                                 ((band_idx * BAND_MAX + coeff_idx)
2712                                  * sizeof(uint32_t) + 1) & 0x7F);
2713
2714         value |= (snd_soc_component_read(component, b2_reg) << 8);
2715         snd_soc_component_write(component, reg,
2716                                 ((band_idx * BAND_MAX + coeff_idx)
2717                                  * sizeof(uint32_t) + 2) & 0x7F);
2718
2719         value |= (snd_soc_component_read(component, b2_reg) << 16);
2720         snd_soc_component_write(component, reg,
2721                 ((band_idx * BAND_MAX + coeff_idx)
2722                 * sizeof(uint32_t) + 3) & 0x7F);
2723
2724         /* Mask bits top 2 bits since they are reserved */
2725         value |= (snd_soc_component_read(component, b2_reg) << 24);
2726         return value;
2727 }
2728
2729 static void set_iir_band_coeff(struct snd_soc_component *component,
2730                                int iir_idx, int band_idx, uint32_t value)
2731 {
2732         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2733
2734         snd_soc_component_write(component, reg, (value & 0xFF));
2735         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2736         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2737         /* Mask top 2 bits, 7-8 are reserved */
2738         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2739 }
2740
2741 static int rx_macro_put_iir_band_audio_mixer(
2742                                         struct snd_kcontrol *kcontrol,
2743                                         struct snd_ctl_elem_value *ucontrol)
2744 {
2745         struct snd_soc_component *component =
2746                         snd_soc_kcontrol_component(kcontrol);
2747         struct wcd_iir_filter_ctl *ctl =
2748                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2749         struct soc_bytes_ext *params = &ctl->bytes_ext;
2750         int iir_idx = ctl->iir_idx;
2751         int band_idx = ctl->band_idx;
2752         u32 coeff[BAND_MAX];
2753         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2754
2755         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2756
2757         /* Mask top bit it is reserved */
2758         /* Updates addr automatically for each B2 write */
2759         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2760                                                  sizeof(uint32_t)) & 0x7F);
2761
2762         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2763         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2764         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2765         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2766         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2767
2768         return 0;
2769 }
2770
2771 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2772                                     struct snd_ctl_elem_value *ucontrol)
2773 {
2774         struct snd_soc_component *component =
2775                         snd_soc_kcontrol_component(kcontrol);
2776         struct wcd_iir_filter_ctl *ctl =
2777                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2778         struct soc_bytes_ext *params = &ctl->bytes_ext;
2779         int iir_idx = ctl->iir_idx;
2780         int band_idx = ctl->band_idx;
2781         u32 coeff[BAND_MAX];
2782
2783         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2784         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2785         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2786         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2787         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2788
2789         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2790
2791         return 0;
2792 }
2793
2794 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
2795                                    struct snd_ctl_elem_info *ucontrol)
2796 {
2797         struct wcd_iir_filter_ctl *ctl =
2798                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2799         struct soc_bytes_ext *params = &ctl->bytes_ext;
2800
2801         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2802         ucontrol->count = params->max;
2803
2804         return 0;
2805 }
2806
2807 static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
2808         SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
2809                           -84, 40, digital_gain),
2810         SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
2811                           -84, 40, digital_gain),
2812         SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
2813                           -84, 40, digital_gain),
2814         SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
2815                           -84, 40, digital_gain),
2816         SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
2817                           -84, 40, digital_gain),
2818         SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
2819                           -84, 40, digital_gain),
2820
2821         SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
2822                 rx_macro_get_compander, rx_macro_set_compander),
2823         SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
2824                 rx_macro_get_compander, rx_macro_set_compander),
2825
2826         SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2827                 rx_macro_get_ear_mode, rx_macro_put_ear_mode),
2828
2829         SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2830                 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
2831
2832         SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
2833                 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
2834
2835         SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
2836                      rx_macro_soft_clip_enable_get,
2837                      rx_macro_soft_clip_enable_put),
2838         SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
2839                         rx_macro_aux_hpf_mode_get,
2840                         rx_macro_aux_hpf_mode_put),
2841
2842         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
2843                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
2844                 digital_gain),
2845         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
2846                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
2847                 digital_gain),
2848         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
2849                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
2850                 digital_gain),
2851         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
2852                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
2853                 digital_gain),
2854         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
2855                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
2856                 digital_gain),
2857         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
2858                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
2859                 digital_gain),
2860         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
2861                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
2862                 digital_gain),
2863         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
2864                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
2865                 digital_gain),
2866
2867         SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2868                    0, 1, 0),
2869         SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2870                    1, 1, 0),
2871         SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2872                    2, 1, 0),
2873         SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2874                    3, 1, 0),
2875         SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2876                    4, 1, 0),
2877         SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2878                    0, 1, 0),
2879         SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2880                    1, 1, 0),
2881         SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2882                    2, 1, 0),
2883         SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2884                    3, 1, 0),
2885         SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2886                    4, 1, 0),
2887
2888         RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
2889         RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
2890         RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
2891         RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
2892         RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
2893
2894         RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
2895         RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
2896         RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
2897         RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
2898         RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
2899
2900 };
2901
2902 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
2903                                 struct snd_kcontrol *kcontrol,
2904                                 int event)
2905 {
2906         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2907         u16 val, ec_hq_reg;
2908         int ec_tx = -1;
2909
2910         val = snd_soc_component_read(component,
2911                         CDC_RX_INP_MUX_RX_MIX_CFG4);
2912         if (!(strcmp(w->name, "RX MIX TX0 MUX")))
2913                 ec_tx = ((val & 0xf0) >> 0x4) - 1;
2914         else if (!(strcmp(w->name, "RX MIX TX1 MUX")))
2915                 ec_tx = (val & 0x0f) - 1;
2916
2917         val = snd_soc_component_read(component,
2918                         CDC_RX_INP_MUX_RX_MIX_CFG5);
2919         if (!(strcmp(w->name, "RX MIX TX2 MUX")))
2920                 ec_tx = (val & 0x0f) - 1;
2921
2922         if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
2923                 dev_err(component->dev, "%s: EC mix control not set correctly\n",
2924                         __func__);
2925                 return -EINVAL;
2926         }
2927         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
2928                             0x40 * ec_tx;
2929         snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
2930         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
2931                                 0x40 * ec_tx;
2932         /* default set to 48k */
2933         snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
2934
2935         return 0;
2936 }
2937
2938 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
2939         SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2940                 SND_SOC_NOPM, 0, 0),
2941
2942         SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2943                 SND_SOC_NOPM, 0, 0),
2944
2945         SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2946                 SND_SOC_NOPM, 0, 0),
2947
2948         SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2949                 SND_SOC_NOPM, 0, 0),
2950
2951         SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2952                 SND_SOC_NOPM, 0, 0),
2953
2954         SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
2955                          &rx_macro_rx0_mux),
2956         SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
2957                          &rx_macro_rx1_mux),
2958         SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
2959                          &rx_macro_rx2_mux),
2960         SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
2961                          &rx_macro_rx3_mux),
2962         SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
2963                          &rx_macro_rx4_mux),
2964         SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
2965                          &rx_macro_rx5_mux),
2966
2967         SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2968         SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2969         SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
2970         SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
2971         SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
2972         SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
2973
2974         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
2975         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
2976         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
2977         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
2978         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
2979         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2980         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
2981         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
2982
2983         SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2984                            RX_MACRO_EC0_MUX, 0,
2985                            &rx_mix_tx0_mux, rx_macro_enable_echo,
2986                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2987         SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2988                            RX_MACRO_EC1_MUX, 0,
2989                            &rx_mix_tx1_mux, rx_macro_enable_echo,
2990                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2991         SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
2992                            RX_MACRO_EC2_MUX, 0,
2993                            &rx_mix_tx2_mux, rx_macro_enable_echo,
2994                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2995
2996         SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
2997                 4, 0, NULL, 0, rx_macro_set_iir_gain,
2998                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2999         SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
3000                 4, 0, NULL, 0, rx_macro_set_iir_gain,
3001                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
3002         SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
3003                 4, 0, NULL, 0),
3004         SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
3005                 4, 0, NULL, 0),
3006
3007         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3008                          &rx_int0_dem_inp_mux),
3009         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3010                          &rx_int1_dem_inp_mux),
3011
3012         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3013                 &rx_int0_2_mux, rx_macro_enable_mix_path,
3014                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3015                 SND_SOC_DAPM_POST_PMD),
3016         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3017                 &rx_int1_2_mux, rx_macro_enable_mix_path,
3018                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3019                 SND_SOC_DAPM_POST_PMD),
3020         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3021                 &rx_int2_2_mux, rx_macro_enable_mix_path,
3022                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3023                 SND_SOC_DAPM_POST_PMD),
3024
3025         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3026         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3027         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3028         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3029         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3030         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3031         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3032         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3033         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3034
3035         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3036                 &rx_int0_1_interp_mux, rx_macro_enable_main_path,
3037                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3038                 SND_SOC_DAPM_POST_PMD),
3039         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3040                 &rx_int1_1_interp_mux, rx_macro_enable_main_path,
3041                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3042                 SND_SOC_DAPM_POST_PMD),
3043         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3044                 &rx_int2_1_interp_mux, rx_macro_enable_main_path,
3045                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3046                 SND_SOC_DAPM_POST_PMD),
3047
3048         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3049                          &rx_int0_2_interp_mux),
3050         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3051                          &rx_int1_2_interp_mux),
3052         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3053                          &rx_int2_2_interp_mux),
3054
3055         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3056         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3057         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3058         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3059         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3060         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3061
3062         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3063                 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3064                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3065         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3066                 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3067                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3068         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3069                 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3070                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3071
3072         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3073         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3074         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3075
3076         SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
3077         SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
3078         SND_SOC_DAPM_OUTPUT("AUX_OUT"),
3079
3080         SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
3081         SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
3082         SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
3083         SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
3084
3085         SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3086         rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3087 };
3088
3089 static const struct snd_soc_dapm_route rx_audio_map[] = {
3090         {"RX AIF1 PB", NULL, "RX_MCLK"},
3091         {"RX AIF2 PB", NULL, "RX_MCLK"},
3092         {"RX AIF3 PB", NULL, "RX_MCLK"},
3093         {"RX AIF4 PB", NULL, "RX_MCLK"},
3094
3095         {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3096         {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3097         {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3098         {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3099         {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3100         {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3101
3102         {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3103         {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3104         {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3105         {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3106         {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3107         {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3108
3109         {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3110         {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3111         {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3112         {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3113         {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3114         {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3115
3116         {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3117         {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3118         {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3119         {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3120         {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3121         {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3122
3123         {"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
3124         {"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
3125         {"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
3126         {"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
3127         {"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
3128         {"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
3129
3130         {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3131         {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3132         {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3133         {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3134         {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3135         {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3136         {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3137         {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3138         {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3139         {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3140         {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3141         {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3142         {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3143         {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3144         {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3145         {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3146         {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3147         {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3148         {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3149         {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3150         {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3151         {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3152         {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3153         {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3154         {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3155         {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3156         {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3157         {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3158         {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3159         {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3160
3161         {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3162         {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3163         {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3164         {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3165         {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3166         {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3167         {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3168         {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3169         {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3170         {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3171         {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3172         {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3173         {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3174         {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3175         {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3176         {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3177         {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3178         {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3179         {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3180         {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3181         {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3182         {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3183         {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3184         {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3185         {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3186         {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3187         {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3188         {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3189         {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3190         {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3191
3192         {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3193         {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3194         {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3195         {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3196         {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3197         {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3198         {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3199         {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3200         {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3201         {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3202         {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3203         {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3204         {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3205         {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3206         {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3207         {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3208         {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3209         {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3210         {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3211         {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3212         {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3213         {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3214         {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3215         {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3216         {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3217         {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3218         {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3219         {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3220         {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3221         {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3222
3223         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3224         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3225         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3226         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3227         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3228         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3229         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3230         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3231         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3232
3233         {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3234         {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3235         {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3236         {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3237         {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3238         {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3239         {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3240         {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3241         {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3242         {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3243         {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3244         {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3245         {"RX AIF_ECHO", NULL, "RX_MCLK"},
3246
3247         /* Mixing path INT0 */
3248         {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3249         {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3250         {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3251         {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3252         {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3253         {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3254         {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3255         {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3256
3257         /* Mixing path INT1 */
3258         {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3259         {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3260         {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3261         {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3262         {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3263         {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3264         {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3265         {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3266
3267         /* Mixing path INT2 */
3268         {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3269         {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3270         {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3271         {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3272         {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3273         {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3274         {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3275         {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3276
3277         {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3278         {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3279         {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3280         {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3281         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3282         {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3283         {"HPHL_OUT", NULL, "RX_MCLK"},
3284
3285         {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3286         {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3287         {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3288         {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3289         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3290         {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3291         {"HPHR_OUT", NULL, "RX_MCLK"},
3292
3293         {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3294
3295         {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3296         {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3297         {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3298         {"AUX_OUT", NULL, "RX INT2 MIX2"},
3299         {"AUX_OUT", NULL, "RX_MCLK"},
3300
3301         {"IIR0", NULL, "RX_MCLK"},
3302         {"IIR0", NULL, "IIR0 INP0 MUX"},
3303         {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3304         {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3305         {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3306         {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3307         {"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3308         {"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3309         {"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3310         {"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3311         {"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3312         {"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3313         {"IIR0", NULL, "IIR0 INP1 MUX"},
3314         {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3315         {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3316         {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3317         {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3318         {"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3319         {"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3320         {"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3321         {"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3322         {"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3323         {"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3324         {"IIR0", NULL, "IIR0 INP2 MUX"},
3325         {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3326         {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3327         {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3328         {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3329         {"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3330         {"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3331         {"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3332         {"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3333         {"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3334         {"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3335         {"IIR0", NULL, "IIR0 INP3 MUX"},
3336         {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3337         {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3338         {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3339         {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3340         {"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3341         {"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3342         {"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3343         {"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3344         {"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3345         {"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3346
3347         {"IIR1", NULL, "RX_MCLK"},
3348         {"IIR1", NULL, "IIR1 INP0 MUX"},
3349         {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3350         {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3351         {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3352         {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3353         {"IIR1 INP0 MUX", "RX0", "RX_RX0"},
3354         {"IIR1 INP0 MUX", "RX1", "RX_RX1"},
3355         {"IIR1 INP0 MUX", "RX2", "RX_RX2"},
3356         {"IIR1 INP0 MUX", "RX3", "RX_RX3"},
3357         {"IIR1 INP0 MUX", "RX4", "RX_RX4"},
3358         {"IIR1 INP0 MUX", "RX5", "RX_RX5"},
3359         {"IIR1", NULL, "IIR1 INP1 MUX"},
3360         {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3361         {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3362         {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3363         {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3364         {"IIR1 INP1 MUX", "RX0", "RX_RX0"},
3365         {"IIR1 INP1 MUX", "RX1", "RX_RX1"},
3366         {"IIR1 INP1 MUX", "RX2", "RX_RX2"},
3367         {"IIR1 INP1 MUX", "RX3", "RX_RX3"},
3368         {"IIR1 INP1 MUX", "RX4", "RX_RX4"},
3369         {"IIR1 INP1 MUX", "RX5", "RX_RX5"},
3370         {"IIR1", NULL, "IIR1 INP2 MUX"},
3371         {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3372         {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3373         {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3374         {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3375         {"IIR1 INP2 MUX", "RX0", "RX_RX0"},
3376         {"IIR1 INP2 MUX", "RX1", "RX_RX1"},
3377         {"IIR1 INP2 MUX", "RX2", "RX_RX2"},
3378         {"IIR1 INP2 MUX", "RX3", "RX_RX3"},
3379         {"IIR1 INP2 MUX", "RX4", "RX_RX4"},
3380         {"IIR1 INP2 MUX", "RX5", "RX_RX5"},
3381         {"IIR1", NULL, "IIR1 INP3 MUX"},
3382         {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3383         {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3384         {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3385         {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3386         {"IIR1 INP3 MUX", "RX0", "RX_RX0"},
3387         {"IIR1 INP3 MUX", "RX1", "RX_RX1"},
3388         {"IIR1 INP3 MUX", "RX2", "RX_RX2"},
3389         {"IIR1 INP3 MUX", "RX3", "RX_RX3"},
3390         {"IIR1 INP3 MUX", "RX4", "RX_RX4"},
3391         {"IIR1 INP3 MUX", "RX5", "RX_RX5"},
3392
3393         {"SRC0", NULL, "IIR0"},
3394         {"SRC1", NULL, "IIR1"},
3395         {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3396         {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3397         {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3398         {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3399         {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3400         {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3401 };
3402
3403 static int rx_macro_component_probe(struct snd_soc_component *component)
3404 {
3405         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
3406
3407         snd_soc_component_init_regmap(component, rx->regmap);
3408
3409         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
3410                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3411                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3412         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
3413                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3414                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3415         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
3416                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3417                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3418         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
3419                                       CDC_RX_DC_COEFF_SEL_MASK,
3420                                       CDC_RX_DC_COEFF_SEL_TWO);
3421         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
3422                                       CDC_RX_DC_COEFF_SEL_MASK,
3423                                       CDC_RX_DC_COEFF_SEL_TWO);
3424         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
3425                                       CDC_RX_DC_COEFF_SEL_MASK,
3426                                       CDC_RX_DC_COEFF_SEL_TWO);
3427
3428         rx->component = component;
3429
3430         return 0;
3431 }
3432
3433 static int swclk_gate_enable(struct clk_hw *hw)
3434 {
3435         struct rx_macro *rx = to_rx_macro(hw);
3436         int ret;
3437
3438         ret = clk_prepare_enable(rx->mclk);
3439         if (ret) {
3440                 dev_err(rx->dev, "unable to prepare mclk\n");
3441                 return ret;
3442         }
3443
3444         rx_macro_mclk_enable(rx, true);
3445         if (rx->reset_swr)
3446                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3447                                    CDC_RX_SWR_RESET_MASK,
3448                                    CDC_RX_SWR_RESET);
3449
3450         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3451                            CDC_RX_SWR_CLK_EN_MASK, 1);
3452
3453         if (rx->reset_swr)
3454                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3455                                    CDC_RX_SWR_RESET_MASK, 0);
3456         rx->reset_swr = false;
3457
3458         return 0;
3459 }
3460
3461 static void swclk_gate_disable(struct clk_hw *hw)
3462 {
3463         struct rx_macro *rx = to_rx_macro(hw);
3464
3465         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3466                            CDC_RX_SWR_CLK_EN_MASK, 0);
3467
3468         rx_macro_mclk_enable(rx, false);
3469         clk_disable_unprepare(rx->mclk);
3470 }
3471
3472 static int swclk_gate_is_enabled(struct clk_hw *hw)
3473 {
3474         struct rx_macro *rx = to_rx_macro(hw);
3475         int ret, val;
3476
3477         regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val);
3478         ret = val & BIT(0);
3479
3480         return ret;
3481 }
3482
3483 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
3484                                        unsigned long parent_rate)
3485 {
3486         return parent_rate / 2;
3487 }
3488
3489 static const struct clk_ops swclk_gate_ops = {
3490         .prepare = swclk_gate_enable,
3491         .unprepare = swclk_gate_disable,
3492         .is_enabled = swclk_gate_is_enabled,
3493         .recalc_rate = swclk_recalc_rate,
3494
3495 };
3496
3497 static int rx_macro_register_mclk_output(struct rx_macro *rx)
3498 {
3499         struct device *dev = rx->dev;
3500         const char *parent_clk_name = NULL;
3501         const char *clk_name = "lpass-rx-mclk";
3502         struct clk_hw *hw;
3503         struct clk_init_data init;
3504         int ret;
3505
3506         parent_clk_name = __clk_get_name(rx->npl);
3507
3508         init.name = clk_name;
3509         init.ops = &swclk_gate_ops;
3510         init.flags = 0;
3511         init.parent_names = &parent_clk_name;
3512         init.num_parents = 1;
3513         rx->hw.init = &init;
3514         hw = &rx->hw;
3515         ret = devm_clk_hw_register(rx->dev, hw);
3516         if (ret)
3517                 return ret;
3518
3519         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
3520 }
3521
3522 static const struct snd_soc_component_driver rx_macro_component_drv = {
3523         .name = "RX-MACRO",
3524         .probe = rx_macro_component_probe,
3525         .controls = rx_macro_snd_controls,
3526         .num_controls = ARRAY_SIZE(rx_macro_snd_controls),
3527         .dapm_widgets = rx_macro_dapm_widgets,
3528         .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
3529         .dapm_routes = rx_audio_map,
3530         .num_dapm_routes = ARRAY_SIZE(rx_audio_map),
3531 };
3532
3533 static int rx_macro_probe(struct platform_device *pdev)
3534 {
3535         struct device *dev = &pdev->dev;
3536         struct rx_macro *rx;
3537         void __iomem *base;
3538         int ret;
3539
3540         rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
3541         if (!rx)
3542                 return -ENOMEM;
3543
3544         rx->macro = devm_clk_get_optional(dev, "macro");
3545         if (IS_ERR(rx->macro))
3546                 return PTR_ERR(rx->macro);
3547
3548         rx->dcodec = devm_clk_get_optional(dev, "dcodec");
3549         if (IS_ERR(rx->dcodec))
3550                 return PTR_ERR(rx->dcodec);
3551
3552         rx->mclk = devm_clk_get(dev, "mclk");
3553         if (IS_ERR(rx->mclk))
3554                 return PTR_ERR(rx->mclk);
3555
3556         rx->npl = devm_clk_get(dev, "npl");
3557         if (IS_ERR(rx->npl))
3558                 return PTR_ERR(rx->npl);
3559
3560         rx->fsgen = devm_clk_get(dev, "fsgen");
3561         if (IS_ERR(rx->fsgen))
3562                 return PTR_ERR(rx->fsgen);
3563
3564         rx->pds = lpass_macro_pds_init(dev);
3565         if (IS_ERR(rx->pds))
3566                 return PTR_ERR(rx->pds);
3567
3568         base = devm_platform_ioremap_resource(pdev, 0);
3569         if (IS_ERR(base)) {
3570                 ret = PTR_ERR(base);
3571                 goto err;
3572         }
3573
3574         rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
3575         if (IS_ERR(rx->regmap)) {
3576                 ret = PTR_ERR(rx->regmap);
3577                 goto err;
3578         }
3579
3580         dev_set_drvdata(dev, rx);
3581
3582         rx->reset_swr = true;
3583         rx->dev = dev;
3584
3585         /* set MCLK and NPL rates */
3586         clk_set_rate(rx->mclk, MCLK_FREQ);
3587         clk_set_rate(rx->npl, 2 * MCLK_FREQ);
3588
3589         ret = clk_prepare_enable(rx->macro);
3590         if (ret)
3591                 goto err;
3592
3593         ret = clk_prepare_enable(rx->dcodec);
3594         if (ret)
3595                 goto err_dcodec;
3596
3597         ret = clk_prepare_enable(rx->mclk);
3598         if (ret)
3599                 goto err_mclk;
3600
3601         ret = clk_prepare_enable(rx->npl);
3602         if (ret)
3603                 goto err_npl;
3604
3605         ret = clk_prepare_enable(rx->fsgen);
3606         if (ret)
3607                 goto err_fsgen;
3608
3609         ret = rx_macro_register_mclk_output(rx);
3610         if (ret)
3611                 goto err_clkout;
3612
3613         ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
3614                                               rx_macro_dai,
3615                                               ARRAY_SIZE(rx_macro_dai));
3616         if (ret)
3617                 goto err_clkout;
3618
3619
3620         pm_runtime_set_autosuspend_delay(dev, 3000);
3621         pm_runtime_use_autosuspend(dev);
3622         pm_runtime_mark_last_busy(dev);
3623         pm_runtime_set_active(dev);
3624         pm_runtime_enable(dev);
3625
3626         return 0;
3627
3628 err_clkout:
3629         clk_disable_unprepare(rx->fsgen);
3630 err_fsgen:
3631         clk_disable_unprepare(rx->npl);
3632 err_npl:
3633         clk_disable_unprepare(rx->mclk);
3634 err_mclk:
3635         clk_disable_unprepare(rx->dcodec);
3636 err_dcodec:
3637         clk_disable_unprepare(rx->macro);
3638 err:
3639         lpass_macro_pds_exit(rx->pds);
3640
3641         return ret;
3642 }
3643
3644 static int rx_macro_remove(struct platform_device *pdev)
3645 {
3646         struct rx_macro *rx = dev_get_drvdata(&pdev->dev);
3647
3648         clk_disable_unprepare(rx->mclk);
3649         clk_disable_unprepare(rx->npl);
3650         clk_disable_unprepare(rx->fsgen);
3651         clk_disable_unprepare(rx->macro);
3652         clk_disable_unprepare(rx->dcodec);
3653
3654         lpass_macro_pds_exit(rx->pds);
3655
3656         return 0;
3657 }
3658
3659 static const struct of_device_id rx_macro_dt_match[] = {
3660         { .compatible = "qcom,sc7280-lpass-rx-macro" },
3661         { .compatible = "qcom,sm8250-lpass-rx-macro" },
3662         { }
3663 };
3664 MODULE_DEVICE_TABLE(of, rx_macro_dt_match);
3665
3666 static int __maybe_unused rx_macro_runtime_suspend(struct device *dev)
3667 {
3668         struct rx_macro *rx = dev_get_drvdata(dev);
3669
3670         regcache_cache_only(rx->regmap, true);
3671         regcache_mark_dirty(rx->regmap);
3672
3673         clk_disable_unprepare(rx->mclk);
3674         clk_disable_unprepare(rx->npl);
3675         clk_disable_unprepare(rx->fsgen);
3676
3677         return 0;
3678 }
3679
3680 static int __maybe_unused rx_macro_runtime_resume(struct device *dev)
3681 {
3682         struct rx_macro *rx = dev_get_drvdata(dev);
3683         int ret;
3684
3685         ret = clk_prepare_enable(rx->mclk);
3686         if (ret) {
3687                 dev_err(dev, "unable to prepare mclk\n");
3688                 return ret;
3689         }
3690
3691         ret = clk_prepare_enable(rx->npl);
3692         if (ret) {
3693                 dev_err(dev, "unable to prepare mclkx2\n");
3694                 goto err_npl;
3695         }
3696
3697         ret = clk_prepare_enable(rx->fsgen);
3698         if (ret) {
3699                 dev_err(dev, "unable to prepare fsgen\n");
3700                 goto err_fsgen;
3701         }
3702         regcache_cache_only(rx->regmap, false);
3703         regcache_sync(rx->regmap);
3704         rx->reset_swr = true;
3705
3706         return 0;
3707 err_fsgen:
3708         clk_disable_unprepare(rx->npl);
3709 err_npl:
3710         clk_disable_unprepare(rx->mclk);
3711
3712         return ret;
3713 }
3714
3715 static const struct dev_pm_ops rx_macro_pm_ops = {
3716         SET_RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL)
3717 };
3718
3719 static struct platform_driver rx_macro_driver = {
3720         .driver = {
3721                 .name = "rx_macro",
3722                 .of_match_table = rx_macro_dt_match,
3723                 .suppress_bind_attrs = true,
3724                 .pm = &rx_macro_pm_ops,
3725         },
3726         .probe = rx_macro_probe,
3727         .remove = rx_macro_remove,
3728 };
3729
3730 module_platform_driver(rx_macro_driver);
3731
3732 MODULE_DESCRIPTION("RX macro driver");
3733 MODULE_LICENSE("GPL");