2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
4 * Copyright 2012 CirrusLogic, Inc.
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/of_gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
43 struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
53 struct input_dev *beep;
54 struct work_struct beep_work;
58 static const struct reg_default cs42l52_reg_defaults[] = {
59 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
60 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
61 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
62 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
63 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
64 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
65 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
66 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
67 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
68 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
69 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
70 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
71 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
72 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
73 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
74 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
75 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
76 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
77 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
78 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
79 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
80 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
81 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
82 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
83 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
84 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
85 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
86 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
87 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
88 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
89 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
90 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
91 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
92 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
93 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
94 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
95 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
96 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
97 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
98 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
99 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
100 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
101 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
102 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
103 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
104 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
105 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
106 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
107 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
110 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
113 case CS42L52_CHIP ... CS42L52_CHARGE_PUMP:
120 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
123 case CS42L52_IFACE_CTL2:
124 case CS42L52_CLK_STATUS:
125 case CS42L52_BATT_LEVEL:
126 case CS42L52_SPK_STATUS:
127 case CS42L52_CHARGE_PUMP:
134 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
136 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
138 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
140 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
142 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
144 static DECLARE_TLV_DB_SCALE(pass_tlv, -6000, 50, 0);
146 static DECLARE_TLV_DB_SCALE(mix_tlv, -5150, 50, 0);
148 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
150 static const DECLARE_TLV_DB_RANGE(limiter_tlv,
151 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
152 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
155 static const char * const cs42l52_adca_text[] = {
156 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
158 static const char * const cs42l52_adcb_text[] = {
159 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
161 static SOC_ENUM_SINGLE_DECL(adca_enum,
162 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
164 static SOC_ENUM_SINGLE_DECL(adcb_enum,
165 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
167 static const struct snd_kcontrol_new adca_mux =
168 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
170 static const struct snd_kcontrol_new adcb_mux =
171 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
173 static const char * const mic_bias_level_text[] = {
174 "0.5 +VA", "0.6 +VA", "0.7 +VA",
175 "0.8 +VA", "0.83 +VA", "0.91 +VA"
178 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
179 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
181 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
183 static SOC_ENUM_SINGLE_DECL(mica_enum,
184 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
186 static SOC_ENUM_SINGLE_DECL(micb_enum,
187 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
189 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
191 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
192 CS42L52_ADC_MISC_CTL, 6,
193 digital_output_mux_text);
195 static const struct snd_kcontrol_new digital_output_mux =
196 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
198 static const char * const hp_gain_num_text[] = {
199 "0.3959", "0.4571", "0.5111", "0.6047",
200 "0.7099", "0.8399", "1.000", "1.1430"
203 static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
207 static const char * const beep_pitch_text[] = {
208 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
209 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
212 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
213 CS42L52_BEEP_FREQ, 4,
216 static const char * const beep_ontime_text[] = {
217 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
218 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
219 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
222 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
223 CS42L52_BEEP_FREQ, 0,
226 static const char * const beep_offtime_text[] = {
227 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
228 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
231 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
235 static const char * const beep_config_text[] = {
236 "Off", "Single", "Multiple", "Continuous"
239 static SOC_ENUM_SINGLE_DECL(beep_config_enum,
240 CS42L52_BEEP_TONE_CTL, 6,
243 static const char * const beep_bass_text[] = {
244 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
247 static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
248 CS42L52_BEEP_TONE_CTL, 1,
251 static const char * const beep_treble_text[] = {
252 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
255 static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
256 CS42L52_BEEP_TONE_CTL, 3,
259 static const char * const ng_threshold_text[] = {
260 "-34dB", "-37dB", "-40dB", "-43dB",
261 "-46dB", "-52dB", "-58dB", "-64dB"
264 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
265 CS42L52_NOISE_GATE_CTL, 2,
268 static const char * const cs42l52_ng_delay_text[] = {
269 "50ms", "100ms", "150ms", "200ms"};
271 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
272 CS42L52_NOISE_GATE_CTL, 0,
273 cs42l52_ng_delay_text);
275 static const char * const cs42l52_ng_type_text[] = {
276 "Apply Specific", "Apply All"
279 static SOC_ENUM_SINGLE_DECL(ng_type_enum,
280 CS42L52_NOISE_GATE_CTL, 6,
281 cs42l52_ng_type_text);
283 static const char * const left_swap_text[] = {
284 "Left", "LR 2", "Right"};
286 static const char * const right_swap_text[] = {
287 "Right", "LR 2", "Left"};
289 static const unsigned int swap_values[] = { 0, 1, 3 };
291 static const struct soc_enum adca_swap_enum =
292 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
293 ARRAY_SIZE(left_swap_text),
297 static const struct snd_kcontrol_new adca_mixer =
298 SOC_DAPM_ENUM("Route", adca_swap_enum);
300 static const struct soc_enum pcma_swap_enum =
301 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
302 ARRAY_SIZE(left_swap_text),
306 static const struct snd_kcontrol_new pcma_mixer =
307 SOC_DAPM_ENUM("Route", pcma_swap_enum);
309 static const struct soc_enum adcb_swap_enum =
310 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
311 ARRAY_SIZE(right_swap_text),
315 static const struct snd_kcontrol_new adcb_mixer =
316 SOC_DAPM_ENUM("Route", adcb_swap_enum);
318 static const struct soc_enum pcmb_swap_enum =
319 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
320 ARRAY_SIZE(right_swap_text),
324 static const struct snd_kcontrol_new pcmb_mixer =
325 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
328 static const struct snd_kcontrol_new passthrul_ctl =
329 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
331 static const struct snd_kcontrol_new passthrur_ctl =
332 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
334 static const struct snd_kcontrol_new spkl_ctl =
335 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
337 static const struct snd_kcontrol_new spkr_ctl =
338 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
340 static const struct snd_kcontrol_new hpl_ctl =
341 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
343 static const struct snd_kcontrol_new hpr_ctl =
344 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
346 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
348 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
349 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
351 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
352 CS42L52_HPB_VOL, 0, 0x34, 0xC0, hpd_tlv),
354 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
356 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
357 CS42L52_SPKB_VOL, 0, 0x40, 0xC0, hl_tlv),
359 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
360 CS42L52_PASSTHRUB_VOL, 0, 0x88, 0x90, pass_tlv),
362 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
364 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
365 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
367 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
369 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
370 CS42L52_ADCB_VOL, 0, 0xA0, 0x78, ipd_tlv),
371 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
372 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
373 0, 0x19, 0x7F, mix_tlv),
375 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
377 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
378 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
380 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
381 CS42L52_PGAB_CTL, 0, 0x28, 0x24, pga_tlv),
383 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
384 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
385 0, 0x19, 0x7f, mix_tlv),
386 SOC_DOUBLE_R("PCM Mixer Switch",
387 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
389 SOC_ENUM("Beep Config", beep_config_enum),
390 SOC_ENUM("Beep Pitch", beep_pitch_enum),
391 SOC_ENUM("Beep on Time", beep_ontime_enum),
392 SOC_ENUM("Beep off Time", beep_offtime_enum),
393 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
394 0, 0x07, 0x1f, beep_tlv),
395 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
396 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
397 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
399 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
400 SOC_SINGLE_TLV("Treble Gain Volume",
401 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
402 SOC_SINGLE_TLV("Bass Gain Volume",
403 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
406 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
407 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
408 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
409 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
410 SOC_SINGLE_TLV("Limiter Release Rate Volume",
411 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
412 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
413 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
415 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
416 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
417 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
420 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
421 0, 63, 0, limiter_tlv),
422 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
423 0, 63, 0, limiter_tlv),
424 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
425 5, 7, 0, limiter_tlv),
426 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
427 2, 7, 0, limiter_tlv),
429 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
430 CS42L52_PGAB_CTL, 7, 1, 1),
431 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
432 CS42L52_PGAB_CTL, 6, 1, 1),
433 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
436 SOC_ENUM("NG Type Switch", ng_type_enum),
437 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
438 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
439 SOC_ENUM("NG Threshold", ng_threshold_enum),
440 SOC_ENUM("NG Delay", ng_delay_enum),
442 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
444 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
445 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
446 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
447 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
448 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
450 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
451 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
452 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
454 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
455 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
456 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
457 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
459 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
460 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
462 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
463 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
465 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
466 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
470 static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
471 SOC_ENUM("MICA Select", mica_enum),
474 static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
475 SOC_ENUM("MICB Select", micb_enum),
478 static int cs42l52_add_mic_controls(struct snd_soc_codec *codec)
480 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
481 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
483 if (!pdata->mica_diff_cfg)
484 snd_soc_add_codec_controls(codec, cs42l52_mica_controls,
485 ARRAY_SIZE(cs42l52_mica_controls));
487 if (!pdata->micb_diff_cfg)
488 snd_soc_add_codec_controls(codec, cs42l52_micb_controls,
489 ARRAY_SIZE(cs42l52_micb_controls));
494 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
496 SND_SOC_DAPM_INPUT("AIN1L"),
497 SND_SOC_DAPM_INPUT("AIN1R"),
498 SND_SOC_DAPM_INPUT("AIN2L"),
499 SND_SOC_DAPM_INPUT("AIN2R"),
500 SND_SOC_DAPM_INPUT("AIN3L"),
501 SND_SOC_DAPM_INPUT("AIN3R"),
502 SND_SOC_DAPM_INPUT("AIN4L"),
503 SND_SOC_DAPM_INPUT("AIN4R"),
504 SND_SOC_DAPM_INPUT("MICA"),
505 SND_SOC_DAPM_INPUT("MICB"),
506 SND_SOC_DAPM_SIGGEN("Beep"),
508 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
510 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
513 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
514 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
515 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
516 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
518 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
519 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
521 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
523 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
526 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
527 0, 0, &digital_output_mux),
529 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
530 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
532 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
533 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
535 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
537 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
540 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
541 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
543 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
544 6, 0, &passthrul_ctl),
545 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
546 7, 0, &passthrur_ctl),
548 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
550 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
553 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
554 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
556 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
557 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
559 SND_SOC_DAPM_OUTPUT("HPOUTA"),
560 SND_SOC_DAPM_OUTPUT("HPOUTB"),
561 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
562 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
566 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
568 {"Capture", NULL, "AIFOUTL"},
569 {"Capture", NULL, "AIFOUTL"},
571 {"AIFOUTL", NULL, "Output Mux"},
572 {"AIFOUTR", NULL, "Output Mux"},
574 {"Output Mux", "ADC", "ADC Left"},
575 {"Output Mux", "ADC", "ADC Right"},
577 {"ADC Left", NULL, "Charge Pump"},
578 {"ADC Right", NULL, "Charge Pump"},
580 {"Charge Pump", NULL, "ADC Left Mux"},
581 {"Charge Pump", NULL, "ADC Right Mux"},
583 {"ADC Left Mux", "Input1A", "AIN1L"},
584 {"ADC Right Mux", "Input1B", "AIN1R"},
585 {"ADC Left Mux", "Input2A", "AIN2L"},
586 {"ADC Right Mux", "Input2B", "AIN2R"},
587 {"ADC Left Mux", "Input3A", "AIN3L"},
588 {"ADC Right Mux", "Input3B", "AIN3R"},
589 {"ADC Left Mux", "Input4A", "AIN4L"},
590 {"ADC Right Mux", "Input4B", "AIN4R"},
591 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
592 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
594 {"PGA Left", "Switch", "AIN1L"},
595 {"PGA Right", "Switch", "AIN1R"},
596 {"PGA Left", "Switch", "AIN2L"},
597 {"PGA Right", "Switch", "AIN2R"},
598 {"PGA Left", "Switch", "AIN3L"},
599 {"PGA Right", "Switch", "AIN3R"},
600 {"PGA Left", "Switch", "AIN4L"},
601 {"PGA Right", "Switch", "AIN4R"},
603 {"PGA Left", "Switch", "PGA MICA"},
604 {"PGA MICA", NULL, "MICA"},
606 {"PGA Right", "Switch", "PGA MICB"},
607 {"PGA MICB", NULL, "MICB"},
609 {"HPOUTA", NULL, "HP Left Amp"},
610 {"HPOUTB", NULL, "HP Right Amp"},
611 {"HP Left Amp", NULL, "Bypass Left"},
612 {"HP Right Amp", NULL, "Bypass Right"},
613 {"Bypass Left", "Switch", "PGA Left"},
614 {"Bypass Right", "Switch", "PGA Right"},
615 {"HP Left Amp", "Switch", "DAC Left"},
616 {"HP Right Amp", "Switch", "DAC Right"},
618 {"SPKOUTA", NULL, "SPK Left Amp"},
619 {"SPKOUTB", NULL, "SPK Right Amp"},
621 {"SPK Left Amp", NULL, "Beep"},
622 {"SPK Right Amp", NULL, "Beep"},
623 {"SPK Left Amp", "Switch", "Playback"},
624 {"SPK Right Amp", "Switch", "Playback"},
626 {"DAC Left", NULL, "Beep"},
627 {"DAC Right", NULL, "Beep"},
628 {"DAC Left", NULL, "Playback"},
629 {"DAC Right", NULL, "Playback"},
631 {"Output Mux", "DSP", "Playback"},
632 {"Output Mux", "DSP", "Playback"},
634 {"AIFINL", NULL, "Playback"},
635 {"AIFINR", NULL, "Playback"},
639 struct cs42l52_clk_para {
649 static const struct cs42l52_clk_para clk_map_table[] = {
651 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
652 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
653 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
654 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
655 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
658 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
659 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
662 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
663 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
664 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
665 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
666 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
669 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
670 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
673 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
674 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
675 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
676 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
677 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
680 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
681 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
684 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
685 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
686 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
687 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
688 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
691 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
692 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
695 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
696 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
697 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
698 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
701 static int cs42l52_get_clk(int mclk, int rate)
703 int i, ret = -EINVAL;
704 u_int mclk1, mclk2 = 0;
706 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
707 if (clk_map_table[i].rate == rate) {
708 mclk1 = clk_map_table[i].mclk;
709 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
718 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
719 int clk_id, unsigned int freq, int dir)
721 struct snd_soc_codec *codec = codec_dai->codec;
722 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
724 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
725 cs42l52->sysclk = freq;
727 dev_err(codec->dev, "Invalid freq parameter\n");
733 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
735 struct snd_soc_codec *codec = codec_dai->codec;
736 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
739 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
740 case SND_SOC_DAIFMT_CBM_CFM:
741 iface = CS42L52_IFACE_CTL1_MASTER;
743 case SND_SOC_DAIFMT_CBS_CFS:
744 iface = CS42L52_IFACE_CTL1_SLAVE;
750 /* interface format */
751 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
752 case SND_SOC_DAIFMT_I2S:
753 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
754 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
756 case SND_SOC_DAIFMT_RIGHT_J:
757 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
759 case SND_SOC_DAIFMT_LEFT_J:
760 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
761 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
763 case SND_SOC_DAIFMT_DSP_A:
764 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
766 case SND_SOC_DAIFMT_DSP_B:
772 /* clock inversion */
773 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
774 case SND_SOC_DAIFMT_NB_NF:
776 case SND_SOC_DAIFMT_IB_IF:
777 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
779 case SND_SOC_DAIFMT_IB_NF:
780 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
782 case SND_SOC_DAIFMT_NB_IF:
787 cs42l52->config.format = iface;
788 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
793 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
795 struct snd_soc_codec *codec = dai->codec;
798 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
799 CS42L52_PB_CTL1_MUTE_MASK,
800 CS42L52_PB_CTL1_MUTE);
802 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
803 CS42L52_PB_CTL1_MUTE_MASK,
804 CS42L52_PB_CTL1_UNMUTE);
809 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
810 struct snd_pcm_hw_params *params,
811 struct snd_soc_dai *dai)
813 struct snd_soc_codec *codec = dai->codec;
814 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
818 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
820 cs42l52->sysclk = clk_map_table[index].mclk;
822 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
823 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
824 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
825 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
826 clk_map_table[index].mclkdiv2;
828 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
830 dev_err(codec->dev, "can't get correct mclk\n");
837 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
838 enum snd_soc_bias_level level)
840 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
843 case SND_SOC_BIAS_ON:
845 case SND_SOC_BIAS_PREPARE:
846 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
847 CS42L52_PWRCTL1_PDN_CODEC, 0);
849 case SND_SOC_BIAS_STANDBY:
850 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
851 regcache_cache_only(cs42l52->regmap, false);
852 regcache_sync(cs42l52->regmap);
854 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
856 case SND_SOC_BIAS_OFF:
857 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
858 regcache_cache_only(cs42l52->regmap, true);
865 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
867 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
868 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
869 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
870 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
872 static const struct snd_soc_dai_ops cs42l52_ops = {
873 .hw_params = cs42l52_pcm_hw_params,
874 .digital_mute = cs42l52_digital_mute,
875 .set_fmt = cs42l52_set_fmt,
876 .set_sysclk = cs42l52_set_sysclk,
879 static struct snd_soc_dai_driver cs42l52_dai = {
882 .stream_name = "Playback",
885 .rates = CS42L52_RATES,
886 .formats = CS42L52_FORMATS,
889 .stream_name = "Capture",
892 .rates = CS42L52_RATES,
893 .formats = CS42L52_FORMATS,
898 static int beep_rates[] = {
899 261, 522, 585, 667, 706, 774, 889, 1000,
900 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
903 static void cs42l52_beep_work(struct work_struct *work)
905 struct cs42l52_private *cs42l52 =
906 container_of(work, struct cs42l52_private, beep_work);
907 struct snd_soc_codec *codec = cs42l52->codec;
908 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
913 if (cs42l52->beep_rate) {
914 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
915 if (abs(cs42l52->beep_rate - beep_rates[i]) <
916 abs(cs42l52->beep_rate - beep_rates[best]))
920 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
921 beep_rates[best], cs42l52->beep_rate);
923 val = (best << CS42L52_BEEP_RATE_SHIFT);
925 snd_soc_dapm_enable_pin(dapm, "Beep");
927 dev_dbg(codec->dev, "Disabling beep\n");
928 snd_soc_dapm_disable_pin(dapm, "Beep");
931 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
932 CS42L52_BEEP_RATE_MASK, val);
934 snd_soc_dapm_sync(dapm);
937 /* For usability define a way of injecting beep events for the device -
938 * many systems will not have a keyboard.
940 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
941 unsigned int code, int hz)
943 struct snd_soc_codec *codec = input_get_drvdata(dev);
944 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
946 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
958 /* Kick the beep from a workqueue */
959 cs42l52->beep_rate = hz;
960 schedule_work(&cs42l52->beep_work);
964 static ssize_t cs42l52_beep_set(struct device *dev,
965 struct device_attribute *attr,
966 const char *buf, size_t count)
968 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
972 ret = kstrtol(buf, 10, &time);
976 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
981 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
983 static void cs42l52_init_beep(struct snd_soc_codec *codec)
985 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
988 cs42l52->beep = devm_input_allocate_device(codec->dev);
989 if (!cs42l52->beep) {
990 dev_err(codec->dev, "Failed to allocate beep device\n");
994 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
995 cs42l52->beep_rate = 0;
997 cs42l52->beep->name = "CS42L52 Beep Generator";
998 cs42l52->beep->phys = dev_name(codec->dev);
999 cs42l52->beep->id.bustype = BUS_I2C;
1001 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1002 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1003 cs42l52->beep->event = cs42l52_beep_event;
1004 cs42l52->beep->dev.parent = codec->dev;
1005 input_set_drvdata(cs42l52->beep, codec);
1007 ret = input_register_device(cs42l52->beep);
1009 cs42l52->beep = NULL;
1010 dev_err(codec->dev, "Failed to register beep device\n");
1013 ret = device_create_file(codec->dev, &dev_attr_beep);
1015 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1020 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1022 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1024 device_remove_file(codec->dev, &dev_attr_beep);
1025 cancel_work_sync(&cs42l52->beep_work);
1026 cs42l52->beep = NULL;
1028 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1029 CS42L52_BEEP_EN_MASK, 0);
1032 static int cs42l52_probe(struct snd_soc_codec *codec)
1034 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1036 regcache_cache_only(cs42l52->regmap, true);
1038 cs42l52_add_mic_controls(codec);
1040 cs42l52_init_beep(codec);
1042 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1043 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1048 static int cs42l52_remove(struct snd_soc_codec *codec)
1050 cs42l52_free_beep(codec);
1055 static const struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1056 .probe = cs42l52_probe,
1057 .remove = cs42l52_remove,
1058 .set_bias_level = cs42l52_set_bias_level,
1059 .suspend_bias_off = true,
1061 .component_driver = {
1062 .controls = cs42l52_snd_controls,
1063 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1064 .dapm_widgets = cs42l52_dapm_widgets,
1065 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1066 .dapm_routes = cs42l52_audio_map,
1067 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1071 /* Current and threshold powerup sequence Pg37 */
1072 static const struct reg_sequence cs42l52_threshold_patch[] = {
1083 static const struct regmap_config cs42l52_regmap = {
1087 .max_register = CS42L52_MAX_REGISTER,
1088 .reg_defaults = cs42l52_reg_defaults,
1089 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1090 .readable_reg = cs42l52_readable_register,
1091 .volatile_reg = cs42l52_volatile_register,
1092 .cache_type = REGCACHE_RBTREE,
1095 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1096 const struct i2c_device_id *id)
1098 struct cs42l52_private *cs42l52;
1099 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1101 unsigned int devid = 0;
1105 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1107 if (cs42l52 == NULL)
1109 cs42l52->dev = &i2c_client->dev;
1111 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1112 if (IS_ERR(cs42l52->regmap)) {
1113 ret = PTR_ERR(cs42l52->regmap);
1114 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1118 cs42l52->pdata = *pdata;
1120 pdata = devm_kzalloc(&i2c_client->dev,
1121 sizeof(struct cs42l52_platform_data),
1124 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1127 if (i2c_client->dev.of_node) {
1128 if (of_property_read_bool(i2c_client->dev.of_node,
1129 "cirrus,mica-differential-cfg"))
1130 pdata->mica_diff_cfg = true;
1132 if (of_property_read_bool(i2c_client->dev.of_node,
1133 "cirrus,micb-differential-cfg"))
1134 pdata->micb_diff_cfg = true;
1136 if (of_property_read_u32(i2c_client->dev.of_node,
1137 "cirrus,micbias-lvl", &val32) >= 0)
1138 pdata->micbias_lvl = val32;
1140 if (of_property_read_u32(i2c_client->dev.of_node,
1141 "cirrus,chgfreq-divisor", &val32) >= 0)
1142 pdata->chgfreq = val32;
1145 of_get_named_gpio(i2c_client->dev.of_node,
1146 "cirrus,reset-gpio", 0);
1148 cs42l52->pdata = *pdata;
1151 if (cs42l52->pdata.reset_gpio) {
1152 ret = devm_gpio_request_one(&i2c_client->dev,
1153 cs42l52->pdata.reset_gpio,
1154 GPIOF_OUT_INIT_HIGH,
1157 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1158 cs42l52->pdata.reset_gpio, ret);
1161 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1162 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1165 i2c_set_clientdata(i2c_client, cs42l52);
1167 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1168 ARRAY_SIZE(cs42l52_threshold_patch));
1170 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1173 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
1174 devid = reg & CS42L52_CHIP_ID_MASK;
1175 if (devid != CS42L52_CHIP_ID) {
1177 dev_err(&i2c_client->dev,
1178 "CS42L52 Device ID (%X). Expected %X\n",
1179 devid, CS42L52_CHIP_ID);
1183 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1184 reg & CS42L52_CHIP_REV_MASK);
1186 /* Set Platform Data */
1187 if (cs42l52->pdata.mica_diff_cfg)
1188 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1189 CS42L52_MIC_CTL_TYPE_MASK,
1190 cs42l52->pdata.mica_diff_cfg <<
1191 CS42L52_MIC_CTL_TYPE_SHIFT);
1193 if (cs42l52->pdata.micb_diff_cfg)
1194 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1195 CS42L52_MIC_CTL_TYPE_MASK,
1196 cs42l52->pdata.micb_diff_cfg <<
1197 CS42L52_MIC_CTL_TYPE_SHIFT);
1199 if (cs42l52->pdata.chgfreq)
1200 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1201 CS42L52_CHARGE_PUMP_MASK,
1202 cs42l52->pdata.chgfreq <<
1203 CS42L52_CHARGE_PUMP_SHIFT);
1205 if (cs42l52->pdata.micbias_lvl)
1206 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1207 CS42L52_IFACE_CTL2_BIAS_LVL,
1208 cs42l52->pdata.micbias_lvl);
1210 ret = snd_soc_register_codec(&i2c_client->dev,
1211 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1217 static int cs42l52_i2c_remove(struct i2c_client *client)
1219 snd_soc_unregister_codec(&client->dev);
1223 static const struct of_device_id cs42l52_of_match[] = {
1224 { .compatible = "cirrus,cs42l52", },
1227 MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1230 static const struct i2c_device_id cs42l52_id[] = {
1234 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1236 static struct i2c_driver cs42l52_i2c_driver = {
1239 .of_match_table = cs42l52_of_match,
1241 .id_table = cs42l52_id,
1242 .probe = cs42l52_i2c_probe,
1243 .remove = cs42l52_i2c_remove,
1246 module_i2c_driver(cs42l52_i2c_driver);
1248 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1249 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1250 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1251 MODULE_LICENSE("GPL");