2 * cs42l42.h -- CS42L42 ALSA SoC audio driver header
4 * Copyright 2016 Cirrus Logic, Inc.
6 * Author: James Schulman <james.schulman@cirrus.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 * Author: Michael White <michael.white@cirrus.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
19 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
20 #define CS42L42_WIN_START 0x00
21 #define CS42L42_WIN_LEN 0x100
22 #define CS42L42_RANGE_MIN 0x00
23 #define CS42L42_RANGE_MAX 0x7F
25 #define CS42L42_PAGE_10 0x1000
26 #define CS42L42_PAGE_11 0x1100
27 #define CS42L42_PAGE_12 0x1200
28 #define CS42L42_PAGE_13 0x1300
29 #define CS42L42_PAGE_15 0x1500
30 #define CS42L42_PAGE_19 0x1900
31 #define CS42L42_PAGE_1B 0x1B00
32 #define CS42L42_PAGE_1C 0x1C00
33 #define CS42L42_PAGE_1D 0x1D00
34 #define CS42L42_PAGE_1F 0x1F00
35 #define CS42L42_PAGE_20 0x2000
36 #define CS42L42_PAGE_21 0x2100
37 #define CS42L42_PAGE_23 0x2300
38 #define CS42L42_PAGE_24 0x2400
39 #define CS42L42_PAGE_25 0x2500
40 #define CS42L42_PAGE_26 0x2600
41 #define CS42L42_PAGE_28 0x2800
42 #define CS42L42_PAGE_29 0x2900
43 #define CS42L42_PAGE_2A 0x2A00
44 #define CS42L42_PAGE_30 0x3000
46 #define CS42L42_CHIP_ID 0x42A42
48 /* Page 0x10 Global Registers */
49 #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
50 #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
51 #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
52 #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
53 #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
54 #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
56 #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
57 #define CS42L42_SRC_BYPASS_DAC_SHIFT 1
58 #define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
60 #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
62 #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
63 #define CS42L42_INTERNAL_FS_SHIFT 1
64 #define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT)
66 #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
67 #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
68 #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
69 #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
71 /* Page 0x11 Power and Headset Detect Registers */
72 #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
73 #define CS42L42_ASP_DAO_PDN_SHIFT 7
74 #define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT)
75 #define CS42L42_ASP_DAI_PDN_SHIFT 6
76 #define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT)
77 #define CS42L42_MIXER_PDN_SHIFT 5
78 #define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT)
79 #define CS42L42_EQ_PDN_SHIFT 4
80 #define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT)
81 #define CS42L42_HP_PDN_SHIFT 3
82 #define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT)
83 #define CS42L42_ADC_PDN_SHIFT 2
84 #define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT)
85 #define CS42L42_PDN_ALL_SHIFT 0
86 #define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT)
88 #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
89 #define CS42L42_ADC_SRC_PDNB_SHIFT 0
90 #define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
91 #define CS42L42_DAC_SRC_PDNB_SHIFT 1
92 #define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
93 #define CS42L42_ASP_DAI1_PDN_SHIFT 2
94 #define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
95 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3
96 #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
97 #define CS42L42_DISCHARGE_FILT_SHIFT 4
98 #define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT)
100 #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
101 #define CS42L42_RING_SENSE_PDNB_SHIFT 1
102 #define CS42L42_RING_SENSE_PDNB_MASK (1 << \
103 CS42L42_RING_SENSE_PDNB_SHIFT)
104 #define CS42L42_VPMON_PDNB_SHIFT 2
105 #define CS42L42_VPMON_PDNB_MASK (1 << \
106 CS42L42_VPMON_PDNB_SHIFT)
107 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5
108 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << \
109 CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
111 #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
112 #define CS42L42_RS_TRIM_R_SHIFT 0
113 #define CS42L42_RS_TRIM_R_MASK (1 << \
114 CS42L42_RS_TRIM_R_SHIFT)
115 #define CS42L42_RS_TRIM_T_SHIFT 1
116 #define CS42L42_RS_TRIM_T_MASK (1 << \
117 CS42L42_RS_TRIM_T_SHIFT)
118 #define CS42L42_HPREF_RS_SHIFT 2
119 #define CS42L42_HPREF_RS_MASK (1 << \
120 CS42L42_HPREF_RS_SHIFT)
121 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3
122 #define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << \
123 CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
124 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6
125 #define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << \
126 CS42L42_RING_SENSE_PU_HIZ_SHIFT)
128 #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
129 #define CS42L42_TS_RS_GATE_SHIFT 7
130 #define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT)
132 #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
133 #define CS42L42_SCLK_PRESENT_SHIFT 0
134 #define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT)
136 #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
137 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
138 #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
139 #define CS42L42_OSC_PDNB_STAT_SHIFT 2
140 #define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
142 #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
143 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
144 #define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << \
145 CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
146 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3
147 #define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << \
148 CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
149 #define CS42L42_RS_PU_EN_SHIFT 6
150 #define CS42L42_RS_PU_EN_MASK (1 << \
151 CS42L42_RS_PU_EN_SHIFT)
152 #define CS42L42_RS_INV_SHIFT 7
153 #define CS42L42_RS_INV_MASK (1 << \
154 CS42L42_RS_INV_SHIFT)
156 #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
157 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
158 #define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << \
159 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
160 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3
161 #define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << \
162 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
163 #define CS42L42_TS_INV_SHIFT 7
164 #define CS42L42_TS_INV_MASK (1 << \
165 CS42L42_TS_INV_SHIFT)
167 #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
168 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
169 #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
170 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1
171 #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
172 #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2
173 #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
174 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3
175 #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
177 #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
178 #define CS42L42_RS_PLUG_DBNC_SHIFT 0
179 #define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
180 #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1
181 #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
182 #define CS42L42_TS_PLUG_DBNC_SHIFT 2
183 #define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
184 #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3
185 #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
187 #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
188 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0
189 #define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
190 #define CS42L42_HSDET_COMP2_LVL_SHIFT 4
191 #define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
193 #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
194 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0
195 #define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
196 #define CS42L42_HSBIAS_REF_SHIFT 3
197 #define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT)
198 #define CS42L42_HSDET_SET_SHIFT 4
199 #define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT)
200 #define CS42L42_HSDET_CTRL_SHIFT 6
201 #define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT)
203 #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
204 #define CS42L42_SW_GNDHS_HS4_SHIFT 0
205 #define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
206 #define CS42L42_SW_GNDHS_HS3_SHIFT 1
207 #define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
208 #define CS42L42_SW_HSB_HS4_SHIFT 2
209 #define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT)
210 #define CS42L42_SW_HSB_HS3_SHIFT 3
211 #define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT)
212 #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4
213 #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
214 #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5
215 #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
216 #define CS42L42_SW_REF_HS4_SHIFT 6
217 #define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT)
218 #define CS42L42_SW_REF_HS3_SHIFT 7
219 #define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT)
221 #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
222 #define CS42L42_HSDET_TYPE_SHIFT 0
223 #define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT)
224 #define CS42L42_HSDET_COMP1_OUT_SHIFT 6
225 #define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
226 #define CS42L42_HSDET_COMP2_OUT_SHIFT 7
227 #define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
228 #define CS42L42_PLUG_CTIA 0
229 #define CS42L42_PLUG_OMTP 1
230 #define CS42L42_PLUG_HEADPHONE 2
231 #define CS42L42_PLUG_INVALID 3
233 #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
234 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
235 #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
237 /* Page 0x12 Clocking Registers */
238 #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
239 #define CS42L42_MCLKDIV_SHIFT 1
240 #define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT)
241 #define CS42L42_MCLK_SRC_SEL_SHIFT 0
242 #define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
244 #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
245 #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
247 #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
248 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
249 #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
250 CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
252 #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
254 #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
255 #define CS42L42_FSYNC_PERIOD_SHIFT 0
256 #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
258 #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
259 #define CS42L42_ASP_SCLK_EN_SHIFT 5
260 #define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT)
261 #define CS42L42_ASP_MASTER_MODE 0x01
262 #define CS42L42_ASP_SLAVE_MODE 0x00
263 #define CS42L42_ASP_MODE_SHIFT 4
264 #define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT)
265 #define CS42L42_ASP_SCPOL_SHIFT 2
266 #define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT)
267 #define CS42L42_ASP_SCPOL_NOR 3
268 #define CS42L42_ASP_LCPOL_SHIFT 0
269 #define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT)
270 #define CS42L42_ASP_LCPOL_INV 3
272 #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
273 #define CS42L42_ASP_STP_SHIFT 4
274 #define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT)
275 #define CS42L42_ASP_5050_SHIFT 3
276 #define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT)
277 #define CS42L42_ASP_FSD_SHIFT 0
278 #define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT)
279 #define CS42L42_ASP_FSD_0_5 1
280 #define CS42L42_ASP_FSD_1_0 2
281 #define CS42L42_ASP_FSD_1_5 3
282 #define CS42L42_ASP_FSD_2_0 4
284 #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
285 #define CS42L42_FS_EN_SHIFT 0
286 #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
287 #define CS42L42_FS_EN_IASRC_96K 0x1
288 #define CS42L42_FS_EN_OASRC_96K 0x2
290 #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
291 #define CS42L42_CLK_IASRC_SEL_SHIFT 0
292 #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
293 #define CS42L42_CLK_IASRC_SEL_12 1
295 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
296 #define CS42L42_CLK_OASRC_SEL_SHIFT 0
297 #define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
298 #define CS42L42_CLK_OASRC_SEL_12 1
300 #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
301 #define CS42L42_SCLK_PREDIV_SHIFT 0
302 #define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT)
304 /* Page 0x13 Interrupt Registers */
306 #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
307 #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
308 #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
309 #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
310 #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
311 #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
312 #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
313 #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
314 #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
315 #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
316 #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
317 #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
319 #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
320 #define CS42L42_ADC_OVFL_SHIFT 0
321 #define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT)
322 #define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK
324 #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
325 #define CS42L42_MIX_CHB_OVFL_SHIFT 0
326 #define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
327 #define CS42L42_MIX_CHA_OVFL_SHIFT 1
328 #define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
329 #define CS42L42_EQ_OVFL_SHIFT 2
330 #define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT)
331 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3
332 #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
333 #define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \
334 CS42L42_MIX_CHA_OVFL_MASK | \
335 CS42L42_EQ_OVFL_MASK | \
336 CS42L42_EQ_BIQUAD_OVFL_MASK)
338 #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
339 #define CS42L42_SRC_ILK_SHIFT 0
340 #define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT)
341 #define CS42L42_SRC_OLK_SHIFT 1
342 #define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT)
343 #define CS42L42_SRC_IUNLK_SHIFT 2
344 #define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT)
345 #define CS42L42_SRC_OUNLK_SHIFT 3
346 #define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT)
347 #define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \
348 CS42L42_SRC_OLK_MASK | \
349 CS42L42_SRC_IUNLK_MASK | \
350 CS42L42_SRC_OUNLK_MASK)
352 #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
353 #define CS42L42_ASPRX_NOLRCK_SHIFT 0
354 #define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
355 #define CS42L42_ASPRX_EARLY_SHIFT 1
356 #define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT)
357 #define CS42L42_ASPRX_LATE_SHIFT 2
358 #define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT)
359 #define CS42L42_ASPRX_ERROR_SHIFT 3
360 #define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT)
361 #define CS42L42_ASPRX_OVLD_SHIFT 4
362 #define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT)
363 #define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \
364 CS42L42_ASPRX_EARLY_MASK | \
365 CS42L42_ASPRX_LATE_MASK | \
366 CS42L42_ASPRX_ERROR_MASK | \
367 CS42L42_ASPRX_OVLD_MASK)
369 #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
370 #define CS42L42_ASPTX_NOLRCK_SHIFT 0
371 #define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
372 #define CS42L42_ASPTX_EARLY_SHIFT 1
373 #define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT)
374 #define CS42L42_ASPTX_LATE_SHIFT 2
375 #define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT)
376 #define CS42L42_ASPTX_SMERROR_SHIFT 3
377 #define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT)
378 #define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \
379 CS42L42_ASPTX_EARLY_MASK | \
380 CS42L42_ASPTX_LATE_MASK | \
381 CS42L42_ASPTX_SMERROR_MASK)
383 #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
384 #define CS42L42_PDN_DONE_SHIFT 0
385 #define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT)
386 #define CS42L42_HSDET_AUTO_DONE_SHIFT 1
387 #define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
388 #define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \
389 CS42L42_HSDET_AUTO_DONE_MASK)
391 #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
392 #define CS42L42_SRCPL_ADC_LK_SHIFT 0
393 #define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
394 #define CS42L42_SRCPL_DAC_LK_SHIFT 2
395 #define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
396 #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5
397 #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
398 #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6
399 #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
400 #define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \
401 CS42L42_SRCPL_DAC_LK_MASK | \
402 CS42L42_SRCPL_ADC_UNLK_MASK | \
403 CS42L42_SRCPL_DAC_UNLK_MASK)
405 #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
406 #define CS42L42_VPMON_SHIFT 0
407 #define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT)
408 #define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK
410 #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
411 #define CS42L42_PLL_LOCK_SHIFT 0
412 #define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT)
413 #define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK
415 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
416 #define CS42L42_RS_PLUG_SHIFT 0
417 #define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT)
418 #define CS42L42_RS_UNPLUG_SHIFT 1
419 #define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT)
420 #define CS42L42_TS_PLUG_SHIFT 2
421 #define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT)
422 #define CS42L42_TS_UNPLUG_SHIFT 3
423 #define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT)
424 #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \
425 CS42L42_RS_UNPLUG_MASK | \
426 CS42L42_TS_PLUG_MASK | \
427 CS42L42_TS_UNPLUG_MASK)
428 #define CS42L42_TS_PLUG 3
429 #define CS42L42_TS_UNPLUG 0
430 #define CS42L42_TS_TRANS 1
432 /* Page 0x15 Fractional-N PLL Registers */
433 #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
434 #define CS42L42_PLL_START_SHIFT 0
435 #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT)
437 #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
438 #define CS42L42_PLL_DIV_FRAC_SHIFT 0
439 #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
441 #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
442 #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
444 #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
445 #define CS42L42_PLL_DIV_INT_SHIFT 0
446 #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
448 #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
449 #define CS42L42_PLL_DIVOUT_SHIFT 0
450 #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
452 #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
453 #define CS42L42_PLL_CAL_RATIO_SHIFT 0
454 #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
456 #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
457 #define CS42L42_PLL_MODE_SHIFT 0
458 #define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT)
460 /* Page 0x19 HP Load Detect Registers */
461 #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
462 #define CS42L42_RLA_STAT_SHIFT 0
463 #define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT)
464 #define CS42L42_RLA_STAT_15_OHM 0
466 #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
467 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0
468 #define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
470 #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
471 #define CS42L42_HP_LD_EN_SHIFT 0
472 #define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT)
474 /* Page 0x1B Headset Interface Registers */
475 #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
476 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
477 #define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << \
478 CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
479 #define CS42L42_TIP_SENSE_EN_SHIFT 5
480 #define CS42L42_TIP_SENSE_EN_MASK (1 << \
481 CS42L42_TIP_SENSE_EN_SHIFT)
482 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6
483 #define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << \
484 CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
485 #define CS42L42_HSBIAS_SENSE_EN_SHIFT 7
486 #define CS42L42_HSBIAS_SENSE_EN_MASK (1 << \
487 CS42L42_HSBIAS_SENSE_EN_SHIFT)
489 #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
490 #define CS42L42_WAKEB_CLEAR_SHIFT 0
491 #define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT)
492 #define CS42L42_WAKEB_MODE_SHIFT 5
493 #define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT)
494 #define CS42L42_M_HP_WAKE_SHIFT 6
495 #define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT)
496 #define CS42L42_M_MIC_WAKE_SHIFT 7
497 #define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT)
499 #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
500 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7
501 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << \
502 CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
504 #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
505 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
506 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << \
507 CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
508 #define CS42L42_TIP_SENSE_INV_SHIFT 5
509 #define CS42L42_TIP_SENSE_INV_MASK (1 << \
510 CS42L42_TIP_SENSE_INV_SHIFT)
511 #define CS42L42_TIP_SENSE_CTRL_SHIFT 6
512 #define CS42L42_TIP_SENSE_CTRL_MASK (3 << \
513 CS42L42_TIP_SENSE_CTRL_SHIFT)
515 #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
516 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
517 #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
518 #define CS42L42_HSBIAS_CTL_SHIFT 1
519 #define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT)
520 #define CS42L42_DETECT_MODE_SHIFT 3
521 #define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT)
523 #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
524 #define CS42L42_HS_DET_LEVEL_SHIFT 0
525 #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
526 #define CS42L42_EVENT_STAT_SEL_SHIFT 6
527 #define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
528 #define CS42L42_LATCH_TO_VP_SHIFT 7
529 #define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT)
531 #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
532 #define CS42L42_DEBOUNCE_TIME_SHIFT 5
533 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
535 #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
536 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6
537 #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
538 #define CS42L42_TIP_SENSE_SHIFT 7
539 #define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT)
541 #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
542 #define CS42L42_SHORT_TRUE_SHIFT 0
543 #define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT)
544 #define CS42L42_HS_TRUE_SHIFT 1
545 #define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT)
547 #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
548 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5
549 #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
550 #define CS42L42_TIP_SENSE_PLUG_SHIFT 6
551 #define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
552 #define CS42L42_HSBIAS_SENSE_SHIFT 7
553 #define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT)
554 #define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \
555 CS42L42_TIP_SENSE_PLUG_MASK | \
556 CS42L42_HSBIAS_SENSE_MASK)
558 #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
559 #define CS42L42_M_SHORT_DET_SHIFT 0
560 #define CS42L42_M_SHORT_DET_MASK (1 << \
561 CS42L42_M_SHORT_DET_SHIFT)
562 #define CS42L42_M_SHORT_RLS_SHIFT 1
563 #define CS42L42_M_SHORT_RLS_MASK (1 << \
564 CS42L42_M_SHORT_RLS_SHIFT)
565 #define CS42L42_M_HSBIAS_HIZ_SHIFT 2
566 #define CS42L42_M_HSBIAS_HIZ_MASK (1 << \
567 CS42L42_M_HSBIAS_HIZ_SHIFT)
568 #define CS42L42_M_DETECT_FT_SHIFT 6
569 #define CS42L42_M_DETECT_FT_MASK (1 << \
570 CS42L42_M_DETECT_FT_SHIFT)
571 #define CS42L42_M_DETECT_TF_SHIFT 7
572 #define CS42L42_M_DETECT_TF_MASK (1 << \
573 CS42L42_M_DETECT_TF_SHIFT)
574 #define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \
575 CS42L42_M_SHORT_RLS_MASK | \
576 CS42L42_M_HSBIAS_HIZ_MASK | \
577 CS42L42_M_DETECT_FT_MASK | \
578 CS42L42_M_DETECT_TF_MASK)
580 /* Page 0x1C Headset Bias Registers */
581 #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
582 #define CS42L42_HSBIAS_RAMP_SHIFT 0
583 #define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT)
584 #define CS42L42_HSBIAS_PD_SHIFT 4
585 #define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT)
586 #define CS42L42_HSBIAS_CAPLESS_SHIFT 7
587 #define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
589 /* Page 0x1D ADC Registers */
590 #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
591 #define CS42L42_ADC_NOTCH_DIS_SHIFT 5
592 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4
593 #define CS42L42_ADC_INV_SHIFT 2
594 #define CS42L42_ADC_DIG_BOOST_SHIFT 0
596 #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
597 #define CS42L42_ADC_VOL_SHIFT 0
599 #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
600 #define CS42L42_ADC_WNF_CF_SHIFT 4
601 #define CS42L42_ADC_WNF_EN_SHIFT 3
602 #define CS42L42_ADC_HPF_CF_SHIFT 1
603 #define CS42L42_ADC_HPF_EN_SHIFT 0
605 /* Page 0x1F DAC Registers */
606 #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
607 #define CS42L42_DACB_INV_SHIFT 1
608 #define CS42L42_DACA_INV_SHIFT 0
610 #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
611 #define CS42L42_HPOUT_PULLDOWN_SHIFT 4
612 #define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
613 #define CS42L42_HPOUT_LOAD_SHIFT 3
614 #define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT)
615 #define CS42L42_HPOUT_CLAMP_SHIFT 2
616 #define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT)
617 #define CS42L42_DAC_HPF_EN_SHIFT 1
618 #define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT)
619 #define CS42L42_DAC_MON_EN_SHIFT 0
620 #define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT)
622 /* Page 0x20 HP CTL Registers */
623 #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
624 #define CS42L42_HP_ANA_BMUTE_SHIFT 3
625 #define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
626 #define CS42L42_HP_ANA_AMUTE_SHIFT 2
627 #define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
628 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
629 #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
631 /* Page 0x21 Class H Registers */
632 #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
634 /* Page 0x23 Mixer Volume Registers */
635 #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
636 #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
638 #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
639 #define CS42L42_MIXER_CH_VOL_SHIFT 0
640 #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
642 /* Page 0x24 EQ Registers */
643 #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
644 #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
645 #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
646 #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
647 #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
648 #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
649 #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
650 #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
651 #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
652 #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
653 #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
654 #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
656 /* Page 0x25 Audio Port Registers */
657 #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
659 #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
660 #define CS42L42_SP_RX_RSYNC_SHIFT 6
661 #define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT)
662 #define CS42L42_SP_RX_NSB_POS_SHIFT 3
663 #define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
664 #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2
665 #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
666 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
667 #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
669 #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
670 #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
671 #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
672 #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
673 #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
675 /* Page 0x26 SRC Registers */
676 #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
677 #define CS42L42_SRC_SDIN_FS_SHIFT 0
678 #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
680 #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
682 /* Page 0x28 S/PDIF Registers */
683 #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
684 #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
685 #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
686 #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
688 /* Page 0x29 Serial Port TX Registers */
689 #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
690 #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
691 #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
692 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
693 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
694 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
695 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
696 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
698 /* Page 0x2A Serial Port RX Registers */
699 #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
700 #define CS42L42_ASP_RX0_CH_EN_SHIFT 2
701 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
702 #define CS42L42_ASP_RX0_CH1_EN 1
703 #define CS42L42_ASP_RX0_CH2_EN 2
704 #define CS42L42_ASP_RX0_CH3_EN 4
705 #define CS42L42_ASP_RX0_CH4_EN 8
707 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
708 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
709 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
710 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
711 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
712 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
713 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
714 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
715 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
716 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
717 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
718 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
719 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
720 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
721 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
722 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
723 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
724 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
726 #define CS42L42_ASP_RX_CH_AP_SHIFT 6
727 #define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
728 #define CS42L42_ASP_RX_CH_AP_LOW 0
729 #define CS42L42_ASP_RX_CH_AP_HI 1
730 #define CS42L42_ASP_RX_CH_RES_SHIFT 0
731 #define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
732 #define CS42L42_ASP_RX_CH_RES_32 3
733 #define CS42L42_ASP_RX_CH_RES_16 1
734 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
735 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
737 /* Page 0x30 ID Registers */
738 #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
739 #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
741 /* Defines for fracturing values spread across multiple registers */
742 #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
743 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
744 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)
746 #define CS42L42_NUM_SUPPLIES 5
747 #define CS42L42_BOOT_TIME_US 3000
749 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
757 struct cs42l42_private {
758 struct regmap *regmap;
759 struct snd_soc_component *component;
760 struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
761 struct gpio_desc *reset_gpio;
762 struct completion pdn_done;
770 u8 btn_det_init_dbnce;
771 u8 btn_det_event_dbnce;
772 u8 bias_thresholds[CS42L42_NUM_BIASES];
773 u8 hs_bias_ramp_rate;
774 u8 hs_bias_ramp_time;
777 #endif /* __CS42L42_H__ */