sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <linux/of.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38
  39 static const struct reg_default cs42l42_reg_defaults[] = {
  40         { CS42L42_FRZ_CTL,                      0x00 },
  41         { CS42L42_SRC_CTL,                      0x10 },
  42         { CS42L42_MCLK_STATUS,                  0x02 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  46         { CS42L42_I2C_STRETCH,                  0x03 },
  47         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  48         { CS42L42_PWR_CTL1,                     0xFF },
  49         { CS42L42_PWR_CTL2,                     0x84 },
  50         { CS42L42_PWR_CTL3,                     0x20 },
  51         { CS42L42_RSENSE_CTL1,                  0x40 },
  52         { CS42L42_RSENSE_CTL2,                  0x00 },
  53         { CS42L42_OSC_SWITCH,                   0x00 },
  54         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_TRSENSE_STATUS,               0x00 },
  59         { CS42L42_HSDET_CTL1,                   0x77 },
  60         { CS42L42_HSDET_CTL2,                   0x00 },
  61         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  62         { CS42L42_HS_DET_STATUS,                0x00 },
  63         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  64         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  65         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  66         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  67         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  68         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  69         { CS42L42_FSYNC_P_UPPER,                0x00 },
  70         { CS42L42_ASP_CLK_CFG,                  0x00 },
  71         { CS42L42_ASP_FRM_CFG,                  0x10 },
  72         { CS42L42_FS_RATE_EN,                   0x00 },
  73         { CS42L42_IN_ASRC_CLK,                  0x00 },
  74         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  75         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  76         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  77         { CS42L42_MIXER_STATUS,                 0x00 },
  78         { CS42L42_SRC_STATUS,                   0x00 },
  79         { CS42L42_ASP_RX_STATUS,                0x00 },
  80         { CS42L42_ASP_TX_STATUS,                0x00 },
  81         { CS42L42_CODEC_STATUS,                 0x00 },
  82         { CS42L42_DET_INT_STATUS1,              0x00 },
  83         { CS42L42_DET_INT_STATUS2,              0x00 },
  84         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  85         { CS42L42_VPMON_STATUS,                 0x00 },
  86         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  87         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  88         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  89         { CS42L42_MIXER_INT_MASK,               0x0F },
  90         { CS42L42_SRC_INT_MASK,                 0x0F },
  91         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  92         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  93         { CS42L42_CODEC_INT_MASK,               0x03 },
  94         { CS42L42_SRCPL_INT_MASK,               0xFF },
  95         { CS42L42_VPMON_INT_MASK,               0x01 },
  96         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  97         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  98         { CS42L42_PLL_CTL1,                     0x00 },
  99         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 100         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 101         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 102         { CS42L42_PLL_DIV_INT,                  0x40 },
 103         { CS42L42_PLL_CTL3,                     0x10 },
 104         { CS42L42_PLL_CAL_RATIO,                0x80 },
 105         { CS42L42_PLL_CTL4,                     0x03 },
 106         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 107         { CS42L42_LOAD_DET_DONE,                0x00 },
 108         { CS42L42_LOAD_DET_EN,                  0x00 },
 109         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 110         { CS42L42_WAKE_CTL,                     0xC0 },
 111         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 112         { CS42L42_TIPSENSE_CTL,                 0x02 },
 113         { CS42L42_MISC_DET_CTL,                 0x03 },
 114         { CS42L42_MIC_DET_CTL1,                 0x1F },
 115         { CS42L42_MIC_DET_CTL2,                 0x2F },
 116         { CS42L42_DET_STATUS1,                  0x00 },
 117         { CS42L42_DET_STATUS2,                  0x00 },
 118         { CS42L42_DET_INT1_MASK,                0xE0 },
 119         { CS42L42_DET_INT2_MASK,                0xFF },
 120         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 121         { CS42L42_ADC_CTL,                      0x00 },
 122         { CS42L42_ADC_VOLUME,                   0x00 },
 123         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 124         { CS42L42_DAC_CTL1,                     0x00 },
 125         { CS42L42_DAC_CTL2,                     0x02 },
 126         { CS42L42_HP_CTL,                       0x0D },
 127         { CS42L42_CLASSH_CTL,                   0x07 },
 128         { CS42L42_MIXER_CHA_VOL,                0x3F },
 129         { CS42L42_MIXER_ADC_VOL,                0x3F },
 130         { CS42L42_MIXER_CHB_VOL,                0x3F },
 131         { CS42L42_EQ_COEF_IN0,                  0x22 },
 132         { CS42L42_EQ_COEF_IN1,                  0x00 },
 133         { CS42L42_EQ_COEF_IN2,                  0x00 },
 134         { CS42L42_EQ_COEF_IN3,                  0x00 },
 135         { CS42L42_EQ_COEF_RW,                   0x00 },
 136         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 137         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 138         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 139         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 140         { CS42L42_EQ_INIT_STAT,                 0x00 },
 141         { CS42L42_EQ_START_FILT,                0x00 },
 142         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 143         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 144         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 145         { CS42L42_SP_RX_FS,                     0x8C },
 146         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 147         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 148         { CS42L42_SP_TX_FS,                     0xCC },
 149         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 150         { CS42L42_SRC_SDIN_FS,                  0x40 },
 151         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 152         { CS42L42_SPDIF_CTL1,                   0x01 },
 153         { CS42L42_SPDIF_CTL2,                   0x00 },
 154         { CS42L42_SPDIF_CTL3,                   0x00 },
 155         { CS42L42_SPDIF_CTL4,                   0x42 },
 156         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 157         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 158         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 159         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 160         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 161         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 162         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 163         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 164         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 165         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 166         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 167         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 168         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 169         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 170         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 172         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 173         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 174         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 175         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 176         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 177         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 178         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 179         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 180         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 181         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 182         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 183         { CS42L42_SUB_REVID,                    0x03 },
 184 };
 185
 186 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 187 {
 188         switch (reg) {
 189         case CS42L42_PAGE_REGISTER:
 190         case CS42L42_DEVID_AB:
 191         case CS42L42_DEVID_CD:
 192         case CS42L42_DEVID_E:
 193         case CS42L42_FABID:
 194         case CS42L42_REVID:
 195         case CS42L42_FRZ_CTL:
 196         case CS42L42_SRC_CTL:
 197         case CS42L42_MCLK_STATUS:
 198         case CS42L42_MCLK_CTL:
 199         case CS42L42_SFTRAMP_RATE:
 200         case CS42L42_I2C_DEBOUNCE:
 201         case CS42L42_I2C_STRETCH:
 202         case CS42L42_I2C_TIMEOUT:
 203         case CS42L42_PWR_CTL1:
 204         case CS42L42_PWR_CTL2:
 205         case CS42L42_PWR_CTL3:
 206         case CS42L42_RSENSE_CTL1:
 207         case CS42L42_RSENSE_CTL2:
 208         case CS42L42_OSC_SWITCH:
 209         case CS42L42_OSC_SWITCH_STATUS:
 210         case CS42L42_RSENSE_CTL3:
 211         case CS42L42_TSENSE_CTL:
 212         case CS42L42_TSRS_INT_DISABLE:
 213         case CS42L42_TRSENSE_STATUS:
 214         case CS42L42_HSDET_CTL1:
 215         case CS42L42_HSDET_CTL2:
 216         case CS42L42_HS_SWITCH_CTL:
 217         case CS42L42_HS_DET_STATUS:
 218         case CS42L42_HS_CLAMP_DISABLE:
 219         case CS42L42_MCLK_SRC_SEL:
 220         case CS42L42_SPDIF_CLK_CFG:
 221         case CS42L42_FSYNC_PW_LOWER:
 222         case CS42L42_FSYNC_PW_UPPER:
 223         case CS42L42_FSYNC_P_LOWER:
 224         case CS42L42_FSYNC_P_UPPER:
 225         case CS42L42_ASP_CLK_CFG:
 226         case CS42L42_ASP_FRM_CFG:
 227         case CS42L42_FS_RATE_EN:
 228         case CS42L42_IN_ASRC_CLK:
 229         case CS42L42_OUT_ASRC_CLK:
 230         case CS42L42_PLL_DIV_CFG1:
 231         case CS42L42_ADC_OVFL_STATUS:
 232         case CS42L42_MIXER_STATUS:
 233         case CS42L42_SRC_STATUS:
 234         case CS42L42_ASP_RX_STATUS:
 235         case CS42L42_ASP_TX_STATUS:
 236         case CS42L42_CODEC_STATUS:
 237         case CS42L42_DET_INT_STATUS1:
 238         case CS42L42_DET_INT_STATUS2:
 239         case CS42L42_SRCPL_INT_STATUS:
 240         case CS42L42_VPMON_STATUS:
 241         case CS42L42_PLL_LOCK_STATUS:
 242         case CS42L42_TSRS_PLUG_STATUS:
 243         case CS42L42_ADC_OVFL_INT_MASK:
 244         case CS42L42_MIXER_INT_MASK:
 245         case CS42L42_SRC_INT_MASK:
 246         case CS42L42_ASP_RX_INT_MASK:
 247         case CS42L42_ASP_TX_INT_MASK:
 248         case CS42L42_CODEC_INT_MASK:
 249         case CS42L42_SRCPL_INT_MASK:
 250         case CS42L42_VPMON_INT_MASK:
 251         case CS42L42_PLL_LOCK_INT_MASK:
 252         case CS42L42_TSRS_PLUG_INT_MASK:
 253         case CS42L42_PLL_CTL1:
 254         case CS42L42_PLL_DIV_FRAC0:
 255         case CS42L42_PLL_DIV_FRAC1:
 256         case CS42L42_PLL_DIV_FRAC2:
 257         case CS42L42_PLL_DIV_INT:
 258         case CS42L42_PLL_CTL3:
 259         case CS42L42_PLL_CAL_RATIO:
 260         case CS42L42_PLL_CTL4:
 261         case CS42L42_LOAD_DET_RCSTAT:
 262         case CS42L42_LOAD_DET_DONE:
 263         case CS42L42_LOAD_DET_EN:
 264         case CS42L42_HSBIAS_SC_AUTOCTL:
 265         case CS42L42_WAKE_CTL:
 266         case CS42L42_ADC_DISABLE_MUTE:
 267         case CS42L42_TIPSENSE_CTL:
 268         case CS42L42_MISC_DET_CTL:
 269         case CS42L42_MIC_DET_CTL1:
 270         case CS42L42_MIC_DET_CTL2:
 271         case CS42L42_DET_STATUS1:
 272         case CS42L42_DET_STATUS2:
 273         case CS42L42_DET_INT1_MASK:
 274         case CS42L42_DET_INT2_MASK:
 275         case CS42L42_HS_BIAS_CTL:
 276         case CS42L42_ADC_CTL:
 277         case CS42L42_ADC_VOLUME:
 278         case CS42L42_ADC_WNF_HPF_CTL:
 279         case CS42L42_DAC_CTL1:
 280         case CS42L42_DAC_CTL2:
 281         case CS42L42_HP_CTL:
 282         case CS42L42_CLASSH_CTL:
 283         case CS42L42_MIXER_CHA_VOL:
 284         case CS42L42_MIXER_ADC_VOL:
 285         case CS42L42_MIXER_CHB_VOL:
 286         case CS42L42_EQ_COEF_IN0:
 287         case CS42L42_EQ_COEF_IN1:
 288         case CS42L42_EQ_COEF_IN2:
 289         case CS42L42_EQ_COEF_IN3:
 290         case CS42L42_EQ_COEF_RW:
 291         case CS42L42_EQ_COEF_OUT0:
 292         case CS42L42_EQ_COEF_OUT1:
 293         case CS42L42_EQ_COEF_OUT2:
 294         case CS42L42_EQ_COEF_OUT3:
 295         case CS42L42_EQ_INIT_STAT:
 296         case CS42L42_EQ_START_FILT:
 297         case CS42L42_EQ_MUTE_CTL:
 298         case CS42L42_SP_RX_CH_SEL:
 299         case CS42L42_SP_RX_ISOC_CTL:
 300         case CS42L42_SP_RX_FS:
 301         case CS42l42_SPDIF_CH_SEL:
 302         case CS42L42_SP_TX_ISOC_CTL:
 303         case CS42L42_SP_TX_FS:
 304         case CS42L42_SPDIF_SW_CTL1:
 305         case CS42L42_SRC_SDIN_FS:
 306         case CS42L42_SRC_SDOUT_FS:
 307         case CS42L42_SPDIF_CTL1:
 308         case CS42L42_SPDIF_CTL2:
 309         case CS42L42_SPDIF_CTL3:
 310         case CS42L42_SPDIF_CTL4:
 311         case CS42L42_ASP_TX_SZ_EN:
 312         case CS42L42_ASP_TX_CH_EN:
 313         case CS42L42_ASP_TX_CH_AP_RES:
 314         case CS42L42_ASP_TX_CH1_BIT_MSB:
 315         case CS42L42_ASP_TX_CH1_BIT_LSB:
 316         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 317         case CS42L42_ASP_TX_CH2_BIT_MSB:
 318         case CS42L42_ASP_TX_CH2_BIT_LSB:
 319         case CS42L42_ASP_RX_DAI0_EN:
 320         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 321         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 322         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 324         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 325         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 326         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 327         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 328         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 329         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 330         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 331         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 332         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 333         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 334         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 335         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 336         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 337         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 338         case CS42L42_SUB_REVID:
 339                 return true;
 340         default:
 341                 return false;
 342         }
 343 }
 344
 345 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 346 {
 347         switch (reg) {
 348         case CS42L42_DEVID_AB:
 349         case CS42L42_DEVID_CD:
 350         case CS42L42_DEVID_E:
 351         case CS42L42_MCLK_STATUS:
 352         case CS42L42_TRSENSE_STATUS:
 353         case CS42L42_HS_DET_STATUS:
 354         case CS42L42_ADC_OVFL_STATUS:
 355         case CS42L42_MIXER_STATUS:
 356         case CS42L42_SRC_STATUS:
 357         case CS42L42_ASP_RX_STATUS:
 358         case CS42L42_ASP_TX_STATUS:
 359         case CS42L42_CODEC_STATUS:
 360         case CS42L42_DET_INT_STATUS1:
 361         case CS42L42_DET_INT_STATUS2:
 362         case CS42L42_SRCPL_INT_STATUS:
 363         case CS42L42_VPMON_STATUS:
 364         case CS42L42_PLL_LOCK_STATUS:
 365         case CS42L42_TSRS_PLUG_STATUS:
 366         case CS42L42_LOAD_DET_RCSTAT:
 367         case CS42L42_LOAD_DET_DONE:
 368         case CS42L42_DET_STATUS1:
 369         case CS42L42_DET_STATUS2:
 370                 return true;
 371         default:
 372                 return false;
 373         }
 374 }
 375
 376 static const struct regmap_range_cfg cs42l42_page_range = {
 377         .name = "Pages",
 378         .range_min = 0,
 379         .range_max = CS42L42_MAX_REGISTER,
 380         .selector_reg = CS42L42_PAGE_REGISTER,
 381         .selector_mask = 0xff,
 382         .selector_shift = 0,
 383         .window_start = 0,
 384         .window_len = 256,
 385 };
 386
 387 static const struct regmap_config cs42l42_regmap = {
 388         .reg_bits = 8,
 389         .val_bits = 8,
 390
 391         .readable_reg = cs42l42_readable_register,
 392         .volatile_reg = cs42l42_volatile_register,
 393
 394         .ranges = &cs42l42_page_range,
 395         .num_ranges = 1,
 396
 397         .max_register = CS42L42_MAX_REGISTER,
 398         .reg_defaults = cs42l42_reg_defaults,
 399         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 400         .cache_type = REGCACHE_RBTREE,
 401
 402         .use_single_read = true,
 403         .use_single_write = true,
 404 };
 405
 406 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 407 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 408
 409 static const char * const cs42l42_hpf_freq_text[] = {
 410         "1.86Hz", "120Hz", "235Hz", "466Hz"
 411 };
 412
 413 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 414                             CS42L42_ADC_HPF_CF_SHIFT,
 415                             cs42l42_hpf_freq_text);
 416
 417 static const char * const cs42l42_wnf3_freq_text[] = {
 418         "160Hz", "180Hz", "200Hz", "220Hz",
 419         "240Hz", "260Hz", "280Hz", "300Hz"
 420 };
 421
 422 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 423                             CS42L42_ADC_WNF_CF_SHIFT,
 424                             cs42l42_wnf3_freq_text);
 425
 426 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 427         /* ADC Volume and Filter Controls */
 428         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 429                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 430         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 431                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 432         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 433                                 CS42L42_ADC_INV_SHIFT, true, false),
 434         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 435                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 436         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 437         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 438                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 439         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 440                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 441         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 442         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 443
 444         /* DAC Volume and Filter Controls */
 445         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 446                                 CS42L42_DACA_INV_SHIFT, true, false),
 447         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 448                                 CS42L42_DACB_INV_SHIFT, true, false),
 449         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 450                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 451         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 452                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 453                                 0x3f, 1, mixer_tlv)
 454 };
 455
 456 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
 457                                 struct snd_kcontrol *kcontrol, int event)
 458 {
 459         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 460
 461         if (event & SND_SOC_DAPM_POST_PMU) {
 462                 /* Enable the channels */
 463                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 464                                 CS42L42_ASP_RX0_CH_EN_MASK,
 465                                 (CS42L42_ASP_RX0_CH1_EN |
 466                                 CS42L42_ASP_RX0_CH2_EN) <<
 467                                 CS42L42_ASP_RX0_CH_EN_SHIFT);
 468
 469                 /* Power up */
 470                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 471                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 472                                 CS42L42_HP_PDN_MASK, 0);
 473         } else if (event & SND_SOC_DAPM_PRE_PMD) {
 474                 /* Disable the channels */
 475                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 476                                 CS42L42_ASP_RX0_CH_EN_MASK, 0);
 477
 478                 /* Power down */
 479                 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
 480                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 481                                 CS42L42_HP_PDN_MASK,
 482                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 483                                 CS42L42_HP_PDN_MASK);
 484         } else {
 485                 dev_err(component->dev, "Invalid event 0x%x\n", event);
 486         }
 487         return 0;
 488 }
 489
 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 491         SND_SOC_DAPM_OUTPUT("HP"),
 492         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
 493                                         CS42L42_ASP_SCLK_EN_SHIFT, false),
 494         SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
 495                                         0, NULL, 0, cs42l42_hpdrv_evt,
 496                                         SND_SOC_DAPM_POST_PMU |
 497                                         SND_SOC_DAPM_PRE_PMD)
 498 };
 499
 500 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 501         {"SDIN", NULL, "Playback"},
 502         {"HPDRV", NULL, "SDIN"},
 503         {"HP", NULL, "HPDRV"}
 504 };
 505
 506 static int cs42l42_set_bias_level(struct snd_soc_component *component,
 507                                         enum snd_soc_bias_level level)
 508 {
 509         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 510         int ret;
 511
 512         switch (level) {
 513         case SND_SOC_BIAS_ON:
 514                 break;
 515         case SND_SOC_BIAS_PREPARE:
 516                 break;
 517         case SND_SOC_BIAS_STANDBY:
 518                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
 519                         regcache_cache_only(cs42l42->regmap, false);
 520                         regcache_sync(cs42l42->regmap);
 521                         ret = regulator_bulk_enable(
 522                                                 ARRAY_SIZE(cs42l42->supplies),
 523                                                 cs42l42->supplies);
 524                         if (ret != 0) {
 525                                 dev_err(component->dev,
 526                                         "Failed to enable regulators: %d\n",
 527                                         ret);
 528                                 return ret;
 529                         }
 530                 }
 531                 break;
 532         case SND_SOC_BIAS_OFF:
 533
 534                 regcache_cache_only(cs42l42->regmap, true);
 535                 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
 536                                                     cs42l42->supplies);
 537                 break;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int cs42l42_component_probe(struct snd_soc_component *component)
 544 {
 545         struct cs42l42_private *cs42l42 =
 546                 (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
 547
 548         cs42l42->component = component;
 549
 550         return 0;
 551 }
 552
 553 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 554         .probe                  = cs42l42_component_probe,
 555         .set_bias_level         = cs42l42_set_bias_level,
 556         .dapm_widgets           = cs42l42_dapm_widgets,
 557         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 558         .dapm_routes            = cs42l42_audio_map,
 559         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 560         .controls               = cs42l42_snd_controls,
 561         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 562         .idle_bias_on           = 1,
 563         .endianness             = 1,
 564         .non_legacy_dai_naming  = 1,
 565 };
 566
 567 struct cs42l42_pll_params {
 568         u32 sclk;
 569         u8 mclk_div;
 570         u8 mclk_src_sel;
 571         u8 sclk_prediv;
 572         u8 pll_div_int;
 573         u32 pll_div_frac;
 574         u8 pll_mode;
 575         u8 pll_divout;
 576         u32 mclk_int;
 577         u8 pll_cal_ratio;
 578 };
 579
 580 /*
 581  * Common PLL Settings for given SCLK
 582  * Table 4-5 from the Datasheet
 583  */
 584 static const struct cs42l42_pll_params pll_ratio_table[] = {
 585         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
 586         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 587         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 588         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 589         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
 590         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
 591         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 592         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 593         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 594         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
 595         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
 596         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
 597         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
 598         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
 599         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
 600 };
 601
 602 static int cs42l42_pll_config(struct snd_soc_component *component)
 603 {
 604         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 605         int i;
 606         u32 fsync;
 607
 608         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 609                 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
 610                         /* Configure the internal sample rate */
 611                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 612                                         CS42L42_INTERNAL_FS_MASK,
 613                                         ((pll_ratio_table[i].mclk_int !=
 614                                         12000000) &&
 615                                         (pll_ratio_table[i].mclk_int !=
 616                                         24000000)) <<
 617                                         CS42L42_INTERNAL_FS_SHIFT);
 618                         /* Set the MCLK src (PLL or SCLK) and the divide
 619                          * ratio
 620                          */
 621                         snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
 622                                         CS42L42_MCLK_SRC_SEL_MASK |
 623                                         CS42L42_MCLKDIV_MASK,
 624                                         (pll_ratio_table[i].mclk_src_sel
 625                                         << CS42L42_MCLK_SRC_SEL_SHIFT) |
 626                                         (pll_ratio_table[i].mclk_div <<
 627                                         CS42L42_MCLKDIV_SHIFT));
 628                         /* Set up the LRCLK */
 629                         fsync = cs42l42->sclk / cs42l42->srate;
 630                         if (((fsync * cs42l42->srate) != cs42l42->sclk)
 631                                 || ((fsync % 2) != 0)) {
 632                                 dev_err(component->dev,
 633                                         "Unsupported sclk %d/sample rate %d\n",
 634                                         cs42l42->sclk,
 635                                         cs42l42->srate);
 636                                 return -EINVAL;
 637                         }
 638                         /* Set the LRCLK period */
 639                         snd_soc_component_update_bits(component,
 640                                         CS42L42_FSYNC_P_LOWER,
 641                                         CS42L42_FSYNC_PERIOD_MASK,
 642                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 643                                         CS42L42_FSYNC_PERIOD_SHIFT);
 644                         snd_soc_component_update_bits(component,
 645                                         CS42L42_FSYNC_P_UPPER,
 646                                         CS42L42_FSYNC_PERIOD_MASK,
 647                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 648                                         CS42L42_FSYNC_PERIOD_SHIFT);
 649                         /* Set the LRCLK to 50% duty cycle */
 650                         fsync = fsync / 2;
 651                         snd_soc_component_update_bits(component,
 652                                         CS42L42_FSYNC_PW_LOWER,
 653                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 654                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 655                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 656                         snd_soc_component_update_bits(component,
 657                                         CS42L42_FSYNC_PW_UPPER,
 658                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 659                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 660                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 661                         /* Set the sample rates (96k or lower) */
 662                         snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
 663                                         CS42L42_FS_EN_MASK,
 664                                         (CS42L42_FS_EN_IASRC_96K |
 665                                         CS42L42_FS_EN_OASRC_96K) <<
 666                                         CS42L42_FS_EN_SHIFT);
 667                         /* Set the input/output internal MCLK clock ~12 MHz */
 668                         snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
 669                                         CS42L42_CLK_IASRC_SEL_MASK,
 670                                         CS42L42_CLK_IASRC_SEL_12 <<
 671                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 672                         snd_soc_component_update_bits(component,
 673                                         CS42L42_OUT_ASRC_CLK,
 674                                         CS42L42_CLK_OASRC_SEL_MASK,
 675                                         CS42L42_CLK_OASRC_SEL_12 <<
 676                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 677                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 678                                 /* Pass the clock straight through */
 679                                 snd_soc_component_update_bits(component,
 680                                         CS42L42_PLL_CTL1,
 681                                         CS42L42_PLL_START_MASK, 0);
 682                         } else {
 683                                 /* Configure PLL per table 4-5 */
 684                                 snd_soc_component_update_bits(component,
 685                                         CS42L42_PLL_DIV_CFG1,
 686                                         CS42L42_SCLK_PREDIV_MASK,
 687                                         pll_ratio_table[i].sclk_prediv
 688                                         << CS42L42_SCLK_PREDIV_SHIFT);
 689                                 snd_soc_component_update_bits(component,
 690                                         CS42L42_PLL_DIV_INT,
 691                                         CS42L42_PLL_DIV_INT_MASK,
 692                                         pll_ratio_table[i].pll_div_int
 693                                         << CS42L42_PLL_DIV_INT_SHIFT);
 694                                 snd_soc_component_update_bits(component,
 695                                         CS42L42_PLL_DIV_FRAC0,
 696                                         CS42L42_PLL_DIV_FRAC_MASK,
 697                                         CS42L42_FRAC0_VAL(
 698                                         pll_ratio_table[i].pll_div_frac)
 699                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 700                                 snd_soc_component_update_bits(component,
 701                                         CS42L42_PLL_DIV_FRAC1,
 702                                         CS42L42_PLL_DIV_FRAC_MASK,
 703                                         CS42L42_FRAC1_VAL(
 704                                         pll_ratio_table[i].pll_div_frac)
 705                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 706                                 snd_soc_component_update_bits(component,
 707                                         CS42L42_PLL_DIV_FRAC2,
 708                                         CS42L42_PLL_DIV_FRAC_MASK,
 709                                         CS42L42_FRAC2_VAL(
 710                                         pll_ratio_table[i].pll_div_frac)
 711                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 712                                 snd_soc_component_update_bits(component,
 713                                         CS42L42_PLL_CTL4,
 714                                         CS42L42_PLL_MODE_MASK,
 715                                         pll_ratio_table[i].pll_mode
 716                                         << CS42L42_PLL_MODE_SHIFT);
 717                                 snd_soc_component_update_bits(component,
 718                                         CS42L42_PLL_CTL3,
 719                                         CS42L42_PLL_DIVOUT_MASK,
 720                                         pll_ratio_table[i].pll_divout
 721                                         << CS42L42_PLL_DIVOUT_SHIFT);
 722                                 snd_soc_component_update_bits(component,
 723                                         CS42L42_PLL_CAL_RATIO,
 724                                         CS42L42_PLL_CAL_RATIO_MASK,
 725                                         pll_ratio_table[i].pll_cal_ratio
 726                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 727                         }
 728                         return 0;
 729                 }
 730         }
 731
 732         return -EINVAL;
 733 }
 734
 735 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 736 {
 737         struct snd_soc_component *component = codec_dai->component;
 738         u32 asp_cfg_val = 0;
 739
 740         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 741         case SND_SOC_DAIFMT_CBS_CFM:
 742                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 743                                 CS42L42_ASP_MODE_SHIFT;
 744                 break;
 745         case SND_SOC_DAIFMT_CBS_CFS:
 746                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 747                                 CS42L42_ASP_MODE_SHIFT;
 748                 break;
 749         default:
 750                 return -EINVAL;
 751         }
 752
 753         /* interface format */
 754         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 755         case SND_SOC_DAIFMT_I2S:
 756                 /*
 757                  * 5050 mode, frame starts on falling edge of LRCLK,
 758                  * frame delayed by 1.0 SCLKs
 759                  */
 760                 snd_soc_component_update_bits(component,
 761                                               CS42L42_ASP_FRM_CFG,
 762                                               CS42L42_ASP_STP_MASK |
 763                                               CS42L42_ASP_5050_MASK |
 764                                               CS42L42_ASP_FSD_MASK,
 765                                               CS42L42_ASP_5050_MASK |
 766                                               (CS42L42_ASP_FSD_1_0 <<
 767                                                 CS42L42_ASP_FSD_SHIFT));
 768                 break;
 769         default:
 770                 return -EINVAL;
 771         }
 772
 773         /* Bitclock/frame inversion */
 774         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 775         case SND_SOC_DAIFMT_NB_NF:
 776                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 777                 break;
 778         case SND_SOC_DAIFMT_NB_IF:
 779                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 780                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 781                 break;
 782         case SND_SOC_DAIFMT_IB_NF:
 783                 break;
 784         case SND_SOC_DAIFMT_IB_IF:
 785                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 786                 break;
 787         }
 788
 789         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 790                                                                       CS42L42_ASP_SCPOL_MASK |
 791                                                                       CS42L42_ASP_LCPOL_MASK,
 792                                                                       asp_cfg_val);
 793
 794         return 0;
 795 }
 796
 797 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 798                                 struct snd_pcm_hw_params *params,
 799                                 struct snd_soc_dai *dai)
 800 {
 801         struct snd_soc_component *component = dai->component;
 802         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 803         unsigned int width = (params_width(params) / 8) - 1;
 804         unsigned int val = 0;
 805
 806         cs42l42->srate = params_rate(params);
 807
 808         switch(substream->stream) {
 809         case SNDRV_PCM_STREAM_PLAYBACK:
 810                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 811                 /* channel 1 on low LRCLK */
 812                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 813                                                          CS42L42_ASP_RX_CH_AP_MASK |
 814                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 815                 /* Channel 2 on high LRCLK */
 816                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 817                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 818                                                          CS42L42_ASP_RX_CH_AP_MASK |
 819                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 820                 break;
 821         default:
 822                 break;
 823         }
 824
 825         return cs42l42_pll_config(component);
 826 }
 827
 828 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 829                                 int clk_id, unsigned int freq, int dir)
 830 {
 831         struct snd_soc_component *component = dai->component;
 832         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 833
 834         cs42l42->sclk = freq;
 835
 836         return 0;
 837 }
 838
 839 static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
 840 {
 841         struct snd_soc_component *component = dai->component;
 842         unsigned int regval;
 843         u8 fullScaleVol;
 844
 845         if (mute) {
 846                 /* Mark SCLK as not present to turn on the internal
 847                  * oscillator.
 848                  */
 849                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 850                                                 CS42L42_SCLK_PRESENT_MASK, 0);
 851
 852                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 853                                 CS42L42_PLL_START_MASK,
 854                                 0 << CS42L42_PLL_START_SHIFT);
 855
 856                 /* Mute the headphone */
 857                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 858                                 CS42L42_HP_ANA_AMUTE_MASK |
 859                                 CS42L42_HP_ANA_BMUTE_MASK,
 860                                 CS42L42_HP_ANA_AMUTE_MASK |
 861                                 CS42L42_HP_ANA_BMUTE_MASK);
 862         } else {
 863                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 864                                 CS42L42_PLL_START_MASK,
 865                                 1 << CS42L42_PLL_START_SHIFT);
 866                 /* Read the headphone load */
 867                 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
 868                 if (((regval & CS42L42_RLA_STAT_MASK) >>
 869                         CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
 870                         fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
 871                 } else {
 872                         fullScaleVol = 0;
 873                 }
 874
 875                 /* Un-mute the headphone, set the full scale volume flag */
 876                 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 877                                 CS42L42_HP_ANA_AMUTE_MASK |
 878                                 CS42L42_HP_ANA_BMUTE_MASK |
 879                                 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
 880
 881                 /* Mark SCLK as present, turn off internal oscillator */
 882                 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
 883                                 CS42L42_SCLK_PRESENT_MASK,
 884                                 CS42L42_SCLK_PRESENT_MASK);
 885         }
 886
 887         return 0;
 888 }
 889
 890 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 891                          SNDRV_PCM_FMTBIT_S24_LE |\
 892                          SNDRV_PCM_FMTBIT_S32_LE )
 893
 894
 895 static const struct snd_soc_dai_ops cs42l42_ops = {
 896         .hw_params      = cs42l42_pcm_hw_params,
 897         .set_fmt        = cs42l42_set_dai_fmt,
 898         .set_sysclk     = cs42l42_set_sysclk,
 899         .mute_stream    = cs42l42_mute,
 900         .no_capture_mute = 1,
 901 };
 902
 903 static struct snd_soc_dai_driver cs42l42_dai = {
 904                 .name = "cs42l42",
 905                 .playback = {
 906                         .stream_name = "Playback",
 907                         .channels_min = 1,
 908                         .channels_max = 2,
 909                         .rates = SNDRV_PCM_RATE_8000_192000,
 910                         .formats = CS42L42_FORMATS,
 911                 },
 912                 .capture = {
 913                         .stream_name = "Capture",
 914                         .channels_min = 1,
 915                         .channels_max = 2,
 916                         .rates = SNDRV_PCM_RATE_8000_192000,
 917                         .formats = CS42L42_FORMATS,
 918                 },
 919                 .ops = &cs42l42_ops,
 920 };
 921
 922 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
 923 {
 924         unsigned int hs_det_status;
 925         unsigned int int_status;
 926
 927         /* Mask the auto detect interrupt */
 928         regmap_update_bits(cs42l42->regmap,
 929                 CS42L42_CODEC_INT_MASK,
 930                 CS42L42_PDN_DONE_MASK |
 931                 CS42L42_HSDET_AUTO_DONE_MASK,
 932                 (1 << CS42L42_PDN_DONE_SHIFT) |
 933                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
 934
 935         /* Set hs detect to automatic, disabled mode */
 936         regmap_update_bits(cs42l42->regmap,
 937                 CS42L42_HSDET_CTL2,
 938                 CS42L42_HSDET_CTRL_MASK |
 939                 CS42L42_HSDET_SET_MASK |
 940                 CS42L42_HSBIAS_REF_MASK |
 941                 CS42L42_HSDET_AUTO_TIME_MASK,
 942                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
 943                 (2 << CS42L42_HSDET_SET_SHIFT) |
 944                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 945                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 946
 947         /* Read and save the hs detection result */
 948         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
 949
 950         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
 951                                 CS42L42_HSDET_TYPE_SHIFT;
 952
 953         /* Set up button detection */
 954         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
 955               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
 956                 /* Set auto HS bias settings to default */
 957                 regmap_update_bits(cs42l42->regmap,
 958                         CS42L42_HSBIAS_SC_AUTOCTL,
 959                         CS42L42_HSBIAS_SENSE_EN_MASK |
 960                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 961                         CS42L42_TIP_SENSE_EN_MASK |
 962                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 963                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 964                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 965                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 966                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 967
 968                 /* Set up hs detect level sensitivity */
 969                 regmap_update_bits(cs42l42->regmap,
 970                         CS42L42_MIC_DET_CTL1,
 971                         CS42L42_LATCH_TO_VP_MASK |
 972                         CS42L42_EVENT_STAT_SEL_MASK |
 973                         CS42L42_HS_DET_LEVEL_MASK,
 974                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
 975                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
 976                         (cs42l42->bias_thresholds[0] <<
 977                         CS42L42_HS_DET_LEVEL_SHIFT));
 978
 979                 /* Set auto HS bias settings to default */
 980                 regmap_update_bits(cs42l42->regmap,
 981                         CS42L42_HSBIAS_SC_AUTOCTL,
 982                         CS42L42_HSBIAS_SENSE_EN_MASK |
 983                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 984                         CS42L42_TIP_SENSE_EN_MASK |
 985                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 986                         (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 987                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 988                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 989                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 990
 991                 /* Turn on level detect circuitry */
 992                 regmap_update_bits(cs42l42->regmap,
 993                         CS42L42_MISC_DET_CTL,
 994                         CS42L42_DETECT_MODE_MASK |
 995                         CS42L42_HSBIAS_CTL_MASK |
 996                         CS42L42_PDN_MIC_LVL_DET_MASK,
 997                         (0 << CS42L42_DETECT_MODE_SHIFT) |
 998                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
 999                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1000
1001                 msleep(cs42l42->btn_det_init_dbnce);
1002
1003                 /* Clear any button interrupts before unmasking them */
1004                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1005                             &int_status);
1006
1007                 /* Unmask button detect interrupts */
1008                 regmap_update_bits(cs42l42->regmap,
1009                         CS42L42_DET_INT2_MASK,
1010                         CS42L42_M_DETECT_TF_MASK |
1011                         CS42L42_M_DETECT_FT_MASK |
1012                         CS42L42_M_HSBIAS_HIZ_MASK |
1013                         CS42L42_M_SHORT_RLS_MASK |
1014                         CS42L42_M_SHORT_DET_MASK,
1015                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1016                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1017                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1018                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1019                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1020         } else {
1021                 /* Make sure button detect and HS bias circuits are off */
1022                 regmap_update_bits(cs42l42->regmap,
1023                         CS42L42_MISC_DET_CTL,
1024                         CS42L42_DETECT_MODE_MASK |
1025                         CS42L42_HSBIAS_CTL_MASK |
1026                         CS42L42_PDN_MIC_LVL_DET_MASK,
1027                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1028                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1029                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1030         }
1031
1032         regmap_update_bits(cs42l42->regmap,
1033                                 CS42L42_DAC_CTL2,
1034                                 CS42L42_HPOUT_PULLDOWN_MASK |
1035                                 CS42L42_HPOUT_LOAD_MASK |
1036                                 CS42L42_HPOUT_CLAMP_MASK |
1037                                 CS42L42_DAC_HPF_EN_MASK |
1038                                 CS42L42_DAC_MON_EN_MASK,
1039                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1040                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1041                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1042                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1043                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1044
1045         /* Unmask tip sense interrupts */
1046         regmap_update_bits(cs42l42->regmap,
1047                 CS42L42_TSRS_PLUG_INT_MASK,
1048                 CS42L42_RS_PLUG_MASK |
1049                 CS42L42_RS_UNPLUG_MASK |
1050                 CS42L42_TS_PLUG_MASK |
1051                 CS42L42_TS_UNPLUG_MASK,
1052                 (1 << CS42L42_RS_PLUG_SHIFT) |
1053                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1054                 (0 << CS42L42_TS_PLUG_SHIFT) |
1055                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1056 }
1057
1058 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1059 {
1060         /* Mask tip sense interrupts */
1061         regmap_update_bits(cs42l42->regmap,
1062                                 CS42L42_TSRS_PLUG_INT_MASK,
1063                                 CS42L42_RS_PLUG_MASK |
1064                                 CS42L42_RS_UNPLUG_MASK |
1065                                 CS42L42_TS_PLUG_MASK |
1066                                 CS42L42_TS_UNPLUG_MASK,
1067                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1068                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1069                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1070                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1071
1072         /* Make sure button detect and HS bias circuits are off */
1073         regmap_update_bits(cs42l42->regmap,
1074                                 CS42L42_MISC_DET_CTL,
1075                                 CS42L42_DETECT_MODE_MASK |
1076                                 CS42L42_HSBIAS_CTL_MASK |
1077                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1078                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1079                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1080                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1081
1082         /* Set auto HS bias settings to default */
1083         regmap_update_bits(cs42l42->regmap,
1084                                 CS42L42_HSBIAS_SC_AUTOCTL,
1085                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1086                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1087                                 CS42L42_TIP_SENSE_EN_MASK |
1088                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1089                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1090                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1091                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1092                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1093
1094         /* Set hs detect to manual, disabled mode */
1095         regmap_update_bits(cs42l42->regmap,
1096                                 CS42L42_HSDET_CTL2,
1097                                 CS42L42_HSDET_CTRL_MASK |
1098                                 CS42L42_HSDET_SET_MASK |
1099                                 CS42L42_HSBIAS_REF_MASK |
1100                                 CS42L42_HSDET_AUTO_TIME_MASK,
1101                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1102                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1103                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1104                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1105
1106         regmap_update_bits(cs42l42->regmap,
1107                                 CS42L42_DAC_CTL2,
1108                                 CS42L42_HPOUT_PULLDOWN_MASK |
1109                                 CS42L42_HPOUT_LOAD_MASK |
1110                                 CS42L42_HPOUT_CLAMP_MASK |
1111                                 CS42L42_DAC_HPF_EN_MASK |
1112                                 CS42L42_DAC_MON_EN_MASK,
1113                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1114                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1115                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1116                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1117                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1118
1119         /* Power up HS bias to 2.7V */
1120         regmap_update_bits(cs42l42->regmap,
1121                                 CS42L42_MISC_DET_CTL,
1122                                 CS42L42_DETECT_MODE_MASK |
1123                                 CS42L42_HSBIAS_CTL_MASK |
1124                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1125                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1126                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1127                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1128
1129         /* Wait for HS bias to ramp up */
1130         msleep(cs42l42->hs_bias_ramp_time);
1131
1132         /* Unmask auto detect interrupt */
1133         regmap_update_bits(cs42l42->regmap,
1134                                 CS42L42_CODEC_INT_MASK,
1135                                 CS42L42_PDN_DONE_MASK |
1136                                 CS42L42_HSDET_AUTO_DONE_MASK,
1137                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1138                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1139
1140         /* Set hs detect to automatic, enabled mode */
1141         regmap_update_bits(cs42l42->regmap,
1142                                 CS42L42_HSDET_CTL2,
1143                                 CS42L42_HSDET_CTRL_MASK |
1144                                 CS42L42_HSDET_SET_MASK |
1145                                 CS42L42_HSBIAS_REF_MASK |
1146                                 CS42L42_HSDET_AUTO_TIME_MASK,
1147                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1148                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1149                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1150                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1151 }
1152
1153 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1154 {
1155         /* Mask button detect interrupts */
1156         regmap_update_bits(cs42l42->regmap,
1157                 CS42L42_DET_INT2_MASK,
1158                 CS42L42_M_DETECT_TF_MASK |
1159                 CS42L42_M_DETECT_FT_MASK |
1160                 CS42L42_M_HSBIAS_HIZ_MASK |
1161                 CS42L42_M_SHORT_RLS_MASK |
1162                 CS42L42_M_SHORT_DET_MASK,
1163                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1164                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1165                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1166                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1167                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1168
1169         /* Ground HS bias */
1170         regmap_update_bits(cs42l42->regmap,
1171                                 CS42L42_MISC_DET_CTL,
1172                                 CS42L42_DETECT_MODE_MASK |
1173                                 CS42L42_HSBIAS_CTL_MASK |
1174                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1175                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1176                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1177                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1178
1179         /* Set auto HS bias settings to default */
1180         regmap_update_bits(cs42l42->regmap,
1181                                 CS42L42_HSBIAS_SC_AUTOCTL,
1182                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1183                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1184                                 CS42L42_TIP_SENSE_EN_MASK |
1185                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1186                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1187                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1188                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1189                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1190
1191         /* Set hs detect to manual, disabled mode */
1192         regmap_update_bits(cs42l42->regmap,
1193                                 CS42L42_HSDET_CTL2,
1194                                 CS42L42_HSDET_CTRL_MASK |
1195                                 CS42L42_HSDET_SET_MASK |
1196                                 CS42L42_HSBIAS_REF_MASK |
1197                                 CS42L42_HSDET_AUTO_TIME_MASK,
1198                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1199                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1200                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1201                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1202 }
1203
1204 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1205 {
1206         int bias_level;
1207         unsigned int detect_status;
1208
1209         /* Mask button detect interrupts */
1210         regmap_update_bits(cs42l42->regmap,
1211                 CS42L42_DET_INT2_MASK,
1212                 CS42L42_M_DETECT_TF_MASK |
1213                 CS42L42_M_DETECT_FT_MASK |
1214                 CS42L42_M_HSBIAS_HIZ_MASK |
1215                 CS42L42_M_SHORT_RLS_MASK |
1216                 CS42L42_M_SHORT_DET_MASK,
1217                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1218                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1219                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1220                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1221                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1222
1223         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1224                      cs42l42->btn_det_event_dbnce * 2000);
1225
1226         /* Test all 4 level detect biases */
1227         bias_level = 1;
1228         do {
1229                 /* Adjust button detect level sensitivity */
1230                 regmap_update_bits(cs42l42->regmap,
1231                         CS42L42_MIC_DET_CTL1,
1232                         CS42L42_LATCH_TO_VP_MASK |
1233                         CS42L42_EVENT_STAT_SEL_MASK |
1234                         CS42L42_HS_DET_LEVEL_MASK,
1235                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1236                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1237                         (cs42l42->bias_thresholds[bias_level] <<
1238                         CS42L42_HS_DET_LEVEL_SHIFT));
1239
1240                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1241                                 &detect_status);
1242         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1243                 (++bias_level < CS42L42_NUM_BIASES));
1244
1245         switch (bias_level) {
1246         case 1: /* Function C button press */
1247                 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1248                 break;
1249         case 2: /* Function B button press */
1250                 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1251                 break;
1252         case 3: /* Function D button press */
1253                 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1254                 break;
1255         case 4: /* Function A button press */
1256                 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1257                 break;
1258         }
1259
1260         /* Set button detect level sensitivity back to default */
1261         regmap_update_bits(cs42l42->regmap,
1262                 CS42L42_MIC_DET_CTL1,
1263                 CS42L42_LATCH_TO_VP_MASK |
1264                 CS42L42_EVENT_STAT_SEL_MASK |
1265                 CS42L42_HS_DET_LEVEL_MASK,
1266                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1267                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1268                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1269
1270         /* Clear any button interrupts before unmasking them */
1271         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1272                     &detect_status);
1273
1274         /* Unmask button detect interrupts */
1275         regmap_update_bits(cs42l42->regmap,
1276                 CS42L42_DET_INT2_MASK,
1277                 CS42L42_M_DETECT_TF_MASK |
1278                 CS42L42_M_DETECT_FT_MASK |
1279                 CS42L42_M_HSBIAS_HIZ_MASK |
1280                 CS42L42_M_SHORT_RLS_MASK |
1281                 CS42L42_M_SHORT_DET_MASK,
1282                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1283                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1284                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1285                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1286                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1287 }
1288
1289 struct cs42l42_irq_params {
1290         u16 status_addr;
1291         u16 mask_addr;
1292         u8 mask;
1293 };
1294
1295 static const struct cs42l42_irq_params irq_params_table[] = {
1296         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1297                 CS42L42_ADC_OVFL_VAL_MASK},
1298         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1299                 CS42L42_MIXER_VAL_MASK},
1300         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1301                 CS42L42_SRC_VAL_MASK},
1302         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1303                 CS42L42_ASP_RX_VAL_MASK},
1304         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1305                 CS42L42_ASP_TX_VAL_MASK},
1306         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1307                 CS42L42_CODEC_VAL_MASK},
1308         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1309                 CS42L42_DET_INT_VAL1_MASK},
1310         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1311                 CS42L42_DET_INT_VAL2_MASK},
1312         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1313                 CS42L42_SRCPL_VAL_MASK},
1314         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1315                 CS42L42_VPMON_VAL_MASK},
1316         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1317                 CS42L42_PLL_LOCK_VAL_MASK},
1318         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1319                 CS42L42_TSRS_PLUG_VAL_MASK}
1320 };
1321
1322 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1323 {
1324         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1325         struct snd_soc_component *component = cs42l42->component;
1326         unsigned int stickies[12];
1327         unsigned int masks[12];
1328         unsigned int current_plug_status;
1329         unsigned int current_button_status;
1330         unsigned int i;
1331
1332         /* Read sticky registers to clear interurpt */
1333         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1334                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1335                                 &(stickies[i]));
1336                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1337                                 &(masks[i]));
1338                 stickies[i] = stickies[i] & (~masks[i]) &
1339                                 irq_params_table[i].mask;
1340         }
1341
1342         /* Read tip sense status before handling type detect */
1343         current_plug_status = (stickies[11] &
1344                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1345                 CS42L42_TS_PLUG_SHIFT;
1346
1347         /* Read button sense status */
1348         current_button_status = stickies[7] &
1349                 (CS42L42_M_DETECT_TF_MASK |
1350                 CS42L42_M_DETECT_FT_MASK |
1351                 CS42L42_M_HSBIAS_HIZ_MASK);
1352
1353         /* Check auto-detect status */
1354         if ((~masks[5]) & irq_params_table[5].mask) {
1355                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1356                         cs42l42_process_hs_type_detect(cs42l42);
1357                         dev_dbg(component->dev,
1358                                 "Auto detect done (%d)\n",
1359                                 cs42l42->hs_type);
1360                 }
1361         }
1362
1363         /* Check tip sense status */
1364         if ((~masks[11]) & irq_params_table[11].mask) {
1365                 switch (current_plug_status) {
1366                 case CS42L42_TS_PLUG:
1367                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1368                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1369                                 cs42l42_init_hs_type_detect(cs42l42);
1370                         }
1371                         break;
1372
1373                 case CS42L42_TS_UNPLUG:
1374                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1375                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1376                                 cs42l42_cancel_hs_type_detect(cs42l42);
1377                                 dev_dbg(component->dev,
1378                                         "Unplug event\n");
1379                         }
1380                         break;
1381
1382                 default:
1383                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1384                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1385                 }
1386         }
1387
1388         /* Check button detect status */
1389         if ((~masks[7]) & irq_params_table[7].mask) {
1390                 if (!(current_button_status &
1391                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1392
1393                         if (current_button_status &
1394                                 CS42L42_M_DETECT_TF_MASK) {
1395                                 dev_dbg(component->dev,
1396                                         "Button released\n");
1397                         } else if (current_button_status &
1398                                 CS42L42_M_DETECT_FT_MASK) {
1399                                 cs42l42_handle_button_press(cs42l42);
1400                         }
1401                 }
1402         }
1403
1404         return IRQ_HANDLED;
1405 }
1406
1407 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1408 {
1409         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1410                         CS42L42_ADC_OVFL_MASK,
1411                         (1 << CS42L42_ADC_OVFL_SHIFT));
1412
1413         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1414                         CS42L42_MIX_CHB_OVFL_MASK |
1415                         CS42L42_MIX_CHA_OVFL_MASK |
1416                         CS42L42_EQ_OVFL_MASK |
1417                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1418                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1419                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1420                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1421                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1422
1423         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1424                         CS42L42_SRC_ILK_MASK |
1425                         CS42L42_SRC_OLK_MASK |
1426                         CS42L42_SRC_IUNLK_MASK |
1427                         CS42L42_SRC_OUNLK_MASK,
1428                         (1 << CS42L42_SRC_ILK_SHIFT) |
1429                         (1 << CS42L42_SRC_OLK_SHIFT) |
1430                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1431                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1432
1433         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1434                         CS42L42_ASPRX_NOLRCK_MASK |
1435                         CS42L42_ASPRX_EARLY_MASK |
1436                         CS42L42_ASPRX_LATE_MASK |
1437                         CS42L42_ASPRX_ERROR_MASK |
1438                         CS42L42_ASPRX_OVLD_MASK,
1439                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1440                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1441                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1442                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1443                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1444
1445         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1446                         CS42L42_ASPTX_NOLRCK_MASK |
1447                         CS42L42_ASPTX_EARLY_MASK |
1448                         CS42L42_ASPTX_LATE_MASK |
1449                         CS42L42_ASPTX_SMERROR_MASK,
1450                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1451                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1452                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1453                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1454
1455         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1456                         CS42L42_PDN_DONE_MASK |
1457                         CS42L42_HSDET_AUTO_DONE_MASK,
1458                         (1 << CS42L42_PDN_DONE_SHIFT) |
1459                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1460
1461         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1462                         CS42L42_SRCPL_ADC_LK_MASK |
1463                         CS42L42_SRCPL_DAC_LK_MASK |
1464                         CS42L42_SRCPL_ADC_UNLK_MASK |
1465                         CS42L42_SRCPL_DAC_UNLK_MASK,
1466                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1467                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1468                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1469                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1470
1471         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1472                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1473                         CS42L42_TIP_SENSE_PLUG_MASK |
1474                         CS42L42_HSBIAS_SENSE_MASK,
1475                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1476                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1477                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1478
1479         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1480                         CS42L42_M_DETECT_TF_MASK |
1481                         CS42L42_M_DETECT_FT_MASK |
1482                         CS42L42_M_HSBIAS_HIZ_MASK |
1483                         CS42L42_M_SHORT_RLS_MASK |
1484                         CS42L42_M_SHORT_DET_MASK,
1485                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1486                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1487                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1488                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1489                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1490
1491         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1492                         CS42L42_VPMON_MASK,
1493                         (1 << CS42L42_VPMON_SHIFT));
1494
1495         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1496                         CS42L42_PLL_LOCK_MASK,
1497                         (1 << CS42L42_PLL_LOCK_SHIFT));
1498
1499         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1500                         CS42L42_RS_PLUG_MASK |
1501                         CS42L42_RS_UNPLUG_MASK |
1502                         CS42L42_TS_PLUG_MASK |
1503                         CS42L42_TS_UNPLUG_MASK,
1504                         (1 << CS42L42_RS_PLUG_SHIFT) |
1505                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1506                         (0 << CS42L42_TS_PLUG_SHIFT) |
1507                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1508 }
1509
1510 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1511 {
1512         unsigned int reg;
1513
1514         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1515
1516         /* Latch analog controls to VP power domain */
1517         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1518                         CS42L42_LATCH_TO_VP_MASK |
1519                         CS42L42_EVENT_STAT_SEL_MASK |
1520                         CS42L42_HS_DET_LEVEL_MASK,
1521                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1522                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1523                         (cs42l42->bias_thresholds[0] <<
1524                         CS42L42_HS_DET_LEVEL_SHIFT));
1525
1526         /* Remove ground noise-suppression clamps */
1527         regmap_update_bits(cs42l42->regmap,
1528                         CS42L42_HS_CLAMP_DISABLE,
1529                         CS42L42_HS_CLAMP_DISABLE_MASK,
1530                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1531
1532         /* Enable the tip sense circuit */
1533         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1534                         CS42L42_TIP_SENSE_CTRL_MASK |
1535                         CS42L42_TIP_SENSE_INV_MASK |
1536                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1537                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1538                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1539                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1540
1541         /* Save the initial status of the tip sense */
1542         regmap_read(cs42l42->regmap,
1543                           CS42L42_TSRS_PLUG_STATUS,
1544                           &reg);
1545         cs42l42->plug_state = (((char) reg) &
1546                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1547                       CS42L42_TS_PLUG_SHIFT;
1548 }
1549
1550 static const unsigned int threshold_defaults[] = {
1551         CS42L42_HS_DET_LEVEL_15,
1552         CS42L42_HS_DET_LEVEL_8,
1553         CS42L42_HS_DET_LEVEL_4,
1554         CS42L42_HS_DET_LEVEL_1
1555 };
1556
1557 static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1558                                         struct cs42l42_private *cs42l42)
1559 {
1560         struct device_node *np = i2c_client->dev.of_node;
1561         unsigned int val;
1562         unsigned int thresholds[CS42L42_NUM_BIASES];
1563         int ret;
1564         int i;
1565
1566         ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1567
1568         if (!ret) {
1569                 switch (val) {
1570                 case CS42L42_TS_INV_EN:
1571                 case CS42L42_TS_INV_DIS:
1572                         cs42l42->ts_inv = val;
1573                         break;
1574                 default:
1575                         dev_err(&i2c_client->dev,
1576                                 "Wrong cirrus,ts-inv DT value %d\n",
1577                                 val);
1578                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1579                 }
1580         } else {
1581                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1582         }
1583
1584         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1585                         CS42L42_TS_INV_MASK,
1586                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1587
1588         ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1589
1590         if (!ret) {
1591                 switch (val) {
1592                 case CS42L42_TS_DBNCE_0:
1593                 case CS42L42_TS_DBNCE_125:
1594                 case CS42L42_TS_DBNCE_250:
1595                 case CS42L42_TS_DBNCE_500:
1596                 case CS42L42_TS_DBNCE_750:
1597                 case CS42L42_TS_DBNCE_1000:
1598                 case CS42L42_TS_DBNCE_1250:
1599                 case CS42L42_TS_DBNCE_1500:
1600                         cs42l42->ts_dbnc_rise = val;
1601                         break;
1602                 default:
1603                         dev_err(&i2c_client->dev,
1604                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1605                                 val);
1606                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1607                 }
1608         } else {
1609                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1610         }
1611
1612         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1613                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1614                         (cs42l42->ts_dbnc_rise <<
1615                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1616
1617         ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1618
1619         if (!ret) {
1620                 switch (val) {
1621                 case CS42L42_TS_DBNCE_0:
1622                 case CS42L42_TS_DBNCE_125:
1623                 case CS42L42_TS_DBNCE_250:
1624                 case CS42L42_TS_DBNCE_500:
1625                 case CS42L42_TS_DBNCE_750:
1626                 case CS42L42_TS_DBNCE_1000:
1627                 case CS42L42_TS_DBNCE_1250:
1628                 case CS42L42_TS_DBNCE_1500:
1629                         cs42l42->ts_dbnc_fall = val;
1630                         break;
1631                 default:
1632                         dev_err(&i2c_client->dev,
1633                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1634                                 val);
1635                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1636                 }
1637         } else {
1638                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1639         }
1640
1641         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1642                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1643                         (cs42l42->ts_dbnc_fall <<
1644                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1645
1646         ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1647
1648         if (!ret) {
1649                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1650                         cs42l42->btn_det_init_dbnce = val;
1651                 else {
1652                         dev_err(&i2c_client->dev,
1653                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1654                                 val);
1655                         cs42l42->btn_det_init_dbnce =
1656                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1657                 }
1658         } else {
1659                 cs42l42->btn_det_init_dbnce =
1660                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1661         }
1662
1663         ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1664
1665         if (!ret) {
1666                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1667                         cs42l42->btn_det_event_dbnce = val;
1668                 else {
1669                         dev_err(&i2c_client->dev,
1670                         "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1671                         cs42l42->btn_det_event_dbnce =
1672                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1673                 }
1674         } else {
1675                 cs42l42->btn_det_event_dbnce =
1676                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1677         }
1678
1679         ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1680                                    (u32 *)thresholds, CS42L42_NUM_BIASES);
1681
1682         if (!ret) {
1683                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1684                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1685                                 cs42l42->bias_thresholds[i] = thresholds[i];
1686                         else {
1687                                 dev_err(&i2c_client->dev,
1688                                 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1689                                         thresholds[i]);
1690                                 cs42l42->bias_thresholds[i] =
1691                                         threshold_defaults[i];
1692                         }
1693                 }
1694         } else {
1695                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1696                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1697         }
1698
1699         ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1700
1701         if (!ret) {
1702                 switch (val) {
1703                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1704                         cs42l42->hs_bias_ramp_rate = val;
1705                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1706                         break;
1707                 case CS42L42_HSBIAS_RAMP_FAST:
1708                         cs42l42->hs_bias_ramp_rate = val;
1709                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1710                         break;
1711                 case CS42L42_HSBIAS_RAMP_SLOW:
1712                         cs42l42->hs_bias_ramp_rate = val;
1713                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1714                         break;
1715                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1716                         cs42l42->hs_bias_ramp_rate = val;
1717                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1718                         break;
1719                 default:
1720                         dev_err(&i2c_client->dev,
1721                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1722                                 val);
1723                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1724                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1725                 }
1726         } else {
1727                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1728                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1729         }
1730
1731         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1732                         CS42L42_HSBIAS_RAMP_MASK,
1733                         (cs42l42->hs_bias_ramp_rate <<
1734                         CS42L42_HSBIAS_RAMP_SHIFT));
1735
1736         return 0;
1737 }
1738
1739 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1740                                        const struct i2c_device_id *id)
1741 {
1742         struct cs42l42_private *cs42l42;
1743         int ret, i;
1744         unsigned int devid = 0;
1745         unsigned int reg;
1746
1747         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1748                                GFP_KERNEL);
1749         if (!cs42l42)
1750                 return -ENOMEM;
1751
1752         i2c_set_clientdata(i2c_client, cs42l42);
1753
1754         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1755         if (IS_ERR(cs42l42->regmap)) {
1756                 ret = PTR_ERR(cs42l42->regmap);
1757                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1758                 return ret;
1759         }
1760
1761         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1762                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1763
1764         ret = devm_regulator_bulk_get(&i2c_client->dev,
1765                                       ARRAY_SIZE(cs42l42->supplies),
1766                                       cs42l42->supplies);
1767         if (ret != 0) {
1768                 dev_err(&i2c_client->dev,
1769                         "Failed to request supplies: %d\n", ret);
1770                 return ret;
1771         }
1772
1773         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1774                                     cs42l42->supplies);
1775         if (ret != 0) {
1776                 dev_err(&i2c_client->dev,
1777                         "Failed to enable supplies: %d\n", ret);
1778                 return ret;
1779         }
1780
1781         /* Reset the Device */
1782         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1783                 "reset", GPIOD_OUT_LOW);
1784         if (IS_ERR(cs42l42->reset_gpio))
1785                 return PTR_ERR(cs42l42->reset_gpio);
1786
1787         if (cs42l42->reset_gpio) {
1788                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1789                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1790         }
1791         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1792
1793         /* Request IRQ */
1794         ret = devm_request_threaded_irq(&i2c_client->dev,
1795                         i2c_client->irq,
1796                         NULL, cs42l42_irq_thread,
1797                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1798                         "cs42l42", cs42l42);
1799
1800         if (ret != 0)
1801                 dev_err(&i2c_client->dev,
1802                         "Failed to request IRQ: %d\n", ret);
1803
1804         /* initialize codec */
1805         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
1806         devid = (reg & 0xFF) << 12;
1807
1808         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
1809         devid |= (reg & 0xFF) << 4;
1810
1811         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
1812         devid |= (reg & 0xF0) >> 4;
1813
1814         if (devid != CS42L42_CHIP_ID) {
1815                 ret = -ENODEV;
1816                 dev_err(&i2c_client->dev,
1817                         "CS42L42 Device ID (%X). Expected %X\n",
1818                         devid, CS42L42_CHIP_ID);
1819                 return ret;
1820         }
1821
1822         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1823         if (ret < 0) {
1824                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1825                 return ret;
1826         }
1827
1828         dev_info(&i2c_client->dev,
1829                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1830
1831         /* Power up the codec */
1832         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1833                         CS42L42_ASP_DAO_PDN_MASK |
1834                         CS42L42_ASP_DAI_PDN_MASK |
1835                         CS42L42_MIXER_PDN_MASK |
1836                         CS42L42_EQ_PDN_MASK |
1837                         CS42L42_HP_PDN_MASK |
1838                         CS42L42_ADC_PDN_MASK |
1839                         CS42L42_PDN_ALL_MASK,
1840                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1841                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1842                         (1 << CS42L42_MIXER_PDN_SHIFT) |
1843                         (1 << CS42L42_EQ_PDN_SHIFT) |
1844                         (1 << CS42L42_HP_PDN_SHIFT) |
1845                         (1 << CS42L42_ADC_PDN_SHIFT) |
1846                         (0 << CS42L42_PDN_ALL_SHIFT));
1847
1848         if (i2c_client->dev.of_node) {
1849                 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1850                 if (ret != 0)
1851                         return ret;
1852         }
1853
1854         /* Setup headset detection */
1855         cs42l42_setup_hs_type_detect(cs42l42);
1856
1857         /* Mask/Unmask Interrupts */
1858         cs42l42_set_interrupt_masks(cs42l42);
1859
1860         /* Register codec for machine driver */
1861         ret = devm_snd_soc_register_component(&i2c_client->dev,
1862                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1863         if (ret < 0)
1864                 goto err_disable;
1865         return 0;
1866
1867 err_disable:
1868         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1869                                 cs42l42->supplies);
1870         return ret;
1871 }
1872
1873 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1874 {
1875         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1876
1877         /* Hold down reset */
1878         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1879
1880         return 0;
1881 }
1882
1883 #ifdef CONFIG_PM
1884 static int cs42l42_runtime_suspend(struct device *dev)
1885 {
1886         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1887
1888         regcache_cache_only(cs42l42->regmap, true);
1889         regcache_mark_dirty(cs42l42->regmap);
1890
1891         /* Hold down reset */
1892         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1893
1894         /* remove power */
1895         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1896                                 cs42l42->supplies);
1897
1898         return 0;
1899 }
1900
1901 static int cs42l42_runtime_resume(struct device *dev)
1902 {
1903         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1904         int ret;
1905
1906         /* Enable power */
1907         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1908                                         cs42l42->supplies);
1909         if (ret != 0) {
1910                 dev_err(dev, "Failed to enable supplies: %d\n",
1911                         ret);
1912                 return ret;
1913         }
1914
1915         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1916         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1917
1918         regcache_cache_only(cs42l42->regmap, false);
1919         regcache_sync(cs42l42->regmap);
1920
1921         return 0;
1922 }
1923 #endif
1924
1925 static const struct dev_pm_ops cs42l42_runtime_pm = {
1926         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1927                            NULL)
1928 };
1929
1930 static const struct of_device_id cs42l42_of_match[] = {
1931         { .compatible = "cirrus,cs42l42", },
1932         {},
1933 };
1934 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1935
1936
1937 static const struct i2c_device_id cs42l42_id[] = {
1938         {"cs42l42", 0},
1939         {}
1940 };
1941
1942 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1943
1944 static struct i2c_driver cs42l42_i2c_driver = {
1945         .driver = {
1946                 .name = "cs42l42",
1947                 .pm = &cs42l42_runtime_pm,
1948                 .of_match_table = cs42l42_of_match,
1949                 },
1950         .id_table = cs42l42_id,
1951         .probe = cs42l42_i2c_probe,
1952         .remove = cs42l42_i2c_remove,
1953 };
1954
1955 module_i2c_driver(cs42l42_i2c_driver);
1956
1957 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1958 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1959 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1960 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1961 MODULE_LICENSE("GPL");