sound/soc/codecs/cs42l42.c

   1 /*
   2  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   3  *
   4  * Copyright 2016 Cirrus Logic, Inc.
   5  *
   6  * Author: James Schulman <james.schulman@cirrus.com>
   7  * Author: Brian Austin <brian.austin@cirrus.com>
   8  * Author: Michael White <michael.white@cirrus.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/version.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/i2c.h>
  23 #include <linux/gpio.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/of.h>
  30 #include <linux/of_gpio.h>
  31 #include <linux/of_device.h>
  32 #include <sound/core.h>
  33 #include <sound/pcm.h>
  34 #include <sound/pcm_params.h>
  35 #include <sound/soc.h>
  36 #include <sound/soc-dapm.h>
  37 #include <sound/initval.h>
  38 #include <sound/tlv.h>
  39 #include <dt-bindings/sound/cs42l42.h>
  40
  41 #include "cs42l42.h"
  42
  43 static const struct reg_default cs42l42_reg_defaults[] = {
  44         { CS42L42_FRZ_CTL,                      0x00 },
  45         { CS42L42_SRC_CTL,                      0x10 },
  46         { CS42L42_MCLK_STATUS,                  0x02 },
  47         { CS42L42_MCLK_CTL,                     0x02 },
  48         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  49         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  50         { CS42L42_I2C_STRETCH,                  0x03 },
  51         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  52         { CS42L42_PWR_CTL1,                     0xFF },
  53         { CS42L42_PWR_CTL2,                     0x84 },
  54         { CS42L42_PWR_CTL3,                     0x20 },
  55         { CS42L42_RSENSE_CTL1,                  0x40 },
  56         { CS42L42_RSENSE_CTL2,                  0x00 },
  57         { CS42L42_OSC_SWITCH,                   0x00 },
  58         { CS42L42_OSC_SWITCH_STATUS,            0x05 },
  59         { CS42L42_RSENSE_CTL3,                  0x1B },
  60         { CS42L42_TSENSE_CTL,                   0x1B },
  61         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  62         { CS42L42_TRSENSE_STATUS,               0x00 },
  63         { CS42L42_HSDET_CTL1,                   0x77 },
  64         { CS42L42_HSDET_CTL2,                   0x00 },
  65         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  66         { CS42L42_HS_DET_STATUS,                0x00 },
  67         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  68         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  69         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  70         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  71         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  72         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  73         { CS42L42_FSYNC_P_UPPER,                0x00 },
  74         { CS42L42_ASP_CLK_CFG,                  0x00 },
  75         { CS42L42_ASP_FRM_CFG,                  0x10 },
  76         { CS42L42_FS_RATE_EN,                   0x00 },
  77         { CS42L42_IN_ASRC_CLK,                  0x00 },
  78         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  79         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  80         { CS42L42_ADC_OVFL_STATUS,              0x00 },
  81         { CS42L42_MIXER_STATUS,                 0x00 },
  82         { CS42L42_SRC_STATUS,                   0x00 },
  83         { CS42L42_ASP_RX_STATUS,                0x00 },
  84         { CS42L42_ASP_TX_STATUS,                0x00 },
  85         { CS42L42_CODEC_STATUS,                 0x00 },
  86         { CS42L42_DET_INT_STATUS1,              0x00 },
  87         { CS42L42_DET_INT_STATUS2,              0x00 },
  88         { CS42L42_SRCPL_INT_STATUS,             0x00 },
  89         { CS42L42_VPMON_STATUS,                 0x00 },
  90         { CS42L42_PLL_LOCK_STATUS,              0x00 },
  91         { CS42L42_TSRS_PLUG_STATUS,             0x00 },
  92         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  93         { CS42L42_MIXER_INT_MASK,               0x0F },
  94         { CS42L42_SRC_INT_MASK,                 0x0F },
  95         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  96         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  97         { CS42L42_CODEC_INT_MASK,               0x03 },
  98         { CS42L42_SRCPL_INT_MASK,               0x7F },
  99         { CS42L42_VPMON_INT_MASK,               0x01 },
 100         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
 101         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
 102         { CS42L42_PLL_CTL1,                     0x00 },
 103         { CS42L42_PLL_DIV_FRAC0,                0x00 },
 104         { CS42L42_PLL_DIV_FRAC1,                0x00 },
 105         { CS42L42_PLL_DIV_FRAC2,                0x00 },
 106         { CS42L42_PLL_DIV_INT,                  0x40 },
 107         { CS42L42_PLL_CTL3,                     0x10 },
 108         { CS42L42_PLL_CAL_RATIO,                0x80 },
 109         { CS42L42_PLL_CTL4,                     0x03 },
 110         { CS42L42_LOAD_DET_RCSTAT,              0x00 },
 111         { CS42L42_LOAD_DET_DONE,                0x00 },
 112         { CS42L42_LOAD_DET_EN,                  0x00 },
 113         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
 114         { CS42L42_WAKE_CTL,                     0xC0 },
 115         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 116         { CS42L42_TIPSENSE_CTL,                 0x02 },
 117         { CS42L42_MISC_DET_CTL,                 0x03 },
 118         { CS42L42_MIC_DET_CTL1,                 0x1F },
 119         { CS42L42_MIC_DET_CTL2,                 0x2F },
 120         { CS42L42_DET_STATUS1,                  0x00 },
 121         { CS42L42_DET_STATUS2,                  0x00 },
 122         { CS42L42_DET_INT1_MASK,                0xE0 },
 123         { CS42L42_DET_INT2_MASK,                0xFF },
 124         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 125         { CS42L42_ADC_CTL,                      0x00 },
 126         { CS42L42_ADC_VOLUME,                   0x00 },
 127         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 128         { CS42L42_DAC_CTL1,                     0x00 },
 129         { CS42L42_DAC_CTL2,                     0x02 },
 130         { CS42L42_HP_CTL,                       0x0D },
 131         { CS42L42_CLASSH_CTL,                   0x07 },
 132         { CS42L42_MIXER_CHA_VOL,                0x3F },
 133         { CS42L42_MIXER_ADC_VOL,                0x3F },
 134         { CS42L42_MIXER_CHB_VOL,                0x3F },
 135         { CS42L42_EQ_COEF_IN0,                  0x00 },
 136         { CS42L42_EQ_COEF_IN1,                  0x00 },
 137         { CS42L42_EQ_COEF_IN2,                  0x00 },
 138         { CS42L42_EQ_COEF_IN3,                  0x00 },
 139         { CS42L42_EQ_COEF_RW,                   0x00 },
 140         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 141         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 142         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 143         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 144         { CS42L42_EQ_INIT_STAT,                 0x00 },
 145         { CS42L42_EQ_START_FILT,                0x00 },
 146         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 147         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 148         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 149         { CS42L42_SP_RX_FS,                     0x8C },
 150         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 151         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 152         { CS42L42_SP_TX_FS,                     0xCC },
 153         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 154         { CS42L42_SRC_SDIN_FS,                  0x40 },
 155         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 156         { CS42L42_SPDIF_CTL1,                   0x01 },
 157         { CS42L42_SPDIF_CTL2,                   0x00 },
 158         { CS42L42_SPDIF_CTL3,                   0x00 },
 159         { CS42L42_SPDIF_CTL4,                   0x42 },
 160         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 161         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 162         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 163         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 164         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 165         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 166         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 167         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 168         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 169         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 170         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 171         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 172         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 173         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 174         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 175         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 176         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 177         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 178         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 179         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 180         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 181         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 182         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 183         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 184         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 185         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 186         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 187         { CS42L42_SUB_REVID,                    0x03 },
 188 };
 189
 190 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 191 {
 192         switch (reg) {
 193         case CS42L42_PAGE_REGISTER:
 194         case CS42L42_DEVID_AB:
 195         case CS42L42_DEVID_CD:
 196         case CS42L42_DEVID_E:
 197         case CS42L42_FABID:
 198         case CS42L42_REVID:
 199         case CS42L42_FRZ_CTL:
 200         case CS42L42_SRC_CTL:
 201         case CS42L42_MCLK_STATUS:
 202         case CS42L42_MCLK_CTL:
 203         case CS42L42_SFTRAMP_RATE:
 204         case CS42L42_I2C_DEBOUNCE:
 205         case CS42L42_I2C_STRETCH:
 206         case CS42L42_I2C_TIMEOUT:
 207         case CS42L42_PWR_CTL1:
 208         case CS42L42_PWR_CTL2:
 209         case CS42L42_PWR_CTL3:
 210         case CS42L42_RSENSE_CTL1:
 211         case CS42L42_RSENSE_CTL2:
 212         case CS42L42_OSC_SWITCH:
 213         case CS42L42_OSC_SWITCH_STATUS:
 214         case CS42L42_RSENSE_CTL3:
 215         case CS42L42_TSENSE_CTL:
 216         case CS42L42_TSRS_INT_DISABLE:
 217         case CS42L42_TRSENSE_STATUS:
 218         case CS42L42_HSDET_CTL1:
 219         case CS42L42_HSDET_CTL2:
 220         case CS42L42_HS_SWITCH_CTL:
 221         case CS42L42_HS_DET_STATUS:
 222         case CS42L42_HS_CLAMP_DISABLE:
 223         case CS42L42_MCLK_SRC_SEL:
 224         case CS42L42_SPDIF_CLK_CFG:
 225         case CS42L42_FSYNC_PW_LOWER:
 226         case CS42L42_FSYNC_PW_UPPER:
 227         case CS42L42_FSYNC_P_LOWER:
 228         case CS42L42_FSYNC_P_UPPER:
 229         case CS42L42_ASP_CLK_CFG:
 230         case CS42L42_ASP_FRM_CFG:
 231         case CS42L42_FS_RATE_EN:
 232         case CS42L42_IN_ASRC_CLK:
 233         case CS42L42_OUT_ASRC_CLK:
 234         case CS42L42_PLL_DIV_CFG1:
 235         case CS42L42_ADC_OVFL_STATUS:
 236         case CS42L42_MIXER_STATUS:
 237         case CS42L42_SRC_STATUS:
 238         case CS42L42_ASP_RX_STATUS:
 239         case CS42L42_ASP_TX_STATUS:
 240         case CS42L42_CODEC_STATUS:
 241         case CS42L42_DET_INT_STATUS1:
 242         case CS42L42_DET_INT_STATUS2:
 243         case CS42L42_SRCPL_INT_STATUS:
 244         case CS42L42_VPMON_STATUS:
 245         case CS42L42_PLL_LOCK_STATUS:
 246         case CS42L42_TSRS_PLUG_STATUS:
 247         case CS42L42_ADC_OVFL_INT_MASK:
 248         case CS42L42_MIXER_INT_MASK:
 249         case CS42L42_SRC_INT_MASK:
 250         case CS42L42_ASP_RX_INT_MASK:
 251         case CS42L42_ASP_TX_INT_MASK:
 252         case CS42L42_CODEC_INT_MASK:
 253         case CS42L42_SRCPL_INT_MASK:
 254         case CS42L42_VPMON_INT_MASK:
 255         case CS42L42_PLL_LOCK_INT_MASK:
 256         case CS42L42_TSRS_PLUG_INT_MASK:
 257         case CS42L42_PLL_CTL1:
 258         case CS42L42_PLL_DIV_FRAC0:
 259         case CS42L42_PLL_DIV_FRAC1:
 260         case CS42L42_PLL_DIV_FRAC2:
 261         case CS42L42_PLL_DIV_INT:
 262         case CS42L42_PLL_CTL3:
 263         case CS42L42_PLL_CAL_RATIO:
 264         case CS42L42_PLL_CTL4:
 265         case CS42L42_LOAD_DET_RCSTAT:
 266         case CS42L42_LOAD_DET_DONE:
 267         case CS42L42_LOAD_DET_EN:
 268         case CS42L42_HSBIAS_SC_AUTOCTL:
 269         case CS42L42_WAKE_CTL:
 270         case CS42L42_ADC_DISABLE_MUTE:
 271         case CS42L42_TIPSENSE_CTL:
 272         case CS42L42_MISC_DET_CTL:
 273         case CS42L42_MIC_DET_CTL1:
 274         case CS42L42_MIC_DET_CTL2:
 275         case CS42L42_DET_STATUS1:
 276         case CS42L42_DET_STATUS2:
 277         case CS42L42_DET_INT1_MASK:
 278         case CS42L42_DET_INT2_MASK:
 279         case CS42L42_HS_BIAS_CTL:
 280         case CS42L42_ADC_CTL:
 281         case CS42L42_ADC_VOLUME:
 282         case CS42L42_ADC_WNF_HPF_CTL:
 283         case CS42L42_DAC_CTL1:
 284         case CS42L42_DAC_CTL2:
 285         case CS42L42_HP_CTL:
 286         case CS42L42_CLASSH_CTL:
 287         case CS42L42_MIXER_CHA_VOL:
 288         case CS42L42_MIXER_ADC_VOL:
 289         case CS42L42_MIXER_CHB_VOL:
 290         case CS42L42_EQ_COEF_IN0:
 291         case CS42L42_EQ_COEF_IN1:
 292         case CS42L42_EQ_COEF_IN2:
 293         case CS42L42_EQ_COEF_IN3:
 294         case CS42L42_EQ_COEF_RW:
 295         case CS42L42_EQ_COEF_OUT0:
 296         case CS42L42_EQ_COEF_OUT1:
 297         case CS42L42_EQ_COEF_OUT2:
 298         case CS42L42_EQ_COEF_OUT3:
 299         case CS42L42_EQ_INIT_STAT:
 300         case CS42L42_EQ_START_FILT:
 301         case CS42L42_EQ_MUTE_CTL:
 302         case CS42L42_SP_RX_CH_SEL:
 303         case CS42L42_SP_RX_ISOC_CTL:
 304         case CS42L42_SP_RX_FS:
 305         case CS42l42_SPDIF_CH_SEL:
 306         case CS42L42_SP_TX_ISOC_CTL:
 307         case CS42L42_SP_TX_FS:
 308         case CS42L42_SPDIF_SW_CTL1:
 309         case CS42L42_SRC_SDIN_FS:
 310         case CS42L42_SRC_SDOUT_FS:
 311         case CS42L42_SPDIF_CTL1:
 312         case CS42L42_SPDIF_CTL2:
 313         case CS42L42_SPDIF_CTL3:
 314         case CS42L42_SPDIF_CTL4:
 315         case CS42L42_ASP_TX_SZ_EN:
 316         case CS42L42_ASP_TX_CH_EN:
 317         case CS42L42_ASP_TX_CH_AP_RES:
 318         case CS42L42_ASP_TX_CH1_BIT_MSB:
 319         case CS42L42_ASP_TX_CH1_BIT_LSB:
 320         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 321         case CS42L42_ASP_TX_CH2_BIT_MSB:
 322         case CS42L42_ASP_TX_CH2_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI0_EN:
 324         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 325         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 326         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 327         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 328         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 329         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 330         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 331         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 332         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 333         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 334         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 335         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 336         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 337         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 338         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 339         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 340         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 341         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 342         case CS42L42_SUB_REVID:
 343                 return true;
 344         default:
 345                 return false;
 346         }
 347 }
 348
 349 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 350 {
 351         switch (reg) {
 352         case CS42L42_DEVID_AB:
 353         case CS42L42_DEVID_CD:
 354         case CS42L42_DEVID_E:
 355         case CS42L42_MCLK_STATUS:
 356         case CS42L42_TRSENSE_STATUS:
 357         case CS42L42_HS_DET_STATUS:
 358         case CS42L42_ADC_OVFL_STATUS:
 359         case CS42L42_MIXER_STATUS:
 360         case CS42L42_SRC_STATUS:
 361         case CS42L42_ASP_RX_STATUS:
 362         case CS42L42_ASP_TX_STATUS:
 363         case CS42L42_CODEC_STATUS:
 364         case CS42L42_DET_INT_STATUS1:
 365         case CS42L42_DET_INT_STATUS2:
 366         case CS42L42_SRCPL_INT_STATUS:
 367         case CS42L42_VPMON_STATUS:
 368         case CS42L42_PLL_LOCK_STATUS:
 369         case CS42L42_TSRS_PLUG_STATUS:
 370         case CS42L42_LOAD_DET_RCSTAT:
 371         case CS42L42_LOAD_DET_DONE:
 372         case CS42L42_DET_STATUS1:
 373         case CS42L42_DET_STATUS2:
 374                 return true;
 375         default:
 376                 return false;
 377         }
 378 }
 379
 380 static const struct regmap_range_cfg cs42l42_page_range = {
 381         .name = "Pages",
 382         .range_min = 0,
 383         .range_max = CS42L42_MAX_REGISTER,
 384         .selector_reg = CS42L42_PAGE_REGISTER,
 385         .selector_mask = 0xff,
 386         .selector_shift = 0,
 387         .window_start = 0,
 388         .window_len = 256,
 389 };
 390
 391 static const struct regmap_config cs42l42_regmap = {
 392         .reg_bits = 8,
 393         .val_bits = 8,
 394
 395         .readable_reg = cs42l42_readable_register,
 396         .volatile_reg = cs42l42_volatile_register,
 397
 398         .ranges = &cs42l42_page_range,
 399         .num_ranges = 1,
 400
 401         .max_register = CS42L42_MAX_REGISTER,
 402         .reg_defaults = cs42l42_reg_defaults,
 403         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 404         .cache_type = REGCACHE_RBTREE,
 405 };
 406
 407 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 408 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 409
 410 static const char * const cs42l42_hpf_freq_text[] = {
 411         "1.86Hz", "120Hz", "235Hz", "466Hz"
 412 };
 413
 414 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 415                             CS42L42_ADC_HPF_CF_SHIFT,
 416                             cs42l42_hpf_freq_text);
 417
 418 static const char * const cs42l42_wnf3_freq_text[] = {
 419         "160Hz", "180Hz", "200Hz", "220Hz",
 420         "240Hz", "260Hz", "280Hz", "300Hz"
 421 };
 422
 423 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 424                             CS42L42_ADC_WNF_CF_SHIFT,
 425                             cs42l42_wnf3_freq_text);
 426
 427 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 428         /* ADC Volume and Filter Controls */
 429         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 430                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 431         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 432                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 433         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 434                                 CS42L42_ADC_INV_SHIFT, true, false),
 435         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 436                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 437         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 438         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 439                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 440         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 441                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 442         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 443         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 444
 445         /* DAC Volume and Filter Controls */
 446         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 447                                 CS42L42_DACA_INV_SHIFT, true, false),
 448         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 449                                 CS42L42_DACB_INV_SHIFT, true, false),
 450         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 451                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 452         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 453                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 454                                 0x3f, 1, mixer_tlv)
 455 };
 456
 457 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
 458                                 struct snd_kcontrol *kcontrol, int event)
 459 {
 460         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 461
 462         if (event & SND_SOC_DAPM_POST_PMU) {
 463                 /* Enable the channels */
 464                 snd_soc_update_bits(codec, CS42L42_ASP_RX_DAI0_EN,
 465                                 CS42L42_ASP_RX0_CH_EN_MASK,
 466                                 (CS42L42_ASP_RX0_CH1_EN |
 467                                 CS42L42_ASP_RX0_CH2_EN) <<
 468                                 CS42L42_ASP_RX0_CH_EN_SHIFT);
 469
 470                 /* Power up */
 471                 snd_soc_update_bits(codec, CS42L42_PWR_CTL1,
 472                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 473                                 CS42L42_HP_PDN_MASK, 0);
 474         } else if (event & SND_SOC_DAPM_PRE_PMD) {
 475                 /* Disable the channels */
 476                 snd_soc_update_bits(codec, CS42L42_ASP_RX_DAI0_EN,
 477                                 CS42L42_ASP_RX0_CH_EN_MASK, 0);
 478
 479                 /* Power down */
 480                 snd_soc_update_bits(codec, CS42L42_PWR_CTL1,
 481                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 482                                 CS42L42_HP_PDN_MASK,
 483                         CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
 484                                 CS42L42_HP_PDN_MASK);
 485         } else {
 486                 dev_err(codec->dev, "Invalid event 0x%x\n", event);
 487         }
 488         return 0;
 489 }
 490
 491 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 492         SND_SOC_DAPM_OUTPUT("HP"),
 493         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
 494                                         CS42L42_ASP_SCLK_EN_SHIFT, false),
 495         SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
 496                                         0, NULL, 0, cs42l42_hpdrv_evt,
 497                                         SND_SOC_DAPM_POST_PMU |
 498                                         SND_SOC_DAPM_PRE_PMD)
 499 };
 500
 501 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 502         {"SDIN", NULL, "Playback"},
 503         {"HPDRV", NULL, "SDIN"},
 504         {"HP", NULL, "HPDRV"}
 505 };
 506
 507 static int cs42l42_set_bias_level(struct snd_soc_codec *codec,
 508                                         enum snd_soc_bias_level level)
 509 {
 510         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 511         int ret;
 512
 513         switch (level) {
 514         case SND_SOC_BIAS_ON:
 515                 break;
 516         case SND_SOC_BIAS_PREPARE:
 517                 break;
 518         case SND_SOC_BIAS_STANDBY:
 519                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 520                         regcache_cache_only(cs42l42->regmap, false);
 521                         regcache_sync(cs42l42->regmap);
 522                         ret = regulator_bulk_enable(
 523                                                 ARRAY_SIZE(cs42l42->supplies),
 524                                                 cs42l42->supplies);
 525                         if (ret != 0) {
 526                                 dev_err(codec->dev,
 527                                         "Failed to enable regulators: %d\n",
 528                                         ret);
 529                                 return ret;
 530                         }
 531                 }
 532                 break;
 533         case SND_SOC_BIAS_OFF:
 534
 535                 regcache_cache_only(cs42l42->regmap, true);
 536                 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
 537                                                     cs42l42->supplies);
 538                 break;
 539         }
 540
 541         return 0;
 542 }
 543
 544 static int cs42l42_codec_probe(struct snd_soc_codec *codec)
 545 {
 546         struct cs42l42_private *cs42l42 =
 547                 (struct cs42l42_private *)snd_soc_codec_get_drvdata(codec);
 548
 549         cs42l42->codec = codec;
 550
 551         return 0;
 552 }
 553
 554 static const struct snd_soc_codec_driver soc_codec_dev_cs42l42 = {
 555         .probe = cs42l42_codec_probe,
 556         .set_bias_level = cs42l42_set_bias_level,
 557         .ignore_pmdown_time = true,
 558
 559         .component_driver = {
 560                 .dapm_widgets = cs42l42_dapm_widgets,
 561                 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
 562                 .dapm_routes = cs42l42_audio_map,
 563                 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
 564
 565                 .controls = cs42l42_snd_controls,
 566                 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
 567         },
 568 };
 569
 570 struct cs42l42_pll_params {
 571         u32 sclk;
 572         u8 mclk_div;
 573         u8 mclk_src_sel;
 574         u8 sclk_prediv;
 575         u8 pll_div_int;
 576         u32 pll_div_frac;
 577         u8 pll_mode;
 578         u8 pll_divout;
 579         u32 mclk_int;
 580         u8 pll_cal_ratio;
 581 };
 582
 583 /*
 584  * Common PLL Settings for given SCLK
 585  * Table 4-5 from the Datasheet
 586  */
 587 static const struct cs42l42_pll_params pll_ratio_table[] = {
 588         { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
 589         { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 590         { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 591         { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 592         { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
 593         { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
 594         { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
 595         { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
 596         { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
 597         { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
 598         { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
 599         { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
 600         { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
 601         { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
 602         { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
 603 };
 604
 605 static int cs42l42_pll_config(struct snd_soc_codec *codec)
 606 {
 607         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 608         int i;
 609         u32 fsync;
 610
 611         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 612                 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
 613                         /* Configure the internal sample rate */
 614                         snd_soc_update_bits(codec, CS42L42_MCLK_CTL,
 615                                         CS42L42_INTERNAL_FS_MASK,
 616                                         ((pll_ratio_table[i].mclk_int !=
 617                                         12000000) &&
 618                                         (pll_ratio_table[i].mclk_int !=
 619                                         24000000)) <<
 620                                         CS42L42_INTERNAL_FS_SHIFT);
 621                         /* Set the MCLK src (PLL or SCLK) and the divide
 622                          * ratio
 623                          */
 624                         snd_soc_update_bits(codec, CS42L42_MCLK_SRC_SEL,
 625                                         CS42L42_MCLK_SRC_SEL_MASK |
 626                                         CS42L42_MCLKDIV_MASK,
 627                                         (pll_ratio_table[i].mclk_src_sel
 628                                         << CS42L42_MCLK_SRC_SEL_SHIFT) |
 629                                         (pll_ratio_table[i].mclk_div <<
 630                                         CS42L42_MCLKDIV_SHIFT));
 631                         /* Set up the LRCLK */
 632                         fsync = cs42l42->sclk / cs42l42->srate;
 633                         if (((fsync * cs42l42->srate) != cs42l42->sclk)
 634                                 || ((fsync % 2) != 0)) {
 635                                 dev_err(codec->dev,
 636                                         "Unsupported sclk %d/sample rate %d\n",
 637                                         cs42l42->sclk,
 638                                         cs42l42->srate);
 639                                 return -EINVAL;
 640                         }
 641                         /* Set the LRCLK period */
 642                         snd_soc_update_bits(codec,
 643                                         CS42L42_FSYNC_P_LOWER,
 644                                         CS42L42_FSYNC_PERIOD_MASK,
 645                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 646                                         CS42L42_FSYNC_PERIOD_SHIFT);
 647                         snd_soc_update_bits(codec,
 648                                         CS42L42_FSYNC_P_UPPER,
 649                                         CS42L42_FSYNC_PERIOD_MASK,
 650                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 651                                         CS42L42_FSYNC_PERIOD_SHIFT);
 652                         /* Set the LRCLK to 50% duty cycle */
 653                         fsync = fsync / 2;
 654                         snd_soc_update_bits(codec,
 655                                         CS42L42_FSYNC_PW_LOWER,
 656                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 657                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 658                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 659                         snd_soc_update_bits(codec,
 660                                         CS42L42_FSYNC_PW_UPPER,
 661                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 662                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 663                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 664                         snd_soc_update_bits(codec,
 665                                         CS42L42_ASP_FRM_CFG,
 666                                         CS42L42_ASP_5050_MASK,
 667                                         CS42L42_ASP_5050_MASK);
 668                         /* Set the frame delay to 1.0 SCLK clocks */
 669                         snd_soc_update_bits(codec, CS42L42_ASP_FRM_CFG,
 670                                         CS42L42_ASP_FSD_MASK,
 671                                         CS42L42_ASP_FSD_1_0 <<
 672                                         CS42L42_ASP_FSD_SHIFT);
 673                         /* Set the sample rates (96k or lower) */
 674                         snd_soc_update_bits(codec, CS42L42_FS_RATE_EN,
 675                                         CS42L42_FS_EN_MASK,
 676                                         (CS42L42_FS_EN_IASRC_96K |
 677                                         CS42L42_FS_EN_OASRC_96K) <<
 678                                         CS42L42_FS_EN_SHIFT);
 679                         /* Set the input/output internal MCLK clock ~12 MHz */
 680                         snd_soc_update_bits(codec, CS42L42_IN_ASRC_CLK,
 681                                         CS42L42_CLK_IASRC_SEL_MASK,
 682                                         CS42L42_CLK_IASRC_SEL_12 <<
 683                                         CS42L42_CLK_IASRC_SEL_SHIFT);
 684                         snd_soc_update_bits(codec,
 685                                         CS42L42_OUT_ASRC_CLK,
 686                                         CS42L42_CLK_OASRC_SEL_MASK,
 687                                         CS42L42_CLK_OASRC_SEL_12 <<
 688                                         CS42L42_CLK_OASRC_SEL_SHIFT);
 689                         /* channel 1 on low LRCLK, 32 bit */
 690                         snd_soc_update_bits(codec,
 691                                         CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 692                                         CS42L42_ASP_RX_CH_AP_MASK |
 693                                         CS42L42_ASP_RX_CH_RES_MASK,
 694                                         (CS42L42_ASP_RX_CH_AP_LOW <<
 695                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 696                                         (CS42L42_ASP_RX_CH_RES_32 <<
 697                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 698                         /* Channel 2 on high LRCLK, 32 bit */
 699                         snd_soc_update_bits(codec,
 700                                         CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 701                                         CS42L42_ASP_RX_CH_AP_MASK |
 702                                         CS42L42_ASP_RX_CH_RES_MASK,
 703                                         (CS42L42_ASP_RX_CH_AP_HI <<
 704                                         CS42L42_ASP_RX_CH_AP_SHIFT) |
 705                                         (CS42L42_ASP_RX_CH_RES_32 <<
 706                                         CS42L42_ASP_RX_CH_RES_SHIFT));
 707                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 708                                 /* Pass the clock straight through */
 709                                 snd_soc_update_bits(codec,
 710                                         CS42L42_PLL_CTL1,
 711                                         CS42L42_PLL_START_MASK, 0);
 712                         } else {
 713                                 /* Configure PLL per table 4-5 */
 714                                 snd_soc_update_bits(codec,
 715                                         CS42L42_PLL_DIV_CFG1,
 716                                         CS42L42_SCLK_PREDIV_MASK,
 717                                         pll_ratio_table[i].sclk_prediv
 718                                         << CS42L42_SCLK_PREDIV_SHIFT);
 719                                 snd_soc_update_bits(codec,
 720                                         CS42L42_PLL_DIV_INT,
 721                                         CS42L42_PLL_DIV_INT_MASK,
 722                                         pll_ratio_table[i].pll_div_int
 723                                         << CS42L42_PLL_DIV_INT_SHIFT);
 724                                 snd_soc_update_bits(codec,
 725                                         CS42L42_PLL_DIV_FRAC0,
 726                                         CS42L42_PLL_DIV_FRAC_MASK,
 727                                         CS42L42_FRAC0_VAL(
 728                                         pll_ratio_table[i].pll_div_frac)
 729                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 730                                 snd_soc_update_bits(codec,
 731                                         CS42L42_PLL_DIV_FRAC1,
 732                                         CS42L42_PLL_DIV_FRAC_MASK,
 733                                         CS42L42_FRAC1_VAL(
 734                                         pll_ratio_table[i].pll_div_frac)
 735                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 736                                 snd_soc_update_bits(codec,
 737                                         CS42L42_PLL_DIV_FRAC2,
 738                                         CS42L42_PLL_DIV_FRAC_MASK,
 739                                         CS42L42_FRAC2_VAL(
 740                                         pll_ratio_table[i].pll_div_frac)
 741                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 742                                 snd_soc_update_bits(codec,
 743                                         CS42L42_PLL_CTL4,
 744                                         CS42L42_PLL_MODE_MASK,
 745                                         pll_ratio_table[i].pll_mode
 746                                         << CS42L42_PLL_MODE_SHIFT);
 747                                 snd_soc_update_bits(codec,
 748                                         CS42L42_PLL_CTL3,
 749                                         CS42L42_PLL_DIVOUT_MASK,
 750                                         pll_ratio_table[i].pll_divout
 751                                         << CS42L42_PLL_DIVOUT_SHIFT);
 752                                 snd_soc_update_bits(codec,
 753                                         CS42L42_PLL_CAL_RATIO,
 754                                         CS42L42_PLL_CAL_RATIO_MASK,
 755                                         pll_ratio_table[i].pll_cal_ratio
 756                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 757                         }
 758                         return 0;
 759                 }
 760         }
 761
 762         return -EINVAL;
 763 }
 764
 765 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 766 {
 767         struct snd_soc_codec *codec = codec_dai->codec;
 768         u32 asp_cfg_val = 0;
 769
 770         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 771         case SND_SOC_DAIFMT_CBS_CFM:
 772                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 773                                 CS42L42_ASP_MODE_SHIFT;
 774                 break;
 775         case SND_SOC_DAIFMT_CBS_CFS:
 776                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 777                                 CS42L42_ASP_MODE_SHIFT;
 778                 break;
 779         default:
 780                 return -EINVAL;
 781         }
 782
 783         /* interface format */
 784         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 785         case SND_SOC_DAIFMT_I2S:
 786                 break;
 787         default:
 788                 return -EINVAL;
 789         }
 790
 791         /* Bitclock/frame inversion */
 792         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 793         case SND_SOC_DAIFMT_NB_NF:
 794                 break;
 795         case SND_SOC_DAIFMT_NB_IF:
 796                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 797                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 798                 break;
 799         case SND_SOC_DAIFMT_IB_NF:
 800                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 801                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 802                 break;
 803         case SND_SOC_DAIFMT_IB_IF:
 804                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 805                                 CS42L42_ASP_LCPOL_IN_SHIFT;
 806                 asp_cfg_val |= CS42L42_ASP_POL_INV <<
 807                                 CS42L42_ASP_SCPOL_IN_DAC_SHIFT;
 808                 break;
 809         }
 810
 811         snd_soc_update_bits(codec, CS42L42_ASP_CLK_CFG,
 812                                 CS42L42_ASP_MODE_MASK |
 813                                 CS42L42_ASP_SCPOL_IN_DAC_MASK |
 814                                 CS42L42_ASP_LCPOL_IN_MASK, asp_cfg_val);
 815
 816         return 0;
 817 }
 818
 819 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 820                                 struct snd_pcm_hw_params *params,
 821                                 struct snd_soc_dai *dai)
 822 {
 823         struct snd_soc_codec *codec = dai->codec;
 824         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 825         int retval;
 826
 827         cs42l42->srate = params_rate(params);
 828         cs42l42->swidth = params_width(params);
 829
 830         retval = cs42l42_pll_config(codec);
 831
 832         return retval;
 833 }
 834
 835 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 836                                 int clk_id, unsigned int freq, int dir)
 837 {
 838         struct snd_soc_codec *codec = dai->codec;
 839         struct cs42l42_private *cs42l42 = snd_soc_codec_get_drvdata(codec);
 840
 841         cs42l42->sclk = freq;
 842
 843         return 0;
 844 }
 845
 846 static int cs42l42_digital_mute(struct snd_soc_dai *dai, int mute)
 847 {
 848         struct snd_soc_codec *codec = dai->codec;
 849         unsigned int regval;
 850         u8 fullScaleVol;
 851
 852         if (mute) {
 853                 /* Mark SCLK as not present to turn on the internal
 854                  * oscillator.
 855                  */
 856                 snd_soc_update_bits(codec, CS42L42_OSC_SWITCH,
 857                                                 CS42L42_SCLK_PRESENT_MASK, 0);
 858
 859                 snd_soc_update_bits(codec, CS42L42_PLL_CTL1,
 860                                 CS42L42_PLL_START_MASK,
 861                                 0 << CS42L42_PLL_START_SHIFT);
 862
 863                 /* Mute the headphone */
 864                 snd_soc_update_bits(codec, CS42L42_HP_CTL,
 865                                 CS42L42_HP_ANA_AMUTE_MASK |
 866                                 CS42L42_HP_ANA_BMUTE_MASK,
 867                                 CS42L42_HP_ANA_AMUTE_MASK |
 868                                 CS42L42_HP_ANA_BMUTE_MASK);
 869         } else {
 870                 snd_soc_update_bits(codec, CS42L42_PLL_CTL1,
 871                                 CS42L42_PLL_START_MASK,
 872                                 1 << CS42L42_PLL_START_SHIFT);
 873                 /* Read the headphone load */
 874                 regval = snd_soc_read(codec, CS42L42_LOAD_DET_RCSTAT);
 875                 if (((regval & CS42L42_RLA_STAT_MASK) >>
 876                         CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
 877                         fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
 878                 } else {
 879                         fullScaleVol = 0;
 880                 }
 881
 882                 /* Un-mute the headphone, set the full scale volume flag */
 883                 snd_soc_update_bits(codec, CS42L42_HP_CTL,
 884                                 CS42L42_HP_ANA_AMUTE_MASK |
 885                                 CS42L42_HP_ANA_BMUTE_MASK |
 886                                 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
 887
 888                 /* Mark SCLK as present, turn off internal oscillator */
 889                 snd_soc_update_bits(codec, CS42L42_OSC_SWITCH,
 890                                 CS42L42_SCLK_PRESENT_MASK,
 891                                 CS42L42_SCLK_PRESENT_MASK);
 892         }
 893
 894         return 0;
 895 }
 896
 897 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
 898                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
 899                         SNDRV_PCM_FMTBIT_S32_LE)
 900
 901
 902 static const struct snd_soc_dai_ops cs42l42_ops = {
 903         .hw_params      = cs42l42_pcm_hw_params,
 904         .set_fmt        = cs42l42_set_dai_fmt,
 905         .set_sysclk     = cs42l42_set_sysclk,
 906         .digital_mute = cs42l42_digital_mute
 907 };
 908
 909 static struct snd_soc_dai_driver cs42l42_dai = {
 910                 .name = "cs42l42",
 911                 .playback = {
 912                         .stream_name = "Playback",
 913                         .channels_min = 1,
 914                         .channels_max = 2,
 915                         .rates = SNDRV_PCM_RATE_8000_192000,
 916                         .formats = CS42L42_FORMATS,
 917                 },
 918                 .capture = {
 919                         .stream_name = "Capture",
 920                         .channels_min = 1,
 921                         .channels_max = 2,
 922                         .rates = SNDRV_PCM_RATE_8000_192000,
 923                         .formats = CS42L42_FORMATS,
 924                 },
 925                 .ops = &cs42l42_ops,
 926 };
 927
 928 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
 929 {
 930         unsigned int hs_det_status;
 931         unsigned int int_status;
 932
 933         /* Mask the auto detect interrupt */
 934         regmap_update_bits(cs42l42->regmap,
 935                 CS42L42_CODEC_INT_MASK,
 936                 CS42L42_PDN_DONE_MASK |
 937                 CS42L42_HSDET_AUTO_DONE_MASK,
 938                 (1 << CS42L42_PDN_DONE_SHIFT) |
 939                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
 940
 941         /* Set hs detect to automatic, disabled mode */
 942         regmap_update_bits(cs42l42->regmap,
 943                 CS42L42_HSDET_CTL2,
 944                 CS42L42_HSDET_CTRL_MASK |
 945                 CS42L42_HSDET_SET_MASK |
 946                 CS42L42_HSBIAS_REF_MASK |
 947                 CS42L42_HSDET_AUTO_TIME_MASK,
 948                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
 949                 (2 << CS42L42_HSDET_SET_SHIFT) |
 950                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
 951                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 952
 953         /* Read and save the hs detection result */
 954         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
 955
 956         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
 957                                 CS42L42_HSDET_TYPE_SHIFT;
 958
 959         /* Set up button detection */
 960         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
 961               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
 962                 /* Set auto HS bias settings to default */
 963                 regmap_update_bits(cs42l42->regmap,
 964                         CS42L42_HSBIAS_SC_AUTOCTL,
 965                         CS42L42_HSBIAS_SENSE_EN_MASK |
 966                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 967                         CS42L42_TIP_SENSE_EN_MASK |
 968                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 969                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 970                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 971                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 972                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 973
 974                 /* Set up hs detect level sensitivity */
 975                 regmap_update_bits(cs42l42->regmap,
 976                         CS42L42_MIC_DET_CTL1,
 977                         CS42L42_LATCH_TO_VP_MASK |
 978                         CS42L42_EVENT_STAT_SEL_MASK |
 979                         CS42L42_HS_DET_LEVEL_MASK,
 980                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
 981                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
 982                         (cs42l42->bias_thresholds[0] <<
 983                         CS42L42_HS_DET_LEVEL_SHIFT));
 984
 985                 /* Set auto HS bias settings to default */
 986                 regmap_update_bits(cs42l42->regmap,
 987                         CS42L42_HSBIAS_SC_AUTOCTL,
 988                         CS42L42_HSBIAS_SENSE_EN_MASK |
 989                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
 990                         CS42L42_TIP_SENSE_EN_MASK |
 991                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
 992                         (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
 993                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
 994                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
 995                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
 996
 997                 /* Turn on level detect circuitry */
 998                 regmap_update_bits(cs42l42->regmap,
 999                         CS42L42_MISC_DET_CTL,
1000                         CS42L42_DETECT_MODE_MASK |
1001                         CS42L42_HSBIAS_CTL_MASK |
1002                         CS42L42_PDN_MIC_LVL_DET_MASK,
1003                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1004                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1005                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1006
1007                 msleep(cs42l42->btn_det_init_dbnce);
1008
1009                 /* Clear any button interrupts before unmasking them */
1010                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1011                             &int_status);
1012
1013                 /* Unmask button detect interrupts */
1014                 regmap_update_bits(cs42l42->regmap,
1015                         CS42L42_DET_INT2_MASK,
1016                         CS42L42_M_DETECT_TF_MASK |
1017                         CS42L42_M_DETECT_FT_MASK |
1018                         CS42L42_M_HSBIAS_HIZ_MASK |
1019                         CS42L42_M_SHORT_RLS_MASK |
1020                         CS42L42_M_SHORT_DET_MASK,
1021                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1022                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1023                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1024                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1025                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1026         } else {
1027                 /* Make sure button detect and HS bias circuits are off */
1028                 regmap_update_bits(cs42l42->regmap,
1029                         CS42L42_MISC_DET_CTL,
1030                         CS42L42_DETECT_MODE_MASK |
1031                         CS42L42_HSBIAS_CTL_MASK |
1032                         CS42L42_PDN_MIC_LVL_DET_MASK,
1033                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1034                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1035                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1036         }
1037
1038         regmap_update_bits(cs42l42->regmap,
1039                                 CS42L42_DAC_CTL2,
1040                                 CS42L42_HPOUT_PULLDOWN_MASK |
1041                                 CS42L42_HPOUT_LOAD_MASK |
1042                                 CS42L42_HPOUT_CLAMP_MASK |
1043                                 CS42L42_DAC_HPF_EN_MASK |
1044                                 CS42L42_DAC_MON_EN_MASK,
1045                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1046                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1047                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1048                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1049                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1050
1051         /* Unmask tip sense interrupts */
1052         regmap_update_bits(cs42l42->regmap,
1053                 CS42L42_TSRS_PLUG_INT_MASK,
1054                 CS42L42_RS_PLUG_MASK |
1055                 CS42L42_RS_UNPLUG_MASK |
1056                 CS42L42_TS_PLUG_MASK |
1057                 CS42L42_TS_UNPLUG_MASK,
1058                 (1 << CS42L42_RS_PLUG_SHIFT) |
1059                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1060                 (0 << CS42L42_TS_PLUG_SHIFT) |
1061                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1062 }
1063
1064 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1065 {
1066         /* Mask tip sense interrupts */
1067         regmap_update_bits(cs42l42->regmap,
1068                                 CS42L42_TSRS_PLUG_INT_MASK,
1069                                 CS42L42_RS_PLUG_MASK |
1070                                 CS42L42_RS_UNPLUG_MASK |
1071                                 CS42L42_TS_PLUG_MASK |
1072                                 CS42L42_TS_UNPLUG_MASK,
1073                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1074                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1075                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1076                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1077
1078         /* Make sure button detect and HS bias circuits are off */
1079         regmap_update_bits(cs42l42->regmap,
1080                                 CS42L42_MISC_DET_CTL,
1081                                 CS42L42_DETECT_MODE_MASK |
1082                                 CS42L42_HSBIAS_CTL_MASK |
1083                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1084                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1085                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1086                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1087
1088         /* Set auto HS bias settings to default */
1089         regmap_update_bits(cs42l42->regmap,
1090                                 CS42L42_HSBIAS_SC_AUTOCTL,
1091                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1092                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1093                                 CS42L42_TIP_SENSE_EN_MASK |
1094                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1095                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1096                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1097                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1098                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1099
1100         /* Set hs detect to manual, disabled mode */
1101         regmap_update_bits(cs42l42->regmap,
1102                                 CS42L42_HSDET_CTL2,
1103                                 CS42L42_HSDET_CTRL_MASK |
1104                                 CS42L42_HSDET_SET_MASK |
1105                                 CS42L42_HSBIAS_REF_MASK |
1106                                 CS42L42_HSDET_AUTO_TIME_MASK,
1107                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1108                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1109                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1110                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1111
1112         regmap_update_bits(cs42l42->regmap,
1113                                 CS42L42_DAC_CTL2,
1114                                 CS42L42_HPOUT_PULLDOWN_MASK |
1115                                 CS42L42_HPOUT_LOAD_MASK |
1116                                 CS42L42_HPOUT_CLAMP_MASK |
1117                                 CS42L42_DAC_HPF_EN_MASK |
1118                                 CS42L42_DAC_MON_EN_MASK,
1119                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1120                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1121                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1122                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1123                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1124
1125         /* Power up HS bias to 2.7V */
1126         regmap_update_bits(cs42l42->regmap,
1127                                 CS42L42_MISC_DET_CTL,
1128                                 CS42L42_DETECT_MODE_MASK |
1129                                 CS42L42_HSBIAS_CTL_MASK |
1130                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1131                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1132                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1133                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1134
1135         /* Wait for HS bias to ramp up */
1136         msleep(cs42l42->hs_bias_ramp_time);
1137
1138         /* Unmask auto detect interrupt */
1139         regmap_update_bits(cs42l42->regmap,
1140                                 CS42L42_CODEC_INT_MASK,
1141                                 CS42L42_PDN_DONE_MASK |
1142                                 CS42L42_HSDET_AUTO_DONE_MASK,
1143                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1144                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1145
1146         /* Set hs detect to automatic, enabled mode */
1147         regmap_update_bits(cs42l42->regmap,
1148                                 CS42L42_HSDET_CTL2,
1149                                 CS42L42_HSDET_CTRL_MASK |
1150                                 CS42L42_HSDET_SET_MASK |
1151                                 CS42L42_HSBIAS_REF_MASK |
1152                                 CS42L42_HSDET_AUTO_TIME_MASK,
1153                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1154                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1155                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1156                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1157 }
1158
1159 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1160 {
1161         /* Mask button detect interrupts */
1162         regmap_update_bits(cs42l42->regmap,
1163                 CS42L42_DET_INT2_MASK,
1164                 CS42L42_M_DETECT_TF_MASK |
1165                 CS42L42_M_DETECT_FT_MASK |
1166                 CS42L42_M_HSBIAS_HIZ_MASK |
1167                 CS42L42_M_SHORT_RLS_MASK |
1168                 CS42L42_M_SHORT_DET_MASK,
1169                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1170                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1171                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1172                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1173                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1174
1175         /* Ground HS bias */
1176         regmap_update_bits(cs42l42->regmap,
1177                                 CS42L42_MISC_DET_CTL,
1178                                 CS42L42_DETECT_MODE_MASK |
1179                                 CS42L42_HSBIAS_CTL_MASK |
1180                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1181                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1182                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1183                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1184
1185         /* Set auto HS bias settings to default */
1186         regmap_update_bits(cs42l42->regmap,
1187                                 CS42L42_HSBIAS_SC_AUTOCTL,
1188                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1189                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1190                                 CS42L42_TIP_SENSE_EN_MASK |
1191                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1192                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1193                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1194                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1195                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1196
1197         /* Set hs detect to manual, disabled mode */
1198         regmap_update_bits(cs42l42->regmap,
1199                                 CS42L42_HSDET_CTL2,
1200                                 CS42L42_HSDET_CTRL_MASK |
1201                                 CS42L42_HSDET_SET_MASK |
1202                                 CS42L42_HSBIAS_REF_MASK |
1203                                 CS42L42_HSDET_AUTO_TIME_MASK,
1204                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1205                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1206                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1207                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1208 }
1209
1210 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1211 {
1212         int bias_level;
1213         unsigned int detect_status;
1214
1215         /* Mask button detect interrupts */
1216         regmap_update_bits(cs42l42->regmap,
1217                 CS42L42_DET_INT2_MASK,
1218                 CS42L42_M_DETECT_TF_MASK |
1219                 CS42L42_M_DETECT_FT_MASK |
1220                 CS42L42_M_HSBIAS_HIZ_MASK |
1221                 CS42L42_M_SHORT_RLS_MASK |
1222                 CS42L42_M_SHORT_DET_MASK,
1223                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1224                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1225                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1226                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1227                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1228
1229         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1230                      cs42l42->btn_det_event_dbnce * 2000);
1231
1232         /* Test all 4 level detect biases */
1233         bias_level = 1;
1234         do {
1235                 /* Adjust button detect level sensitivity */
1236                 regmap_update_bits(cs42l42->regmap,
1237                         CS42L42_MIC_DET_CTL1,
1238                         CS42L42_LATCH_TO_VP_MASK |
1239                         CS42L42_EVENT_STAT_SEL_MASK |
1240                         CS42L42_HS_DET_LEVEL_MASK,
1241                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1242                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1243                         (cs42l42->bias_thresholds[bias_level] <<
1244                         CS42L42_HS_DET_LEVEL_SHIFT));
1245
1246                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1247                                 &detect_status);
1248         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1249                 (++bias_level < CS42L42_NUM_BIASES));
1250
1251         switch (bias_level) {
1252         case 1: /* Function C button press */
1253                 dev_dbg(cs42l42->codec->dev, "Function C button press\n");
1254                 break;
1255         case 2: /* Function B button press */
1256                 dev_dbg(cs42l42->codec->dev, "Function B button press\n");
1257                 break;
1258         case 3: /* Function D button press */
1259                 dev_dbg(cs42l42->codec->dev, "Function D button press\n");
1260                 break;
1261         case 4: /* Function A button press */
1262                 dev_dbg(cs42l42->codec->dev, "Function A button press\n");
1263                 break;
1264         }
1265
1266         /* Set button detect level sensitivity back to default */
1267         regmap_update_bits(cs42l42->regmap,
1268                 CS42L42_MIC_DET_CTL1,
1269                 CS42L42_LATCH_TO_VP_MASK |
1270                 CS42L42_EVENT_STAT_SEL_MASK |
1271                 CS42L42_HS_DET_LEVEL_MASK,
1272                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1273                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1274                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1275
1276         /* Clear any button interrupts before unmasking them */
1277         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1278                     &detect_status);
1279
1280         /* Unmask button detect interrupts */
1281         regmap_update_bits(cs42l42->regmap,
1282                 CS42L42_DET_INT2_MASK,
1283                 CS42L42_M_DETECT_TF_MASK |
1284                 CS42L42_M_DETECT_FT_MASK |
1285                 CS42L42_M_HSBIAS_HIZ_MASK |
1286                 CS42L42_M_SHORT_RLS_MASK |
1287                 CS42L42_M_SHORT_DET_MASK,
1288                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1289                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1290                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1291                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1292                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1293 }
1294
1295 struct cs42l42_irq_params {
1296         u16 status_addr;
1297         u16 mask_addr;
1298         u8 mask;
1299 };
1300
1301 static const struct cs42l42_irq_params irq_params_table[] = {
1302         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1303                 CS42L42_ADC_OVFL_VAL_MASK},
1304         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1305                 CS42L42_MIXER_VAL_MASK},
1306         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1307                 CS42L42_SRC_VAL_MASK},
1308         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1309                 CS42L42_ASP_RX_VAL_MASK},
1310         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1311                 CS42L42_ASP_TX_VAL_MASK},
1312         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1313                 CS42L42_CODEC_VAL_MASK},
1314         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1315                 CS42L42_DET_INT_VAL1_MASK},
1316         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1317                 CS42L42_DET_INT_VAL2_MASK},
1318         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1319                 CS42L42_SRCPL_VAL_MASK},
1320         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1321                 CS42L42_VPMON_VAL_MASK},
1322         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1323                 CS42L42_PLL_LOCK_VAL_MASK},
1324         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1325                 CS42L42_TSRS_PLUG_VAL_MASK}
1326 };
1327
1328 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1329 {
1330         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1331         struct snd_soc_codec *codec = cs42l42->codec;
1332         unsigned int stickies[12];
1333         unsigned int masks[12];
1334         unsigned int current_plug_status;
1335         unsigned int current_button_status;
1336         unsigned int i;
1337
1338         /* Read sticky registers to clear interurpt */
1339         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1340                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1341                                 &(stickies[i]));
1342                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1343                                 &(masks[i]));
1344                 stickies[i] = stickies[i] & (~masks[i]) &
1345                                 irq_params_table[i].mask;
1346         }
1347
1348         /* Read tip sense status before handling type detect */
1349         current_plug_status = (stickies[11] &
1350                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1351                 CS42L42_TS_PLUG_SHIFT;
1352
1353         /* Read button sense status */
1354         current_button_status = stickies[7] &
1355                 (CS42L42_M_DETECT_TF_MASK |
1356                 CS42L42_M_DETECT_FT_MASK |
1357                 CS42L42_M_HSBIAS_HIZ_MASK);
1358
1359         /* Check auto-detect status */
1360         if ((~masks[5]) & irq_params_table[5].mask) {
1361                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1362                         cs42l42_process_hs_type_detect(cs42l42);
1363                         dev_dbg(codec->dev,
1364                                 "Auto detect done (%d)\n",
1365                                 cs42l42->hs_type);
1366                 }
1367         }
1368
1369         /* Check tip sense status */
1370         if ((~masks[11]) & irq_params_table[11].mask) {
1371                 switch (current_plug_status) {
1372                 case CS42L42_TS_PLUG:
1373                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1374                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1375                                 cs42l42_init_hs_type_detect(cs42l42);
1376                         }
1377                         break;
1378
1379                 case CS42L42_TS_UNPLUG:
1380                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1381                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1382                                 cs42l42_cancel_hs_type_detect(cs42l42);
1383                                 dev_dbg(codec->dev,
1384                                         "Unplug event\n");
1385                         }
1386                         break;
1387
1388                 default:
1389                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1390                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1391                 }
1392         }
1393
1394         /* Check button detect status */
1395         if ((~masks[7]) & irq_params_table[7].mask) {
1396                 if (!(current_button_status &
1397                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1398
1399                         if (current_button_status &
1400                                 CS42L42_M_DETECT_TF_MASK) {
1401                                 dev_dbg(codec->dev,
1402                                         "Button released\n");
1403                         } else if (current_button_status &
1404                                 CS42L42_M_DETECT_FT_MASK) {
1405                                 cs42l42_handle_button_press(cs42l42);
1406                         }
1407                 }
1408         }
1409
1410         return IRQ_HANDLED;
1411 }
1412
1413 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1414 {
1415         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1416                         CS42L42_ADC_OVFL_MASK,
1417                         (1 << CS42L42_ADC_OVFL_SHIFT));
1418
1419         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1420                         CS42L42_MIX_CHB_OVFL_MASK |
1421                         CS42L42_MIX_CHA_OVFL_MASK |
1422                         CS42L42_EQ_OVFL_MASK |
1423                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1424                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1425                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1426                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1427                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1428
1429         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1430                         CS42L42_SRC_ILK_MASK |
1431                         CS42L42_SRC_OLK_MASK |
1432                         CS42L42_SRC_IUNLK_MASK |
1433                         CS42L42_SRC_OUNLK_MASK,
1434                         (1 << CS42L42_SRC_ILK_SHIFT) |
1435                         (1 << CS42L42_SRC_OLK_SHIFT) |
1436                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1437                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1438
1439         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1440                         CS42L42_ASPRX_NOLRCK_MASK |
1441                         CS42L42_ASPRX_EARLY_MASK |
1442                         CS42L42_ASPRX_LATE_MASK |
1443                         CS42L42_ASPRX_ERROR_MASK |
1444                         CS42L42_ASPRX_OVLD_MASK,
1445                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1446                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1447                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1448                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1449                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1450
1451         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1452                         CS42L42_ASPTX_NOLRCK_MASK |
1453                         CS42L42_ASPTX_EARLY_MASK |
1454                         CS42L42_ASPTX_LATE_MASK |
1455                         CS42L42_ASPTX_SMERROR_MASK,
1456                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1457                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1458                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1459                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1460
1461         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1462                         CS42L42_PDN_DONE_MASK |
1463                         CS42L42_HSDET_AUTO_DONE_MASK,
1464                         (1 << CS42L42_PDN_DONE_SHIFT) |
1465                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1466
1467         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1468                         CS42L42_SRCPL_ADC_LK_MASK |
1469                         CS42L42_SRCPL_DAC_LK_MASK |
1470                         CS42L42_SRCPL_ADC_UNLK_MASK |
1471                         CS42L42_SRCPL_DAC_UNLK_MASK,
1472                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1473                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1474                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1475                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1476
1477         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1478                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1479                         CS42L42_TIP_SENSE_PLUG_MASK |
1480                         CS42L42_HSBIAS_SENSE_MASK,
1481                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1482                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1483                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1484
1485         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1486                         CS42L42_M_DETECT_TF_MASK |
1487                         CS42L42_M_DETECT_FT_MASK |
1488                         CS42L42_M_HSBIAS_HIZ_MASK |
1489                         CS42L42_M_SHORT_RLS_MASK |
1490                         CS42L42_M_SHORT_DET_MASK,
1491                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1492                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1493                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1494                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1495                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1496
1497         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1498                         CS42L42_VPMON_MASK,
1499                         (1 << CS42L42_VPMON_SHIFT));
1500
1501         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1502                         CS42L42_PLL_LOCK_MASK,
1503                         (1 << CS42L42_PLL_LOCK_SHIFT));
1504
1505         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1506                         CS42L42_RS_PLUG_MASK |
1507                         CS42L42_RS_UNPLUG_MASK |
1508                         CS42L42_TS_PLUG_MASK |
1509                         CS42L42_TS_UNPLUG_MASK,
1510                         (1 << CS42L42_RS_PLUG_SHIFT) |
1511                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1512                         (0 << CS42L42_TS_PLUG_SHIFT) |
1513                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1514 }
1515
1516 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1517 {
1518         unsigned int reg;
1519
1520         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1521
1522         /* Latch analog controls to VP power domain */
1523         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1524                         CS42L42_LATCH_TO_VP_MASK |
1525                         CS42L42_EVENT_STAT_SEL_MASK |
1526                         CS42L42_HS_DET_LEVEL_MASK,
1527                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1528                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1529                         (cs42l42->bias_thresholds[0] <<
1530                         CS42L42_HS_DET_LEVEL_SHIFT));
1531
1532         /* Remove ground noise-suppression clamps */
1533         regmap_update_bits(cs42l42->regmap,
1534                         CS42L42_HS_CLAMP_DISABLE,
1535                         CS42L42_HS_CLAMP_DISABLE_MASK,
1536                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1537
1538         /* Enable the tip sense circuit */
1539         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1540                         CS42L42_TIP_SENSE_CTRL_MASK |
1541                         CS42L42_TIP_SENSE_INV_MASK |
1542                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1543                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1544                         (0 << CS42L42_TIP_SENSE_INV_SHIFT) |
1545                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1546
1547         /* Save the initial status of the tip sense */
1548         regmap_read(cs42l42->regmap,
1549                           CS42L42_TSRS_PLUG_STATUS,
1550                           &reg);
1551         cs42l42->plug_state = (((char) reg) &
1552                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1553                       CS42L42_TS_PLUG_SHIFT;
1554 }
1555
1556 static const unsigned int threshold_defaults[] = {
1557         CS42L42_HS_DET_LEVEL_15,
1558         CS42L42_HS_DET_LEVEL_8,
1559         CS42L42_HS_DET_LEVEL_4,
1560         CS42L42_HS_DET_LEVEL_1
1561 };
1562
1563 static int cs42l42_handle_device_data(struct i2c_client *i2c_client,
1564                                         struct cs42l42_private *cs42l42)
1565 {
1566         struct device_node *np = i2c_client->dev.of_node;
1567         unsigned int val;
1568         unsigned int thresholds[CS42L42_NUM_BIASES];
1569         int ret;
1570         int i;
1571
1572         ret = of_property_read_u32(np, "cirrus,ts-inv", &val);
1573
1574         if (!ret) {
1575                 switch (val) {
1576                 case CS42L42_TS_INV_EN:
1577                 case CS42L42_TS_INV_DIS:
1578                         cs42l42->ts_inv = val;
1579                         break;
1580                 default:
1581                         dev_err(&i2c_client->dev,
1582                                 "Wrong cirrus,ts-inv DT value %d\n",
1583                                 val);
1584                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1585                 }
1586         } else {
1587                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1588         }
1589
1590         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1591                         CS42L42_TS_INV_MASK,
1592                         (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT));
1593
1594         ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val);
1595
1596         if (!ret) {
1597                 switch (val) {
1598                 case CS42L42_TS_DBNCE_0:
1599                 case CS42L42_TS_DBNCE_125:
1600                 case CS42L42_TS_DBNCE_250:
1601                 case CS42L42_TS_DBNCE_500:
1602                 case CS42L42_TS_DBNCE_750:
1603                 case CS42L42_TS_DBNCE_1000:
1604                 case CS42L42_TS_DBNCE_1250:
1605                 case CS42L42_TS_DBNCE_1500:
1606                         cs42l42->ts_dbnc_rise = val;
1607                         break;
1608                 default:
1609                         dev_err(&i2c_client->dev,
1610                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1611                                 val);
1612                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1613                 }
1614         } else {
1615                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1616         }
1617
1618         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1619                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1620                         (cs42l42->ts_dbnc_rise <<
1621                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1622
1623         ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val);
1624
1625         if (!ret) {
1626                 switch (val) {
1627                 case CS42L42_TS_DBNCE_0:
1628                 case CS42L42_TS_DBNCE_125:
1629                 case CS42L42_TS_DBNCE_250:
1630                 case CS42L42_TS_DBNCE_500:
1631                 case CS42L42_TS_DBNCE_750:
1632                 case CS42L42_TS_DBNCE_1000:
1633                 case CS42L42_TS_DBNCE_1250:
1634                 case CS42L42_TS_DBNCE_1500:
1635                         cs42l42->ts_dbnc_fall = val;
1636                         break;
1637                 default:
1638                         dev_err(&i2c_client->dev,
1639                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1640                                 val);
1641                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1642                 }
1643         } else {
1644                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1645         }
1646
1647         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1648                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1649                         (cs42l42->ts_dbnc_fall <<
1650                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1651
1652         ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val);
1653
1654         if (!ret) {
1655                 if ((val >= CS42L42_BTN_DET_INIT_DBNCE_MIN) &&
1656                         (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX))
1657                         cs42l42->btn_det_init_dbnce = val;
1658                 else {
1659                         dev_err(&i2c_client->dev,
1660                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1661                                 val);
1662                         cs42l42->btn_det_init_dbnce =
1663                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1664                 }
1665         } else {
1666                 cs42l42->btn_det_init_dbnce =
1667                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1668         }
1669
1670         ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val);
1671
1672         if (!ret) {
1673                 if ((val >= CS42L42_BTN_DET_EVENT_DBNCE_MIN) &&
1674                         (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX))
1675                         cs42l42->btn_det_event_dbnce = val;
1676                 else {
1677                         dev_err(&i2c_client->dev,
1678                         "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1679                         cs42l42->btn_det_event_dbnce =
1680                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1681                 }
1682         } else {
1683                 cs42l42->btn_det_event_dbnce =
1684                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1685         }
1686
1687         ret = of_property_read_u32_array(np, "cirrus,bias-lvls",
1688                                    (u32 *)thresholds, CS42L42_NUM_BIASES);
1689
1690         if (!ret) {
1691                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1692                         if ((thresholds[i] >= CS42L42_HS_DET_LEVEL_MIN) &&
1693                                 (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX))
1694                                 cs42l42->bias_thresholds[i] = thresholds[i];
1695                         else {
1696                                 dev_err(&i2c_client->dev,
1697                                 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1698                                         thresholds[i]);
1699                                 cs42l42->bias_thresholds[i] =
1700                                         threshold_defaults[i];
1701                         }
1702                 }
1703         } else {
1704                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1705                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1706         }
1707
1708         ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val);
1709
1710         if (!ret) {
1711                 switch (val) {
1712                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1713                         cs42l42->hs_bias_ramp_rate = val;
1714                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1715                         break;
1716                 case CS42L42_HSBIAS_RAMP_FAST:
1717                         cs42l42->hs_bias_ramp_rate = val;
1718                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1719                         break;
1720                 case CS42L42_HSBIAS_RAMP_SLOW:
1721                         cs42l42->hs_bias_ramp_rate = val;
1722                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1723                         break;
1724                 case CS42L42_HSBIAS_RAMP_SLOWEST:
1725                         cs42l42->hs_bias_ramp_rate = val;
1726                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1727                         break;
1728                 default:
1729                         dev_err(&i2c_client->dev,
1730                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1731                                 val);
1732                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1733                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1734                 }
1735         } else {
1736                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1737                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1738         }
1739
1740         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1741                         CS42L42_HSBIAS_RAMP_MASK,
1742                         (cs42l42->hs_bias_ramp_rate <<
1743                         CS42L42_HSBIAS_RAMP_SHIFT));
1744
1745         return 0;
1746 }
1747
1748 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1749                                        const struct i2c_device_id *id)
1750 {
1751         struct cs42l42_private *cs42l42;
1752         int ret, i;
1753         unsigned int devid = 0;
1754         unsigned int reg;
1755
1756         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1757                                GFP_KERNEL);
1758         if (!cs42l42)
1759                 return -ENOMEM;
1760
1761         i2c_set_clientdata(i2c_client, cs42l42);
1762
1763         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1764         if (IS_ERR(cs42l42->regmap)) {
1765                 ret = PTR_ERR(cs42l42->regmap);
1766                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1767                 return ret;
1768         }
1769
1770         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1771                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1772
1773         ret = devm_regulator_bulk_get(&i2c_client->dev,
1774                                       ARRAY_SIZE(cs42l42->supplies),
1775                                       cs42l42->supplies);
1776         if (ret != 0) {
1777                 dev_err(&i2c_client->dev,
1778                         "Failed to request supplies: %d\n", ret);
1779                 return ret;
1780         }
1781
1782         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1783                                     cs42l42->supplies);
1784         if (ret != 0) {
1785                 dev_err(&i2c_client->dev,
1786                         "Failed to enable supplies: %d\n", ret);
1787                 return ret;
1788         }
1789
1790         /* Reset the Device */
1791         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1792                 "reset", GPIOD_OUT_LOW);
1793         if (IS_ERR(cs42l42->reset_gpio))
1794                 return PTR_ERR(cs42l42->reset_gpio);
1795
1796         if (cs42l42->reset_gpio) {
1797                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1798                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1799         }
1800         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1801
1802         /* Request IRQ */
1803         ret = devm_request_threaded_irq(&i2c_client->dev,
1804                         i2c_client->irq,
1805                         NULL, cs42l42_irq_thread,
1806                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1807                         "cs42l42", cs42l42);
1808         if (ret == -EPROBE_DEFER)
1809                 goto err_disable;
1810         else if (ret != 0)
1811                 dev_err(&i2c_client->dev,
1812                         "Failed to request IRQ: %d\n", ret);
1813
1814         /* initialize codec */
1815         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, &reg);
1816         devid = (reg & 0xFF) << 12;
1817
1818         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, &reg);
1819         devid |= (reg & 0xFF) << 4;
1820
1821         ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, &reg);
1822         devid |= (reg & 0xF0) >> 4;
1823
1824         if (devid != CS42L42_CHIP_ID) {
1825                 ret = -ENODEV;
1826                 dev_err(&i2c_client->dev,
1827                         "CS42L42 Device ID (%X). Expected %X\n",
1828                         devid, CS42L42_CHIP_ID);
1829                 return ret;
1830         }
1831
1832         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
1833         if (ret < 0) {
1834                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1835                 return ret;
1836         }
1837
1838         dev_info(&i2c_client->dev,
1839                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1840
1841         /* Power up the codec */
1842         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1843                         CS42L42_ASP_DAO_PDN_MASK |
1844                         CS42L42_ASP_DAI_PDN_MASK |
1845                         CS42L42_MIXER_PDN_MASK |
1846                         CS42L42_EQ_PDN_MASK |
1847                         CS42L42_HP_PDN_MASK |
1848                         CS42L42_ADC_PDN_MASK |
1849                         CS42L42_PDN_ALL_MASK,
1850                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1851                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1852                         (1 << CS42L42_MIXER_PDN_SHIFT) |
1853                         (1 << CS42L42_EQ_PDN_SHIFT) |
1854                         (1 << CS42L42_HP_PDN_SHIFT) |
1855                         (1 << CS42L42_ADC_PDN_SHIFT) |
1856                         (0 << CS42L42_PDN_ALL_SHIFT));
1857
1858         if (i2c_client->dev.of_node) {
1859                 ret = cs42l42_handle_device_data(i2c_client, cs42l42);
1860                 if (ret != 0)
1861                         return ret;
1862         }
1863
1864         /* Setup headset detection */
1865         cs42l42_setup_hs_type_detect(cs42l42);
1866
1867         /* Mask/Unmask Interrupts */
1868         cs42l42_set_interrupt_masks(cs42l42);
1869
1870         /* Register codec for machine driver */
1871         ret =  snd_soc_register_codec(&i2c_client->dev,
1872                         &soc_codec_dev_cs42l42, &cs42l42_dai, 1);
1873         if (ret < 0)
1874                 goto err_disable;
1875         return 0;
1876
1877 err_disable:
1878         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1879                                 cs42l42->supplies);
1880         return ret;
1881 }
1882
1883 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1884 {
1885         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1886
1887         snd_soc_unregister_codec(&i2c_client->dev);
1888
1889         /* Hold down reset */
1890         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1891
1892         return 0;
1893 }
1894
1895 #ifdef CONFIG_PM
1896 static int cs42l42_runtime_suspend(struct device *dev)
1897 {
1898         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1899
1900         regcache_cache_only(cs42l42->regmap, true);
1901         regcache_mark_dirty(cs42l42->regmap);
1902
1903         /* Hold down reset */
1904         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1905
1906         /* remove power */
1907         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1908                                 cs42l42->supplies);
1909
1910         return 0;
1911 }
1912
1913 static int cs42l42_runtime_resume(struct device *dev)
1914 {
1915         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1916         int ret;
1917
1918         /* Enable power */
1919         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1920                                         cs42l42->supplies);
1921         if (ret != 0) {
1922                 dev_err(dev, "Failed to enable supplies: %d\n",
1923                         ret);
1924                 return ret;
1925         }
1926
1927         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1928         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1929
1930         regcache_cache_only(cs42l42->regmap, false);
1931         regcache_sync(cs42l42->regmap);
1932
1933         return 0;
1934 }
1935 #endif
1936
1937 static const struct dev_pm_ops cs42l42_runtime_pm = {
1938         SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1939                            NULL)
1940 };
1941
1942 static const struct of_device_id cs42l42_of_match[] = {
1943         { .compatible = "cirrus,cs42l42", },
1944         {},
1945 };
1946 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1947
1948
1949 static const struct i2c_device_id cs42l42_id[] = {
1950         {"cs42l42", 0},
1951         {}
1952 };
1953
1954 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1955
1956 static struct i2c_driver cs42l42_i2c_driver = {
1957         .driver = {
1958                 .name = "cs42l42",
1959                 .pm = &cs42l42_runtime_pm,
1960                 .of_match_table = cs42l42_of_match,
1961                 },
1962         .id_table = cs42l42_id,
1963         .probe = cs42l42_i2c_probe,
1964         .remove = cs42l42_i2c_remove,
1965 };
1966
1967 module_i2c_driver(cs42l42_i2c_driver);
1968
1969 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1970 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1971 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1972 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1973 MODULE_LICENSE("GPL");