sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/acpi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38 #include "cirrus_legacy.h"
  39
  40 static const struct reg_default cs42l42_reg_defaults[] = {
  41         { CS42L42_FRZ_CTL,                      0x00 },
  42         { CS42L42_SRC_CTL,                      0x10 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_SLOW_START_ENABLE,            0x70 },
  46         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  47         { CS42L42_I2C_STRETCH,                  0x03 },
  48         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  49         { CS42L42_PWR_CTL1,                     0xFF },
  50         { CS42L42_PWR_CTL2,                     0x84 },
  51         { CS42L42_PWR_CTL3,                     0x20 },
  52         { CS42L42_RSENSE_CTL1,                  0x40 },
  53         { CS42L42_RSENSE_CTL2,                  0x00 },
  54         { CS42L42_OSC_SWITCH,                   0x00 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_HSDET_CTL1,                   0x77 },
  59         { CS42L42_HSDET_CTL2,                   0x00 },
  60         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  61         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  62         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  63         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  64         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  65         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  66         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  67         { CS42L42_FSYNC_P_UPPER,                0x00 },
  68         { CS42L42_ASP_CLK_CFG,                  0x00 },
  69         { CS42L42_ASP_FRM_CFG,                  0x10 },
  70         { CS42L42_FS_RATE_EN,                   0x00 },
  71         { CS42L42_IN_ASRC_CLK,                  0x00 },
  72         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  73         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  74         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  75         { CS42L42_MIXER_INT_MASK,               0x0F },
  76         { CS42L42_SRC_INT_MASK,                 0x0F },
  77         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  78         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  79         { CS42L42_CODEC_INT_MASK,               0x03 },
  80         { CS42L42_SRCPL_INT_MASK,               0x7F },
  81         { CS42L42_VPMON_INT_MASK,               0x01 },
  82         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  83         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  84         { CS42L42_PLL_CTL1,                     0x00 },
  85         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  86         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  87         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  88         { CS42L42_PLL_DIV_INT,                  0x40 },
  89         { CS42L42_PLL_CTL3,                     0x10 },
  90         { CS42L42_PLL_CAL_RATIO,                0x80 },
  91         { CS42L42_PLL_CTL4,                     0x03 },
  92         { CS42L42_LOAD_DET_EN,                  0x00 },
  93         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
  94         { CS42L42_WAKE_CTL,                     0xC0 },
  95         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
  96         { CS42L42_TIPSENSE_CTL,                 0x02 },
  97         { CS42L42_MISC_DET_CTL,                 0x03 },
  98         { CS42L42_MIC_DET_CTL1,                 0x1F },
  99         { CS42L42_MIC_DET_CTL2,                 0x2F },
 100         { CS42L42_DET_INT1_MASK,                0xE0 },
 101         { CS42L42_DET_INT2_MASK,                0xFF },
 102         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 103         { CS42L42_ADC_CTL,                      0x00 },
 104         { CS42L42_ADC_VOLUME,                   0x00 },
 105         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 106         { CS42L42_DAC_CTL1,                     0x00 },
 107         { CS42L42_DAC_CTL2,                     0x02 },
 108         { CS42L42_HP_CTL,                       0x0D },
 109         { CS42L42_CLASSH_CTL,                   0x07 },
 110         { CS42L42_MIXER_CHA_VOL,                0x3F },
 111         { CS42L42_MIXER_ADC_VOL,                0x3F },
 112         { CS42L42_MIXER_CHB_VOL,                0x3F },
 113         { CS42L42_EQ_COEF_IN0,                  0x00 },
 114         { CS42L42_EQ_COEF_IN1,                  0x00 },
 115         { CS42L42_EQ_COEF_IN2,                  0x00 },
 116         { CS42L42_EQ_COEF_IN3,                  0x00 },
 117         { CS42L42_EQ_COEF_RW,                   0x00 },
 118         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 119         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 120         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 121         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 122         { CS42L42_EQ_INIT_STAT,                 0x00 },
 123         { CS42L42_EQ_START_FILT,                0x00 },
 124         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 125         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 126         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 127         { CS42L42_SP_RX_FS,                     0x8C },
 128         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 129         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 130         { CS42L42_SP_TX_FS,                     0xCC },
 131         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 132         { CS42L42_SRC_SDIN_FS,                  0x40 },
 133         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 134         { CS42L42_SPDIF_CTL1,                   0x01 },
 135         { CS42L42_SPDIF_CTL2,                   0x00 },
 136         { CS42L42_SPDIF_CTL3,                   0x00 },
 137         { CS42L42_SPDIF_CTL4,                   0x42 },
 138         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 139         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 140         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 141         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 142         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 143         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 144         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 145         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 146         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 147         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 148         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 149         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 150         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 151         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 152         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 153         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 154         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 155         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 156         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 157         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 158         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 159         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 160         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 161         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 162         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 163         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 164         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 165 };
 166
 167 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 168 {
 169         switch (reg) {
 170         case CS42L42_PAGE_REGISTER:
 171         case CS42L42_DEVID_AB:
 172         case CS42L42_DEVID_CD:
 173         case CS42L42_DEVID_E:
 174         case CS42L42_FABID:
 175         case CS42L42_REVID:
 176         case CS42L42_FRZ_CTL:
 177         case CS42L42_SRC_CTL:
 178         case CS42L42_MCLK_STATUS:
 179         case CS42L42_MCLK_CTL:
 180         case CS42L42_SFTRAMP_RATE:
 181         case CS42L42_SLOW_START_ENABLE:
 182         case CS42L42_I2C_DEBOUNCE:
 183         case CS42L42_I2C_STRETCH:
 184         case CS42L42_I2C_TIMEOUT:
 185         case CS42L42_PWR_CTL1:
 186         case CS42L42_PWR_CTL2:
 187         case CS42L42_PWR_CTL3:
 188         case CS42L42_RSENSE_CTL1:
 189         case CS42L42_RSENSE_CTL2:
 190         case CS42L42_OSC_SWITCH:
 191         case CS42L42_OSC_SWITCH_STATUS:
 192         case CS42L42_RSENSE_CTL3:
 193         case CS42L42_TSENSE_CTL:
 194         case CS42L42_TSRS_INT_DISABLE:
 195         case CS42L42_TRSENSE_STATUS:
 196         case CS42L42_HSDET_CTL1:
 197         case CS42L42_HSDET_CTL2:
 198         case CS42L42_HS_SWITCH_CTL:
 199         case CS42L42_HS_DET_STATUS:
 200         case CS42L42_HS_CLAMP_DISABLE:
 201         case CS42L42_MCLK_SRC_SEL:
 202         case CS42L42_SPDIF_CLK_CFG:
 203         case CS42L42_FSYNC_PW_LOWER:
 204         case CS42L42_FSYNC_PW_UPPER:
 205         case CS42L42_FSYNC_P_LOWER:
 206         case CS42L42_FSYNC_P_UPPER:
 207         case CS42L42_ASP_CLK_CFG:
 208         case CS42L42_ASP_FRM_CFG:
 209         case CS42L42_FS_RATE_EN:
 210         case CS42L42_IN_ASRC_CLK:
 211         case CS42L42_OUT_ASRC_CLK:
 212         case CS42L42_PLL_DIV_CFG1:
 213         case CS42L42_ADC_OVFL_STATUS:
 214         case CS42L42_MIXER_STATUS:
 215         case CS42L42_SRC_STATUS:
 216         case CS42L42_ASP_RX_STATUS:
 217         case CS42L42_ASP_TX_STATUS:
 218         case CS42L42_CODEC_STATUS:
 219         case CS42L42_DET_INT_STATUS1:
 220         case CS42L42_DET_INT_STATUS2:
 221         case CS42L42_SRCPL_INT_STATUS:
 222         case CS42L42_VPMON_STATUS:
 223         case CS42L42_PLL_LOCK_STATUS:
 224         case CS42L42_TSRS_PLUG_STATUS:
 225         case CS42L42_ADC_OVFL_INT_MASK:
 226         case CS42L42_MIXER_INT_MASK:
 227         case CS42L42_SRC_INT_MASK:
 228         case CS42L42_ASP_RX_INT_MASK:
 229         case CS42L42_ASP_TX_INT_MASK:
 230         case CS42L42_CODEC_INT_MASK:
 231         case CS42L42_SRCPL_INT_MASK:
 232         case CS42L42_VPMON_INT_MASK:
 233         case CS42L42_PLL_LOCK_INT_MASK:
 234         case CS42L42_TSRS_PLUG_INT_MASK:
 235         case CS42L42_PLL_CTL1:
 236         case CS42L42_PLL_DIV_FRAC0:
 237         case CS42L42_PLL_DIV_FRAC1:
 238         case CS42L42_PLL_DIV_FRAC2:
 239         case CS42L42_PLL_DIV_INT:
 240         case CS42L42_PLL_CTL3:
 241         case CS42L42_PLL_CAL_RATIO:
 242         case CS42L42_PLL_CTL4:
 243         case CS42L42_LOAD_DET_RCSTAT:
 244         case CS42L42_LOAD_DET_DONE:
 245         case CS42L42_LOAD_DET_EN:
 246         case CS42L42_HSBIAS_SC_AUTOCTL:
 247         case CS42L42_WAKE_CTL:
 248         case CS42L42_ADC_DISABLE_MUTE:
 249         case CS42L42_TIPSENSE_CTL:
 250         case CS42L42_MISC_DET_CTL:
 251         case CS42L42_MIC_DET_CTL1:
 252         case CS42L42_MIC_DET_CTL2:
 253         case CS42L42_DET_STATUS1:
 254         case CS42L42_DET_STATUS2:
 255         case CS42L42_DET_INT1_MASK:
 256         case CS42L42_DET_INT2_MASK:
 257         case CS42L42_HS_BIAS_CTL:
 258         case CS42L42_ADC_CTL:
 259         case CS42L42_ADC_VOLUME:
 260         case CS42L42_ADC_WNF_HPF_CTL:
 261         case CS42L42_DAC_CTL1:
 262         case CS42L42_DAC_CTL2:
 263         case CS42L42_HP_CTL:
 264         case CS42L42_CLASSH_CTL:
 265         case CS42L42_MIXER_CHA_VOL:
 266         case CS42L42_MIXER_ADC_VOL:
 267         case CS42L42_MIXER_CHB_VOL:
 268         case CS42L42_EQ_COEF_IN0:
 269         case CS42L42_EQ_COEF_IN1:
 270         case CS42L42_EQ_COEF_IN2:
 271         case CS42L42_EQ_COEF_IN3:
 272         case CS42L42_EQ_COEF_RW:
 273         case CS42L42_EQ_COEF_OUT0:
 274         case CS42L42_EQ_COEF_OUT1:
 275         case CS42L42_EQ_COEF_OUT2:
 276         case CS42L42_EQ_COEF_OUT3:
 277         case CS42L42_EQ_INIT_STAT:
 278         case CS42L42_EQ_START_FILT:
 279         case CS42L42_EQ_MUTE_CTL:
 280         case CS42L42_SP_RX_CH_SEL:
 281         case CS42L42_SP_RX_ISOC_CTL:
 282         case CS42L42_SP_RX_FS:
 283         case CS42l42_SPDIF_CH_SEL:
 284         case CS42L42_SP_TX_ISOC_CTL:
 285         case CS42L42_SP_TX_FS:
 286         case CS42L42_SPDIF_SW_CTL1:
 287         case CS42L42_SRC_SDIN_FS:
 288         case CS42L42_SRC_SDOUT_FS:
 289         case CS42L42_SPDIF_CTL1:
 290         case CS42L42_SPDIF_CTL2:
 291         case CS42L42_SPDIF_CTL3:
 292         case CS42L42_SPDIF_CTL4:
 293         case CS42L42_ASP_TX_SZ_EN:
 294         case CS42L42_ASP_TX_CH_EN:
 295         case CS42L42_ASP_TX_CH_AP_RES:
 296         case CS42L42_ASP_TX_CH1_BIT_MSB:
 297         case CS42L42_ASP_TX_CH1_BIT_LSB:
 298         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 299         case CS42L42_ASP_TX_CH2_BIT_MSB:
 300         case CS42L42_ASP_TX_CH2_BIT_LSB:
 301         case CS42L42_ASP_RX_DAI0_EN:
 302         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 303         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 304         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 305         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 306         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 307         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 308         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 309         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 310         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 311         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 312         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 313         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 314         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 315         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 316         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 317         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 318         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 319         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 320         case CS42L42_SUB_REVID:
 321                 return true;
 322         default:
 323                 return false;
 324         }
 325 }
 326
 327 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 328 {
 329         switch (reg) {
 330         case CS42L42_DEVID_AB:
 331         case CS42L42_DEVID_CD:
 332         case CS42L42_DEVID_E:
 333         case CS42L42_MCLK_STATUS:
 334         case CS42L42_OSC_SWITCH_STATUS:
 335         case CS42L42_TRSENSE_STATUS:
 336         case CS42L42_HS_DET_STATUS:
 337         case CS42L42_ADC_OVFL_STATUS:
 338         case CS42L42_MIXER_STATUS:
 339         case CS42L42_SRC_STATUS:
 340         case CS42L42_ASP_RX_STATUS:
 341         case CS42L42_ASP_TX_STATUS:
 342         case CS42L42_CODEC_STATUS:
 343         case CS42L42_DET_INT_STATUS1:
 344         case CS42L42_DET_INT_STATUS2:
 345         case CS42L42_SRCPL_INT_STATUS:
 346         case CS42L42_VPMON_STATUS:
 347         case CS42L42_PLL_LOCK_STATUS:
 348         case CS42L42_TSRS_PLUG_STATUS:
 349         case CS42L42_LOAD_DET_RCSTAT:
 350         case CS42L42_LOAD_DET_DONE:
 351         case CS42L42_DET_STATUS1:
 352         case CS42L42_DET_STATUS2:
 353                 return true;
 354         default:
 355                 return false;
 356         }
 357 }
 358
 359 static const struct regmap_range_cfg cs42l42_page_range = {
 360         .name = "Pages",
 361         .range_min = 0,
 362         .range_max = CS42L42_MAX_REGISTER,
 363         .selector_reg = CS42L42_PAGE_REGISTER,
 364         .selector_mask = 0xff,
 365         .selector_shift = 0,
 366         .window_start = 0,
 367         .window_len = 256,
 368 };
 369
 370 static const struct regmap_config cs42l42_regmap = {
 371         .reg_bits = 8,
 372         .val_bits = 8,
 373
 374         .readable_reg = cs42l42_readable_register,
 375         .volatile_reg = cs42l42_volatile_register,
 376
 377         .ranges = &cs42l42_page_range,
 378         .num_ranges = 1,
 379
 380         .max_register = CS42L42_MAX_REGISTER,
 381         .reg_defaults = cs42l42_reg_defaults,
 382         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 383         .cache_type = REGCACHE_RBTREE,
 384
 385         .use_single_read = true,
 386         .use_single_write = true,
 387 };
 388
 389 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 390 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 391
 392 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 393                                   struct snd_ctl_elem_value *ucontrol)
 394 {
 395         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 396         u8 val;
 397
 398         /* all bits of SLOW_START_EN much change together */
 399         switch (ucontrol->value.integer.value[0]) {
 400         case 0:
 401                 val = 0;
 402                 break;
 403         case 1:
 404                 val = CS42L42_SLOW_START_EN_MASK;
 405                 break;
 406         default:
 407                 return -EINVAL;
 408         }
 409
 410         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 411                                              CS42L42_SLOW_START_EN_MASK, val);
 412 }
 413
 414 static const char * const cs42l42_hpf_freq_text[] = {
 415         "1.86Hz", "120Hz", "235Hz", "466Hz"
 416 };
 417
 418 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 419                             CS42L42_ADC_HPF_CF_SHIFT,
 420                             cs42l42_hpf_freq_text);
 421
 422 static const char * const cs42l42_wnf3_freq_text[] = {
 423         "160Hz", "180Hz", "200Hz", "220Hz",
 424         "240Hz", "260Hz", "280Hz", "300Hz"
 425 };
 426
 427 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 428                             CS42L42_ADC_WNF_CF_SHIFT,
 429                             cs42l42_wnf3_freq_text);
 430
 431 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 432         /* ADC Volume and Filter Controls */
 433         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 434                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 435         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 436                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 437         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 438                                 CS42L42_ADC_INV_SHIFT, true, false),
 439         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 440                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 441         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 442         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 443                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 444         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 446         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 447         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 448
 449         /* DAC Volume and Filter Controls */
 450         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 451                                 CS42L42_DACA_INV_SHIFT, true, false),
 452         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 453                                 CS42L42_DACB_INV_SHIFT, true, false),
 454         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 455                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 456         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 457                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 458                                 0x3f, 1, mixer_tlv),
 459
 460         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 461                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 462                         snd_soc_get_volsw, cs42l42_slow_start_put),
 463 };
 464
 465 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 466                              struct snd_kcontrol *kcontrol, int event)
 467 {
 468         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 469         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 470
 471         switch (event) {
 472         case SND_SOC_DAPM_PRE_PMU:
 473                 cs42l42->hp_adc_up_pending = true;
 474                 break;
 475         case SND_SOC_DAPM_POST_PMU:
 476                 /* Only need one delay if HP and ADC are both powering-up */
 477                 if (cs42l42->hp_adc_up_pending) {
 478                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 479                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 480                         cs42l42->hp_adc_up_pending = false;
 481                 }
 482                 break;
 483         default:
 484                 break;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 491         /* Playback Path */
 492         SND_SOC_DAPM_OUTPUT("HP"),
 493         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 494                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 495         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 496         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 497         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 498
 499         /* Playback Requirements */
 500         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 501
 502         /* Capture Path */
 503         SND_SOC_DAPM_INPUT("HS"),
 504         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 507         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 508
 509         /* Capture Requirements */
 510         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 511         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 512
 513         /* Playback/Capture Requirements */
 514         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 515 };
 516
 517 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 518         /* Playback Path */
 519         {"HP", NULL, "DAC"},
 520         {"DAC", NULL, "MIXER"},
 521         {"MIXER", NULL, "SDIN1"},
 522         {"MIXER", NULL, "SDIN2"},
 523         {"SDIN1", NULL, "Playback"},
 524         {"SDIN2", NULL, "Playback"},
 525
 526         /* Playback Requirements */
 527         {"SDIN1", NULL, "ASP DAI0"},
 528         {"SDIN2", NULL, "ASP DAI0"},
 529         {"SDIN1", NULL, "SCLK"},
 530         {"SDIN2", NULL, "SCLK"},
 531
 532         /* Capture Path */
 533         {"ADC", NULL, "HS"},
 534         { "SDOUT1", NULL, "ADC" },
 535         { "SDOUT2", NULL, "ADC" },
 536         { "Capture", NULL, "SDOUT1" },
 537         { "Capture", NULL, "SDOUT2" },
 538
 539         /* Capture Requirements */
 540         { "SDOUT1", NULL, "ASP DAO0" },
 541         { "SDOUT2", NULL, "ASP DAO0" },
 542         { "SDOUT1", NULL, "SCLK" },
 543         { "SDOUT2", NULL, "SCLK" },
 544         { "SDOUT1", NULL, "ASP TX EN" },
 545         { "SDOUT2", NULL, "ASP TX EN" },
 546 };
 547
 548 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 549 {
 550         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 551
 552         /* Prevent race with interrupt handler */
 553         mutex_lock(&cs42l42->irq_lock);
 554         cs42l42->jack = jk;
 555
 556         if (jk) {
 557                 switch (cs42l42->hs_type) {
 558                 case CS42L42_PLUG_CTIA:
 559                 case CS42L42_PLUG_OMTP:
 560                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
 561                         break;
 562                 case CS42L42_PLUG_HEADPHONE:
 563                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
 564                         break;
 565                 default:
 566                         break;
 567                 }
 568         }
 569         mutex_unlock(&cs42l42->irq_lock);
 570
 571         return 0;
 572 }
 573
 574 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 575         .set_jack               = cs42l42_set_jack,
 576         .dapm_widgets           = cs42l42_dapm_widgets,
 577         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 578         .dapm_routes            = cs42l42_audio_map,
 579         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 580         .controls               = cs42l42_snd_controls,
 581         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 582         .idle_bias_on           = 1,
 583         .endianness             = 1,
 584         .non_legacy_dai_naming  = 1,
 585 };
 586
 587 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 588 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 589         {
 590                 .reg = CS42L42_OSC_SWITCH,
 591                 .def = CS42L42_SCLK_PRESENT_MASK,
 592                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 593         },
 594 };
 595
 596 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 597 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 598         {
 599                 .reg = CS42L42_OSC_SWITCH,
 600                 .def = 0,
 601                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 602         },
 603 };
 604
 605 struct cs42l42_pll_params {
 606         u32 sclk;
 607         u8 mclk_src_sel;
 608         u8 sclk_prediv;
 609         u8 pll_div_int;
 610         u32 pll_div_frac;
 611         u8 pll_mode;
 612         u8 pll_divout;
 613         u32 mclk_int;
 614         u8 pll_cal_ratio;
 615         u8 n;
 616 };
 617
 618 /*
 619  * Common PLL Settings for given SCLK
 620  * Table 4-5 from the Datasheet
 621  */
 622 static const struct cs42l42_pll_params pll_ratio_table[] = {
 623         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 624         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 625         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 626         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 627         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 628         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 629         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 630         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 631         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 632         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 633         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 634         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 635         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 636         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 637         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 638         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 639         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 640         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 641 };
 642
 643 static int cs42l42_pll_config(struct snd_soc_component *component)
 644 {
 645         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 646         int i;
 647         u32 clk;
 648         u32 fsync;
 649
 650         if (!cs42l42->sclk)
 651                 clk = cs42l42->bclk;
 652         else
 653                 clk = cs42l42->sclk;
 654
 655         /* Don't reconfigure if there is an audio stream running */
 656         if (cs42l42->stream_use) {
 657                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 658                         return 0;
 659                 else
 660                         return -EBUSY;
 661         }
 662
 663         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 664                 if (pll_ratio_table[i].sclk == clk) {
 665                         cs42l42->pll_config = i;
 666
 667                         /* Configure the internal sample rate */
 668                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 669                                         CS42L42_INTERNAL_FS_MASK,
 670                                         ((pll_ratio_table[i].mclk_int !=
 671                                         12000000) &&
 672                                         (pll_ratio_table[i].mclk_int !=
 673                                         24000000)) <<
 674                                         CS42L42_INTERNAL_FS_SHIFT);
 675
 676                         /* Set up the LRCLK */
 677                         fsync = clk / cs42l42->srate;
 678                         if (((fsync * cs42l42->srate) != clk)
 679                                 || ((fsync % 2) != 0)) {
 680                                 dev_err(component->dev,
 681                                         "Unsupported sclk %d/sample rate %d\n",
 682                                         clk,
 683                                         cs42l42->srate);
 684                                 return -EINVAL;
 685                         }
 686                         /* Set the LRCLK period */
 687                         snd_soc_component_update_bits(component,
 688                                         CS42L42_FSYNC_P_LOWER,
 689                                         CS42L42_FSYNC_PERIOD_MASK,
 690                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 691                                         CS42L42_FSYNC_PERIOD_SHIFT);
 692                         snd_soc_component_update_bits(component,
 693                                         CS42L42_FSYNC_P_UPPER,
 694                                         CS42L42_FSYNC_PERIOD_MASK,
 695                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 696                                         CS42L42_FSYNC_PERIOD_SHIFT);
 697                         /* Set the LRCLK to 50% duty cycle */
 698                         fsync = fsync / 2;
 699                         snd_soc_component_update_bits(component,
 700                                         CS42L42_FSYNC_PW_LOWER,
 701                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 702                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 703                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 704                         snd_soc_component_update_bits(component,
 705                                         CS42L42_FSYNC_PW_UPPER,
 706                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 707                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 708                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 709                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 710                                 /* Pass the clock straight through */
 711                                 snd_soc_component_update_bits(component,
 712                                         CS42L42_PLL_CTL1,
 713                                         CS42L42_PLL_START_MASK, 0);
 714                         } else {
 715                                 /* Configure PLL per table 4-5 */
 716                                 snd_soc_component_update_bits(component,
 717                                         CS42L42_PLL_DIV_CFG1,
 718                                         CS42L42_SCLK_PREDIV_MASK,
 719                                         pll_ratio_table[i].sclk_prediv
 720                                         << CS42L42_SCLK_PREDIV_SHIFT);
 721                                 snd_soc_component_update_bits(component,
 722                                         CS42L42_PLL_DIV_INT,
 723                                         CS42L42_PLL_DIV_INT_MASK,
 724                                         pll_ratio_table[i].pll_div_int
 725                                         << CS42L42_PLL_DIV_INT_SHIFT);
 726                                 snd_soc_component_update_bits(component,
 727                                         CS42L42_PLL_DIV_FRAC0,
 728                                         CS42L42_PLL_DIV_FRAC_MASK,
 729                                         CS42L42_FRAC0_VAL(
 730                                         pll_ratio_table[i].pll_div_frac)
 731                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 732                                 snd_soc_component_update_bits(component,
 733                                         CS42L42_PLL_DIV_FRAC1,
 734                                         CS42L42_PLL_DIV_FRAC_MASK,
 735                                         CS42L42_FRAC1_VAL(
 736                                         pll_ratio_table[i].pll_div_frac)
 737                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 738                                 snd_soc_component_update_bits(component,
 739                                         CS42L42_PLL_DIV_FRAC2,
 740                                         CS42L42_PLL_DIV_FRAC_MASK,
 741                                         CS42L42_FRAC2_VAL(
 742                                         pll_ratio_table[i].pll_div_frac)
 743                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 744                                 snd_soc_component_update_bits(component,
 745                                         CS42L42_PLL_CTL4,
 746                                         CS42L42_PLL_MODE_MASK,
 747                                         pll_ratio_table[i].pll_mode
 748                                         << CS42L42_PLL_MODE_SHIFT);
 749                                 snd_soc_component_update_bits(component,
 750                                         CS42L42_PLL_CTL3,
 751                                         CS42L42_PLL_DIVOUT_MASK,
 752                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 753                                         << CS42L42_PLL_DIVOUT_SHIFT);
 754                                 snd_soc_component_update_bits(component,
 755                                         CS42L42_PLL_CAL_RATIO,
 756                                         CS42L42_PLL_CAL_RATIO_MASK,
 757                                         pll_ratio_table[i].pll_cal_ratio
 758                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 759                         }
 760                         return 0;
 761                 }
 762         }
 763
 764         return -EINVAL;
 765 }
 766
 767 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 768 {
 769         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 770         unsigned int fs;
 771
 772         /* Don't reconfigure if there is an audio stream running */
 773         if (cs42l42->stream_use)
 774                 return;
 775
 776         /* SRC MCLK must be as close as possible to 125 * sample rate */
 777         if (sample_rate <= 48000)
 778                 fs = CS42L42_CLK_IASRC_SEL_6;
 779         else
 780                 fs = CS42L42_CLK_IASRC_SEL_12;
 781
 782         /* Set the sample rates (96k or lower) */
 783         snd_soc_component_update_bits(component,
 784                                       CS42L42_FS_RATE_EN,
 785                                       CS42L42_FS_EN_MASK,
 786                                       (CS42L42_FS_EN_IASRC_96K |
 787                                        CS42L42_FS_EN_OASRC_96K) <<
 788                                       CS42L42_FS_EN_SHIFT);
 789
 790         snd_soc_component_update_bits(component,
 791                                       CS42L42_IN_ASRC_CLK,
 792                                       CS42L42_CLK_IASRC_SEL_MASK,
 793                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 794         snd_soc_component_update_bits(component,
 795                                       CS42L42_OUT_ASRC_CLK,
 796                                       CS42L42_CLK_OASRC_SEL_MASK,
 797                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 798 }
 799
 800 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 801 {
 802         struct snd_soc_component *component = codec_dai->component;
 803         u32 asp_cfg_val = 0;
 804
 805         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 806         case SND_SOC_DAIFMT_CBS_CFM:
 807                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 808                                 CS42L42_ASP_MODE_SHIFT;
 809                 break;
 810         case SND_SOC_DAIFMT_CBS_CFS:
 811                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 812                                 CS42L42_ASP_MODE_SHIFT;
 813                 break;
 814         default:
 815                 return -EINVAL;
 816         }
 817
 818         /* interface format */
 819         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 820         case SND_SOC_DAIFMT_I2S:
 821                 /*
 822                  * 5050 mode, frame starts on falling edge of LRCLK,
 823                  * frame delayed by 1.0 SCLKs
 824                  */
 825                 snd_soc_component_update_bits(component,
 826                                               CS42L42_ASP_FRM_CFG,
 827                                               CS42L42_ASP_STP_MASK |
 828                                               CS42L42_ASP_5050_MASK |
 829                                               CS42L42_ASP_FSD_MASK,
 830                                               CS42L42_ASP_5050_MASK |
 831                                               (CS42L42_ASP_FSD_1_0 <<
 832                                                 CS42L42_ASP_FSD_SHIFT));
 833                 break;
 834         default:
 835                 return -EINVAL;
 836         }
 837
 838         /* Bitclock/frame inversion */
 839         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 840         case SND_SOC_DAIFMT_NB_NF:
 841                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 842                 break;
 843         case SND_SOC_DAIFMT_NB_IF:
 844                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 845                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 846                 break;
 847         case SND_SOC_DAIFMT_IB_NF:
 848                 break;
 849         case SND_SOC_DAIFMT_IB_IF:
 850                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 851                 break;
 852         }
 853
 854         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 855                                                                       CS42L42_ASP_SCPOL_MASK |
 856                                                                       CS42L42_ASP_LCPOL_MASK,
 857                                                                       asp_cfg_val);
 858
 859         return 0;
 860 }
 861
 862 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 863 {
 864         struct snd_soc_component *component = dai->component;
 865         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 866
 867         /*
 868          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 869          * a standard I2S frame. If the machine driver sets SCLK it must be
 870          * legal.
 871          */
 872         if (cs42l42->sclk)
 873                 return 0;
 874
 875         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 876         return snd_pcm_hw_constraint_minmax(substream->runtime,
 877                                             SNDRV_PCM_HW_PARAM_RATE,
 878                                             44100, 96000);
 879 }
 880
 881 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 882                                 struct snd_pcm_hw_params *params,
 883                                 struct snd_soc_dai *dai)
 884 {
 885         struct snd_soc_component *component = dai->component;
 886         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 887         unsigned int channels = params_channels(params);
 888         unsigned int width = (params_width(params) / 8) - 1;
 889         unsigned int val = 0;
 890         int ret;
 891
 892         cs42l42->srate = params_rate(params);
 893         cs42l42->bclk = snd_soc_params_to_bclk(params);
 894
 895         /* I2S frame always has 2 channels even for mono audio */
 896         if (channels == 1)
 897                 cs42l42->bclk *= 2;
 898
 899         /*
 900          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 901          * more than assumed (which would result in overclocking).
 902          */
 903         if (params_width(params) == 24)
 904                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 905
 906         switch (substream->stream) {
 907         case SNDRV_PCM_STREAM_CAPTURE:
 908                 /* channel 2 on high LRCLK */
 909                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 910                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 911                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 912
 913                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 914                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 915                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 916                 break;
 917         case SNDRV_PCM_STREAM_PLAYBACK:
 918                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 919                 /* channel 1 on low LRCLK */
 920                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 921                                                          CS42L42_ASP_RX_CH_AP_MASK |
 922                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 923                 /* Channel 2 on high LRCLK */
 924                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 925                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 926                                                          CS42L42_ASP_RX_CH_AP_MASK |
 927                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 928
 929                 /* Channel B comes from the last active channel */
 930                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 931                                               CS42L42_SP_RX_CHB_SEL_MASK,
 932                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 933
 934                 /* Both LRCLK slots must be enabled */
 935                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 936                                               CS42L42_ASP_RX0_CH_EN_MASK,
 937                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 938                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 939                 break;
 940         default:
 941                 break;
 942         }
 943
 944         ret = cs42l42_pll_config(component);
 945         if (ret)
 946                 return ret;
 947
 948         cs42l42_src_config(component, params_rate(params));
 949
 950         return 0;
 951 }
 952
 953 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 954                                 int clk_id, unsigned int freq, int dir)
 955 {
 956         struct snd_soc_component *component = dai->component;
 957         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 958         int i;
 959
 960         if (freq == 0) {
 961                 cs42l42->sclk = 0;
 962                 return 0;
 963         }
 964
 965         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 966                 if (pll_ratio_table[i].sclk == freq) {
 967                         cs42l42->sclk = freq;
 968                         return 0;
 969                 }
 970         }
 971
 972         dev_err(component->dev, "SCLK %u not supported\n", freq);
 973
 974         return -EINVAL;
 975 }
 976
 977 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 978 {
 979         struct snd_soc_component *component = dai->component;
 980         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 981         unsigned int regval;
 982         int ret;
 983
 984         if (mute) {
 985                 /* Mute the headphone */
 986                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 987                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 988                                                       CS42L42_HP_ANA_AMUTE_MASK |
 989                                                       CS42L42_HP_ANA_BMUTE_MASK,
 990                                                       CS42L42_HP_ANA_AMUTE_MASK |
 991                                                       CS42L42_HP_ANA_BMUTE_MASK);
 992
 993                 cs42l42->stream_use &= ~(1 << stream);
 994                 if (!cs42l42->stream_use) {
 995                         /*
 996                          * Switch to the internal oscillator.
 997                          * SCLK must remain running until after this clock switch.
 998                          * Without a source of clock the I2C bus doesn't work.
 999                          */
1000                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1001                                                ARRAY_SIZE(cs42l42_to_osc_seq));
1002
1003                         /* Must disconnect PLL before stopping it */
1004                         snd_soc_component_update_bits(component,
1005                                                       CS42L42_MCLK_SRC_SEL,
1006                                                       CS42L42_MCLK_SRC_SEL_MASK,
1007                                                       0);
1008                         usleep_range(100, 200);
1009
1010                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1011                                                       CS42L42_PLL_START_MASK, 0);
1012                 }
1013         } else {
1014                 if (!cs42l42->stream_use) {
1015                         /* SCLK must be running before codec unmute.
1016                          *
1017                          * PLL must not be started with ADC and HP both off
1018                          * otherwise the FILT+ supply will not charge properly.
1019                          * DAPM widgets power-up before stream unmute so at least
1020                          * one of the "DAC" or "ADC" widgets will already have
1021                          * powered-up.
1022                          */
1023                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1024                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1025                                                               CS42L42_PLL_START_MASK, 1);
1026
1027                                 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1028                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1029                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1030                                         regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1031                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1032                                                                       CS42L42_PLL_DIVOUT_MASK,
1033                                                                       regval <<
1034                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1035                                 }
1036
1037                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1038                                                                CS42L42_PLL_LOCK_STATUS,
1039                                                                regval,
1040                                                                (regval & 1),
1041                                                                CS42L42_PLL_LOCK_POLL_US,
1042                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1043                                 if (ret < 0)
1044                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1045
1046                                 /* PLL must be running to drive glitchless switch logic */
1047                                 snd_soc_component_update_bits(component,
1048                                                               CS42L42_MCLK_SRC_SEL,
1049                                                               CS42L42_MCLK_SRC_SEL_MASK,
1050                                                               CS42L42_MCLK_SRC_SEL_MASK);
1051                         }
1052
1053                         /* Mark SCLK as present, turn off internal oscillator */
1054                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1055                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1056                 }
1057                 cs42l42->stream_use |= 1 << stream;
1058
1059                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1060                         /* Un-mute the headphone */
1061                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1062                                                       CS42L42_HP_ANA_AMUTE_MASK |
1063                                                       CS42L42_HP_ANA_BMUTE_MASK,
1064                                                       0);
1065                 }
1066         }
1067
1068         return 0;
1069 }
1070
1071 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1072                          SNDRV_PCM_FMTBIT_S24_LE |\
1073                          SNDRV_PCM_FMTBIT_S32_LE)
1074
1075 static const struct snd_soc_dai_ops cs42l42_ops = {
1076         .startup        = cs42l42_dai_startup,
1077         .hw_params      = cs42l42_pcm_hw_params,
1078         .set_fmt        = cs42l42_set_dai_fmt,
1079         .set_sysclk     = cs42l42_set_sysclk,
1080         .mute_stream    = cs42l42_mute_stream,
1081 };
1082
1083 static struct snd_soc_dai_driver cs42l42_dai = {
1084                 .name = "cs42l42",
1085                 .playback = {
1086                         .stream_name = "Playback",
1087                         .channels_min = 1,
1088                         .channels_max = 2,
1089                         .rates = SNDRV_PCM_RATE_8000_96000,
1090                         .formats = CS42L42_FORMATS,
1091                 },
1092                 .capture = {
1093                         .stream_name = "Capture",
1094                         .channels_min = 1,
1095                         .channels_max = 2,
1096                         .rates = SNDRV_PCM_RATE_8000_96000,
1097                         .formats = CS42L42_FORMATS,
1098                 },
1099                 .symmetric_rate = 1,
1100                 .symmetric_sample_bits = 1,
1101                 .ops = &cs42l42_ops,
1102 };
1103
1104 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1105 {
1106         unsigned int hs_det_status;
1107         unsigned int hs_det_comp1;
1108         unsigned int hs_det_comp2;
1109         unsigned int hs_det_sw;
1110
1111         /* Set hs detect to manual, active mode */
1112         regmap_update_bits(cs42l42->regmap,
1113                 CS42L42_HSDET_CTL2,
1114                 CS42L42_HSDET_CTRL_MASK |
1115                 CS42L42_HSDET_SET_MASK |
1116                 CS42L42_HSBIAS_REF_MASK |
1117                 CS42L42_HSDET_AUTO_TIME_MASK,
1118                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1119                 (0 << CS42L42_HSDET_SET_SHIFT) |
1120                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1121                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1122
1123         /* Configure HS DET comparator reference levels. */
1124         regmap_update_bits(cs42l42->regmap,
1125                                 CS42L42_HSDET_CTL1,
1126                                 CS42L42_HSDET_COMP1_LVL_MASK |
1127                                 CS42L42_HSDET_COMP2_LVL_MASK,
1128                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1129                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1130
1131         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1132         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1133
1134         msleep(100);
1135
1136         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1137
1138         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1139                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1140         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1141                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1142
1143         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1144         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1145
1146         msleep(100);
1147
1148         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1149
1150         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1151                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1152         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1153                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1154
1155         /* Use Comparator 1 with 1.25V Threshold. */
1156         switch (hs_det_comp1) {
1157         case CS42L42_HSDET_COMP_TYPE1:
1158                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1159                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1160                 break;
1161         case CS42L42_HSDET_COMP_TYPE2:
1162                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1163                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1164                 break;
1165         default:
1166                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1167                 switch (hs_det_comp2) {
1168                 case CS42L42_HSDET_COMP_TYPE1:
1169                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1170                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1171                         break;
1172                 case CS42L42_HSDET_COMP_TYPE2:
1173                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1174                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1175                         break;
1176                 case CS42L42_HSDET_COMP_TYPE3:
1177                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1178                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1179                         break;
1180                 default:
1181                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1182                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1183                         break;
1184                 }
1185         }
1186
1187         /* Set Switches */
1188         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1189
1190         /* Set HSDET mode to Manual—Disabled */
1191         regmap_update_bits(cs42l42->regmap,
1192                 CS42L42_HSDET_CTL2,
1193                 CS42L42_HSDET_CTRL_MASK |
1194                 CS42L42_HSDET_SET_MASK |
1195                 CS42L42_HSBIAS_REF_MASK |
1196                 CS42L42_HSDET_AUTO_TIME_MASK,
1197                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1198                 (0 << CS42L42_HSDET_SET_SHIFT) |
1199                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1200                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1201
1202         /* Configure HS DET comparator reference levels. */
1203         regmap_update_bits(cs42l42->regmap,
1204                                 CS42L42_HSDET_CTL1,
1205                                 CS42L42_HSDET_COMP1_LVL_MASK |
1206                                 CS42L42_HSDET_COMP2_LVL_MASK,
1207                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1208                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1209 }
1210
1211 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1212 {
1213         unsigned int hs_det_status;
1214         unsigned int int_status;
1215
1216         /* Read and save the hs detection result */
1217         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1218
1219         /* Mask the auto detect interrupt */
1220         regmap_update_bits(cs42l42->regmap,
1221                 CS42L42_CODEC_INT_MASK,
1222                 CS42L42_PDN_DONE_MASK |
1223                 CS42L42_HSDET_AUTO_DONE_MASK,
1224                 (1 << CS42L42_PDN_DONE_SHIFT) |
1225                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1226
1227
1228         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1229                                 CS42L42_HSDET_TYPE_SHIFT;
1230
1231         /* Set hs detect to automatic, disabled mode */
1232         regmap_update_bits(cs42l42->regmap,
1233                 CS42L42_HSDET_CTL2,
1234                 CS42L42_HSDET_CTRL_MASK |
1235                 CS42L42_HSDET_SET_MASK |
1236                 CS42L42_HSBIAS_REF_MASK |
1237                 CS42L42_HSDET_AUTO_TIME_MASK,
1238                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1239                 (2 << CS42L42_HSDET_SET_SHIFT) |
1240                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1241                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1242
1243         /* Run Manual detection if auto detect has not found a headset.
1244          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1245          * to ensure that a headset mic is detected in all cases.
1246          */
1247         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1248                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1249                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1250                 cs42l42_manual_hs_type_detect(cs42l42);
1251         }
1252
1253         /* Set up button detection */
1254         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1255               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1256                 /* Set auto HS bias settings to default */
1257                 regmap_update_bits(cs42l42->regmap,
1258                         CS42L42_HSBIAS_SC_AUTOCTL,
1259                         CS42L42_HSBIAS_SENSE_EN_MASK |
1260                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1261                         CS42L42_TIP_SENSE_EN_MASK |
1262                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1263                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1264                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1265                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1266                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1267
1268                 /* Set up hs detect level sensitivity */
1269                 regmap_update_bits(cs42l42->regmap,
1270                         CS42L42_MIC_DET_CTL1,
1271                         CS42L42_LATCH_TO_VP_MASK |
1272                         CS42L42_EVENT_STAT_SEL_MASK |
1273                         CS42L42_HS_DET_LEVEL_MASK,
1274                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1275                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1276                         (cs42l42->bias_thresholds[0] <<
1277                         CS42L42_HS_DET_LEVEL_SHIFT));
1278
1279                 /* Set auto HS bias settings to default */
1280                 regmap_update_bits(cs42l42->regmap,
1281                         CS42L42_HSBIAS_SC_AUTOCTL,
1282                         CS42L42_HSBIAS_SENSE_EN_MASK |
1283                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1284                         CS42L42_TIP_SENSE_EN_MASK |
1285                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1286                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1287                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1288                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1289                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1290
1291                 /* Turn on level detect circuitry */
1292                 regmap_update_bits(cs42l42->regmap,
1293                         CS42L42_MISC_DET_CTL,
1294                         CS42L42_HSBIAS_CTL_MASK |
1295                         CS42L42_PDN_MIC_LVL_DET_MASK,
1296                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1297                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1298
1299                 msleep(cs42l42->btn_det_init_dbnce);
1300
1301                 /* Clear any button interrupts before unmasking them */
1302                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1303                             &int_status);
1304
1305                 /* Unmask button detect interrupts */
1306                 regmap_update_bits(cs42l42->regmap,
1307                         CS42L42_DET_INT2_MASK,
1308                         CS42L42_M_DETECT_TF_MASK |
1309                         CS42L42_M_DETECT_FT_MASK |
1310                         CS42L42_M_HSBIAS_HIZ_MASK |
1311                         CS42L42_M_SHORT_RLS_MASK |
1312                         CS42L42_M_SHORT_DET_MASK,
1313                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1314                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1315                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1316                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1317                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1318         } else {
1319                 /* Make sure button detect and HS bias circuits are off */
1320                 regmap_update_bits(cs42l42->regmap,
1321                         CS42L42_MISC_DET_CTL,
1322                         CS42L42_HSBIAS_CTL_MASK |
1323                         CS42L42_PDN_MIC_LVL_DET_MASK,
1324                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1325                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1326         }
1327
1328         regmap_update_bits(cs42l42->regmap,
1329                                 CS42L42_DAC_CTL2,
1330                                 CS42L42_HPOUT_PULLDOWN_MASK |
1331                                 CS42L42_HPOUT_LOAD_MASK |
1332                                 CS42L42_HPOUT_CLAMP_MASK |
1333                                 CS42L42_DAC_HPF_EN_MASK |
1334                                 CS42L42_DAC_MON_EN_MASK,
1335                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1336                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1337                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1338                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1339                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1340
1341         /* Unmask tip sense interrupts */
1342         regmap_update_bits(cs42l42->regmap,
1343                 CS42L42_TSRS_PLUG_INT_MASK,
1344                 CS42L42_TS_PLUG_MASK |
1345                 CS42L42_TS_UNPLUG_MASK,
1346                 (0 << CS42L42_TS_PLUG_SHIFT) |
1347                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1348 }
1349
1350 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1351 {
1352         /* Mask tip sense interrupts */
1353         regmap_update_bits(cs42l42->regmap,
1354                                 CS42L42_TSRS_PLUG_INT_MASK,
1355                                 CS42L42_TS_PLUG_MASK |
1356                                 CS42L42_TS_UNPLUG_MASK,
1357                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1358                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1359
1360         /* Make sure button detect and HS bias circuits are off */
1361         regmap_update_bits(cs42l42->regmap,
1362                                 CS42L42_MISC_DET_CTL,
1363                                 CS42L42_HSBIAS_CTL_MASK |
1364                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1365                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1366                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1367
1368         /* Set auto HS bias settings to default */
1369         regmap_update_bits(cs42l42->regmap,
1370                                 CS42L42_HSBIAS_SC_AUTOCTL,
1371                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1372                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1373                                 CS42L42_TIP_SENSE_EN_MASK |
1374                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1375                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1376                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1377                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1378                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1379
1380         /* Set hs detect to manual, disabled mode */
1381         regmap_update_bits(cs42l42->regmap,
1382                                 CS42L42_HSDET_CTL2,
1383                                 CS42L42_HSDET_CTRL_MASK |
1384                                 CS42L42_HSDET_SET_MASK |
1385                                 CS42L42_HSBIAS_REF_MASK |
1386                                 CS42L42_HSDET_AUTO_TIME_MASK,
1387                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1388                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1389                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1390                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1391
1392         regmap_update_bits(cs42l42->regmap,
1393                                 CS42L42_DAC_CTL2,
1394                                 CS42L42_HPOUT_PULLDOWN_MASK |
1395                                 CS42L42_HPOUT_LOAD_MASK |
1396                                 CS42L42_HPOUT_CLAMP_MASK |
1397                                 CS42L42_DAC_HPF_EN_MASK |
1398                                 CS42L42_DAC_MON_EN_MASK,
1399                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1400                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1401                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1402                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1403                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1404
1405         /* Power up HS bias to 2.7V */
1406         regmap_update_bits(cs42l42->regmap,
1407                                 CS42L42_MISC_DET_CTL,
1408                                 CS42L42_HSBIAS_CTL_MASK |
1409                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1410                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1411                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1412
1413         /* Wait for HS bias to ramp up */
1414         msleep(cs42l42->hs_bias_ramp_time);
1415
1416         /* Unmask auto detect interrupt */
1417         regmap_update_bits(cs42l42->regmap,
1418                                 CS42L42_CODEC_INT_MASK,
1419                                 CS42L42_PDN_DONE_MASK |
1420                                 CS42L42_HSDET_AUTO_DONE_MASK,
1421                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1422                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1423
1424         /* Set hs detect to automatic, enabled mode */
1425         regmap_update_bits(cs42l42->regmap,
1426                                 CS42L42_HSDET_CTL2,
1427                                 CS42L42_HSDET_CTRL_MASK |
1428                                 CS42L42_HSDET_SET_MASK |
1429                                 CS42L42_HSBIAS_REF_MASK |
1430                                 CS42L42_HSDET_AUTO_TIME_MASK,
1431                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1432                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1433                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1434                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1435 }
1436
1437 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1438 {
1439         /* Mask button detect interrupts */
1440         regmap_update_bits(cs42l42->regmap,
1441                 CS42L42_DET_INT2_MASK,
1442                 CS42L42_M_DETECT_TF_MASK |
1443                 CS42L42_M_DETECT_FT_MASK |
1444                 CS42L42_M_HSBIAS_HIZ_MASK |
1445                 CS42L42_M_SHORT_RLS_MASK |
1446                 CS42L42_M_SHORT_DET_MASK,
1447                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1448                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1449                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1450                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1451                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1452
1453         /* Ground HS bias */
1454         regmap_update_bits(cs42l42->regmap,
1455                                 CS42L42_MISC_DET_CTL,
1456                                 CS42L42_HSBIAS_CTL_MASK |
1457                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1458                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1459                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1460
1461         /* Set auto HS bias settings to default */
1462         regmap_update_bits(cs42l42->regmap,
1463                                 CS42L42_HSBIAS_SC_AUTOCTL,
1464                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1465                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1466                                 CS42L42_TIP_SENSE_EN_MASK |
1467                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1468                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1469                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1470                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1471                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1472
1473         /* Set hs detect to manual, disabled mode */
1474         regmap_update_bits(cs42l42->regmap,
1475                                 CS42L42_HSDET_CTL2,
1476                                 CS42L42_HSDET_CTRL_MASK |
1477                                 CS42L42_HSDET_SET_MASK |
1478                                 CS42L42_HSBIAS_REF_MASK |
1479                                 CS42L42_HSDET_AUTO_TIME_MASK,
1480                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1481                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1482                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1483                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1484 }
1485
1486 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1487 {
1488         int bias_level;
1489         unsigned int detect_status;
1490
1491         /* Mask button detect interrupts */
1492         regmap_update_bits(cs42l42->regmap,
1493                 CS42L42_DET_INT2_MASK,
1494                 CS42L42_M_DETECT_TF_MASK |
1495                 CS42L42_M_DETECT_FT_MASK |
1496                 CS42L42_M_HSBIAS_HIZ_MASK |
1497                 CS42L42_M_SHORT_RLS_MASK |
1498                 CS42L42_M_SHORT_DET_MASK,
1499                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1500                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1501                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1502                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1503                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1504
1505         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1506                      cs42l42->btn_det_event_dbnce * 2000);
1507
1508         /* Test all 4 level detect biases */
1509         bias_level = 1;
1510         do {
1511                 /* Adjust button detect level sensitivity */
1512                 regmap_update_bits(cs42l42->regmap,
1513                         CS42L42_MIC_DET_CTL1,
1514                         CS42L42_LATCH_TO_VP_MASK |
1515                         CS42L42_EVENT_STAT_SEL_MASK |
1516                         CS42L42_HS_DET_LEVEL_MASK,
1517                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1518                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1519                         (cs42l42->bias_thresholds[bias_level] <<
1520                         CS42L42_HS_DET_LEVEL_SHIFT));
1521
1522                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1523                                 &detect_status);
1524         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1525                 (++bias_level < CS42L42_NUM_BIASES));
1526
1527         switch (bias_level) {
1528         case 1: /* Function C button press */
1529                 bias_level = SND_JACK_BTN_2;
1530                 dev_dbg(cs42l42->dev, "Function C button press\n");
1531                 break;
1532         case 2: /* Function B button press */
1533                 bias_level = SND_JACK_BTN_1;
1534                 dev_dbg(cs42l42->dev, "Function B button press\n");
1535                 break;
1536         case 3: /* Function D button press */
1537                 bias_level = SND_JACK_BTN_3;
1538                 dev_dbg(cs42l42->dev, "Function D button press\n");
1539                 break;
1540         case 4: /* Function A button press */
1541                 bias_level = SND_JACK_BTN_0;
1542                 dev_dbg(cs42l42->dev, "Function A button press\n");
1543                 break;
1544         default:
1545                 bias_level = 0;
1546                 break;
1547         }
1548
1549         /* Set button detect level sensitivity back to default */
1550         regmap_update_bits(cs42l42->regmap,
1551                 CS42L42_MIC_DET_CTL1,
1552                 CS42L42_LATCH_TO_VP_MASK |
1553                 CS42L42_EVENT_STAT_SEL_MASK |
1554                 CS42L42_HS_DET_LEVEL_MASK,
1555                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1556                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1557                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1558
1559         /* Clear any button interrupts before unmasking them */
1560         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1561                     &detect_status);
1562
1563         /* Unmask button detect interrupts */
1564         regmap_update_bits(cs42l42->regmap,
1565                 CS42L42_DET_INT2_MASK,
1566                 CS42L42_M_DETECT_TF_MASK |
1567                 CS42L42_M_DETECT_FT_MASK |
1568                 CS42L42_M_HSBIAS_HIZ_MASK |
1569                 CS42L42_M_SHORT_RLS_MASK |
1570                 CS42L42_M_SHORT_DET_MASK,
1571                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1572                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1573                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1574                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1575                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1576
1577         return bias_level;
1578 }
1579
1580 struct cs42l42_irq_params {
1581         u16 status_addr;
1582         u16 mask_addr;
1583         u8 mask;
1584 };
1585
1586 static const struct cs42l42_irq_params irq_params_table[] = {
1587         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1588                 CS42L42_ADC_OVFL_VAL_MASK},
1589         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1590                 CS42L42_MIXER_VAL_MASK},
1591         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1592                 CS42L42_SRC_VAL_MASK},
1593         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1594                 CS42L42_ASP_RX_VAL_MASK},
1595         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1596                 CS42L42_ASP_TX_VAL_MASK},
1597         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1598                 CS42L42_CODEC_VAL_MASK},
1599         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1600                 CS42L42_DET_INT_VAL1_MASK},
1601         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1602                 CS42L42_DET_INT_VAL2_MASK},
1603         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1604                 CS42L42_SRCPL_VAL_MASK},
1605         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1606                 CS42L42_VPMON_VAL_MASK},
1607         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1608                 CS42L42_PLL_LOCK_VAL_MASK},
1609         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1610                 CS42L42_TSRS_PLUG_VAL_MASK}
1611 };
1612
1613 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1614 {
1615         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1616         unsigned int stickies[12];
1617         unsigned int masks[12];
1618         unsigned int current_plug_status;
1619         unsigned int current_button_status;
1620         unsigned int i;
1621         int report = 0;
1622
1623         mutex_lock(&cs42l42->irq_lock);
1624         if (cs42l42->suspended) {
1625                 mutex_unlock(&cs42l42->irq_lock);
1626                 return IRQ_NONE;
1627         }
1628
1629         /* Read sticky registers to clear interurpt */
1630         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1631                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1632                                 &(stickies[i]));
1633                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1634                                 &(masks[i]));
1635                 stickies[i] = stickies[i] & (~masks[i]) &
1636                                 irq_params_table[i].mask;
1637         }
1638
1639         /* Read tip sense status before handling type detect */
1640         current_plug_status = (stickies[11] &
1641                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1642                 CS42L42_TS_PLUG_SHIFT;
1643
1644         /* Read button sense status */
1645         current_button_status = stickies[7] &
1646                 (CS42L42_M_DETECT_TF_MASK |
1647                 CS42L42_M_DETECT_FT_MASK |
1648                 CS42L42_M_HSBIAS_HIZ_MASK);
1649
1650         /*
1651          * Check auto-detect status. Don't assume a previous unplug event has
1652          * cleared the flags. If the jack is unplugged and plugged during
1653          * system suspend there won't have been an unplug event.
1654          */
1655         if ((~masks[5]) & irq_params_table[5].mask) {
1656                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1657                         cs42l42_process_hs_type_detect(cs42l42);
1658                         switch (cs42l42->hs_type) {
1659                         case CS42L42_PLUG_CTIA:
1660                         case CS42L42_PLUG_OMTP:
1661                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1662                                                     SND_JACK_HEADSET |
1663                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1664                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1665                                 break;
1666                         case CS42L42_PLUG_HEADPHONE:
1667                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1668                                                     SND_JACK_HEADSET |
1669                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1670                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1671                                 break;
1672                         default:
1673                                 break;
1674                         }
1675                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1676                 }
1677         }
1678
1679         /* Check tip sense status */
1680         if ((~masks[11]) & irq_params_table[11].mask) {
1681                 switch (current_plug_status) {
1682                 case CS42L42_TS_PLUG:
1683                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1684                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1685                                 cs42l42_init_hs_type_detect(cs42l42);
1686                         }
1687                         break;
1688
1689                 case CS42L42_TS_UNPLUG:
1690                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1691                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1692                                 cs42l42_cancel_hs_type_detect(cs42l42);
1693
1694                                 snd_soc_jack_report(cs42l42->jack, 0,
1695                                                     SND_JACK_HEADSET |
1696                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1697                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1698
1699                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1700                         }
1701                         break;
1702
1703                 default:
1704                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1705                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1706                 }
1707         }
1708
1709         /* Check button detect status */
1710         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1711                 if (!(current_button_status &
1712                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1713
1714                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1715                                 dev_dbg(cs42l42->dev, "Button released\n");
1716                                 report = 0;
1717                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1718                                 report = cs42l42_handle_button_press(cs42l42);
1719
1720                         }
1721                         snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1722                                                                    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1723                 }
1724         }
1725
1726         mutex_unlock(&cs42l42->irq_lock);
1727
1728         return IRQ_HANDLED;
1729 }
1730
1731 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1732 {
1733         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1734                         CS42L42_ADC_OVFL_MASK,
1735                         (1 << CS42L42_ADC_OVFL_SHIFT));
1736
1737         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1738                         CS42L42_MIX_CHB_OVFL_MASK |
1739                         CS42L42_MIX_CHA_OVFL_MASK |
1740                         CS42L42_EQ_OVFL_MASK |
1741                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1742                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1743                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1744                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1745                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1746
1747         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1748                         CS42L42_SRC_ILK_MASK |
1749                         CS42L42_SRC_OLK_MASK |
1750                         CS42L42_SRC_IUNLK_MASK |
1751                         CS42L42_SRC_OUNLK_MASK,
1752                         (1 << CS42L42_SRC_ILK_SHIFT) |
1753                         (1 << CS42L42_SRC_OLK_SHIFT) |
1754                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1755                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1756
1757         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1758                         CS42L42_ASPRX_NOLRCK_MASK |
1759                         CS42L42_ASPRX_EARLY_MASK |
1760                         CS42L42_ASPRX_LATE_MASK |
1761                         CS42L42_ASPRX_ERROR_MASK |
1762                         CS42L42_ASPRX_OVLD_MASK,
1763                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1764                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1765                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1766                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1767                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1768
1769         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1770                         CS42L42_ASPTX_NOLRCK_MASK |
1771                         CS42L42_ASPTX_EARLY_MASK |
1772                         CS42L42_ASPTX_LATE_MASK |
1773                         CS42L42_ASPTX_SMERROR_MASK,
1774                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1775                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1776                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1777                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1778
1779         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1780                         CS42L42_PDN_DONE_MASK |
1781                         CS42L42_HSDET_AUTO_DONE_MASK,
1782                         (1 << CS42L42_PDN_DONE_SHIFT) |
1783                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1784
1785         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1786                         CS42L42_SRCPL_ADC_LK_MASK |
1787                         CS42L42_SRCPL_DAC_LK_MASK |
1788                         CS42L42_SRCPL_ADC_UNLK_MASK |
1789                         CS42L42_SRCPL_DAC_UNLK_MASK,
1790                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1791                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1792                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1793                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1794
1795         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1796                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1797                         CS42L42_TIP_SENSE_PLUG_MASK |
1798                         CS42L42_HSBIAS_SENSE_MASK,
1799                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1800                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1801                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1802
1803         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1804                         CS42L42_M_DETECT_TF_MASK |
1805                         CS42L42_M_DETECT_FT_MASK |
1806                         CS42L42_M_HSBIAS_HIZ_MASK |
1807                         CS42L42_M_SHORT_RLS_MASK |
1808                         CS42L42_M_SHORT_DET_MASK,
1809                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1810                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1811                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1812                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1813                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1814
1815         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1816                         CS42L42_VPMON_MASK,
1817                         (1 << CS42L42_VPMON_SHIFT));
1818
1819         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1820                         CS42L42_PLL_LOCK_MASK,
1821                         (1 << CS42L42_PLL_LOCK_SHIFT));
1822
1823         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1824                         CS42L42_RS_PLUG_MASK |
1825                         CS42L42_RS_UNPLUG_MASK |
1826                         CS42L42_TS_PLUG_MASK |
1827                         CS42L42_TS_UNPLUG_MASK,
1828                         (1 << CS42L42_RS_PLUG_SHIFT) |
1829                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1830                         (0 << CS42L42_TS_PLUG_SHIFT) |
1831                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1832 }
1833
1834 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1835 {
1836         unsigned int reg;
1837
1838         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1839
1840         /*
1841          * DETECT_MODE must always be 0 with ADC and HP both off otherwise the
1842          * FILT+ supply will not charge properly.
1843          */
1844         regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1845                            CS42L42_DETECT_MODE_MASK, 0);
1846
1847         /* Latch analog controls to VP power domain */
1848         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1849                         CS42L42_LATCH_TO_VP_MASK |
1850                         CS42L42_EVENT_STAT_SEL_MASK |
1851                         CS42L42_HS_DET_LEVEL_MASK,
1852                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1853                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1854                         (cs42l42->bias_thresholds[0] <<
1855                         CS42L42_HS_DET_LEVEL_SHIFT));
1856
1857         /* Remove ground noise-suppression clamps */
1858         regmap_update_bits(cs42l42->regmap,
1859                         CS42L42_HS_CLAMP_DISABLE,
1860                         CS42L42_HS_CLAMP_DISABLE_MASK,
1861                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1862
1863         /* Enable the tip sense circuit */
1864         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1865                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1866
1867         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1868                         CS42L42_TIP_SENSE_CTRL_MASK |
1869                         CS42L42_TIP_SENSE_INV_MASK |
1870                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1871                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1872                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1873                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1874
1875         /* Save the initial status of the tip sense */
1876         regmap_read(cs42l42->regmap,
1877                           CS42L42_TSRS_PLUG_STATUS,
1878                           &reg);
1879         cs42l42->plug_state = (((char) reg) &
1880                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1881                       CS42L42_TS_PLUG_SHIFT;
1882 }
1883
1884 static const unsigned int threshold_defaults[] = {
1885         CS42L42_HS_DET_LEVEL_15,
1886         CS42L42_HS_DET_LEVEL_8,
1887         CS42L42_HS_DET_LEVEL_4,
1888         CS42L42_HS_DET_LEVEL_1
1889 };
1890
1891 static int cs42l42_handle_device_data(struct device *dev,
1892                                         struct cs42l42_private *cs42l42)
1893 {
1894         unsigned int val;
1895         u32 thresholds[CS42L42_NUM_BIASES];
1896         int ret;
1897         int i;
1898
1899         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1900         if (!ret) {
1901                 switch (val) {
1902                 case CS42L42_TS_INV_EN:
1903                 case CS42L42_TS_INV_DIS:
1904                         cs42l42->ts_inv = val;
1905                         break;
1906                 default:
1907                         dev_err(dev,
1908                                 "Wrong cirrus,ts-inv DT value %d\n",
1909                                 val);
1910                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1911                 }
1912         } else {
1913                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1914         }
1915
1916         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1917         if (!ret) {
1918                 switch (val) {
1919                 case CS42L42_TS_DBNCE_0:
1920                 case CS42L42_TS_DBNCE_125:
1921                 case CS42L42_TS_DBNCE_250:
1922                 case CS42L42_TS_DBNCE_500:
1923                 case CS42L42_TS_DBNCE_750:
1924                 case CS42L42_TS_DBNCE_1000:
1925                 case CS42L42_TS_DBNCE_1250:
1926                 case CS42L42_TS_DBNCE_1500:
1927                         cs42l42->ts_dbnc_rise = val;
1928                         break;
1929                 default:
1930                         dev_err(dev,
1931                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1932                                 val);
1933                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1934                 }
1935         } else {
1936                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1937         }
1938
1939         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1940                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1941                         (cs42l42->ts_dbnc_rise <<
1942                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1943
1944         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1945         if (!ret) {
1946                 switch (val) {
1947                 case CS42L42_TS_DBNCE_0:
1948                 case CS42L42_TS_DBNCE_125:
1949                 case CS42L42_TS_DBNCE_250:
1950                 case CS42L42_TS_DBNCE_500:
1951                 case CS42L42_TS_DBNCE_750:
1952                 case CS42L42_TS_DBNCE_1000:
1953                 case CS42L42_TS_DBNCE_1250:
1954                 case CS42L42_TS_DBNCE_1500:
1955                         cs42l42->ts_dbnc_fall = val;
1956                         break;
1957                 default:
1958                         dev_err(dev,
1959                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1960                                 val);
1961                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1962                 }
1963         } else {
1964                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1965         }
1966
1967         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1968                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1969                         (cs42l42->ts_dbnc_fall <<
1970                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1971
1972         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1973         if (!ret) {
1974                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1975                         cs42l42->btn_det_init_dbnce = val;
1976                 else {
1977                         dev_err(dev,
1978                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1979                                 val);
1980                         cs42l42->btn_det_init_dbnce =
1981                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1982                 }
1983         } else {
1984                 cs42l42->btn_det_init_dbnce =
1985                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1986         }
1987
1988         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1989         if (!ret) {
1990                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1991                         cs42l42->btn_det_event_dbnce = val;
1992                 else {
1993                         dev_err(dev,
1994                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1995                         cs42l42->btn_det_event_dbnce =
1996                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1997                 }
1998         } else {
1999                 cs42l42->btn_det_event_dbnce =
2000                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2001         }
2002
2003         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
2004                                              thresholds, ARRAY_SIZE(thresholds));
2005         if (!ret) {
2006                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
2007                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
2008                                 cs42l42->bias_thresholds[i] = thresholds[i];
2009                         else {
2010                                 dev_err(dev,
2011                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
2012                                         thresholds[i]);
2013                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2014                         }
2015                 }
2016         } else {
2017                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2018                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2019         }
2020
2021         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2022         if (!ret) {
2023                 switch (val) {
2024                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2025                         cs42l42->hs_bias_ramp_rate = val;
2026                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2027                         break;
2028                 case CS42L42_HSBIAS_RAMP_FAST:
2029                         cs42l42->hs_bias_ramp_rate = val;
2030                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2031                         break;
2032                 case CS42L42_HSBIAS_RAMP_SLOW:
2033                         cs42l42->hs_bias_ramp_rate = val;
2034                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2035                         break;
2036                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2037                         cs42l42->hs_bias_ramp_rate = val;
2038                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2039                         break;
2040                 default:
2041                         dev_err(dev,
2042                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2043                                 val);
2044                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2045                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2046                 }
2047         } else {
2048                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2049                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2050         }
2051
2052         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2053                         CS42L42_HSBIAS_RAMP_MASK,
2054                         (cs42l42->hs_bias_ramp_rate <<
2055                         CS42L42_HSBIAS_RAMP_SHIFT));
2056
2057         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2058                 cs42l42->hs_bias_sense_en = 0;
2059         else
2060                 cs42l42->hs_bias_sense_en = 1;
2061
2062         return 0;
2063 }
2064
2065 /* Datasheet suspend sequence */
2066 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
2067         REG_SEQ0(CS42L42_MIC_DET_CTL1,          0x9F),
2068         REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK,     0x01),
2069         REG_SEQ0(CS42L42_MIXER_INT_MASK,        0x0F),
2070         REG_SEQ0(CS42L42_SRC_INT_MASK,          0x0F),
2071         REG_SEQ0(CS42L42_ASP_RX_INT_MASK,       0x1F),
2072         REG_SEQ0(CS42L42_ASP_TX_INT_MASK,       0x0F),
2073         REG_SEQ0(CS42L42_CODEC_INT_MASK,        0x03),
2074         REG_SEQ0(CS42L42_SRCPL_INT_MASK,        0x7F),
2075         REG_SEQ0(CS42L42_VPMON_INT_MASK,        0x01),
2076         REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK,     0x01),
2077         REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK,    0x0F),
2078         REG_SEQ0(CS42L42_WAKE_CTL,              0xE1),
2079         REG_SEQ0(CS42L42_DET_INT1_MASK,         0xE0),
2080         REG_SEQ0(CS42L42_DET_INT2_MASK,         0xFF),
2081         REG_SEQ0(CS42L42_MIXER_CHA_VOL,         0x3F),
2082         REG_SEQ0(CS42L42_MIXER_ADC_VOL,         0x3F),
2083         REG_SEQ0(CS42L42_MIXER_CHB_VOL,         0x3F),
2084         REG_SEQ0(CS42L42_HP_CTL,                0x0F),
2085         REG_SEQ0(CS42L42_ASP_RX_DAI0_EN,        0x00),
2086         REG_SEQ0(CS42L42_ASP_CLK_CFG,           0x00),
2087         REG_SEQ0(CS42L42_HSDET_CTL2,            0x00),
2088         REG_SEQ0(CS42L42_PWR_CTL1,              0xFE),
2089         REG_SEQ0(CS42L42_PWR_CTL2,              0x8C),
2090         REG_SEQ0(CS42L42_DAC_CTL2,              0x02),
2091         REG_SEQ0(CS42L42_HS_CLAMP_DISABLE,      0x00),
2092         REG_SEQ0(CS42L42_MISC_DET_CTL,          0x03),
2093         REG_SEQ0(CS42L42_TIPSENSE_CTL,          0x02),
2094         REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL,     0x03),
2095         REG_SEQ0(CS42L42_PWR_CTL1,              0xFF)
2096 };
2097
2098 static int __maybe_unused cs42l42_suspend(struct device *dev)
2099 {
2100         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2101         unsigned int reg;
2102         u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
2103         int i, ret;
2104
2105         /*
2106          * Wait for threaded irq handler to be idle and stop it processing
2107          * future interrupts. This ensures a safe disable if the interrupt
2108          * is shared.
2109          */
2110         mutex_lock(&cs42l42->irq_lock);
2111         cs42l42->suspended = true;
2112
2113         /* Save register values that will be overwritten by shutdown sequence */
2114         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
2115                 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, &reg);
2116                 save_regs[i] = (u8)reg;
2117         }
2118
2119         /* Shutdown codec */
2120         regmap_multi_reg_write(cs42l42->regmap,
2121                                cs42l42_shutdown_seq,
2122                                ARRAY_SIZE(cs42l42_shutdown_seq));
2123
2124         /* All interrupt sources are now disabled */
2125         mutex_unlock(&cs42l42->irq_lock);
2126
2127         /* Wait for power-down complete */
2128         msleep(CS42L42_PDN_DONE_TIME_MS);
2129         ret = regmap_read_poll_timeout(cs42l42->regmap,
2130                                        CS42L42_CODEC_STATUS, reg,
2131                                        (reg & CS42L42_PDN_DONE_MASK),
2132                                        CS42L42_PDN_DONE_POLL_US,
2133                                        CS42L42_PDN_DONE_TIMEOUT_US);
2134         if (ret)
2135                 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
2136
2137         /* Discharge FILT+ */
2138         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2139                            CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
2140         msleep(CS42L42_FILT_DISCHARGE_TIME_MS);
2141
2142         regcache_cache_only(cs42l42->regmap, true);
2143         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2144         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2145
2146         /* Restore register values to the regmap cache */
2147         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
2148                 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
2149
2150         /* The cached address page register value is now stale */
2151         regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
2152
2153         dev_dbg(dev, "System suspended\n");
2154
2155         return 0;
2156
2157 }
2158
2159 static int __maybe_unused cs42l42_resume(struct device *dev)
2160 {
2161         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2162         int ret;
2163
2164         /*
2165          * If jack was unplugged and re-plugged during suspend it could
2166          * have changed type but the tip-sense state hasn't changed.
2167          * Force a plugged state to be re-evaluated.
2168          */
2169         if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
2170                 cs42l42->plug_state = CS42L42_TS_TRANS;
2171
2172         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2173         if (ret != 0) {
2174                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2175                 return ret;
2176         }
2177
2178         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2179         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2180
2181         regcache_cache_only(cs42l42->regmap, false);
2182         regcache_mark_dirty(cs42l42->regmap);
2183
2184         mutex_lock(&cs42l42->irq_lock);
2185         /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
2186         regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
2187         regcache_sync(cs42l42->regmap);
2188
2189         cs42l42->suspended = false;
2190         mutex_unlock(&cs42l42->irq_lock);
2191
2192         dev_dbg(dev, "System resumed\n");
2193
2194         return 0;
2195 }
2196
2197 static int cs42l42_i2c_probe(struct i2c_client *i2c_client)
2198 {
2199         struct cs42l42_private *cs42l42;
2200         int ret, i, devid;
2201         unsigned int reg;
2202
2203         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
2204                                GFP_KERNEL);
2205         if (!cs42l42)
2206                 return -ENOMEM;
2207
2208         cs42l42->dev = &i2c_client->dev;
2209         i2c_set_clientdata(i2c_client, cs42l42);
2210         mutex_init(&cs42l42->irq_lock);
2211
2212         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
2213         if (IS_ERR(cs42l42->regmap)) {
2214                 ret = PTR_ERR(cs42l42->regmap);
2215                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
2216                 return ret;
2217         }
2218
2219         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2220                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2221
2222         ret = devm_regulator_bulk_get(&i2c_client->dev,
2223                                       ARRAY_SIZE(cs42l42->supplies),
2224                                       cs42l42->supplies);
2225         if (ret != 0) {
2226                 dev_err(&i2c_client->dev,
2227                         "Failed to request supplies: %d\n", ret);
2228                 return ret;
2229         }
2230
2231         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2232                                     cs42l42->supplies);
2233         if (ret != 0) {
2234                 dev_err(&i2c_client->dev,
2235                         "Failed to enable supplies: %d\n", ret);
2236                 return ret;
2237         }
2238
2239         /* Reset the Device */
2240         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
2241                 "reset", GPIOD_OUT_LOW);
2242         if (IS_ERR(cs42l42->reset_gpio)) {
2243                 ret = PTR_ERR(cs42l42->reset_gpio);
2244                 goto err_disable_noreset;
2245         }
2246
2247         if (cs42l42->reset_gpio) {
2248                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
2249                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2250         }
2251         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2252
2253         /* Request IRQ if one was specified */
2254         if (i2c_client->irq) {
2255                 ret = request_threaded_irq(i2c_client->irq,
2256                                            NULL, cs42l42_irq_thread,
2257                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2258                                            "cs42l42", cs42l42);
2259                 if (ret == -EPROBE_DEFER) {
2260                         goto err_disable_noirq;
2261                 } else if (ret != 0) {
2262                         dev_err(&i2c_client->dev,
2263                                 "Failed to request IRQ: %d\n", ret);
2264                         goto err_disable_noirq;
2265                 }
2266         }
2267
2268         /* initialize codec */
2269         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2270         if (devid < 0) {
2271                 ret = devid;
2272                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
2273                 goto err_disable;
2274         }
2275
2276         if (devid != CS42L42_CHIP_ID) {
2277                 ret = -ENODEV;
2278                 dev_err(&i2c_client->dev,
2279                         "CS42L42 Device ID (%X). Expected %X\n",
2280                         devid, CS42L42_CHIP_ID);
2281                 goto err_disable;
2282         }
2283
2284         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2285         if (ret < 0) {
2286                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
2287                 goto err_shutdown;
2288         }
2289
2290         dev_info(&i2c_client->dev,
2291                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
2292
2293         /* Power up the codec */
2294         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2295                         CS42L42_ASP_DAO_PDN_MASK |
2296                         CS42L42_ASP_DAI_PDN_MASK |
2297                         CS42L42_MIXER_PDN_MASK |
2298                         CS42L42_EQ_PDN_MASK |
2299                         CS42L42_HP_PDN_MASK |
2300                         CS42L42_ADC_PDN_MASK |
2301                         CS42L42_PDN_ALL_MASK,
2302                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2303                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2304                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2305                         (1 << CS42L42_EQ_PDN_SHIFT) |
2306                         (1 << CS42L42_HP_PDN_SHIFT) |
2307                         (1 << CS42L42_ADC_PDN_SHIFT) |
2308                         (0 << CS42L42_PDN_ALL_SHIFT));
2309
2310         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2311         if (ret != 0)
2312                 goto err_shutdown;
2313
2314         /* Setup headset detection */
2315         cs42l42_setup_hs_type_detect(cs42l42);
2316
2317         /* Mask/Unmask Interrupts */
2318         cs42l42_set_interrupt_masks(cs42l42);
2319
2320         /* Register codec for machine driver */
2321         ret = devm_snd_soc_register_component(&i2c_client->dev,
2322                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2323         if (ret < 0)
2324                 goto err_shutdown;
2325
2326         return 0;
2327
2328 err_shutdown:
2329         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2330         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2331         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2332
2333 err_disable:
2334         if (i2c_client->irq)
2335                 free_irq(i2c_client->irq, cs42l42);
2336
2337 err_disable_noirq:
2338         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2339 err_disable_noreset:
2340         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2341                                 cs42l42->supplies);
2342         return ret;
2343 }
2344
2345 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2346 {
2347         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2348
2349         if (i2c_client->irq)
2350                 free_irq(i2c_client->irq, cs42l42);
2351
2352         /*
2353          * The driver might not have control of reset and power supplies,
2354          * so ensure that the chip internals are powered down.
2355          */
2356         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2357         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2358         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2359
2360         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2361         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2362
2363         return 0;
2364 }
2365
2366 static const struct dev_pm_ops cs42l42_pm_ops = {
2367         SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_resume)
2368 };
2369
2370 #ifdef CONFIG_OF
2371 static const struct of_device_id cs42l42_of_match[] = {
2372         { .compatible = "cirrus,cs42l42", },
2373         {}
2374 };
2375 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2376 #endif
2377
2378 #ifdef CONFIG_ACPI
2379 static const struct acpi_device_id cs42l42_acpi_match[] = {
2380         {"10134242", 0,},
2381         {}
2382 };
2383 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2384 #endif
2385
2386 static const struct i2c_device_id cs42l42_id[] = {
2387         {"cs42l42", 0},
2388         {}
2389 };
2390
2391 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2392
2393 static struct i2c_driver cs42l42_i2c_driver = {
2394         .driver = {
2395                 .name = "cs42l42",
2396                 .pm = &cs42l42_pm_ops,
2397                 .of_match_table = of_match_ptr(cs42l42_of_match),
2398                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2399                 },
2400         .id_table = cs42l42_id,
2401         .probe_new = cs42l42_i2c_probe,
2402         .remove = cs42l42_i2c_remove,
2403 };
2404
2405 module_i2c_driver(cs42l42_i2c_driver);
2406
2407 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2408 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2409 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2410 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2411 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2412 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2413 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2414 MODULE_LICENSE("GPL");