sound/soc/codecs/cs35l45.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * cs35l45.h - CS35L45 ALSA SoC audio driver
   4  *
   5  * Copyright 2019-2022 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  *
   9  */
  10
  11 #ifndef CS35L45_H
  12 #define CS35L45_H
  13
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <dt-bindings/sound/cs35l45.h>
  18 #include "wm_adsp.h"
  19
  20 #define CS35L45_DEVID                           0x00000000
  21 #define CS35L45_REVID                           0x00000004
  22 #define CS35L45_RELID                           0x0000000C
  23 #define CS35L45_OTPID                           0x00000010
  24 #define CS35L45_SFT_RESET                       0x00000020
  25 #define CS35L45_GLOBAL_ENABLES                  0x00002014
  26 #define CS35L45_BLOCK_ENABLES                   0x00002018
  27 #define CS35L45_BLOCK_ENABLES2                  0x0000201C
  28 #define CS35L45_ERROR_RELEASE                   0x00002034
  29 #define CS35L45_SYNC_GPIO1                      0x00002430
  30 #define CS35L45_INTB_GPIO2_MCLK_REF             0x00002434
  31 #define CS35L45_GPIO3                           0x00002438
  32 #define CS35L45_PWRMGT_CTL                      0x00002900
  33 #define CS35L45_WAKESRC_CTL                     0x00002904
  34 #define CS35L45_WKI2C_CTL                       0x00002908
  35 #define CS35L45_PWRMGT_STS                      0x0000290C
  36 #define CS35L45_REFCLK_INPUT                    0x00002C04
  37 #define CS35L45_GLOBAL_SAMPLE_RATE              0x00002C0C
  38 #define CS35L45_BOOST_CCM_CFG                   0x00003808
  39 #define CS35L45_BOOST_DCM_CFG                   0x0000380C
  40 #define CS35L45_BOOST_OV_CFG                    0x0000382C
  41 #define CS35L45_ASP_ENABLES1                    0x00004800
  42 #define CS35L45_ASP_CONTROL1                    0x00004804
  43 #define CS35L45_ASP_CONTROL2                    0x00004808
  44 #define CS35L45_ASP_CONTROL3                    0x0000480C
  45 #define CS35L45_ASP_FRAME_CONTROL1              0x00004810
  46 #define CS35L45_ASP_FRAME_CONTROL2              0x00004814
  47 #define CS35L45_ASP_FRAME_CONTROL5              0x00004820
  48 #define CS35L45_ASP_DATA_CONTROL1               0x00004830
  49 #define CS35L45_ASP_DATA_CONTROL5               0x00004840
  50 #define CS35L45_DACPCM1_INPUT                   0x00004C00
  51 #define CS35L45_ASPTX1_INPUT                    0x00004C20
  52 #define CS35L45_ASPTX2_INPUT                    0x00004C24
  53 #define CS35L45_ASPTX3_INPUT                    0x00004C28
  54 #define CS35L45_ASPTX4_INPUT                    0x00004C2C
  55 #define CS35L45_ASPTX5_INPUT                    0x00004C30
  56 #define CS35L45_DSP1RX1_INPUT                   0x00004C40
  57 #define CS35L45_DSP1RX2_INPUT                   0x00004C44
  58 #define CS35L45_DSP1RX3_INPUT                   0x00004C48
  59 #define CS35L45_DSP1RX4_INPUT                   0x00004C4C
  60 #define CS35L45_DSP1RX5_INPUT                   0x00004C50
  61 #define CS35L45_DSP1RX6_INPUT                   0x00004C54
  62 #define CS35L45_DSP1RX7_INPUT                   0x00004C58
  63 #define CS35L45_DSP1RX8_INPUT                   0x00004C5C
  64 #define CS35L45_HVLV_CONFIG                     0x00006400
  65 #define CS35L45_LDPM_CONFIG                     0x00006404
  66 #define CS35L45_AMP_PCM_CONTROL                 0x00007000
  67 #define CS35L45_AMP_PCM_HPF_TST                 0x00007004
  68 #define CS35L45_AMP_GAIN                        0x00007800
  69 #define CS35L45_IRQ1_CFG                        0x0000E000
  70 #define CS35L45_IRQ1_STATUS                     0x0000E004
  71 #define CS35L45_IRQ1_EINT_1                     0x0000E010
  72 #define CS35L45_IRQ1_EINT_2                     0x0000E014
  73 #define CS35L45_IRQ1_EINT_3                     0x0000E018
  74 #define CS35L45_IRQ1_EINT_4                     0x0000E01C
  75 #define CS35L45_IRQ1_EINT_5                     0x0000E020
  76 #define CS35L45_IRQ1_EINT_7                     0x0000E028
  77 #define CS35L45_IRQ1_EINT_8                     0x0000E02C
  78 #define CS35L45_IRQ1_EINT_18                    0x0000E054
  79 #define CS35L45_IRQ1_STS_1                      0x0000E090
  80 #define CS35L45_IRQ1_STS_2                      0x0000E094
  81 #define CS35L45_IRQ1_STS_3                      0x0000E098
  82 #define CS35L45_IRQ1_STS_4                      0x0000E09C
  83 #define CS35L45_IRQ1_STS_5                      0x0000E0A0
  84 #define CS35L45_IRQ1_STS_7                      0x0000E0A8
  85 #define CS35L45_IRQ1_STS_8                      0x0000E0AC
  86 #define CS35L45_IRQ1_STS_18                     0x0000E0D4
  87 #define CS35L45_IRQ1_MASK_1                     0x0000E110
  88 #define CS35L45_IRQ1_MASK_2                     0x0000E114
  89 #define CS35L45_IRQ1_MASK_3                     0x0000E118
  90 #define CS35L45_IRQ1_MASK_4                     0x0000E11C
  91 #define CS35L45_IRQ1_MASK_5                     0x0000E120
  92 #define CS35L45_IRQ1_MASK_6                     0x0000E124
  93 #define CS35L45_IRQ1_MASK_7                     0x0000E128
  94 #define CS35L45_IRQ1_MASK_8                     0x0000E12C
  95 #define CS35L45_IRQ1_MASK_9                     0x0000E130
  96 #define CS35L45_IRQ1_MASK_10                    0x0000E134
  97 #define CS35L45_IRQ1_MASK_11                    0x0000E138
  98 #define CS35L45_IRQ1_MASK_12                    0x0000E13C
  99 #define CS35L45_IRQ1_MASK_13                    0x0000E140
 100 #define CS35L45_IRQ1_MASK_14                    0x0000E144
 101 #define CS35L45_IRQ1_MASK_15                    0x0000E148
 102 #define CS35L45_IRQ1_MASK_16                    0x0000E14C
 103 #define CS35L45_IRQ1_MASK_17                    0x0000E150
 104 #define CS35L45_IRQ1_MASK_18                    0x0000E154
 105 #define CS35L45_GPIO_STATUS1                    0x0000F000
 106 #define CS35L45_GPIO1_CTRL1                     0x0000F008
 107 #define CS35L45_GPIO2_CTRL1                     0x0000F00C
 108 #define CS35L45_GPIO3_CTRL1                     0x0000F010
 109 #define CS35L45_DSP_MBOX_1                      0x00011000
 110 #define CS35L45_DSP_MBOX_2                      0x00011004
 111 #define CS35L45_DSP_VIRT1_MBOX_1                0x00011020
 112 #define CS35L45_DSP_VIRT1_MBOX_2                0x00011024
 113 #define CS35L45_DSP_VIRT1_MBOX_3                0x00011028
 114 #define CS35L45_DSP_VIRT1_MBOX_4                0x0001102C
 115 #define CS35L45_DSP_VIRT2_MBOX_1                0x00011040
 116 #define CS35L45_DSP_VIRT2_MBOX_2                0x00011044
 117 #define CS35L45_DSP_VIRT2_MBOX_3                0x00011048
 118 #define CS35L45_DSP_VIRT2_MBOX_4                0x0001104C
 119 #define CS35L45_DSP1_XMEM_PACK_0                0x02000000
 120 #define CS35L45_DSP1_XMEM_PACK_4607             0x020047FC
 121 #define CS35L45_DSP1_XMEM_UNPACK32_0            0x02400000
 122 #define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC
 123 #define CS35L45_DSP1_SYS_ID                     0x025E0000
 124 #define CS35L45_DSP1_XMEM_UNPACK24_0            0x02800000
 125 #define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC
 126 #define CS35L45_DSP1_CLOCK_FREQ         0x02B80000
 127 #define CS35L45_DSP1_RX1_RATE                   0x02B80080
 128 #define CS35L45_DSP1_RX2_RATE                   0x02B80088
 129 #define CS35L45_DSP1_RX3_RATE                   0x02B80090
 130 #define CS35L45_DSP1_RX4_RATE                   0x02B80098
 131 #define CS35L45_DSP1_RX5_RATE                   0x02B800A0
 132 #define CS35L45_DSP1_RX6_RATE                   0x02B800A8
 133 #define CS35L45_DSP1_RX7_RATE                   0x02B800B0
 134 #define CS35L45_DSP1_RX8_RATE                   0x02B800B8
 135 #define CS35L45_DSP1_TX1_RATE                   0x02B80280
 136 #define CS35L45_DSP1_TX2_RATE                   0x02B80288
 137 #define CS35L45_DSP1_TX3_RATE                   0x02B80290
 138 #define CS35L45_DSP1_TX4_RATE                   0x02B80298
 139 #define CS35L45_DSP1_TX5_RATE                   0x02B802A0
 140 #define CS35L45_DSP1_TX6_RATE                   0x02B802A8
 141 #define CS35L45_DSP1_TX7_RATE                   0x02B802B0
 142 #define CS35L45_DSP1_TX8_RATE                   0x02B802B8
 143 #define CS35L45_DSP1_SCRATCH1                   0x02B805C0
 144 #define CS35L45_DSP1_SCRATCH2                   0x02B805C8
 145 #define CS35L45_DSP1_SCRATCH3                   0x02B805D0
 146 #define CS35L45_DSP1_SCRATCH4                   0x02B805D8
 147 #define CS35L45_DSP1_CCM_CORE_CONTROL           0x02BC1000
 148 #define CS35L45_DSP1_YMEM_PACK_0                0x02C00000
 149 #define CS35L45_DSP1_YMEM_PACK_1532             0x02C017F0
 150 #define CS35L45_DSP1_YMEM_UNPACK32_0            0x03000000
 151 #define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8
 152 #define CS35L45_DSP1_YMEM_UNPACK24_0            0x03400000
 153 #define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC
 154 #define CS35L45_DSP1_PMEM_0                     0x03800000
 155 #define CS35L45_DSP1_PMEM_3834                  0x03803BE8
 156 #define CS35L45_LASTREG                 0x03C6EFE8
 157
 158 /* SFT_RESET */
 159 #define CS35L45_SOFT_RESET_TRIGGER              0x5A000000
 160
 161 /* GLOBAL_ENABLES */
 162 #define CS35L45_GLOBAL_EN_SHIFT                 0
 163 #define CS35L45_GLOBAL_EN_MASK                  BIT(0)
 164
 165 /* BLOCK_ENABLES */
 166 #define CS35L45_IMON_EN_SHIFT                   13
 167 #define CS35L45_VMON_EN_SHIFT                   12
 168 #define CS35L45_TEMPMON_EN_SHIFT                10
 169 #define CS35L45_VDD_BSTMON_EN_SHIFT             9
 170 #define CS35L45_VDD_BATTMON_EN_SHIFT            8
 171 #define CS35L45_BST_EN_SHIFT                    4
 172 #define CS35L45_BST_EN_MASK                     GENMASK(5, 4)
 173 #define CS35L45_RCV_EN_SHIFT                    2
 174 #define CS35L45_RCV_EN_MASK                     BIT(2)
 175 #define CS35L45_AMP_EN_SHIFT                    0
 176 #define CS35L45_AMP_EN_MASK                     BIT(0)
 177
 178 #define CS35L45_BST_DISABLE_FET_OFF             0x00
 179 #define CS35L45_BST_DISABLE_FET_ON              0x01
 180 #define CS35L45_BST_ENABLE                      0x02
 181
 182 /* BLOCK_ENABLES2 */
 183 #define CS35L45_ASP_EN_SHIFT                    27
 184 #define CS35L45_AMP_DRE_EN_SHIFT                20
 185 #define CS35L45_AMP_DRE_EN_MASK         BIT(20)
 186 #define CS35L45_MEM_RDY_SHIFT                   1
 187 #define CS35L45_MEM_RDY_MASK                    BIT(1)
 188
 189 /* ERROR_RELEASE */
 190 #define CS35L45_GLOBAL_ERR_RLS_MASK             BIT(11)
 191
 192 /* CCM_CORE */
 193 #define CS35L45_CCM_CORE_RESET_SHIFT            9
 194 #define CS35L45_CCM_CORE_RESET_MASK             BIT(9)
 195 #define CS35L45_CCM_PM_REMAP_SHIFT              7
 196 #define CS35L45_CCM_PM_REMAP_MASK               BIT(7)
 197 #define CS35L45_CCM_CORE_EN_SHIFT               0
 198 #define CS35L45_CCM_CORE_EN_MASK                BIT(0)
 199
 200 /* REFCLK_INPUT */
 201 #define CS35L45_PLL_FORCE_EN_SHIFT              16
 202 #define CS35L45_PLL_FORCE_EN_MASK               BIT(16)
 203 #define CS35L45_PLL_OPEN_LOOP_SHIFT             11
 204 #define CS35L45_PLL_OPEN_LOOP_MASK              BIT(11)
 205 #define CS35L45_PLL_REFCLK_FREQ_SHIFT           5
 206 #define CS35L45_PLL_REFCLK_FREQ_MASK            GENMASK(10, 5)
 207 #define CS35L45_PLL_REFCLK_EN_SHIFT             4
 208 #define CS35L45_PLL_REFCLK_EN_MASK              BIT(4)
 209 #define CS35L45_PLL_REFCLK_SEL_SHIFT            0
 210 #define CS35L45_PLL_REFCLK_SEL_MASK             GENMASK(2, 0)
 211
 212 #define CS35L45_PLL_REFCLK_SEL_BCLK             0x0
 213
 214 /* GLOBAL_SAMPLE_RATE */
 215 #define CS35L45_GLOBAL_FS_SHIFT                 0
 216 #define CS35L45_GLOBAL_FS_MASK                  GENMASK(4, 0)
 217
 218 #define CS35L45_48P0_KHZ                        0x03
 219 #define CS35L45_96P0_KHZ                        0x04
 220 #define CS35L45_44P100_KHZ                      0x0B
 221 #define CS35L45_88P200_KHZ                      0x0C
 222
 223 /* ASP_ENABLES_1 */
 224 #define CS35L45_ASP_RX2_EN_SHIFT                17
 225 #define CS35L45_ASP_RX1_EN_SHIFT                16
 226 #define CS35L45_ASP_TX5_EN_SHIFT                4
 227 #define CS35L45_ASP_TX4_EN_SHIFT                3
 228 #define CS35L45_ASP_TX3_EN_SHIFT                2
 229 #define CS35L45_ASP_TX2_EN_SHIFT                1
 230 #define CS35L45_ASP_TX1_EN_SHIFT                0
 231
 232 /* ASP_CONTROL2 */
 233 #define CS35L45_ASP_WIDTH_RX_SHIFT              24
 234 #define CS35L45_ASP_WIDTH_RX_MASK               GENMASK(31, 24)
 235 #define CS35L45_ASP_WIDTH_TX_SHIFT              16
 236 #define CS35L45_ASP_WIDTH_TX_MASK               GENMASK(23, 16)
 237 #define CS35L45_ASP_FMT_SHIFT                   8
 238 #define CS35L45_ASP_FMT_MASK                    GENMASK(10, 8)
 239 #define CS35L45_ASP_BCLK_INV_SHIFT              6
 240 #define CS35L45_ASP_BCLK_INV_MASK               BIT(6)
 241 #define CS35L45_ASP_FSYNC_INV_SHIFT             2
 242 #define CS35L45_ASP_FSYNC_INV_MASK              BIT(2)
 243
 244 #define CS35l45_ASP_FMT_DSP_A                   0
 245 #define CS35L45_ASP_FMT_I2S                     2
 246
 247 /* ASP_CONTROL3 */
 248 #define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT         0
 249 #define CS35L45_ASP_DOUT_HIZ_CTRL_MASK          GENMASK(1, 0)
 250
 251 /* ASP_FRAME_CONTROL1 */
 252 #define CS35L45_ASP_TX4_SLOT_SHIFT              24
 253 #define CS35L45_ASP_TX4_SLOT_MASK               GENMASK(29, 24)
 254 #define CS35L45_ASP_TX3_SLOT_SHIFT              16
 255 #define CS35L45_ASP_TX3_SLOT_MASK               GENMASK(21, 16)
 256 #define CS35L45_ASP_TX2_SLOT_SHIFT              8
 257 #define CS35L45_ASP_TX2_SLOT_MASK               GENMASK(13, 8)
 258 #define CS35L45_ASP_TX1_SLOT_SHIFT              0
 259 #define CS35L45_ASP_TX1_SLOT_MASK               GENMASK(5, 0)
 260
 261 #define CS35L45_ASP_TX_ALL_SLOTS                (CS35L45_ASP_TX4_SLOT_MASK | \
 262                                                 CS35L45_ASP_TX3_SLOT_MASK  | \
 263                                                 CS35L45_ASP_TX2_SLOT_MASK  | \
 264                                                 CS35L45_ASP_TX1_SLOT_MASK)
 265 /* ASP_FRAME_CONTROL5 */
 266 #define CS35L45_ASP_RX2_SLOT_SHIFT              8
 267 #define CS35L45_ASP_RX2_SLOT_MASK               GENMASK(13, 8)
 268 #define CS35L45_ASP_RX1_SLOT_SHIFT              0
 269 #define CS35L45_ASP_RX1_SLOT_MASK               GENMASK(5, 0)
 270
 271 #define CS35L45_ASP_RX_ALL_SLOTS                (CS35L45_ASP_RX2_SLOT_MASK | \
 272                                                 CS35L45_ASP_RX1_SLOT_MASK)
 273
 274 /* ASP_DATA_CONTROL1 */
 275 /* ASP_DATA_CONTROL5 */
 276 #define CS35L45_ASP_WL_SHIFT                    0
 277 #define CS35L45_ASP_WL_MASK                     GENMASK(5, 0)
 278
 279 /* HVLV_CONFIG */
 280 #define CS35L45_FORCE_LV_OPERATION              0x01
 281 #define CS35L45_FORCE_HV_OPERATION              0x02
 282 #define CS35L45_HVLV_OPERATION                  0x03
 283 #define CS35L45_HVLV_MODE_SHIFT         0
 284 #define CS35L45_HVLV_MODE_MASK                  GENMASK(1, 0)
 285
 286 /* AMP_PCM_CONTROL */
 287 #define CS35L45_AMP_VOL_PCM_SHIFT               0
 288 #define CS35L45_AMP_VOL_PCM_WIDTH               11
 289
 290 /* AMP_PCM_HPF_TST */
 291 #define CS35l45_HPF_DEFAULT                     0x00000000
 292 #define CS35L45_HPF_44P1                        0x000108BD
 293 #define CS35L45_HPF_88P2                        0x0001045F
 294
 295 /* AMP_GAIN_PCM */
 296 #define CS35L45_AMP_GAIN_PCM_10DBV              0x00
 297 #define CS35L45_AMP_GAIN_PCM_13DBV              0x01
 298 #define CS35L45_AMP_GAIN_PCM_16DBV              0x02
 299 #define CS35L45_AMP_GAIN_PCM_19DBV              0x03
 300
 301 #define CS35L45_AMP_GAIN_PCM_SHIFT              8
 302 #define CS35L45_AMP_GAIN_PCM_MASK               GENMASK(9, 8)
 303
 304 /* IRQ1_EINT_4 */
 305 #define CS35L45_OTP_BOOT_DONE_STS_MASK          BIT(1)
 306 #define CS35L45_OTP_BUSY_MASK                   BIT(0)
 307
 308 /* GPIOX_CTRL1 */
 309 #define CS35L45_GPIO_DIR_SHIFT                  31
 310 #define CS35L45_GPIO_DIR_MASK                   BIT(31)
 311 #define CS35L45_GPIO_LVL_SHIFT                  15
 312 #define CS35L45_GPIO_LVL_MASK                   BIT(15)
 313 #define CS35L45_GPIO_OP_CFG_SHIFT               14
 314 #define CS35L45_GPIO_OP_CFG_MASK                BIT(14)
 315 #define CS35L45_GPIO_POL_SHIFT                  12
 316 #define CS35L45_GPIO_POL_MASK                   BIT(12)
 317
 318 /* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */
 319 #define CS35L45_GPIO_CTRL_SHIFT         20
 320 #define CS35L45_GPIO_CTRL_MASK                  GENMASK(22, 20)
 321 #define CS35L45_GPIO_INVERT_SHIFT               19
 322 #define CS35L45_GPIO_INVERT_MASK                BIT(19)
 323
 324 /* CS35L45_IRQ1_EINT_1 */
 325 #define CS35L45_BST_UVP_ERR_SHIFT               7
 326 #define CS35L45_BST_UVP_ERR_MASK                BIT(7)
 327 #define CS35L45_BST_SHORT_ERR_SHIFT             8
 328 #define CS35L45_BST_SHORT_ERR_MASK              BIT(8)
 329 #define CS35L45_TEMP_ERR_SHIFT                  17
 330 #define CS35L45_TEMP_ERR_MASK                   BIT(17)
 331 #define CS35L45_MSM_GLOBAL_EN_ASSERT_SHIFT      22
 332 #define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK       BIT(22)
 333 #define CS35L45_UVLO_VDDBATT_ERR_SHIFT  29
 334 #define CS35L45_UVLO_VDDBATT_ERR_MASK           BIT(29)
 335 #define CS35L45_AMP_SHORT_ERR_SHIFT             31
 336 #define CS35L45_AMP_SHORT_ERR_MASK              BIT(31)
 337
 338 /* CS35L45_IRQ1_EINT_2 */
 339 #define CS35L45_DSP_WDT_EXPIRE_SHIFT            4
 340 #define CS35L45_DSP_WDT_EXPIRE_MASK             BIT(4)
 341 #define CS35L45_DSP_VIRT2_MBOX_SHIFT            21
 342 #define CS35L45_DSP_VIRT2_MBOX_MASK             BIT(21)
 343
 344 /* CS35L45_IRQ1_EINT_3 */
 345 #define CS35L45_PLL_LOCK_FLAG_SHIFT             1
 346 #define CS35L45_PLL_LOCK_FLAG_MASK              BIT(1)
 347 #define CS35L45_PLL_UNLOCK_FLAG_RISE_SHIFT      4
 348 #define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK       BIT(4)
 349 #define CS35L45_AMP_CAL_ERR_SHIFT               25
 350 #define CS35L45_AMP_CAL_ERR_MASK                BIT(25)
 351
 352 /* CS35L45_IRQ1_EINT_18 */
 353 #define CS35L45_GLOBAL_ERROR_SHIFT              15
 354 #define CS35L45_GLOBAL_ERROR_MASK               BIT(15)
 355 #define CS35L45_UVLO_VDDLV_ERR_SHIFT            16
 356 #define CS35L45_UVLO_VDDLV_ERR_MASK             BIT(16)
 357
 358 /* Mixer sources */
 359 #define CS35L45_PCM_SRC_MASK                    0x7F
 360 #define CS35L45_PCM_SRC_ZERO                    0x00
 361 #define CS35L45_PCM_SRC_ASP_RX1                 0x08
 362 #define CS35L45_PCM_SRC_ASP_RX2                 0x09
 363 #define CS35L45_PCM_SRC_VMON                    0x18
 364 #define CS35L45_PCM_SRC_IMON                    0x19
 365 #define CS35L45_PCM_SRC_ERR_VOL                 0x20
 366 #define CS35L45_PCM_SRC_CLASSH_TGT              0x21
 367 #define CS35L45_PCM_SRC_VDD_BATTMON             0x28
 368 #define CS35L45_PCM_SRC_VDD_BSTMON              0x29
 369 #define CS35L45_PCM_SRC_DSP_TX1                 0x32
 370 #define CS35L45_PCM_SRC_DSP_TX2                 0x33
 371 #define CS35L45_PCM_SRC_TEMPMON                 0x3A
 372 #define CS35L45_PCM_SRC_INTERPOLATOR            0x40
 373 #define CS35L45_PCM_SRC_IL_TARGET               0x48
 374
 375 #define CS35L45_RESET_HOLD_US                   2000
 376 #define CS35L45_RESET_US                        2000
 377 #define CS35L45_POST_GLOBAL_EN_US               5000
 378 #define CS35L45_PRE_GLOBAL_DIS_US               3000
 379
 380 /* WAKESRC_CTL */
 381 #define CS35L45_WKSRC_SYNC_GPIO1                BIT(0)
 382 #define CS35L45_WKSRC_INT_GPIO2                 BIT(1)
 383 #define CS35L45_WKSRC_GPIO3                     BIT(2)
 384 #define CS35L45_WKSRC_SPI                       BIT(3)
 385 #define CS35L45_WKSRC_I2C                       BIT(4)
 386 #define CS35L45_UPDT_WKCTL_SHIFT                15
 387 #define CS35L45_UPDT_WKCTL_MASK                 BIT(15)
 388 #define CS35L45_WKSRC_EN_SHIFT                  8
 389 #define CS35L45_WKSRC_EN_MASK                   GENMASK(12, 8)
 390 #define CS35L45_WKSRC_POL_SHIFT                 0
 391 #define CS35L45_WKSRC_POL_MASK                  GENMASK(3, 0)
 392
 393 /* WAKEI2C_CTL */
 394 #define CS35L45_UPDT_WKI2C_SHIFT                15
 395 #define CS35L45_UPDT_WKI2C_MASK                 BIT(15)
 396 #define CS35L45_WKI2C_ADDR_SHIFT                0
 397 #define CS35L45_WKI2C_ADDR_MASK                 GENMASK(6, 0)
 398
 399 #define CS35L45_SPI_MAX_FREQ                    4000000
 400
 401 enum cs35l45_cspl_mboxstate {
 402         CSPL_MBOX_STS_RUNNING = 0,
 403         CSPL_MBOX_STS_PAUSED = 1,
 404         CSPL_MBOX_STS_RDY_FOR_REINIT = 2,
 405         CSPL_MBOX_STS_HIBERNATE = 3,
 406 };
 407
 408 enum cs35l45_cspl_mboxcmd {
 409         CSPL_MBOX_CMD_NONE = 0,
 410         CSPL_MBOX_CMD_PAUSE = 1,
 411         CSPL_MBOX_CMD_RESUME = 2,
 412         CSPL_MBOX_CMD_REINIT = 3,
 413         CSPL_MBOX_CMD_STOP_PRE_REINIT = 4,
 414         CSPL_MBOX_CMD_HIBERNATE = 5,
 415         CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6,
 416         CSPL_MBOX_CMD_UNKNOWN_CMD = -1,
 417         CSPL_MBOX_CMD_INVALID_SEQUENCE = -2,
 418 };
 419
 420 enum control_bus_type {
 421         CONTROL_BUS_I2C = 0,
 422         CONTROL_BUS_SPI = 1,
 423 };
 424
 425 enum amp_mode {
 426         AMP_MODE_SPK  = 0,
 427         AMP_MODE_RCV  = 1,
 428 };
 429
 430 #define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 431                          SNDRV_PCM_FMTBIT_S24_3LE| \
 432                          SNDRV_PCM_FMTBIT_S24_LE)
 433
 434 #define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \
 435                        SNDRV_PCM_RATE_48000 | \
 436                        SNDRV_PCM_RATE_88200 | \
 437                        SNDRV_PCM_RATE_96000)
 438
 439 /*
 440  * IRQs
 441  */
 442 #define CS35L45_IRQ(_irq, _name, _hand)         \
 443         {                                       \
 444                 .irq = CS35L45_ ## _irq ## _IRQ,\
 445                 .name = _name,                  \
 446                 .handler = _hand,               \
 447         }
 448
 449 struct cs35l45_irq {
 450         int irq;
 451         const char *name;
 452         irqreturn_t (*handler)(int irq, void *data);
 453 };
 454
 455 #define CS35L45_REG_IRQ(_reg, _irq)                                     \
 456         [CS35L45_ ## _irq ## _IRQ] = {                                  \
 457                 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \
 458                 .mask = CS35L45_ ## _irq ## _MASK                       \
 459         }
 460
 461 enum cs35l45_irq_list {
 462         CS35L45_AMP_SHORT_ERR_IRQ,
 463         CS35L45_UVLO_VDDBATT_ERR_IRQ,
 464         CS35L45_BST_SHORT_ERR_IRQ,
 465         CS35L45_BST_UVP_ERR_IRQ,
 466         CS35L45_TEMP_ERR_IRQ,
 467         CS35L45_AMP_CAL_ERR_IRQ,
 468         CS35L45_UVLO_VDDLV_ERR_IRQ,
 469         CS35L45_GLOBAL_ERROR_IRQ,
 470         CS35L45_DSP_WDT_EXPIRE_IRQ,
 471         CS35L45_PLL_UNLOCK_FLAG_RISE_IRQ,
 472         CS35L45_PLL_LOCK_FLAG_IRQ,
 473         CS35L45_DSP_VIRT2_MBOX_IRQ,
 474         CS35L45_NUM_IRQ
 475 };
 476
 477 #define CS35L45_MBOX3_CMD_MASK          0xFF
 478 #define CS35L45_MBOX3_CMD_SHIFT         0
 479 #define CS35L45_MBOX3_DATA_MASK         0xFFFFFF00
 480 #define CS35L45_MBOX3_DATA_SHIFT        8
 481
 482 enum mbox3_events {
 483         EVENT_SPEAKER_STATUS = 0x66,
 484         EVENT_BOOT_DONE = 0x67,
 485 };
 486
 487 struct cs35l45_private {
 488         struct wm_adsp dsp; /* needs to be first member */
 489         struct device *dev;
 490         struct regmap *regmap;
 491         struct gpio_desc *reset_gpio;
 492         struct regulator *vdd_batt;
 493         struct regulator *vdd_a;
 494         bool initialized;
 495         bool sysclk_set;
 496         u8 slot_width;
 497         u8 slot_count;
 498         int amplifier_mode;
 499         int irq_invert;
 500         int irq;
 501         unsigned int i2c_addr;
 502         enum control_bus_type bus_type;
 503         struct regmap_irq_chip_data *irq_data;
 504 };
 505
 506 extern const struct dev_pm_ops cs35l45_pm_ops;
 507 extern const struct regmap_config cs35l45_i2c_regmap;
 508 extern const struct regmap_config cs35l45_spi_regmap;
 509 int cs35l45_apply_patch(struct cs35l45_private *cs35l45);
 510 unsigned int cs35l45_get_clk_freq_id(unsigned int freq);
 511 int cs35l45_probe(struct cs35l45_private *cs35l45);
 512 void cs35l45_remove(struct cs35l45_private *cs35l45);
 513
 514 #endif /* CS35L45_H */