sound/soc/codecs/cs35l45.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * cs35l45.h - CS35L45 ALSA SoC audio driver
   4  *
   5  * Copyright 2019-2022 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  *
   9  */
  10
  11 #ifndef CS35L45_H
  12 #define CS35L45_H
  13
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17
  18 #define CS35L45_DEVID                           0x00000000
  19 #define CS35L45_REVID                           0x00000004
  20 #define CS35L45_RELID                           0x0000000C
  21 #define CS35L45_OTPID                           0x00000010
  22 #define CS35L45_SFT_RESET                       0x00000020
  23 #define CS35L45_GLOBAL_ENABLES                  0x00002014
  24 #define CS35L45_BLOCK_ENABLES                   0x00002018
  25 #define CS35L45_BLOCK_ENABLES2                  0x0000201C
  26 #define CS35L45_ERROR_RELEASE                   0x00002034
  27 #define CS35L45_REFCLK_INPUT                    0x00002C04
  28 #define CS35L45_GLOBAL_SAMPLE_RATE              0x00002C0C
  29 #define CS35L45_BOOST_CCM_CFG                   0x00003808
  30 #define CS35L45_BOOST_DCM_CFG                   0x0000380C
  31 #define CS35L45_BOOST_OV_CFG                    0x0000382C
  32 #define CS35L45_ASP_ENABLES1                    0x00004800
  33 #define CS35L45_ASP_CONTROL1                    0x00004804
  34 #define CS35L45_ASP_CONTROL2                    0x00004808
  35 #define CS35L45_ASP_CONTROL3                    0x0000480C
  36 #define CS35L45_ASP_FRAME_CONTROL1              0x00004810
  37 #define CS35L45_ASP_FRAME_CONTROL2              0x00004814
  38 #define CS35L45_ASP_FRAME_CONTROL5              0x00004820
  39 #define CS35L45_ASP_DATA_CONTROL1               0x00004830
  40 #define CS35L45_ASP_DATA_CONTROL5               0x00004840
  41 #define CS35L45_DACPCM1_INPUT                   0x00004C00
  42 #define CS35L45_ASPTX1_INPUT                    0x00004C20
  43 #define CS35L45_ASPTX2_INPUT                    0x00004C24
  44 #define CS35L45_ASPTX3_INPUT                    0x00004C28
  45 #define CS35L45_ASPTX4_INPUT                    0x00004C2C
  46 #define CS35L45_ASPTX5_INPUT                    0x00004C30
  47 #define CS35L45_LDPM_CONFIG                     0x00006404
  48 #define CS35L45_AMP_PCM_CONTROL                 0x00007000
  49 #define CS35L45_AMP_PCM_HPF_TST                 0x00007004
  50 #define CS35L45_IRQ1_EINT_4                     0x0000E01C
  51 #define CS35L45_LASTREG                         0x0000E01C
  52
  53 /* SFT_RESET */
  54 #define CS35L45_SOFT_RESET_TRIGGER              0x5A000000
  55
  56 /* GLOBAL_ENABLES */
  57 #define CS35L45_GLOBAL_EN_SHIFT                 0
  58 #define CS35L45_GLOBAL_EN_MASK                  BIT(0)
  59
  60 /* BLOCK_ENABLES */
  61 #define CS35L45_IMON_EN_SHIFT                   13
  62 #define CS35L45_VMON_EN_SHIFT                   12
  63 #define CS35L45_VDD_BSTMON_EN_SHIFT             9
  64 #define CS35L45_VDD_BATTMON_EN_SHIFT            8
  65 #define CS35L45_BST_EN_SHIFT                    4
  66 #define CS35L45_BST_EN_MASK                     GENMASK(5, 4)
  67
  68 #define CS35L45_BST_DISABLE_FET_ON              0x01
  69
  70 /* BLOCK_ENABLES2 */
  71 #define CS35L45_ASP_EN_SHIFT                    27
  72
  73 /* ERROR_RELEASE */
  74 #define CS35L45_GLOBAL_ERR_RLS_MASK             BIT(11)
  75
  76 /* REFCLK_INPUT */
  77 #define CS35L45_PLL_FORCE_EN_SHIFT              16
  78 #define CS35L45_PLL_FORCE_EN_MASK               BIT(16)
  79 #define CS35L45_PLL_OPEN_LOOP_SHIFT             11
  80 #define CS35L45_PLL_OPEN_LOOP_MASK              BIT(11)
  81 #define CS35L45_PLL_REFCLK_FREQ_SHIFT           5
  82 #define CS35L45_PLL_REFCLK_FREQ_MASK            GENMASK(10, 5)
  83 #define CS35L45_PLL_REFCLK_EN_SHIFT             4
  84 #define CS35L45_PLL_REFCLK_EN_MASK              BIT(4)
  85 #define CS35L45_PLL_REFCLK_SEL_SHIFT            0
  86 #define CS35L45_PLL_REFCLK_SEL_MASK             GENMASK(2, 0)
  87
  88 #define CS35L45_PLL_REFCLK_SEL_BCLK             0x0
  89
  90 /* GLOBAL_SAMPLE_RATE */
  91 #define CS35L45_GLOBAL_FS_SHIFT                 0
  92 #define CS35L45_GLOBAL_FS_MASK                  GENMASK(4, 0)
  93
  94 #define CS35L45_48P0_KHZ                        0x03
  95 #define CS35L45_96P0_KHZ                        0x04
  96 #define CS35L45_44P100_KHZ                      0x0B
  97 #define CS35L45_88P200_KHZ                      0x0C
  98
  99 /* ASP_ENABLES_1 */
 100 #define CS35L45_ASP_RX2_EN_SHIFT                17
 101 #define CS35L45_ASP_RX1_EN_SHIFT                16
 102 #define CS35L45_ASP_TX5_EN_SHIFT                4
 103 #define CS35L45_ASP_TX4_EN_SHIFT                3
 104 #define CS35L45_ASP_TX3_EN_SHIFT                2
 105 #define CS35L45_ASP_TX2_EN_SHIFT                1
 106 #define CS35L45_ASP_TX1_EN_SHIFT                0
 107
 108 /* ASP_CONTROL2 */
 109 #define CS35L45_ASP_WIDTH_RX_SHIFT              24
 110 #define CS35L45_ASP_WIDTH_RX_MASK               GENMASK(31, 24)
 111 #define CS35L45_ASP_WIDTH_TX_SHIFT              16
 112 #define CS35L45_ASP_WIDTH_TX_MASK               GENMASK(23, 16)
 113 #define CS35L45_ASP_FMT_SHIFT                   8
 114 #define CS35L45_ASP_FMT_MASK                    GENMASK(10, 8)
 115 #define CS35L45_ASP_BCLK_INV_SHIFT              6
 116 #define CS35L45_ASP_BCLK_INV_MASK               BIT(6)
 117 #define CS35L45_ASP_FSYNC_INV_SHIFT             2
 118 #define CS35L45_ASP_FSYNC_INV_MASK              BIT(2)
 119
 120 #define CS35l45_ASP_FMT_DSP_A                   0
 121 #define CS35L45_ASP_FMT_I2S                     2
 122
 123 /* ASP_CONTROL3 */
 124 #define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT         0
 125 #define CS35L45_ASP_DOUT_HIZ_CTRL_MASK          GENMASK(1, 0)
 126
 127 /* ASP_FRAME_CONTROL1 */
 128 #define CS35L45_ASP_TX4_SLOT_SHIFT              24
 129 #define CS35L45_ASP_TX4_SLOT_MASK               GENMASK(29, 24)
 130 #define CS35L45_ASP_TX3_SLOT_SHIFT              16
 131 #define CS35L45_ASP_TX3_SLOT_MASK               GENMASK(21, 16)
 132 #define CS35L45_ASP_TX2_SLOT_SHIFT              8
 133 #define CS35L45_ASP_TX2_SLOT_MASK               GENMASK(13, 8)
 134 #define CS35L45_ASP_TX1_SLOT_SHIFT              0
 135 #define CS35L45_ASP_TX1_SLOT_MASK               GENMASK(5, 0)
 136
 137 #define CS35L45_ASP_TX_ALL_SLOTS                (CS35L45_ASP_TX4_SLOT_MASK | \
 138                                                 CS35L45_ASP_TX3_SLOT_MASK  | \
 139                                                 CS35L45_ASP_TX2_SLOT_MASK  | \
 140                                                 CS35L45_ASP_TX1_SLOT_MASK)
 141 /* ASP_FRAME_CONTROL5 */
 142 #define CS35L45_ASP_RX2_SLOT_SHIFT              8
 143 #define CS35L45_ASP_RX2_SLOT_MASK               GENMASK(13, 8)
 144 #define CS35L45_ASP_RX1_SLOT_SHIFT              0
 145 #define CS35L45_ASP_RX1_SLOT_MASK               GENMASK(5, 0)
 146
 147 #define CS35L45_ASP_RX_ALL_SLOTS                (CS35L45_ASP_RX2_SLOT_MASK | \
 148                                                 CS35L45_ASP_RX1_SLOT_MASK)
 149
 150 /* ASP_DATA_CONTROL1 */
 151 /* ASP_DATA_CONTROL5 */
 152 #define CS35L45_ASP_WL_SHIFT                    0
 153 #define CS35L45_ASP_WL_MASK                     GENMASK(5, 0)
 154
 155 /* AMP_PCM_CONTROL */
 156 #define CS35L45_AMP_VOL_PCM_SHIFT               0
 157 #define CS35L45_AMP_VOL_PCM_WIDTH               11
 158
 159 /* AMP_PCM_HPF_TST */
 160 #define CS35l45_HPF_DEFAULT                     0x00000000
 161 #define CS35L45_HPF_44P1                        0x000108BD
 162 #define CS35L45_HPF_88P2                        0x0001045F
 163
 164 /* IRQ1_EINT_4 */
 165 #define CS35L45_OTP_BOOT_DONE_STS_MASK          BIT(1)
 166 #define CS35L45_OTP_BUSY_MASK                   BIT(0)
 167
 168 /* Mixer sources */
 169 #define CS35L45_PCM_SRC_MASK                    0x7F
 170 #define CS35L45_PCM_SRC_ZERO                    0x00
 171 #define CS35L45_PCM_SRC_ASP_RX1                 0x08
 172 #define CS35L45_PCM_SRC_ASP_RX2                 0x09
 173 #define CS35L45_PCM_SRC_VMON                    0x18
 174 #define CS35L45_PCM_SRC_IMON                    0x19
 175 #define CS35L45_PCM_SRC_ERR_VOL                 0x20
 176 #define CS35L45_PCM_SRC_CLASSH_TGT              0x21
 177 #define CS35L45_PCM_SRC_VDD_BATTMON             0x28
 178 #define CS35L45_PCM_SRC_VDD_BSTMON              0x29
 179 #define CS35L45_PCM_SRC_TEMPMON                 0x3A
 180 #define CS35L45_PCM_SRC_INTERPOLATOR            0x40
 181 #define CS35L45_PCM_SRC_IL_TARGET               0x48
 182
 183 #define CS35L45_RESET_HOLD_US                   2000
 184 #define CS35L45_RESET_US                        2000
 185 #define CS35L45_POST_GLOBAL_EN_US               5000
 186 #define CS35L45_PRE_GLOBAL_DIS_US               3000
 187
 188 #define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 189                          SNDRV_PCM_FMTBIT_S24_3LE| \
 190                          SNDRV_PCM_FMTBIT_S24_LE)
 191
 192 #define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \
 193                        SNDRV_PCM_RATE_48000 | \
 194                        SNDRV_PCM_RATE_88200 | \
 195                        SNDRV_PCM_RATE_96000)
 196
 197 struct cs35l45_private {
 198         struct device *dev;
 199         struct regmap *regmap;
 200         struct gpio_desc *reset_gpio;
 201         struct regulator *vdd_batt;
 202         struct regulator *vdd_a;
 203         bool initialized;
 204         bool sysclk_set;
 205         u8 slot_width;
 206         u8 slot_count;
 207 };
 208
 209 extern const struct dev_pm_ops cs35l45_pm_ops;
 210 extern const struct regmap_config cs35l45_i2c_regmap;
 211 extern const struct regmap_config cs35l45_spi_regmap;
 212 int cs35l45_apply_patch(struct cs35l45_private *cs43l45);
 213 unsigned int cs35l45_get_clk_freq_id(unsigned int freq);
 214 int cs35l45_probe(struct cs35l45_private *cs35l45);
 215 int cs35l45_remove(struct cs35l45_private *cs35l45);
 216
 217 #endif /* CS35L45_H */