sound/soc/codecs/cs35l33.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs35l33.c -- CS35L33 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: Paul Handrigan <paul.handrigan@cirrus.com>
   8  */
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/platform_device.h>
  18 #include <sound/core.h>
  19 #include <sound/pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/soc.h>
  22 #include <sound/soc-dapm.h>
  23 #include <sound/initval.h>
  24 #include <sound/tlv.h>
  25 #include <linux/gpio.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <sound/cs35l33.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/regulator/machine.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of.h>
  33
  34 #include "cs35l33.h"
  35 #include "cirrus_legacy.h"
  36
  37 #define CS35L33_BOOT_DELAY      50
  38
  39 struct cs35l33_private {
  40         struct snd_soc_component *component;
  41         struct cs35l33_pdata pdata;
  42         struct regmap *regmap;
  43         struct gpio_desc *reset_gpio;
  44         bool amp_cal;
  45         int mclk_int;
  46         struct regulator_bulk_data core_supplies[2];
  47         int num_core_supplies;
  48         bool is_tdm_mode;
  49         bool enable_soft_ramp;
  50 };
  51
  52 static const struct reg_default cs35l33_reg[] = {
  53         {CS35L33_PWRCTL1, 0x85},
  54         {CS35L33_PWRCTL2, 0xFE},
  55         {CS35L33_CLK_CTL, 0x0C},
  56         {CS35L33_BST_PEAK_CTL, 0x90},
  57         {CS35L33_PROTECT_CTL, 0x55},
  58         {CS35L33_BST_CTL1, 0x00},
  59         {CS35L33_BST_CTL2, 0x01},
  60         {CS35L33_ADSP_CTL, 0x00},
  61         {CS35L33_ADC_CTL, 0xC8},
  62         {CS35L33_DAC_CTL, 0x14},
  63         {CS35L33_DIG_VOL_CTL, 0x00},
  64         {CS35L33_CLASSD_CTL, 0x04},
  65         {CS35L33_AMP_CTL, 0x90},
  66         {CS35L33_INT_MASK_1, 0xFF},
  67         {CS35L33_INT_MASK_2, 0xFF},
  68         {CS35L33_DIAG_LOCK, 0x00},
  69         {CS35L33_DIAG_CTRL_1, 0x40},
  70         {CS35L33_DIAG_CTRL_2, 0x00},
  71         {CS35L33_HG_MEMLDO_CTL, 0x62},
  72         {CS35L33_HG_REL_RATE, 0x03},
  73         {CS35L33_LDO_DEL, 0x12},
  74         {CS35L33_HG_HEAD, 0x0A},
  75         {CS35L33_HG_EN, 0x05},
  76         {CS35L33_TX_VMON, 0x00},
  77         {CS35L33_TX_IMON, 0x03},
  78         {CS35L33_TX_VPMON, 0x02},
  79         {CS35L33_TX_VBSTMON, 0x05},
  80         {CS35L33_TX_FLAG, 0x06},
  81         {CS35L33_TX_EN1, 0x00},
  82         {CS35L33_TX_EN2, 0x00},
  83         {CS35L33_TX_EN3, 0x00},
  84         {CS35L33_TX_EN4, 0x00},
  85         {CS35L33_RX_AUD, 0x40},
  86         {CS35L33_RX_SPLY, 0x03},
  87         {CS35L33_RX_ALIVE, 0x04},
  88         {CS35L33_BST_CTL4, 0x63},
  89 };
  90
  91 static const struct reg_sequence cs35l33_patch[] = {
  92         { 0x00,  0x99, 0 },
  93         { 0x59,  0x02, 0 },
  94         { 0x52,  0x30, 0 },
  95         { 0x39,  0x45, 0 },
  96         { 0x57,  0x30, 0 },
  97         { 0x2C,  0x68, 0 },
  98         { 0x00,  0x00, 0 },
  99 };
 100
 101 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg)
 102 {
 103         switch (reg) {
 104         case CS35L33_DEVID_AB:
 105         case CS35L33_DEVID_CD:
 106         case CS35L33_DEVID_E:
 107         case CS35L33_REV_ID:
 108         case CS35L33_INT_STATUS_1:
 109         case CS35L33_INT_STATUS_2:
 110         case CS35L33_HG_STATUS:
 111                 return true;
 112         default:
 113                 return false;
 114         }
 115 }
 116
 117 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg)
 118 {
 119         switch (reg) {
 120         /* these are read only registers */
 121         case CS35L33_DEVID_AB:
 122         case CS35L33_DEVID_CD:
 123         case CS35L33_DEVID_E:
 124         case CS35L33_REV_ID:
 125         case CS35L33_INT_STATUS_1:
 126         case CS35L33_INT_STATUS_2:
 127         case CS35L33_HG_STATUS:
 128                 return false;
 129         default:
 130                 return true;
 131         }
 132 }
 133
 134 static bool cs35l33_readable_register(struct device *dev, unsigned int reg)
 135 {
 136         switch (reg) {
 137         case CS35L33_DEVID_AB:
 138         case CS35L33_DEVID_CD:
 139         case CS35L33_DEVID_E:
 140         case CS35L33_REV_ID:
 141         case CS35L33_PWRCTL1:
 142         case CS35L33_PWRCTL2:
 143         case CS35L33_CLK_CTL:
 144         case CS35L33_BST_PEAK_CTL:
 145         case CS35L33_PROTECT_CTL:
 146         case CS35L33_BST_CTL1:
 147         case CS35L33_BST_CTL2:
 148         case CS35L33_ADSP_CTL:
 149         case CS35L33_ADC_CTL:
 150         case CS35L33_DAC_CTL:
 151         case CS35L33_DIG_VOL_CTL:
 152         case CS35L33_CLASSD_CTL:
 153         case CS35L33_AMP_CTL:
 154         case CS35L33_INT_MASK_1:
 155         case CS35L33_INT_MASK_2:
 156         case CS35L33_INT_STATUS_1:
 157         case CS35L33_INT_STATUS_2:
 158         case CS35L33_DIAG_LOCK:
 159         case CS35L33_DIAG_CTRL_1:
 160         case CS35L33_DIAG_CTRL_2:
 161         case CS35L33_HG_MEMLDO_CTL:
 162         case CS35L33_HG_REL_RATE:
 163         case CS35L33_LDO_DEL:
 164         case CS35L33_HG_HEAD:
 165         case CS35L33_HG_EN:
 166         case CS35L33_TX_VMON:
 167         case CS35L33_TX_IMON:
 168         case CS35L33_TX_VPMON:
 169         case CS35L33_TX_VBSTMON:
 170         case CS35L33_TX_FLAG:
 171         case CS35L33_TX_EN1:
 172         case CS35L33_TX_EN2:
 173         case CS35L33_TX_EN3:
 174         case CS35L33_TX_EN4:
 175         case CS35L33_RX_AUD:
 176         case CS35L33_RX_SPLY:
 177         case CS35L33_RX_ALIVE:
 178         case CS35L33_BST_CTL4:
 179                 return true;
 180         default:
 181                 return false;
 182         }
 183 }
 184
 185 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0);
 186 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0);
 187
 188 static const struct snd_kcontrol_new cs35l33_snd_controls[] = {
 189
 190         SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL,
 191                        4, 0x09, 0, classd_ctl_tlv),
 192         SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL,
 193                         0, 0x34, 0xE4, dac_tlv),
 194 };
 195
 196 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w,
 197         struct snd_kcontrol *kcontrol, int event)
 198 {
 199         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 200         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 201
 202         switch (event) {
 203         case SND_SOC_DAPM_POST_PMU:
 204                 if (!priv->amp_cal) {
 205                         usleep_range(8000, 9000);
 206                         priv->amp_cal = true;
 207                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
 208                                     CS35L33_AMP_CAL, 0);
 209                         dev_dbg(component->dev, "Amp calibration done\n");
 210                 }
 211                 dev_dbg(component->dev, "Amp turned on\n");
 212                 break;
 213         case SND_SOC_DAPM_POST_PMD:
 214                 dev_dbg(component->dev, "Amp turned off\n");
 215                 break;
 216         default:
 217                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
 218                 break;
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w,
 225         struct snd_kcontrol *kcontrol, int event)
 226 {
 227         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 228         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 229         unsigned int val;
 230
 231         switch (event) {
 232         case SND_SOC_DAPM_PRE_PMU:
 233                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 234                                     CS35L33_PDN_BST, 0);
 235                 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM;
 236                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 237                                     CS35L33_PDN_TDM, val);
 238                 dev_dbg(component->dev, "BST turned on\n");
 239                 break;
 240         case SND_SOC_DAPM_POST_PMU:
 241                 dev_dbg(component->dev, "SDIN turned on\n");
 242                 if (!priv->amp_cal) {
 243                         regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL,
 244                                     CS35L33_AMP_CAL, CS35L33_AMP_CAL);
 245                         dev_dbg(component->dev, "Amp calibration started\n");
 246                         usleep_range(10000, 11000);
 247                 }
 248                 break;
 249         case SND_SOC_DAPM_POST_PMD:
 250                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 251                                     CS35L33_PDN_TDM, CS35L33_PDN_TDM);
 252                 usleep_range(4000, 4100);
 253                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 254                                     CS35L33_PDN_BST, CS35L33_PDN_BST);
 255                 dev_dbg(component->dev, "BST and SDIN turned off\n");
 256                 break;
 257         default:
 258                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
 259
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w,
 266         struct snd_kcontrol *kcontrol, int event)
 267 {
 268         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 269         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 270         unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
 271         unsigned int mask2 = CS35L33_SDOUT_3ST_TDM;
 272         unsigned int val, val2;
 273
 274         switch (event) {
 275         case SND_SOC_DAPM_PRE_PMU:
 276                 if (priv->is_tdm_mode) {
 277                         /* set sdout_3st_i2s and reset pdn_tdm */
 278                         val = CS35L33_SDOUT_3ST_I2S;
 279                         /* reset sdout_3st_tdm */
 280                         val2 = 0;
 281                 } else {
 282                         /* reset sdout_3st_i2s and set pdn_tdm */
 283                         val = CS35L33_PDN_TDM;
 284                         /* set sdout_3st_tdm */
 285                         val2 = CS35L33_SDOUT_3ST_TDM;
 286                 }
 287                 dev_dbg(component->dev, "SDOUT turned on\n");
 288                 break;
 289         case SND_SOC_DAPM_PRE_PMD:
 290                 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM;
 291                 val2 = CS35L33_SDOUT_3ST_TDM;
 292                 dev_dbg(component->dev, "SDOUT turned off\n");
 293                 break;
 294         default:
 295                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
 296                 return 0;
 297         }
 298
 299         regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 300                 mask, val);
 301         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 302                 mask2, val2);
 303
 304         return 0;
 305 }
 306
 307 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = {
 308
 309         SND_SOC_DAPM_OUTPUT("SPK"),
 310         SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0,
 311                 cs35l33_spkrdrv_event,
 312                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 313         SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2,
 314                 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU |
 315                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 316
 317         SND_SOC_DAPM_INPUT("MON"),
 318
 319         SND_SOC_DAPM_ADC("VMON", NULL,
 320                 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1),
 321         SND_SOC_DAPM_ADC("IMON", NULL,
 322                 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1),
 323         SND_SOC_DAPM_ADC("VPMON", NULL,
 324                 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1),
 325         SND_SOC_DAPM_ADC("VBSTMON", NULL,
 326                 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1),
 327
 328         SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0,
 329                 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU |
 330                 SND_SOC_DAPM_PRE_PMD),
 331 };
 332
 333 static const struct snd_soc_dapm_route cs35l33_audio_map[] = {
 334         {"SDIN", NULL, "CS35L33 Playback"},
 335         {"SPKDRV", NULL, "SDIN"},
 336         {"SPK", NULL, "SPKDRV"},
 337
 338         {"VMON", NULL, "MON"},
 339         {"IMON", NULL, "MON"},
 340
 341         {"SDOUT", NULL, "VMON"},
 342         {"SDOUT", NULL, "IMON"},
 343         {"CS35L33 Capture", NULL, "SDOUT"},
 344 };
 345
 346 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = {
 347         {"SPKDRV", NULL, "VPMON"},
 348         {"VPMON", NULL, "CS35L33 Playback"},
 349 };
 350
 351 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = {
 352         {"SDOUT", NULL, "VPMON"},
 353         {"VPMON", NULL, "MON"},
 354         {"SDOUT", NULL, "VBSTMON"},
 355         {"VBSTMON", NULL, "MON"},
 356 };
 357
 358 static int cs35l33_set_bias_level(struct snd_soc_component *component,
 359                                   enum snd_soc_bias_level level)
 360 {
 361         unsigned int val;
 362         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 363
 364         switch (level) {
 365         case SND_SOC_BIAS_ON:
 366                 break;
 367         case SND_SOC_BIAS_PREPARE:
 368                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 369                                     CS35L33_PDN_ALL, 0);
 370                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 371                                     CS35L33_MCLKDIS, 0);
 372                 break;
 373         case SND_SOC_BIAS_STANDBY:
 374                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1,
 375                                     CS35L33_PDN_ALL, CS35L33_PDN_ALL);
 376                 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val);
 377                 usleep_range(1000, 1100);
 378                 if (val & CS35L33_PDN_DONE)
 379                         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 380                                             CS35L33_MCLKDIS, CS35L33_MCLKDIS);
 381                 break;
 382         case SND_SOC_BIAS_OFF:
 383                 break;
 384         default:
 385                 return -EINVAL;
 386         }
 387
 388         return 0;
 389 }
 390
 391 struct cs35l33_mclk_div {
 392         int mclk;
 393         int srate;
 394         u8 adsp_rate;
 395         u8 int_fs_ratio;
 396 };
 397
 398 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = {
 399         /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */
 400         {5644800, 11025, 0x4, CS35L33_INT_FS_RATE},
 401         {5644800, 22050, 0x8, CS35L33_INT_FS_RATE},
 402         {5644800, 44100, 0xC, CS35L33_INT_FS_RATE},
 403
 404         {6000000,  8000, 0x1, 0},
 405         {6000000, 11025, 0x2, 0},
 406         {6000000, 11029, 0x3, 0},
 407         {6000000, 12000, 0x4, 0},
 408         {6000000, 16000, 0x5, 0},
 409         {6000000, 22050, 0x6, 0},
 410         {6000000, 22059, 0x7, 0},
 411         {6000000, 24000, 0x8, 0},
 412         {6000000, 32000, 0x9, 0},
 413         {6000000, 44100, 0xA, 0},
 414         {6000000, 44118, 0xB, 0},
 415         {6000000, 48000, 0xC, 0},
 416
 417         {6144000,  8000, 0x1, CS35L33_INT_FS_RATE},
 418         {6144000, 12000, 0x4, CS35L33_INT_FS_RATE},
 419         {6144000, 16000, 0x5, CS35L33_INT_FS_RATE},
 420         {6144000, 24000, 0x8, CS35L33_INT_FS_RATE},
 421         {6144000, 32000, 0x9, CS35L33_INT_FS_RATE},
 422         {6144000, 48000, 0xC, CS35L33_INT_FS_RATE},
 423 };
 424
 425 static int cs35l33_get_mclk_coeff(int mclk, int srate)
 426 {
 427         int i;
 428
 429         for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) {
 430                 if (cs35l33_mclk_coeffs[i].mclk == mclk &&
 431                         cs35l33_mclk_coeffs[i].srate == srate)
 432                         return i;
 433         }
 434         return -EINVAL;
 435 }
 436
 437 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 438 {
 439         struct snd_soc_component *component = codec_dai->component;
 440         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 441
 442         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 443         case SND_SOC_DAIFMT_CBM_CFM:
 444                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
 445                         CS35L33_MS_MASK, CS35L33_MS_MASK);
 446                 dev_dbg(component->dev, "Audio port in master mode\n");
 447                 break;
 448         case SND_SOC_DAIFMT_CBS_CFS:
 449                 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL,
 450                         CS35L33_MS_MASK, 0);
 451                 dev_dbg(component->dev, "Audio port in slave mode\n");
 452                 break;
 453         default:
 454                 return -EINVAL;
 455         }
 456
 457         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 458         case SND_SOC_DAIFMT_DSP_A:
 459                 /*
 460                  * tdm mode in cs35l33 resembles dsp-a mode very
 461                  * closely, it is dsp-a with fsync shifted left by half bclk
 462                  */
 463                 priv->is_tdm_mode = true;
 464                 dev_dbg(component->dev, "Audio port in TDM mode\n");
 465                 break;
 466         case SND_SOC_DAIFMT_I2S:
 467                 priv->is_tdm_mode = false;
 468                 dev_dbg(component->dev, "Audio port in I2S mode\n");
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream,
 478                                  struct snd_pcm_hw_params *params,
 479                                  struct snd_soc_dai *dai)
 480 {
 481         struct snd_soc_component *component = dai->component;
 482         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 483         int sample_size = params_width(params);
 484         int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params));
 485
 486         if (coeff < 0)
 487                 return coeff;
 488
 489         regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 490                 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE,
 491                 cs35l33_mclk_coeffs[coeff].int_fs_ratio
 492                 | cs35l33_mclk_coeffs[coeff].adsp_rate);
 493
 494         if (priv->is_tdm_mode) {
 495                 sample_size = (sample_size / 8) - 1;
 496                 if (sample_size > 2)
 497                         sample_size = 2;
 498                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
 499                         CS35L33_AUDIN_RX_DEPTH,
 500                         sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT);
 501         }
 502
 503         dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n",
 504                 params_rate(params), params_width(params));
 505
 506         return 0;
 507 }
 508
 509 static const unsigned int cs35l33_src_rates[] = {
 510         8000, 11025, 11029, 12000, 16000, 22050,
 511         22059, 24000, 32000, 44100, 44118, 48000
 512 };
 513
 514 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = {
 515         .count  = ARRAY_SIZE(cs35l33_src_rates),
 516         .list   = cs35l33_src_rates,
 517 };
 518
 519 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream,
 520                                struct snd_soc_dai *dai)
 521 {
 522         snd_pcm_hw_constraint_list(substream->runtime, 0,
 523                                         SNDRV_PCM_HW_PARAM_RATE,
 524                                         &cs35l33_constraints);
 525         return 0;
 526 }
 527
 528 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate)
 529 {
 530         struct snd_soc_component *component = dai->component;
 531         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 532
 533         if (tristate) {
 534                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 535                         CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S);
 536                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 537                         CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM);
 538         } else {
 539                 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2,
 540                         CS35L33_SDOUT_3ST_I2S, 0);
 541                 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL,
 542                         CS35L33_SDOUT_3ST_TDM, 0);
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 549                                 unsigned int rx_mask, int slots, int slot_width)
 550 {
 551         struct snd_soc_component *component = dai->component;
 552         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 553         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 554         unsigned int reg, bit_pos, i;
 555         int slot, slot_num;
 556
 557         if (slot_width != 8)
 558                 return -EINVAL;
 559
 560         /* scan rx_mask for aud slot */
 561         slot = ffs(rx_mask) - 1;
 562         if (slot >= 0) {
 563                 regmap_update_bits(priv->regmap, CS35L33_RX_AUD,
 564                         CS35L33_X_LOC, slot);
 565                 dev_dbg(component->dev, "Audio starts from slots %d", slot);
 566         }
 567
 568         /*
 569          * scan tx_mask: vmon(2 slots); imon (2 slots);
 570          * vpmon (1 slot) vbstmon (1 slot)
 571          */
 572         slot = ffs(tx_mask) - 1;
 573         slot_num = 0;
 574
 575         for (i = 0; i < 2 ; i++) {
 576                 /* disable vpmon/vbstmon: enable later if set in tx_mask */
 577                 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i,
 578                         CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE
 579                         | CS35L33_X_LOC);
 580         }
 581
 582         /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/
 583         snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route,
 584                 ARRAY_SIZE(cs35l33_vp_vbst_mon_route));
 585
 586         while (slot >= 0) {
 587                 /* configure VMON_TX_LOC */
 588                 if (slot_num == 0) {
 589                         regmap_update_bits(priv->regmap, CS35L33_TX_VMON,
 590                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 591                         dev_dbg(component->dev, "VMON enabled in slots %d-%d",
 592                                 slot, slot + 1);
 593                 }
 594
 595                 /* configure IMON_TX_LOC */
 596                 if (slot_num == 3) {
 597                         regmap_update_bits(priv->regmap, CS35L33_TX_IMON,
 598                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 599                         dev_dbg(component->dev, "IMON enabled in slots %d-%d",
 600                                 slot, slot + 1);
 601                 }
 602
 603                 /* configure VPMON_TX_LOC */
 604                 if (slot_num == 4) {
 605                         regmap_update_bits(priv->regmap, CS35L33_TX_VPMON,
 606                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 607                         snd_soc_dapm_add_routes(dapm,
 608                                 &cs35l33_vp_vbst_mon_route[0], 2);
 609                         dev_dbg(component->dev, "VPMON enabled in slots %d", slot);
 610                 }
 611
 612                 /* configure VBSTMON_TX_LOC */
 613                 if (slot_num == 5) {
 614                         regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON,
 615                                 CS35L33_X_STATE | CS35L33_X_LOC, slot);
 616                         snd_soc_dapm_add_routes(dapm,
 617                                 &cs35l33_vp_vbst_mon_route[2], 2);
 618                         dev_dbg(component->dev,
 619                                 "VBSTMON enabled in slots %d", slot);
 620                 }
 621
 622                 /* Enable the relevant tx slot */
 623                 reg = CS35L33_TX_EN4 - (slot/8);
 624                 bit_pos = slot - ((slot / 8) * (8));
 625                 regmap_update_bits(priv->regmap, reg,
 626                         1 << bit_pos, 1 << bit_pos);
 627
 628                 tx_mask &= ~(1 << slot);
 629                 slot = ffs(tx_mask) - 1;
 630                 slot_num++;
 631         }
 632
 633         return 0;
 634 }
 635
 636 static int cs35l33_component_set_sysclk(struct snd_soc_component *component,
 637                 int clk_id, int source, unsigned int freq, int dir)
 638 {
 639         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
 640
 641         switch (freq) {
 642         case CS35L33_MCLK_5644:
 643         case CS35L33_MCLK_6:
 644         case CS35L33_MCLK_6144:
 645                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
 646                         CS35L33_MCLKDIV2, 0);
 647                 cs35l33->mclk_int = freq;
 648                 break;
 649         case CS35L33_MCLK_11289:
 650         case CS35L33_MCLK_12:
 651         case CS35L33_MCLK_12288:
 652                 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
 653                         CS35L33_MCLKDIV2, CS35L33_MCLKDIV2);
 654                 cs35l33->mclk_int = freq/2;
 655                 break;
 656         default:
 657                 cs35l33->mclk_int = 0;
 658                 return -EINVAL;
 659         }
 660
 661         dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n",
 662                 freq, cs35l33->mclk_int);
 663
 664         return 0;
 665 }
 666
 667 static const struct snd_soc_dai_ops cs35l33_ops = {
 668         .startup = cs35l33_pcm_startup,
 669         .set_tristate = cs35l33_set_tristate,
 670         .set_fmt = cs35l33_set_dai_fmt,
 671         .hw_params = cs35l33_pcm_hw_params,
 672         .set_tdm_slot = cs35l33_set_tdm_slot,
 673 };
 674
 675 static struct snd_soc_dai_driver cs35l33_dai = {
 676                 .name = "cs35l33-dai",
 677                 .id = 0,
 678                 .playback = {
 679                         .stream_name = "CS35L33 Playback",
 680                         .channels_min = 1,
 681                         .channels_max = 1,
 682                         .rates = CS35L33_RATES,
 683                         .formats = CS35L33_FORMATS,
 684                 },
 685                 .capture = {
 686                         .stream_name = "CS35L33 Capture",
 687                         .channels_min = 2,
 688                         .channels_max = 2,
 689                         .rates = CS35L33_RATES,
 690                         .formats = CS35L33_FORMATS,
 691                 },
 692                 .ops = &cs35l33_ops,
 693                 .symmetric_rate = 1,
 694 };
 695
 696 static int cs35l33_set_hg_data(struct snd_soc_component *component,
 697                                struct cs35l33_pdata *pdata)
 698 {
 699         struct cs35l33_hg *hg_config = &pdata->hg_config;
 700         struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 701         struct cs35l33_private *priv = snd_soc_component_get_drvdata(component);
 702
 703         if (hg_config->enable_hg_algo) {
 704                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 705                         CS35L33_MEM_DEPTH_MASK,
 706                         hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT);
 707                 regmap_write(priv->regmap, CS35L33_HG_REL_RATE,
 708                         hg_config->release_rate);
 709                 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD,
 710                         CS35L33_HD_RM_MASK,
 711                         hg_config->hd_rm << CS35L33_HD_RM_SHIFT);
 712                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 713                         CS35L33_LDO_THLD_MASK,
 714                         hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT);
 715                 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL,
 716                         CS35L33_LDO_DISABLE_MASK,
 717                         hg_config->ldo_path_disable <<
 718                                 CS35L33_LDO_DISABLE_SHIFT);
 719                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 720                         CS35L33_LDO_ENTRY_DELAY_MASK,
 721                         hg_config->ldo_entry_delay <<
 722                                 CS35L33_LDO_ENTRY_DELAY_SHIFT);
 723                 if (hg_config->vp_hg_auto) {
 724                         regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 725                                 CS35L33_VP_HG_AUTO_MASK,
 726                                 CS35L33_VP_HG_AUTO_MASK);
 727                         snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route,
 728                                 ARRAY_SIZE(cs35l33_vphg_auto_route));
 729                 }
 730                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 731                         CS35L33_VP_HG_MASK,
 732                         hg_config->vp_hg << CS35L33_VP_HG_SHIFT);
 733                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 734                         CS35L33_VP_HG_RATE_MASK,
 735                         hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT);
 736                 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL,
 737                         CS35L33_VP_HG_VA_MASK,
 738                         hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT);
 739                 regmap_update_bits(priv->regmap, CS35L33_HG_EN,
 740                         CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK);
 741         }
 742         return 0;
 743 }
 744
 745 static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst)
 746 {
 747         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
 748         int ret = 0, steps = 0;
 749
 750         /* Boost current in uA */
 751         if (bst > 3600000 || bst < 1850000) {
 752                 dev_err(component->dev, "Invalid boost current %d\n", bst);
 753                 ret = -EINVAL;
 754                 goto err;
 755         }
 756
 757         if (bst % 15625) {
 758                 dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n",
 759                         bst);
 760                 ret = -EINVAL;
 761                 goto err;
 762         }
 763
 764         while (bst > 1850000) {
 765                 bst -= 15625;
 766                 steps++;
 767         }
 768
 769         regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL,
 770                 steps+0x70);
 771
 772 err:
 773         return ret;
 774 }
 775
 776 static int cs35l33_probe(struct snd_soc_component *component)
 777 {
 778         struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component);
 779
 780         cs35l33->component = component;
 781         pm_runtime_get_sync(component->dev);
 782
 783         regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL,
 784                 CS35L33_ALIVE_WD_DIS, 0x8);
 785         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2,
 786                                 CS35L33_ALIVE_WD_DIS2,
 787                                 CS35L33_ALIVE_WD_DIS2);
 788
 789         /* Set Platform Data */
 790         regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1,
 791                 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl);
 792         regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL,
 793                 CS35L33_AMP_DRV_SEL_MASK,
 794                 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT);
 795
 796         if (cs35l33->pdata.boost_ipk)
 797                 cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk);
 798
 799         if (cs35l33->enable_soft_ramp) {
 800                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
 801                         CS35L33_DIGSFT, CS35L33_DIGSFT);
 802                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
 803                         CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate);
 804         } else {
 805                 snd_soc_component_update_bits(component, CS35L33_DAC_CTL,
 806                         CS35L33_DIGSFT, 0);
 807         }
 808
 809         /* update IMON scaling rate if different from default of 0x8 */
 810         if (cs35l33->pdata.imon_adc_scale != 0x8)
 811                 snd_soc_component_update_bits(component, CS35L33_ADC_CTL,
 812                         CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale);
 813
 814         cs35l33_set_hg_data(component, &(cs35l33->pdata));
 815
 816         /*
 817          * unmask important interrupts that causes the chip to enter
 818          * speaker safe mode and hence deserves user attention
 819          */
 820         regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1,
 821                 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT |
 822                 CS35L33_M_CAL_ERR, 0);
 823
 824         pm_runtime_put_sync(component->dev);
 825
 826         return 0;
 827 }
 828
 829 static const struct snd_soc_component_driver soc_component_dev_cs35l33 = {
 830         .probe                  = cs35l33_probe,
 831         .set_bias_level         = cs35l33_set_bias_level,
 832         .set_sysclk             = cs35l33_component_set_sysclk,
 833         .controls               = cs35l33_snd_controls,
 834         .num_controls           = ARRAY_SIZE(cs35l33_snd_controls),
 835         .dapm_widgets           = cs35l33_dapm_widgets,
 836         .num_dapm_widgets       = ARRAY_SIZE(cs35l33_dapm_widgets),
 837         .dapm_routes            = cs35l33_audio_map,
 838         .num_dapm_routes        = ARRAY_SIZE(cs35l33_audio_map),
 839         .use_pmdown_time        = 1,
 840         .endianness             = 1,
 841 };
 842
 843 static const struct regmap_config cs35l33_regmap = {
 844         .reg_bits = 8,
 845         .val_bits = 8,
 846
 847         .max_register = CS35L33_MAX_REGISTER,
 848         .reg_defaults = cs35l33_reg,
 849         .num_reg_defaults = ARRAY_SIZE(cs35l33_reg),
 850         .volatile_reg = cs35l33_volatile_register,
 851         .readable_reg = cs35l33_readable_register,
 852         .writeable_reg = cs35l33_writeable_register,
 853         .cache_type = REGCACHE_MAPLE,
 854         .use_single_read = true,
 855         .use_single_write = true,
 856 };
 857
 858 static int __maybe_unused cs35l33_runtime_resume(struct device *dev)
 859 {
 860         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
 861         int ret;
 862
 863         dev_dbg(dev, "%s\n", __func__);
 864
 865         gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
 866
 867         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
 868                 cs35l33->core_supplies);
 869         if (ret != 0) {
 870                 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
 871                 return ret;
 872         }
 873
 874         regcache_cache_only(cs35l33->regmap, false);
 875
 876         gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
 877
 878         msleep(CS35L33_BOOT_DELAY);
 879
 880         ret = regcache_sync(cs35l33->regmap);
 881         if (ret != 0) {
 882                 dev_err(dev, "Failed to restore register cache\n");
 883                 goto err;
 884         }
 885
 886         return 0;
 887
 888 err:
 889         regcache_cache_only(cs35l33->regmap, true);
 890         regulator_bulk_disable(cs35l33->num_core_supplies,
 891                 cs35l33->core_supplies);
 892
 893         return ret;
 894 }
 895
 896 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev)
 897 {
 898         struct cs35l33_private *cs35l33 = dev_get_drvdata(dev);
 899
 900         dev_dbg(dev, "%s\n", __func__);
 901
 902         /* redo the calibration in next power up */
 903         cs35l33->amp_cal = false;
 904
 905         regcache_cache_only(cs35l33->regmap, true);
 906         regcache_mark_dirty(cs35l33->regmap);
 907         regulator_bulk_disable(cs35l33->num_core_supplies,
 908                 cs35l33->core_supplies);
 909
 910         return 0;
 911 }
 912
 913 static const struct dev_pm_ops cs35l33_pm_ops = {
 914         SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend,
 915                            cs35l33_runtime_resume,
 916                            NULL)
 917 };
 918
 919 static int cs35l33_get_hg_data(const struct device_node *np,
 920                                struct cs35l33_pdata *pdata)
 921 {
 922         struct device_node *hg;
 923         struct cs35l33_hg *hg_config = &pdata->hg_config;
 924         u32 val32;
 925
 926         hg = of_get_child_by_name(np, "cirrus,hg-algo");
 927         hg_config->enable_hg_algo = hg ? true : false;
 928
 929         if (hg_config->enable_hg_algo) {
 930                 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0)
 931                         hg_config->mem_depth = val32;
 932                 if (of_property_read_u32(hg, "cirrus,release-rate",
 933                                 &val32) >= 0)
 934                         hg_config->release_rate = val32;
 935                 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0)
 936                         hg_config->ldo_thld = val32;
 937                 if (of_property_read_u32(hg, "cirrus,ldo-path-disable",
 938                                 &val32) >= 0)
 939                         hg_config->ldo_path_disable = val32;
 940                 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay",
 941                                 &val32) >= 0)
 942                         hg_config->ldo_entry_delay = val32;
 943
 944                 hg_config->vp_hg_auto = of_property_read_bool(hg,
 945                         "cirrus,vp-hg-auto");
 946
 947                 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0)
 948                         hg_config->vp_hg = val32;
 949                 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0)
 950                         hg_config->vp_hg_rate = val32;
 951                 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0)
 952                         hg_config->vp_hg_va = val32;
 953         }
 954
 955         of_node_put(hg);
 956
 957         return 0;
 958 }
 959
 960 static irqreturn_t cs35l33_irq_thread(int irq, void *data)
 961 {
 962         struct cs35l33_private *cs35l33 = data;
 963         struct snd_soc_component *component = cs35l33->component;
 964         unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2;
 965
 966         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2,
 967                 &sticky_val2);
 968         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
 969                 &sticky_val1);
 970         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2);
 971         regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1);
 972
 973         /* Check to see if the unmasked bits are active,
 974          *  if not then exit.
 975          */
 976         if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2))
 977                 return IRQ_NONE;
 978
 979         regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1,
 980                 &current_val);
 981
 982         /* handle the interrupts */
 983
 984         if (sticky_val1 & CS35L33_AMP_SHORT) {
 985                 dev_crit(component->dev, "Amp short error\n");
 986                 if (!(current_val & CS35L33_AMP_SHORT)) {
 987                         dev_dbg(component->dev,
 988                                 "Amp short error release\n");
 989                         regmap_update_bits(cs35l33->regmap,
 990                                 CS35L33_AMP_CTL,
 991                                 CS35L33_AMP_SHORT_RLS, 0);
 992                         regmap_update_bits(cs35l33->regmap,
 993                                 CS35L33_AMP_CTL,
 994                                 CS35L33_AMP_SHORT_RLS,
 995                                 CS35L33_AMP_SHORT_RLS);
 996                         regmap_update_bits(cs35l33->regmap,
 997                                 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS,
 998                                 0);
 999                 }
1000         }
1001
1002         if (sticky_val1 & CS35L33_CAL_ERR) {
1003                 dev_err(component->dev, "Cal error\n");
1004
1005                 /* redo the calibration in next power up */
1006                 cs35l33->amp_cal = false;
1007
1008                 if (!(current_val & CS35L33_CAL_ERR)) {
1009                         dev_dbg(component->dev, "Cal error release\n");
1010                         regmap_update_bits(cs35l33->regmap,
1011                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1012                                 0);
1013                         regmap_update_bits(cs35l33->regmap,
1014                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1015                                 CS35L33_CAL_ERR_RLS);
1016                         regmap_update_bits(cs35l33->regmap,
1017                                 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS,
1018                                 0);
1019                 }
1020         }
1021
1022         if (sticky_val1 & CS35L33_OTE) {
1023                 dev_crit(component->dev, "Over temperature error\n");
1024                 if (!(current_val & CS35L33_OTE)) {
1025                         dev_dbg(component->dev,
1026                                 "Over temperature error release\n");
1027                         regmap_update_bits(cs35l33->regmap,
1028                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1029                         regmap_update_bits(cs35l33->regmap,
1030                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS,
1031                                 CS35L33_OTE_RLS);
1032                         regmap_update_bits(cs35l33->regmap,
1033                                 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0);
1034                 }
1035         }
1036
1037         if (sticky_val1 & CS35L33_OTW) {
1038                 dev_err(component->dev, "Over temperature warning\n");
1039                 if (!(current_val & CS35L33_OTW)) {
1040                         dev_dbg(component->dev,
1041                                 "Over temperature warning release\n");
1042                         regmap_update_bits(cs35l33->regmap,
1043                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1044                         regmap_update_bits(cs35l33->regmap,
1045                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS,
1046                                 CS35L33_OTW_RLS);
1047                         regmap_update_bits(cs35l33->regmap,
1048                                 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0);
1049                 }
1050         }
1051         if (CS35L33_ALIVE_ERR & sticky_val1)
1052                 dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n");
1053
1054         if (CS35L33_MCLK_ERR & sticky_val1)
1055                 dev_err(component->dev, "ERROR: MCLK Interrupt\n");
1056
1057         if (CS35L33_VMON_OVFL & sticky_val2)
1058                 dev_err(component->dev,
1059                         "ERROR: VMON Overflow Interrupt\n");
1060
1061         if (CS35L33_IMON_OVFL & sticky_val2)
1062                 dev_err(component->dev,
1063                         "ERROR: IMON Overflow Interrupt\n");
1064
1065         if (CS35L33_VPMON_OVFL & sticky_val2)
1066                 dev_err(component->dev,
1067                         "ERROR: VPMON Overflow Interrupt\n");
1068
1069         return IRQ_HANDLED;
1070 }
1071
1072 static const char * const cs35l33_core_supplies[] = {
1073         "VA",
1074         "VP",
1075 };
1076
1077 static int cs35l33_of_get_pdata(struct device *dev,
1078                                 struct cs35l33_private *cs35l33)
1079 {
1080         struct device_node *np = dev->of_node;
1081         struct cs35l33_pdata *pdata = &cs35l33->pdata;
1082         u32 val32;
1083
1084         if (!np)
1085                 return 0;
1086
1087         if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) {
1088                 pdata->boost_ctl = val32;
1089                 pdata->amp_drv_sel = 1;
1090         }
1091
1092         if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) {
1093                 pdata->ramp_rate = val32;
1094                 cs35l33->enable_soft_ramp = true;
1095         }
1096
1097         if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0)
1098                 pdata->boost_ipk = val32;
1099
1100         if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) {
1101                 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6))
1102                         pdata->imon_adc_scale = val32;
1103                 else
1104                         /* use default value */
1105                         pdata->imon_adc_scale = 0x8;
1106         } else {
1107                 /* use default value */
1108                 pdata->imon_adc_scale = 0x8;
1109         }
1110
1111         cs35l33_get_hg_data(np, pdata);
1112
1113         return 0;
1114 }
1115
1116 static int cs35l33_i2c_probe(struct i2c_client *i2c_client)
1117 {
1118         struct cs35l33_private *cs35l33;
1119         struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev);
1120         int ret, devid, i;
1121         unsigned int reg;
1122
1123         cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private),
1124                                GFP_KERNEL);
1125         if (!cs35l33)
1126                 return -ENOMEM;
1127
1128         i2c_set_clientdata(i2c_client, cs35l33);
1129         cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap);
1130         if (IS_ERR(cs35l33->regmap)) {
1131                 ret = PTR_ERR(cs35l33->regmap);
1132                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1133                 return ret;
1134         }
1135
1136         regcache_cache_only(cs35l33->regmap, true);
1137
1138         for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++)
1139                 cs35l33->core_supplies[i].supply
1140                         = cs35l33_core_supplies[i];
1141         cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies);
1142
1143         ret = devm_regulator_bulk_get(&i2c_client->dev,
1144                         cs35l33->num_core_supplies,
1145                         cs35l33->core_supplies);
1146         if (ret != 0) {
1147                 dev_err(&i2c_client->dev,
1148                         "Failed to request core supplies: %d\n",
1149                         ret);
1150                 return ret;
1151         }
1152
1153         if (pdata) {
1154                 cs35l33->pdata = *pdata;
1155         } else {
1156                 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33);
1157                 pdata = &cs35l33->pdata;
1158         }
1159
1160         ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
1161                         cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1162                         "cs35l33", cs35l33);
1163         if (ret != 0)
1164                 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
1165
1166         /* We could issue !RST or skip it based on AMP topology */
1167         cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1168                         "reset-gpios", GPIOD_OUT_HIGH);
1169         if (IS_ERR(cs35l33->reset_gpio)) {
1170                 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n",
1171                         __func__);
1172                 return PTR_ERR(cs35l33->reset_gpio);
1173         }
1174
1175         ret = regulator_bulk_enable(cs35l33->num_core_supplies,
1176                                         cs35l33->core_supplies);
1177         if (ret != 0) {
1178                 dev_err(&i2c_client->dev,
1179                         "Failed to enable core supplies: %d\n",
1180                         ret);
1181                 return ret;
1182         }
1183
1184         gpiod_set_value_cansleep(cs35l33->reset_gpio, 1);
1185
1186         msleep(CS35L33_BOOT_DELAY);
1187         regcache_cache_only(cs35l33->regmap, false);
1188
1189         /* initialize codec */
1190         devid = cirrus_read_device_id(cs35l33->regmap, CS35L33_DEVID_AB);
1191         if (devid < 0) {
1192                 ret = devid;
1193                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
1194                 goto err_enable;
1195         }
1196
1197         if (devid != CS35L33_CHIP_ID) {
1198                 dev_err(&i2c_client->dev,
1199                         "CS35L33 Device ID (%X). Expected ID %X\n",
1200                         devid, CS35L33_CHIP_ID);
1201                 ret = -EINVAL;
1202                 goto err_enable;
1203         }
1204
1205         ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, &reg);
1206         if (ret < 0) {
1207                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1208                 goto err_enable;
1209         }
1210
1211         dev_info(&i2c_client->dev,
1212                  "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF);
1213
1214         ret = regmap_register_patch(cs35l33->regmap,
1215                         cs35l33_patch, ARRAY_SIZE(cs35l33_patch));
1216         if (ret < 0) {
1217                 dev_err(&i2c_client->dev,
1218                         "Error in applying regmap patch: %d\n", ret);
1219                 goto err_enable;
1220         }
1221
1222         /* disable mclk and tdm */
1223         regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL,
1224                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM,
1225                 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM);
1226
1227         pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100);
1228         pm_runtime_use_autosuspend(&i2c_client->dev);
1229         pm_runtime_set_active(&i2c_client->dev);
1230         pm_runtime_enable(&i2c_client->dev);
1231
1232         ret = devm_snd_soc_register_component(&i2c_client->dev,
1233                         &soc_component_dev_cs35l33, &cs35l33_dai, 1);
1234         if (ret < 0) {
1235                 dev_err(&i2c_client->dev, "%s: Register component failed\n",
1236                         __func__);
1237                 goto err_enable;
1238         }
1239
1240         return 0;
1241
1242 err_enable:
1243         gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1244
1245         regulator_bulk_disable(cs35l33->num_core_supplies,
1246                                cs35l33->core_supplies);
1247
1248         return ret;
1249 }
1250
1251 static void cs35l33_i2c_remove(struct i2c_client *client)
1252 {
1253         struct cs35l33_private *cs35l33 = i2c_get_clientdata(client);
1254
1255         gpiod_set_value_cansleep(cs35l33->reset_gpio, 0);
1256
1257         pm_runtime_disable(&client->dev);
1258         regulator_bulk_disable(cs35l33->num_core_supplies,
1259                 cs35l33->core_supplies);
1260 }
1261
1262 static const struct of_device_id cs35l33_of_match[] = {
1263         { .compatible = "cirrus,cs35l33", },
1264         {},
1265 };
1266 MODULE_DEVICE_TABLE(of, cs35l33_of_match);
1267
1268 static const struct i2c_device_id cs35l33_id[] = {
1269         {"cs35l33", 0},
1270         {}
1271 };
1272
1273 MODULE_DEVICE_TABLE(i2c, cs35l33_id);
1274
1275 static struct i2c_driver cs35l33_i2c_driver = {
1276         .driver = {
1277                 .name = "cs35l33",
1278                 .pm = &cs35l33_pm_ops,
1279                 .of_match_table = cs35l33_of_match,
1280
1281                 },
1282         .id_table = cs35l33_id,
1283         .probe = cs35l33_i2c_probe,
1284         .remove = cs35l33_i2c_remove,
1285
1286 };
1287 module_i2c_driver(cs35l33_i2c_driver);
1288
1289 MODULE_DESCRIPTION("ASoC CS35L33 driver");
1290 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
1291 MODULE_LICENSE("GPL");