1 // SPDX-License-Identifier: GPL-2.0-only
3 // aw88395_reg.h -- AW88395 chip register file
5 // Copyright (c) 2022-2023 AWINIC Technology CO., LTD
7 // Author: Bruce zhao <zhaolei@awinic.com>
10 #ifndef __AW88395_REG_H__
11 #define __AW88395_REG_H__
13 #define AW88395_ID_REG (0x00)
14 #define AW88395_SYSST_REG (0x01)
15 #define AW88395_SYSINT_REG (0x02)
16 #define AW88395_SYSINTM_REG (0x03)
17 #define AW88395_SYSCTRL_REG (0x04)
18 #define AW88395_SYSCTRL2_REG (0x05)
19 #define AW88395_I2SCTRL_REG (0x06)
20 #define AW88395_I2SCFG1_REG (0x07)
21 #define AW88395_I2SCFG2_REG (0x08)
22 #define AW88395_HAGCCFG1_REG (0x09)
23 #define AW88395_HAGCCFG2_REG (0x0A)
24 #define AW88395_HAGCCFG3_REG (0x0B)
25 #define AW88395_HAGCCFG4_REG (0x0C)
26 #define AW88395_HAGCCFG5_REG (0x0D)
27 #define AW88395_HAGCCFG6_REG (0x0E)
28 #define AW88395_HAGCCFG7_REG (0x0F)
29 #define AW88395_MPDCFG_REG (0x10)
30 #define AW88395_PWMCTRL_REG (0x11)
31 #define AW88395_I2SCFG3_REG (0x12)
32 #define AW88395_DBGCTRL_REG (0x13)
33 #define AW88395_HAGCST_REG (0x20)
34 #define AW88395_VBAT_REG (0x21)
35 #define AW88395_TEMP_REG (0x22)
36 #define AW88395_PVDD_REG (0x23)
37 #define AW88395_ISNDAT_REG (0x24)
38 #define AW88395_VSNDAT_REG (0x25)
39 #define AW88395_I2SINT_REG (0x26)
40 #define AW88395_I2SCAPCNT_REG (0x27)
41 #define AW88395_ANASTA1_REG (0x28)
42 #define AW88395_ANASTA2_REG (0x29)
43 #define AW88395_ANASTA3_REG (0x2A)
44 #define AW88395_ANASTA4_REG (0x2B)
45 #define AW88395_TESTDET_REG (0x2C)
46 #define AW88395_TESTIN_REG (0x38)
47 #define AW88395_TESTOUT_REG (0x39)
48 #define AW88395_DSPMADD_REG (0x40)
49 #define AW88395_DSPMDAT_REG (0x41)
50 #define AW88395_WDT_REG (0x42)
51 #define AW88395_ACR1_REG (0x43)
52 #define AW88395_ACR2_REG (0x44)
53 #define AW88395_ASR1_REG (0x45)
54 #define AW88395_ASR2_REG (0x46)
55 #define AW88395_DSPCFG_REG (0x47)
56 #define AW88395_ASR3_REG (0x48)
57 #define AW88395_ASR4_REG (0x49)
58 #define AW88395_VSNCTRL1_REG (0x50)
59 #define AW88395_ISNCTRL1_REG (0x51)
60 #define AW88395_PLLCTRL1_REG (0x52)
61 #define AW88395_PLLCTRL2_REG (0x53)
62 #define AW88395_PLLCTRL3_REG (0x54)
63 #define AW88395_CDACTRL1_REG (0x55)
64 #define AW88395_CDACTRL2_REG (0x56)
65 #define AW88395_SADCCTRL1_REG (0x57)
66 #define AW88395_SADCCTRL2_REG (0x58)
67 #define AW88395_CPCTRL1_REG (0x59)
68 #define AW88395_BSTCTRL1_REG (0x60)
69 #define AW88395_BSTCTRL2_REG (0x61)
70 #define AW88395_BSTCTRL3_REG (0x62)
71 #define AW88395_BSTCTRL4_REG (0x63)
72 #define AW88395_BSTCTRL5_REG (0x64)
73 #define AW88395_BSTCTRL6_REG (0x65)
74 #define AW88395_BSTCTRL7_REG (0x66)
75 #define AW88395_DSMCFG1_REG (0x67)
76 #define AW88395_DSMCFG2_REG (0x68)
77 #define AW88395_DSMCFG3_REG (0x69)
78 #define AW88395_DSMCFG4_REG (0x6A)
79 #define AW88395_DSMCFG5_REG (0x6B)
80 #define AW88395_DSMCFG6_REG (0x6C)
81 #define AW88395_DSMCFG7_REG (0x6D)
82 #define AW88395_DSMCFG8_REG (0x6E)
83 #define AW88395_TESTCTRL1_REG (0x70)
84 #define AW88395_TESTCTRL2_REG (0x71)
85 #define AW88395_EFCTRL1_REG (0x72)
86 #define AW88395_EFCTRL2_REG (0x73)
87 #define AW88395_EFWH_REG (0x74)
88 #define AW88395_EFWM2_REG (0x75)
89 #define AW88395_EFWM1_REG (0x76)
90 #define AW88395_EFWL_REG (0x77)
91 #define AW88395_EFRH_REG (0x78)
92 #define AW88395_EFRM2_REG (0x79)
93 #define AW88395_EFRM1_REG (0x7A)
94 #define AW88395_EFRL_REG (0x7B)
95 #define AW88395_TM_REG (0x7C)
98 AW88399_CHIP_ID = 0x2183,
99 AW88395_CHIP_ID = 0x2049,
100 AW88261_CHIP_ID = 0x2113,
101 AW87390_CHIP_ID = 0x76,
104 #define AW88395_REG_MAX (0x7D)
106 #define AW88395_VOLUME_STEP_DB (6 * 8)
108 #define AW88395_UVLS_START_BIT (14)
109 #define AW88395_UVLS_NORMAL (0)
110 #define AW88395_UVLS_NORMAL_VALUE \
111 (AW88395_UVLS_NORMAL << AW88395_UVLS_START_BIT)
113 #define AW88395_DSPS_START_BIT (12)
114 #define AW88395_DSPS_BITS_LEN (1)
115 #define AW88395_DSPS_MASK \
116 (~(((1<<AW88395_DSPS_BITS_LEN)-1) << AW88395_DSPS_START_BIT))
118 #define AW88395_DSPS_NORMAL (0)
119 #define AW88395_DSPS_NORMAL_VALUE \
120 (AW88395_DSPS_NORMAL << AW88395_DSPS_START_BIT)
122 #define AW88395_BSTOCS_START_BIT (11)
123 #define AW88395_BSTOCS_OVER_CURRENT (1)
124 #define AW88395_BSTOCS_OVER_CURRENT_VALUE \
125 (AW88395_BSTOCS_OVER_CURRENT << AW88395_BSTOCS_START_BIT)
127 #define AW88395_BSTS_START_BIT (9)
128 #define AW88395_BSTS_FINISHED (1)
129 #define AW88395_BSTS_FINISHED_VALUE \
130 (AW88395_BSTS_FINISHED << AW88395_BSTS_START_BIT)
132 #define AW88395_SWS_START_BIT (8)
133 #define AW88395_SWS_SWITCHING (1)
134 #define AW88395_SWS_SWITCHING_VALUE \
135 (AW88395_SWS_SWITCHING << AW88395_SWS_START_BIT)
137 #define AW88395_NOCLKS_START_BIT (5)
138 #define AW88395_NOCLKS_NO_CLOCK (1)
139 #define AW88395_NOCLKS_NO_CLOCK_VALUE \
140 (AW88395_NOCLKS_NO_CLOCK << AW88395_NOCLKS_START_BIT)
142 #define AW88395_CLKS_START_BIT (4)
143 #define AW88395_CLKS_STABLE (1)
144 #define AW88395_CLKS_STABLE_VALUE \
145 (AW88395_CLKS_STABLE << AW88395_CLKS_START_BIT)
147 #define AW88395_OCDS_START_BIT (3)
148 #define AW88395_OCDS_OC (1)
149 #define AW88395_OCDS_OC_VALUE \
150 (AW88395_OCDS_OC << AW88395_OCDS_START_BIT)
152 #define AW88395_OTHS_START_BIT (1)
153 #define AW88395_OTHS_OT (1)
154 #define AW88395_OTHS_OT_VALUE \
155 (AW88395_OTHS_OT << AW88395_OTHS_START_BIT)
157 #define AW88395_PLLS_START_BIT (0)
158 #define AW88395_PLLS_LOCKED (1)
159 #define AW88395_PLLS_LOCKED_VALUE \
160 (AW88395_PLLS_LOCKED << AW88395_PLLS_START_BIT)
162 #define AW88395_BIT_PLL_CHECK \
163 (AW88395_CLKS_STABLE_VALUE | \
164 AW88395_PLLS_LOCKED_VALUE)
166 #define AW88395_BIT_SYSST_CHECK_MASK \
167 (~(AW88395_UVLS_NORMAL_VALUE | \
168 AW88395_BSTOCS_OVER_CURRENT_VALUE | \
169 AW88395_BSTS_FINISHED_VALUE | \
170 AW88395_SWS_SWITCHING_VALUE | \
171 AW88395_NOCLKS_NO_CLOCK_VALUE | \
172 AW88395_CLKS_STABLE_VALUE | \
173 AW88395_OCDS_OC_VALUE | \
174 AW88395_OTHS_OT_VALUE | \
175 AW88395_PLLS_LOCKED_VALUE))
177 #define AW88395_BIT_SYSST_CHECK \
178 (AW88395_BSTS_FINISHED_VALUE | \
179 AW88395_SWS_SWITCHING_VALUE | \
180 AW88395_CLKS_STABLE_VALUE | \
181 AW88395_PLLS_LOCKED_VALUE)
183 #define AW88395_WDI_START_BIT (6)
184 #define AW88395_WDI_INT_VALUE (1)
185 #define AW88395_WDI_INTERRUPT \
186 (AW88395_WDI_INT_VALUE << AW88395_WDI_START_BIT)
188 #define AW88395_NOCLKI_START_BIT (5)
189 #define AW88395_NOCLKI_INT_VALUE (1)
190 #define AW88395_NOCLKI_INTERRUPT \
191 (AW88395_NOCLKI_INT_VALUE << AW88395_NOCLKI_START_BIT)
193 #define AW88395_CLKI_START_BIT (4)
194 #define AW88395_CLKI_INT_VALUE (1)
195 #define AW88395_CLKI_INTERRUPT \
196 (AW88395_CLKI_INT_VALUE << AW88395_CLKI_START_BIT)
198 #define AW88395_PLLI_START_BIT (0)
199 #define AW88395_PLLI_INT_VALUE (1)
200 #define AW88395_PLLI_INTERRUPT \
201 (AW88395_PLLI_INT_VALUE << AW88395_PLLI_START_BIT)
203 #define AW88395_BIT_SYSINT_CHECK \
204 (AW88395_WDI_INTERRUPT | \
205 AW88395_CLKI_INTERRUPT | \
206 AW88395_NOCLKI_INTERRUPT | \
207 AW88395_PLLI_INTERRUPT)
209 #define AW88395_HMUTE_START_BIT (8)
210 #define AW88395_HMUTE_BITS_LEN (1)
211 #define AW88395_HMUTE_MASK \
212 (~(((1<<AW88395_HMUTE_BITS_LEN)-1) << AW88395_HMUTE_START_BIT))
214 #define AW88395_HMUTE_DISABLE (0)
215 #define AW88395_HMUTE_DISABLE_VALUE \
216 (AW88395_HMUTE_DISABLE << AW88395_HMUTE_START_BIT)
218 #define AW88395_HMUTE_ENABLE (1)
219 #define AW88395_HMUTE_ENABLE_VALUE \
220 (AW88395_HMUTE_ENABLE << AW88395_HMUTE_START_BIT)
222 #define AW88395_RCV_MODE_START_BIT (7)
223 #define AW88395_RCV_MODE_BITS_LEN (1)
224 #define AW88395_RCV_MODE_MASK \
225 (~(((1<<AW88395_RCV_MODE_BITS_LEN)-1) << AW88395_RCV_MODE_START_BIT))
227 #define AW88395_RCV_MODE_RECEIVER (1)
228 #define AW88395_RCV_MODE_RECEIVER_VALUE \
229 (AW88395_RCV_MODE_RECEIVER << AW88395_RCV_MODE_START_BIT)
231 #define AW88395_DSPBY_START_BIT (2)
232 #define AW88395_DSPBY_BITS_LEN (1)
233 #define AW88395_DSPBY_MASK \
234 (~(((1<<AW88395_DSPBY_BITS_LEN)-1) << AW88395_DSPBY_START_BIT))
236 #define AW88395_DSPBY_WORKING (0)
237 #define AW88395_DSPBY_WORKING_VALUE \
238 (AW88395_DSPBY_WORKING << AW88395_DSPBY_START_BIT)
240 #define AW88395_DSPBY_BYPASS (1)
241 #define AW88395_DSPBY_BYPASS_VALUE \
242 (AW88395_DSPBY_BYPASS << AW88395_DSPBY_START_BIT)
244 #define AW88395_AMPPD_START_BIT (1)
245 #define AW88395_AMPPD_BITS_LEN (1)
246 #define AW88395_AMPPD_MASK \
247 (~(((1<<AW88395_AMPPD_BITS_LEN)-1) << AW88395_AMPPD_START_BIT))
249 #define AW88395_AMPPD_WORKING (0)
250 #define AW88395_AMPPD_WORKING_VALUE \
251 (AW88395_AMPPD_WORKING << AW88395_AMPPD_START_BIT)
253 #define AW88395_AMPPD_POWER_DOWN (1)
254 #define AW88395_AMPPD_POWER_DOWN_VALUE \
255 (AW88395_AMPPD_POWER_DOWN << AW88395_AMPPD_START_BIT)
257 #define AW88395_PWDN_START_BIT (0)
258 #define AW88395_PWDN_BITS_LEN (1)
259 #define AW88395_PWDN_MASK \
260 (~(((1<<AW88395_PWDN_BITS_LEN)-1) << AW88395_PWDN_START_BIT))
262 #define AW88395_PWDN_WORKING (0)
263 #define AW88395_PWDN_WORKING_VALUE \
264 (AW88395_PWDN_WORKING << AW88395_PWDN_START_BIT)
266 #define AW88395_PWDN_POWER_DOWN (1)
267 #define AW88395_PWDN_POWER_DOWN_VALUE \
268 (AW88395_PWDN_POWER_DOWN << AW88395_PWDN_START_BIT)
270 #define AW88395_MUTE_VOL (90 * 8)
271 #define AW88395_VOLUME_STEP_DB (6 * 8)
273 #define AW88395_VOL_6DB_START (6)
274 #define AW88395_VOL_START_BIT (6)
275 #define AW88395_VOL_BITS_LEN (10)
276 #define AW88395_VOL_MASK \
277 (~(((1<<AW88395_VOL_BITS_LEN)-1) << AW88395_VOL_START_BIT))
279 #define AW88395_VOL_DEFAULT_VALUE (0)
281 #define AW88395_I2STXEN_START_BIT (0)
282 #define AW88395_I2STXEN_BITS_LEN (1)
283 #define AW88395_I2STXEN_MASK \
284 (~(((1<<AW88395_I2STXEN_BITS_LEN)-1) << AW88395_I2STXEN_START_BIT))
286 #define AW88395_I2STXEN_DISABLE (0)
287 #define AW88395_I2STXEN_DISABLE_VALUE \
288 (AW88395_I2STXEN_DISABLE << AW88395_I2STXEN_START_BIT)
290 #define AW88395_I2STXEN_ENABLE (1)
291 #define AW88395_I2STXEN_ENABLE_VALUE \
292 (AW88395_I2STXEN_ENABLE << AW88395_I2STXEN_START_BIT)
294 #define AW88395_AGC_DSP_CTL_START_BIT (15)
295 #define AW88395_AGC_DSP_CTL_BITS_LEN (1)
296 #define AW88395_AGC_DSP_CTL_MASK \
297 (~(((1<<AW88395_AGC_DSP_CTL_BITS_LEN)-1) << AW88395_AGC_DSP_CTL_START_BIT))
299 #define AW88395_AGC_DSP_CTL_DISABLE (0)
300 #define AW88395_AGC_DSP_CTL_DISABLE_VALUE \
301 (AW88395_AGC_DSP_CTL_DISABLE << AW88395_AGC_DSP_CTL_START_BIT)
303 #define AW88395_AGC_DSP_CTL_ENABLE (1)
304 #define AW88395_AGC_DSP_CTL_ENABLE_VALUE \
305 (AW88395_AGC_DSP_CTL_ENABLE << AW88395_AGC_DSP_CTL_START_BIT)
307 #define AW88395_VDSEL_START_BIT (0)
308 #define AW88395_VDSEL_BITS_LEN (1)
309 #define AW88395_VDSEL_MASK \
310 (~(((1<<AW88395_VDSEL_BITS_LEN)-1) << AW88395_VDSEL_START_BIT))
312 #define AW88395_MEM_CLKSEL_START_BIT (3)
313 #define AW88395_MEM_CLKSEL_BITS_LEN (1)
314 #define AW88395_MEM_CLKSEL_MASK \
315 (~(((1<<AW88395_MEM_CLKSEL_BITS_LEN)-1) << AW88395_MEM_CLKSEL_START_BIT))
317 #define AW88395_MEM_CLKSEL_OSC_CLK (0)
318 #define AW88395_MEM_CLKSEL_OSC_CLK_VALUE \
319 (AW88395_MEM_CLKSEL_OSC_CLK << AW88395_MEM_CLKSEL_START_BIT)
321 #define AW88395_MEM_CLKSEL_DAP_HCLK (1)
322 #define AW88395_MEM_CLKSEL_DAP_HCLK_VALUE \
323 (AW88395_MEM_CLKSEL_DAP_HCLK << AW88395_MEM_CLKSEL_START_BIT)
325 #define AW88395_CCO_MUX_START_BIT (14)
326 #define AW88395_CCO_MUX_BITS_LEN (1)
327 #define AW88395_CCO_MUX_MASK \
328 (~(((1<<AW88395_CCO_MUX_BITS_LEN)-1) << AW88395_CCO_MUX_START_BIT))
330 #define AW88395_CCO_MUX_DIVIDED (0)
331 #define AW88395_CCO_MUX_DIVIDED_VALUE \
332 (AW88395_CCO_MUX_DIVIDED << AW88395_CCO_MUX_START_BIT)
334 #define AW88395_CCO_MUX_BYPASS (1)
335 #define AW88395_CCO_MUX_BYPASS_VALUE \
336 (AW88395_CCO_MUX_BYPASS << AW88395_CCO_MUX_START_BIT)
338 #define AW88395_EF_VSN_GESLP_START_BIT (0)
339 #define AW88395_EF_VSN_GESLP_BITS_LEN (10)
340 #define AW88395_EF_VSN_GESLP_MASK \
341 (~(((1<<AW88395_EF_VSN_GESLP_BITS_LEN)-1) << AW88395_EF_VSN_GESLP_START_BIT))
343 #define AW88395_EF_VSN_GESLP_SIGN_MASK (~(1 << 9))
344 #define AW88395_EF_VSN_GESLP_SIGN_NEG (0xfe00)
346 #define AW88395_EF_ISN_GESLP_START_BIT (0)
347 #define AW88395_EF_ISN_GESLP_BITS_LEN (10)
348 #define AW88395_EF_ISN_GESLP_MASK \
349 (~(((1<<AW88395_EF_ISN_GESLP_BITS_LEN)-1) << AW88395_EF_ISN_GESLP_START_BIT))
351 #define AW88395_EF_ISN_GESLP_SIGN_MASK (~(1 << 9))
352 #define AW88395_EF_ISN_GESLP_SIGN_NEG (0xfe00)
354 #define AW88395_CABL_BASE_VALUE (1000)
355 #define AW88395_ICABLK_FACTOR (1)
356 #define AW88395_VCABLK_FACTOR (1)
357 #define AW88395_VCAL_FACTOR (1 << 12)
358 #define AW88395_VSCAL_FACTOR (16500)
359 #define AW88395_ISCAL_FACTOR (3667)
360 #define AW88395_EF_VSENSE_GAIN_SHIFT (0)
362 #define AW88395_VCABLK_FACTOR_DAC (2)
363 #define AW88395_VSCAL_FACTOR_DAC (11790)
364 #define AW88395_EF_DAC_GESLP_SHIFT (10)
365 #define AW88395_EF_DAC_GESLP_SIGN_MASK (1 << 5)
366 #define AW88395_EF_DAC_GESLP_SIGN_NEG (0xffc0)
368 #define AW88395_VCALB_ADJ_FACTOR (12)
370 #define AW88395_WDT_CNT_START_BIT (0)
371 #define AW88395_WDT_CNT_BITS_LEN (8)
372 #define AW88395_WDT_CNT_MASK \
373 (~(((1<<AW88395_WDT_CNT_BITS_LEN)-1) << AW88395_WDT_CNT_START_BIT))
375 #define AW88395_DSP_CFG_ADDR (0x9C80)
376 #define AW88395_DSP_FW_ADDR (0x8C00)
377 #define AW88395_DSP_REG_VMAX (0x9C94)
378 #define AW88395_DSP_REG_CFG_ADPZ_RE (0x9D00)
379 #define AW88395_DSP_REG_VCALB (0x9CF7)
380 #define AW88395_DSP_RE_SHIFT (12)
382 #define AW88395_DSP_REG_CFG_ADPZ_RA (0x9D02)
383 #define AW88395_DSP_REG_CRC_ADDR (0x9F42)
384 #define AW88395_DSP_CALI_F0_DELAY (0x9CFD)