2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include <sound/tlv.h>
20 #include <linux/gcd.h>
21 #include <linux/i2c.h>
22 #include <linux/spi/spi.h>
23 #include <linux/regmap.h>
27 #include "adau-utils.h"
29 static const char * const adau17x1_capture_mixer_boost_text[] = {
30 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
33 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
34 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
36 static const char * const adau17x1_mic_bias_mode_text[] = {
37 "Normal operation", "High performance",
40 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
41 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
43 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
45 static const struct snd_kcontrol_new adau17x1_controls[] = {
46 SOC_DOUBLE_R_TLV("Digital Capture Volume",
47 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
48 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
49 0, 0xff, 1, adau17x1_digital_tlv),
50 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
51 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
53 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
55 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
58 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
60 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
63 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
64 struct snd_kcontrol *kcontrol, int event)
66 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
67 struct adau *adau = snd_soc_codec_get_drvdata(codec);
70 if (SND_SOC_DAPM_EVENT_ON(event)) {
71 adau->pll_regs[5] = 1;
73 adau->pll_regs[5] = 0;
74 /* Bypass the PLL when disabled, otherwise registers will become
76 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
77 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
80 /* The PLL register is 6 bytes long and can only be written at once. */
81 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
82 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
84 if (SND_SOC_DAPM_EVENT_ON(event)) {
86 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
87 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
88 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
94 static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w,
95 struct snd_kcontrol *kcontrol, int event)
97 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
98 struct adau *adau = snd_soc_codec_get_drvdata(codec);
101 * If we are capturing, toggle the ADOSR bit in Converter Control 0 to
102 * avoid losing SNR (workaround from ADI). This must be done after
103 * the ADC(s) have been enabled. According to the data sheet, it is
104 * normally illegal to set this bit when the sampling rate is 96 kHz,
105 * but according to ADI it is acceptable for this workaround.
107 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
108 ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR);
109 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
110 ADAU17X1_CONVERTER0_ADOSR, 0);
115 static const char * const adau17x1_mono_stereo_text[] = {
117 "Mono Left Channel (L+R)",
118 "Mono Right Channel (L+R)",
122 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
123 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
125 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
126 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
128 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
129 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
130 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
132 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
134 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
136 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
138 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
141 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
142 &adau17x1_dac_mode_mux),
143 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
144 &adau17x1_dac_mode_mux),
146 SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0,
147 adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU),
148 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
149 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
150 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
153 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
154 { "Left Decimator", NULL, "SYSCLK" },
155 { "Right Decimator", NULL, "SYSCLK" },
156 { "Left DAC", NULL, "SYSCLK" },
157 { "Right DAC", NULL, "SYSCLK" },
158 { "Capture", NULL, "SYSCLK" },
159 { "Playback", NULL, "SYSCLK" },
161 { "Left DAC", NULL, "Left DAC Mode Mux" },
162 { "Right DAC", NULL, "Right DAC Mode Mux" },
164 { "Capture", NULL, "AIFCLK" },
165 { "Playback", NULL, "AIFCLK" },
168 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
169 "SYSCLK", NULL, "PLL",
173 * The MUX register for the Capture and Playback MUXs selects either DSP as
174 * source/destination or one of the TDM slots. The TDM slot is selected via
175 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
176 * directly to the DAI interface with this control.
178 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
179 struct snd_ctl_elem_value *ucontrol)
181 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
182 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
183 struct adau *adau = snd_soc_codec_get_drvdata(codec);
184 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
185 struct snd_soc_dapm_update update;
186 unsigned int stream = e->shift_l;
187 unsigned int val, change;
190 if (ucontrol->value.enumerated.item[0] >= e->items)
193 switch (ucontrol->value.enumerated.item[0]) {
196 adau->dsp_bypass[stream] = false;
199 val = (adau->tdm_slot[stream] * 2) + 1;
200 adau->dsp_bypass[stream] = true;
204 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
205 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
207 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
209 change = snd_soc_test_bits(codec, reg, 0xff, val);
211 update.kcontrol = kcontrol;
216 snd_soc_dapm_mux_update_power(dapm, kcontrol,
217 ucontrol->value.enumerated.item[0], e, &update);
223 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
224 struct snd_ctl_elem_value *ucontrol)
226 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
227 struct adau *adau = snd_soc_codec_get_drvdata(codec);
228 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
229 unsigned int stream = e->shift_l;
230 unsigned int reg, val;
233 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
234 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
236 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
238 ret = regmap_read(adau->regmap, reg, &val);
244 ucontrol->value.enumerated.item[0] = val;
249 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
250 const struct snd_kcontrol_new _name = \
251 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
252 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
253 ARRAY_SIZE(_text), _text), \
254 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
256 static const char * const adau17x1_dac_mux_text[] = {
261 static const char * const adau17x1_capture_mux_text[] = {
266 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
267 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
269 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
270 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
272 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
273 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
274 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
276 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
278 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
279 &adau17x1_capture_mux),
282 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
283 { "DAC Playback Mux", "DSP", "DSP" },
284 { "DAC Playback Mux", "AIFIN", "Playback" },
286 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
287 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
288 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
289 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
290 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
291 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
293 { "Capture Mux", "DSP", "DSP" },
294 { "Capture Mux", "Decimator", "Left Decimator" },
295 { "Capture Mux", "Decimator", "Right Decimator" },
297 { "Capture", NULL, "Capture Mux" },
299 { "DSP", NULL, "DSP Siggen" },
301 { "DSP", NULL, "Left Decimator" },
302 { "DSP", NULL, "Right Decimator" },
305 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
306 { "Left DAC Mode Mux", "Stereo", "Playback" },
307 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
308 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
309 { "Right DAC Mode Mux", "Stereo", "Playback" },
310 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
311 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
312 { "Capture", NULL, "Left Decimator" },
313 { "Capture", NULL, "Right Decimator" },
316 bool adau17x1_has_dsp(struct adau *adau)
318 switch (adau->type) {
327 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
329 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
330 int source, unsigned int freq_in, unsigned int freq_out)
332 struct snd_soc_codec *codec = dai->codec;
333 struct adau *adau = snd_soc_codec_get_drvdata(codec);
336 if (freq_in < 8000000 || freq_in > 27000000)
339 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
343 /* The PLL register is 6 bytes long and can only be written at once. */
344 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
345 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
349 adau->pll_freq = freq_out;
354 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
355 int clk_id, unsigned int freq, int dir)
357 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec);
358 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
363 case ADAU17X1_CLK_SRC_MCLK:
366 case ADAU17X1_CLK_SRC_PLL_AUTO:
370 case ADAU17X1_CLK_SRC_PLL:
377 switch (adau->clk_src) {
378 case ADAU17X1_CLK_SRC_MCLK:
381 case ADAU17X1_CLK_SRC_PLL:
382 case ADAU17X1_CLK_SRC_PLL_AUTO:
391 if (is_pll != was_pll) {
393 snd_soc_dapm_add_routes(dapm,
394 &adau17x1_dapm_pll_route, 1);
396 snd_soc_dapm_del_routes(dapm,
397 &adau17x1_dapm_pll_route, 1);
401 adau->clk_src = clk_id;
406 static int adau17x1_auto_pll(struct snd_soc_dai *dai,
407 struct snd_pcm_hw_params *params)
409 struct adau *adau = snd_soc_dai_get_drvdata(dai);
410 unsigned int pll_rate;
412 switch (params_rate(params)) {
420 pll_rate = 48000 * 1024;
429 pll_rate = 44100 * 1024;
435 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
436 clk_get_rate(adau->mclk), pll_rate);
439 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
440 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
442 struct snd_soc_codec *codec = dai->codec;
443 struct adau *adau = snd_soc_codec_get_drvdata(codec);
444 unsigned int val, div, dsp_div;
448 switch (adau->clk_src) {
449 case ADAU17X1_CLK_SRC_PLL_AUTO:
450 ret = adau17x1_auto_pll(dai, params);
454 case ADAU17X1_CLK_SRC_PLL:
455 freq = adau->pll_freq;
462 if (freq % params_rate(params) != 0)
465 switch (freq / params_rate(params)) {
470 case 6144: /* fs / 6 */
474 case 4096: /* fs / 4 */
478 case 3072: /* fs / 3 */
482 case 2048: /* fs / 2 */
486 case 1536: /* fs / 1.5 */
490 case 512: /* fs / 0.5 */
498 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
499 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
500 if (adau17x1_has_dsp(adau)) {
501 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
502 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
505 if (adau->sigmadsp) {
506 ret = adau17x1_setup_firmware(adau, params_rate(params));
511 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
514 switch (params_width(params)) {
516 val = ADAU17X1_SERIAL_PORT1_DELAY16;
519 val = ADAU17X1_SERIAL_PORT1_DELAY8;
522 val = ADAU17X1_SERIAL_PORT1_DELAY0;
528 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
529 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
532 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
535 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
536 unsigned int ctrl0, ctrl1;
539 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
540 case SND_SOC_DAIFMT_CBM_CFM:
541 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
544 case SND_SOC_DAIFMT_CBS_CFS:
546 adau->master = false;
552 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
553 case SND_SOC_DAIFMT_I2S:
555 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
557 case SND_SOC_DAIFMT_LEFT_J:
558 case SND_SOC_DAIFMT_RIGHT_J:
560 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
562 case SND_SOC_DAIFMT_DSP_A:
564 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
565 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
567 case SND_SOC_DAIFMT_DSP_B:
569 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
570 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
576 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
577 case SND_SOC_DAIFMT_NB_NF:
579 case SND_SOC_DAIFMT_IB_NF:
580 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
582 case SND_SOC_DAIFMT_NB_IF:
583 lrclk_pol = !lrclk_pol;
585 case SND_SOC_DAIFMT_IB_IF:
586 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
587 lrclk_pol = !lrclk_pol;
594 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
596 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
597 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
599 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
604 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
605 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
607 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
608 unsigned int ser_ctrl0, ser_ctrl1;
609 unsigned int conv_ctrl0, conv_ctrl1;
621 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
624 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
627 if (adau->type == ADAU1361)
630 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
636 switch (slot_width * slots) {
638 if (adau->type == ADAU1761)
641 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
644 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
647 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
650 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
653 if (adau->type == ADAU1361)
656 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
664 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
665 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
668 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
669 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
672 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
673 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
676 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
677 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
685 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
686 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
689 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
690 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
693 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
694 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
697 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
698 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
704 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
705 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
706 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
707 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
708 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
709 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
710 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
711 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
713 if (!adau17x1_has_dsp(adau))
716 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
717 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
718 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
721 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
722 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
723 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
729 static int adau17x1_startup(struct snd_pcm_substream *substream,
730 struct snd_soc_dai *dai)
732 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
735 return sigmadsp_restrict_params(adau->sigmadsp, substream);
740 const struct snd_soc_dai_ops adau17x1_dai_ops = {
741 .hw_params = adau17x1_hw_params,
742 .set_sysclk = adau17x1_set_dai_sysclk,
743 .set_fmt = adau17x1_set_dai_fmt,
744 .set_pll = adau17x1_set_dai_pll,
745 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
746 .startup = adau17x1_startup,
748 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
750 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
751 enum adau17x1_micbias_voltage micbias)
753 struct adau *adau = snd_soc_codec_get_drvdata(codec);
756 case ADAU17X1_MICBIAS_0_90_AVDD:
757 case ADAU17X1_MICBIAS_0_65_AVDD:
763 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
765 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
767 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
769 /* SigmaDSP parameter memory */
775 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
777 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
779 /* SigmaDSP parameter memory */
784 case ADAU17X1_CLOCK_CONTROL:
785 case ADAU17X1_PLL_CONTROL:
786 case ADAU17X1_REC_POWER_MGMT:
787 case ADAU17X1_MICBIAS:
788 case ADAU17X1_SERIAL_PORT0:
789 case ADAU17X1_SERIAL_PORT1:
790 case ADAU17X1_CONVERTER0:
791 case ADAU17X1_CONVERTER1:
792 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
793 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
794 case ADAU17X1_ADC_CONTROL:
795 case ADAU17X1_PLAY_POWER_MGMT:
796 case ADAU17X1_DAC_CONTROL0:
797 case ADAU17X1_DAC_CONTROL1:
798 case ADAU17X1_DAC_CONTROL2:
799 case ADAU17X1_SERIAL_PORT_PAD:
800 case ADAU17X1_CONTROL_PORT_PAD0:
801 case ADAU17X1_CONTROL_PORT_PAD1:
802 case ADAU17X1_DSP_SAMPLING_RATE:
803 case ADAU17X1_SERIAL_INPUT_ROUTE:
804 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
805 case ADAU17X1_DSP_ENABLE:
806 case ADAU17X1_DSP_RUN:
807 case ADAU17X1_SERIAL_SAMPLING_RATE:
814 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
816 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
818 /* SigmaDSP parameter and program memory */
823 /* The PLL register is 6 bytes long */
824 case ADAU17X1_PLL_CONTROL:
825 case ADAU17X1_PLL_CONTROL + 1:
826 case ADAU17X1_PLL_CONTROL + 2:
827 case ADAU17X1_PLL_CONTROL + 3:
828 case ADAU17X1_PLL_CONTROL + 4:
829 case ADAU17X1_PLL_CONTROL + 5:
837 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
839 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
844 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
848 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
849 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
851 ret = sigmadsp_setup(adau->sigmadsp, rate);
853 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
856 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
860 EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);
862 int adau17x1_add_widgets(struct snd_soc_codec *codec)
864 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
865 struct adau *adau = snd_soc_codec_get_drvdata(codec);
868 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
869 ARRAY_SIZE(adau17x1_controls));
872 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
873 ARRAY_SIZE(adau17x1_dapm_widgets));
877 if (adau17x1_has_dsp(adau)) {
878 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
879 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
886 ret = sigmadsp_attach(adau->sigmadsp, &codec->component);
888 dev_err(codec->dev, "Failed to attach firmware: %d\n",
896 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
898 int adau17x1_add_routes(struct snd_soc_codec *codec)
900 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
901 struct adau *adau = snd_soc_codec_get_drvdata(codec);
904 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
905 ARRAY_SIZE(adau17x1_dapm_routes));
909 if (adau17x1_has_dsp(adau)) {
910 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
911 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
913 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
914 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
917 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
918 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
922 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
924 int adau17x1_resume(struct snd_soc_codec *codec)
926 struct adau *adau = snd_soc_codec_get_drvdata(codec);
928 if (adau->switch_mode)
929 adau->switch_mode(codec->dev);
931 regcache_sync(adau->regmap);
935 EXPORT_SYMBOL_GPL(adau17x1_resume);
937 int adau17x1_probe(struct device *dev, struct regmap *regmap,
938 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
939 const char *firmware_name)
945 return PTR_ERR(regmap);
947 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
951 adau->mclk = devm_clk_get(dev, "mclk");
952 if (IS_ERR(adau->mclk)) {
953 if (PTR_ERR(adau->mclk) != -ENOENT)
954 return PTR_ERR(adau->mclk);
955 /* Clock is optional (for the driver) */
957 } else if (adau->mclk) {
958 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
961 * Any valid PLL output rate will work at this point, use one
962 * that is likely to be chosen later as well. The register will
963 * be written when the PLL is powered up for the first time.
965 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
970 ret = clk_prepare_enable(adau->mclk);
975 adau->regmap = regmap;
976 adau->switch_mode = switch_mode;
979 dev_set_drvdata(dev, adau);
982 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL,
984 if (IS_ERR(adau->sigmadsp)) {
985 dev_warn(dev, "Could not find firmware file: %ld\n",
986 PTR_ERR(adau->sigmadsp));
987 adau->sigmadsp = NULL;
996 EXPORT_SYMBOL_GPL(adau17x1_probe);
998 void adau17x1_remove(struct device *dev)
1000 struct adau *adau = dev_get_drvdata(dev);
1002 snd_soc_unregister_codec(dev);
1004 clk_disable_unprepare(adau->mclk);
1006 EXPORT_SYMBOL_GPL(adau17x1_remove);
1008 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
1009 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1010 MODULE_LICENSE("GPL");