1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/soc/ep93xx-i2s.c
6 * Copyright (C) 2010 Ryan Mallon
8 * Based on the original driver by:
9 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
19 #include <sound/core.h>
20 #include <sound/dmaengine_pcm.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/initval.h>
24 #include <sound/soc.h>
26 #include <linux/platform_data/dma-ep93xx.h>
27 #include <linux/soc/cirrus/ep93xx.h>
29 #include "ep93xx-pcm.h"
31 #define EP93XX_I2S_TXCLKCFG 0x00
32 #define EP93XX_I2S_RXCLKCFG 0x04
33 #define EP93XX_I2S_GLSTS 0x08
34 #define EP93XX_I2S_GLCTRL 0x0C
36 #define EP93XX_I2S_I2STX0LFT 0x10
37 #define EP93XX_I2S_I2STX0RT 0x14
39 #define EP93XX_I2S_TXLINCTRLDATA 0x28
40 #define EP93XX_I2S_TXCTRL 0x2C
41 #define EP93XX_I2S_TXWRDLEN 0x30
42 #define EP93XX_I2S_TX0EN 0x34
44 #define EP93XX_I2S_RXLINCTRLDATA 0x58
45 #define EP93XX_I2S_RXCTRL 0x5C
46 #define EP93XX_I2S_RXWRDLEN 0x60
47 #define EP93XX_I2S_RX0EN 0x64
49 #define EP93XX_I2S_WRDLEN_16 (0 << 0)
50 #define EP93XX_I2S_WRDLEN_24 (1 << 0)
51 #define EP93XX_I2S_WRDLEN_32 (2 << 0)
53 #define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
55 #define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
58 * Transmit empty interrupt level select:
59 * 0 - Generate interrupt when FIFO is half empty
60 * 1 - Generate interrupt when FIFO is empty
62 #define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
63 #define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
65 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
66 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
67 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
68 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
69 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
71 #define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
73 struct ep93xx_i2s_info {
78 struct snd_dmaengine_dai_dma_data dma_params_rx;
79 struct snd_dmaengine_dai_dma_data dma_params_tx;
82 static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
83 [SNDRV_PCM_STREAM_PLAYBACK] = {
84 .name = "i2s-pcm-out",
85 .port = EP93XX_DMA_I2S1,
86 .direction = DMA_MEM_TO_DEV,
88 [SNDRV_PCM_STREAM_CAPTURE] = {
90 .port = EP93XX_DMA_I2S1,
91 .direction = DMA_DEV_TO_MEM,
95 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
96 unsigned reg, unsigned val)
98 __raw_writel(val, info->regs + reg);
101 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
104 return __raw_readl(info->regs + reg);
107 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
111 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
112 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
114 clk_enable(info->mclk);
115 clk_enable(info->sclk);
116 clk_enable(info->lrclk);
119 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
123 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
124 base_reg = EP93XX_I2S_TX0EN;
126 base_reg = EP93XX_I2S_RX0EN;
127 ep93xx_i2s_write_reg(info, base_reg, 1);
129 /* Enable TX IRQs (FIFO empty or underflow) */
130 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
131 stream == SNDRV_PCM_STREAM_PLAYBACK)
132 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
133 EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
134 EP93XX_I2S_TXCTRL_TXUFIE);
137 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
142 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
143 stream == SNDRV_PCM_STREAM_PLAYBACK)
144 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
147 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
148 base_reg = EP93XX_I2S_TX0EN;
150 base_reg = EP93XX_I2S_RX0EN;
151 ep93xx_i2s_write_reg(info, base_reg, 0);
153 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
154 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
156 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
159 clk_disable(info->lrclk);
160 clk_disable(info->sclk);
161 clk_disable(info->mclk);
166 * According to documentation I2S controller can handle underflow conditions
167 * just fine, but in reality the state machine is sometimes confused so that
168 * the whole stream is shifted by one byte. The watchdog below disables the TX
169 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
170 * is being reset and by filling the buffer we get some time before next
173 static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
175 struct ep93xx_i2s_info *info = dev_id;
178 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
180 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
181 * possible and get more time for DMA to catch up. Actually there are
182 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
185 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
186 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
187 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
191 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
196 static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
198 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
200 info->dma_params_tx.filter_data =
201 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
202 info->dma_params_rx.filter_data =
203 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
205 dai->playback_dma_data = &info->dma_params_tx;
206 dai->capture_dma_data = &info->dma_params_rx;
211 static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
212 struct snd_soc_dai *dai)
214 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
216 ep93xx_i2s_disable(info, substream->stream);
219 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
222 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
223 unsigned int clk_cfg;
224 unsigned int txlin_ctrl = 0;
225 unsigned int rxlin_ctrl = 0;
227 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_I2S:
231 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
234 case SND_SOC_DAIFMT_LEFT_J:
235 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
238 case SND_SOC_DAIFMT_RIGHT_J:
239 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
240 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
241 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
248 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249 case SND_SOC_DAIFMT_CBS_CFS:
251 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
254 case SND_SOC_DAIFMT_CBM_CFM:
255 /* Codec is master */
256 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
263 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
264 case SND_SOC_DAIFMT_NB_NF:
265 /* Negative bit clock, lrclk low on left word */
266 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
269 case SND_SOC_DAIFMT_NB_IF:
270 /* Negative bit clock, lrclk low on right word */
271 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
272 clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
275 case SND_SOC_DAIFMT_IB_NF:
276 /* Positive bit clock, lrclk low on left word */
277 clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
278 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
281 case SND_SOC_DAIFMT_IB_IF:
282 /* Positive bit clock, lrclk low on right word */
283 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
287 /* Write new register values */
288 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
289 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
290 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
291 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
295 static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
296 struct snd_pcm_hw_params *params,
297 struct snd_soc_dai *dai)
299 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
300 unsigned word_len, div, sdiv, lrdiv;
303 switch (params_format(params)) {
304 case SNDRV_PCM_FORMAT_S16_LE:
305 word_len = EP93XX_I2S_WRDLEN_16;
308 case SNDRV_PCM_FORMAT_S24_LE:
309 word_len = EP93XX_I2S_WRDLEN_24;
312 case SNDRV_PCM_FORMAT_S32_LE:
313 word_len = EP93XX_I2S_WRDLEN_32;
320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
321 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
323 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
326 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
327 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
328 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
329 * value is 64, because our sample size is 32 bit * 2 channels.
330 * I2S standard permits us to transmit more bits than
333 div = clk_get_rate(info->mclk) / params_rate(params);
335 if (div > (256 + 512) / 2) {
339 if (div < (128 + 256) / 2)
343 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
347 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
351 ep93xx_i2s_enable(info, substream->stream);
355 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
356 unsigned int freq, int dir)
358 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
360 if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
363 return clk_set_rate(info->mclk, freq);
367 static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
369 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
374 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
375 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
380 static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
382 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
387 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
388 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
393 #define ep93xx_i2s_suspend NULL
394 #define ep93xx_i2s_resume NULL
397 static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
398 .shutdown = ep93xx_i2s_shutdown,
399 .hw_params = ep93xx_i2s_hw_params,
400 .set_sysclk = ep93xx_i2s_set_sysclk,
401 .set_fmt = ep93xx_i2s_set_dai_fmt,
404 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
406 static struct snd_soc_dai_driver ep93xx_i2s_dai = {
408 .probe = ep93xx_i2s_dai_probe,
409 .suspend = ep93xx_i2s_suspend,
410 .resume = ep93xx_i2s_resume,
414 .rates = SNDRV_PCM_RATE_8000_192000,
415 .formats = EP93XX_I2S_FORMATS,
420 .rates = SNDRV_PCM_RATE_8000_192000,
421 .formats = EP93XX_I2S_FORMATS,
423 .ops = &ep93xx_i2s_dai_ops,
426 static const struct snd_soc_component_driver ep93xx_i2s_component = {
427 .name = "ep93xx-i2s",
430 static int ep93xx_i2s_probe(struct platform_device *pdev)
432 struct ep93xx_i2s_info *info;
435 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
439 info->regs = devm_platform_ioremap_resource(pdev, 0);
440 if (IS_ERR(info->regs))
441 return PTR_ERR(info->regs);
443 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
444 int irq = platform_get_irq(pdev, 0);
446 return irq < 0 ? irq : -ENODEV;
448 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
454 info->mclk = clk_get(&pdev->dev, "mclk");
455 if (IS_ERR(info->mclk)) {
456 err = PTR_ERR(info->mclk);
460 info->sclk = clk_get(&pdev->dev, "sclk");
461 if (IS_ERR(info->sclk)) {
462 err = PTR_ERR(info->sclk);
466 info->lrclk = clk_get(&pdev->dev, "lrclk");
467 if (IS_ERR(info->lrclk)) {
468 err = PTR_ERR(info->lrclk);
472 dev_set_drvdata(&pdev->dev, info);
474 err = devm_snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
479 err = devm_ep93xx_pcm_platform_register(&pdev->dev);
486 clk_put(info->lrclk);
495 static int ep93xx_i2s_remove(struct platform_device *pdev)
497 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
499 clk_put(info->lrclk);
505 static struct platform_driver ep93xx_i2s_driver = {
506 .probe = ep93xx_i2s_probe,
507 .remove = ep93xx_i2s_remove,
509 .name = "ep93xx-i2s",
513 module_platform_driver(ep93xx_i2s_driver);
515 MODULE_ALIAS("platform:ep93xx-i2s");
516 MODULE_AUTHOR("Ryan Mallon");
517 MODULE_DESCRIPTION("EP93XX I2S driver");
518 MODULE_LICENSE("GPL");