2 * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2008 Atmel
7 * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
10 * Based on at91-ssc.c by
11 * Frank Mandarino <fmandarino@endrelia.com>
12 * Based on pxa2xx Platform drivers by
13 * Liam Girdwood <lrg@slimlogic.co.uk>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
49 #define NUM_SSC_DEVICES 3
52 * SSC PDC registers required by the PCM DMA engine.
54 static struct atmel_pdc_regs pdc_tx_reg = {
57 .xnpr = ATMEL_PDC_TNPR,
58 .xncr = ATMEL_PDC_TNCR,
61 static struct atmel_pdc_regs pdc_rx_reg = {
64 .xnpr = ATMEL_PDC_RNPR,
65 .xncr = ATMEL_PDC_RNCR,
69 * SSC & PDC status bits for transmit and receive.
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 .ssc_enable = SSC_BIT(CR_TXEN),
73 .ssc_disable = SSC_BIT(CR_TXDIS),
74 .ssc_endx = SSC_BIT(SR_ENDTX),
75 .ssc_endbuf = SSC_BIT(SR_TXBUFE),
76 .ssc_error = SSC_BIT(SR_OVRUN),
77 .pdc_enable = ATMEL_PDC_TXTEN,
78 .pdc_disable = ATMEL_PDC_TXTDIS,
81 static struct atmel_ssc_mask ssc_rx_mask = {
82 .ssc_enable = SSC_BIT(CR_RXEN),
83 .ssc_disable = SSC_BIT(CR_RXDIS),
84 .ssc_endx = SSC_BIT(SR_ENDRX),
85 .ssc_endbuf = SSC_BIT(SR_RXBUFF),
86 .ssc_error = SSC_BIT(SR_OVRUN),
87 .pdc_enable = ATMEL_PDC_RXTEN,
88 .pdc_disable = ATMEL_PDC_RXTDIS,
95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
97 .name = "SSC0 PCM out",
102 .name = "SSC0 PCM in",
104 .mask = &ssc_rx_mask,
107 .name = "SSC1 PCM out",
109 .mask = &ssc_tx_mask,
112 .name = "SSC1 PCM in",
114 .mask = &ssc_rx_mask,
117 .name = "SSC2 PCM out",
119 .mask = &ssc_tx_mask,
122 .name = "SSC2 PCM in",
124 .mask = &ssc_rx_mask,
129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
132 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133 .dir_mask = SSC_DIR_MASK_UNUSED,
138 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139 .dir_mask = SSC_DIR_MASK_UNUSED,
144 .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145 .dir_mask = SSC_DIR_MASK_UNUSED,
152 * SSC interrupt handler. Passes PDC interrupts to the DMA
153 * interrupt handler in the PCM driver.
155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
157 struct atmel_ssc_info *ssc_p = dev_id;
158 struct atmel_pcm_dma_params *dma_params;
160 u32 ssc_substream_mask;
163 ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
164 & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
167 * Loop through the substreams attached to this SSC. If
168 * a DMA-related interrupt occurred on that substream, call
169 * the DMA interrupt handler function, if one has been
170 * registered in the dma_params structure by the PCM driver.
172 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
173 dma_params = ssc_p->dma_params[i];
175 if ((dma_params != NULL) &&
176 (dma_params->dma_intr_handler != NULL)) {
177 ssc_substream_mask = (dma_params->mask->ssc_endx |
178 dma_params->mask->ssc_endbuf);
179 if (ssc_sr & ssc_substream_mask) {
180 dma_params->dma_intr_handler(ssc_sr,
191 * When the bit clock is input, limit the maximum rate according to the
192 * Serial Clock Ratio Considerations section from the SSC documentation:
194 * The Transmitter and the Receiver can be programmed to operate
195 * with the clock signals provided on either the TK or RK pins.
196 * This allows the SSC to support many slave-mode data transfers.
197 * In this case, the maximum clock speed allowed on the RK pin is:
198 * - Peripheral clock divided by 2 if Receiver Frame Synchro is input
199 * - Peripheral clock divided by 3 if Receiver Frame Synchro is output
200 * In addition, the maximum clock speed allowed on the TK pin is:
201 * - Peripheral clock divided by 6 if Transmit Frame Synchro is input
202 * - Peripheral clock divided by 2 if Transmit Frame Synchro is output
204 * When the bit clock is output, limit the rate according to the
205 * SSC divider restrictions.
207 static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params,
208 struct snd_pcm_hw_rule *rule)
210 struct atmel_ssc_info *ssc_p = rule->private;
211 struct ssc_device *ssc = ssc_p->ssc;
212 struct snd_interval *i = hw_param_interval(params, rule->var);
213 struct snd_interval t;
214 struct snd_ratnum r = {
219 unsigned int num = 0, den = 0;
224 frame_size = snd_soc_params_to_frame_size(params);
228 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
229 case SND_SOC_DAIFMT_CBM_CFS:
230 if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE)
231 && ssc->clk_from_rk_pin)
232 /* Receiver Frame Synchro (i.e. capture)
233 * is output (format is _CFS) and the RK pin
234 * is used for input (format is _CBM_).
239 case SND_SOC_DAIFMT_CBM_CFM:
240 if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK)
241 && !ssc->clk_from_rk_pin)
242 /* Transmit Frame Synchro (i.e. playback)
243 * is input (format is _CFM) and the TK pin
244 * is used for input (format _CBM_ but not
251 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
252 case SND_SOC_DAIFMT_CBS_CFS:
253 r.num = ssc_p->mck_rate / mck_div / frame_size;
255 ret = snd_interval_ratnum(i, 1, &r, &num, &den);
256 if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) {
257 params->rate_num = num;
258 params->rate_den = den;
262 case SND_SOC_DAIFMT_CBM_CFS:
263 case SND_SOC_DAIFMT_CBM_CFM:
265 t.max = ssc_p->mck_rate / mck_div / frame_size;
266 t.openmin = t.openmax = 0;
268 ret = snd_interval_refine(i, &t);
279 /*-------------------------------------------------------------------------*\
281 \*-------------------------------------------------------------------------*/
283 * Startup. Only that one substream allowed in each direction.
285 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai)
288 struct platform_device *pdev = to_platform_device(dai->dev);
289 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
290 struct atmel_pcm_dma_params *dma_params;
294 pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n",
295 ssc_readl(ssc_p->ssc->regs, SR));
297 /* Enable PMC peripheral clock for this SSC */
298 pr_debug("atmel_ssc_dai: Starting clock\n");
299 ret = clk_enable(ssc_p->ssc->clk);
303 ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
305 /* Reset the SSC unless initialized to keep it in a clean state */
306 if (!ssc_p->initialized)
307 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
309 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
311 dir_mask = SSC_DIR_MASK_PLAYBACK;
314 dir_mask = SSC_DIR_MASK_CAPTURE;
317 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
318 SNDRV_PCM_HW_PARAM_RATE,
319 atmel_ssc_hw_rule_rate,
321 SNDRV_PCM_HW_PARAM_FRAME_BITS,
322 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
324 dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret);
328 dma_params = &ssc_dma_params[pdev->id][dir];
329 dma_params->ssc = ssc_p->ssc;
330 dma_params->substream = substream;
332 ssc_p->dma_params[dir] = dma_params;
334 snd_soc_dai_set_dma_data(dai, substream, dma_params);
336 spin_lock_irq(&ssc_p->lock);
337 if (ssc_p->dir_mask & dir_mask) {
338 spin_unlock_irq(&ssc_p->lock);
341 ssc_p->dir_mask |= dir_mask;
342 spin_unlock_irq(&ssc_p->lock);
348 * Shutdown. Clear DMA parameters and shutdown the SSC if there
349 * are no other substreams open.
351 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
352 struct snd_soc_dai *dai)
354 struct platform_device *pdev = to_platform_device(dai->dev);
355 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
356 struct atmel_pcm_dma_params *dma_params;
359 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
364 dma_params = ssc_p->dma_params[dir];
366 if (dma_params != NULL) {
367 dma_params->ssc = NULL;
368 dma_params->substream = NULL;
369 ssc_p->dma_params[dir] = NULL;
374 spin_lock_irq(&ssc_p->lock);
375 ssc_p->dir_mask &= ~dir_mask;
376 if (!ssc_p->dir_mask) {
377 if (ssc_p->initialized) {
378 free_irq(ssc_p->ssc->irq, ssc_p);
379 ssc_p->initialized = 0;
383 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
384 /* Clear the SSC dividers */
385 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
386 ssc_p->forced_divider = 0;
388 spin_unlock_irq(&ssc_p->lock);
390 /* Shutdown the SSC clock. */
391 pr_debug("atmel_ssc_dai: Stopping clock\n");
392 clk_disable(ssc_p->ssc->clk);
397 * Record the DAI format for use in hw_params().
399 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
402 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
403 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
410 * Record SSC clock dividers for use in hw_params().
412 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
415 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
416 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
419 case ATMEL_SSC_CMR_DIV:
421 * The same master clock divider is used for both
422 * transmit and receive, so if a value has already
423 * been set, it must match this value.
425 if (ssc_p->dir_mask !=
426 (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
427 ssc_p->cmr_div = div;
428 else if (ssc_p->cmr_div == 0)
429 ssc_p->cmr_div = div;
431 if (div != ssc_p->cmr_div)
433 ssc_p->forced_divider |= BIT(ATMEL_SSC_CMR_DIV);
436 case ATMEL_SSC_TCMR_PERIOD:
437 ssc_p->tcmr_period = div;
438 ssc_p->forced_divider |= BIT(ATMEL_SSC_TCMR_PERIOD);
441 case ATMEL_SSC_RCMR_PERIOD:
442 ssc_p->rcmr_period = div;
443 ssc_p->forced_divider |= BIT(ATMEL_SSC_RCMR_PERIOD);
453 /* Is the cpu-dai master of the frame clock? */
454 static int atmel_ssc_cfs(struct atmel_ssc_info *ssc_p)
456 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
457 case SND_SOC_DAIFMT_CBM_CFS:
458 case SND_SOC_DAIFMT_CBS_CFS:
464 /* Is the cpu-dai master of the bit clock? */
465 static int atmel_ssc_cbs(struct atmel_ssc_info *ssc_p)
467 switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) {
468 case SND_SOC_DAIFMT_CBS_CFM:
469 case SND_SOC_DAIFMT_CBS_CFS:
478 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
479 struct snd_pcm_hw_params *params,
480 struct snd_soc_dai *dai)
482 struct platform_device *pdev = to_platform_device(dai->dev);
484 struct atmel_ssc_info *ssc_p = &ssc_info[id];
485 struct ssc_device *ssc = ssc_p->ssc;
486 struct atmel_pcm_dma_params *dma_params;
487 int dir, channels, bits;
488 u32 tfmr, rfmr, tcmr, rcmr;
490 int fslen, fslen_ext;
496 * Currently, there is only one set of dma params for
497 * each direction. If more are added, this code will
498 * have to be changed to select the proper set.
500 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
506 * If the cpu dai should provide BCLK, but noone has provided the
507 * divider needed for that to work, fall back to something sensible.
509 cmr_div = ssc_p->cmr_div;
510 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_CMR_DIV)) &&
511 atmel_ssc_cbs(ssc_p)) {
512 int bclk_rate = snd_soc_params_to_bclk(params);
515 dev_err(dai->dev, "unable to calculate cmr_div: %d\n",
520 cmr_div = DIV_ROUND_CLOSEST(ssc_p->mck_rate, 2 * bclk_rate);
524 * If the cpu dai should provide LRCLK, but noone has provided the
525 * dividers needed for that to work, fall back to something sensible.
527 tcmr_period = ssc_p->tcmr_period;
528 rcmr_period = ssc_p->rcmr_period;
529 if (atmel_ssc_cfs(ssc_p)) {
530 int frame_size = snd_soc_params_to_frame_size(params);
532 if (frame_size < 0) {
534 "unable to calculate tx/rx cmr_period: %d\n",
539 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_TCMR_PERIOD)))
540 tcmr_period = frame_size / 2 - 1;
541 if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_RCMR_PERIOD)))
542 rcmr_period = frame_size / 2 - 1;
545 dma_params = ssc_p->dma_params[dir];
547 channels = params_channels(params);
550 * Determine sample size in bits and the PDC increment.
552 switch (params_format(params)) {
553 case SNDRV_PCM_FORMAT_S8:
555 dma_params->pdc_xfer_size = 1;
557 case SNDRV_PCM_FORMAT_S16_LE:
559 dma_params->pdc_xfer_size = 2;
561 case SNDRV_PCM_FORMAT_S24_LE:
563 dma_params->pdc_xfer_size = 4;
565 case SNDRV_PCM_FORMAT_S32_LE:
567 dma_params->pdc_xfer_size = 4;
570 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
575 * Compute SSC register settings.
577 switch (ssc_p->daifmt
578 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
580 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
582 * I2S format, SSC provides BCLK and LRC clocks.
584 * The SSC transmit and receive clocks are generated
585 * from the MCK divider, and the BCLK signal
586 * is output on the SSC TK line.
589 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
591 "sample size %d is too large for SSC device\n",
596 fslen_ext = (bits - 1) / 16;
597 fslen = (bits - 1) % 16;
599 rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
600 | SSC_BF(RCMR_STTDLY, START_DELAY)
601 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
602 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
603 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
604 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
606 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
607 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
608 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
609 | SSC_BF(RFMR_FSLEN, fslen)
610 | SSC_BF(RFMR_DATNB, (channels - 1))
612 | SSC_BF(RFMR_LOOP, 0)
613 | SSC_BF(RFMR_DATLEN, (bits - 1));
615 tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
616 | SSC_BF(TCMR_STTDLY, START_DELAY)
617 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
618 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
619 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
620 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
622 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
623 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
624 | SSC_BF(TFMR_FSDEN, 0)
625 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
626 | SSC_BF(TFMR_FSLEN, fslen)
627 | SSC_BF(TFMR_DATNB, (channels - 1))
629 | SSC_BF(TFMR_DATDEF, 0)
630 | SSC_BF(TFMR_DATLEN, (bits - 1));
633 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
634 /* I2S format, CODEC supplies BCLK and LRC clocks. */
635 rcmr = SSC_BF(RCMR_PERIOD, 0)
636 | SSC_BF(RCMR_STTDLY, START_DELAY)
637 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
638 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
639 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
640 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
641 SSC_CKS_PIN : SSC_CKS_CLOCK);
643 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
644 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
645 | SSC_BF(RFMR_FSLEN, 0)
646 | SSC_BF(RFMR_DATNB, (channels - 1))
648 | SSC_BF(RFMR_LOOP, 0)
649 | SSC_BF(RFMR_DATLEN, (bits - 1));
651 tcmr = SSC_BF(TCMR_PERIOD, 0)
652 | SSC_BF(TCMR_STTDLY, START_DELAY)
653 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
654 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
655 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
656 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
657 SSC_CKS_CLOCK : SSC_CKS_PIN);
659 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
660 | SSC_BF(TFMR_FSDEN, 0)
661 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
662 | SSC_BF(TFMR_FSLEN, 0)
663 | SSC_BF(TFMR_DATNB, (channels - 1))
665 | SSC_BF(TFMR_DATDEF, 0)
666 | SSC_BF(TFMR_DATLEN, (bits - 1));
669 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
670 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
671 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
673 "sample size %d is too large for SSC device\n",
678 fslen_ext = (bits - 1) / 16;
679 fslen = (bits - 1) % 16;
681 rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
682 | SSC_BF(RCMR_STTDLY, START_DELAY)
683 | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
684 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
685 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
686 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
687 SSC_CKS_PIN : SSC_CKS_CLOCK);
689 rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
690 | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
691 | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
692 | SSC_BF(RFMR_FSLEN, fslen)
693 | SSC_BF(RFMR_DATNB, (channels - 1))
695 | SSC_BF(RFMR_LOOP, 0)
696 | SSC_BF(RFMR_DATLEN, (bits - 1));
698 tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
699 | SSC_BF(TCMR_STTDLY, START_DELAY)
700 | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
701 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
702 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
703 | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
704 SSC_CKS_CLOCK : SSC_CKS_PIN);
706 tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
707 | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
708 | SSC_BF(TFMR_FSDEN, 0)
709 | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
710 | SSC_BF(TFMR_FSLEN, fslen)
711 | SSC_BF(TFMR_DATNB, (channels - 1))
713 | SSC_BF(TFMR_DATDEF, 0)
714 | SSC_BF(TFMR_DATLEN, (bits - 1));
717 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
719 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
721 * The SSC transmit and receive clocks are generated from the
722 * MCK divider, and the BCLK signal is output
723 * on the SSC TK line.
725 rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
726 | SSC_BF(RCMR_STTDLY, 1)
727 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
728 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
729 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
730 | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
732 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
733 | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
734 | SSC_BF(RFMR_FSLEN, 0)
735 | SSC_BF(RFMR_DATNB, (channels - 1))
737 | SSC_BF(RFMR_LOOP, 0)
738 | SSC_BF(RFMR_DATLEN, (bits - 1));
740 tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
741 | SSC_BF(TCMR_STTDLY, 1)
742 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
743 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
744 | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
745 | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
747 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
748 | SSC_BF(TFMR_FSDEN, 0)
749 | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
750 | SSC_BF(TFMR_FSLEN, 0)
751 | SSC_BF(TFMR_DATNB, (channels - 1))
753 | SSC_BF(TFMR_DATDEF, 0)
754 | SSC_BF(TFMR_DATLEN, (bits - 1));
757 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
759 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
761 * Data is transferred on first BCLK after LRC pulse rising
762 * edge.If stereo, the right channel data is contiguous with
763 * the left channel data.
765 rcmr = SSC_BF(RCMR_PERIOD, 0)
766 | SSC_BF(RCMR_STTDLY, START_DELAY)
767 | SSC_BF(RCMR_START, SSC_START_RISING_RF)
768 | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
769 | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
770 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
771 SSC_CKS_PIN : SSC_CKS_CLOCK);
773 rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
774 | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
775 | SSC_BF(RFMR_FSLEN, 0)
776 | SSC_BF(RFMR_DATNB, (channels - 1))
778 | SSC_BF(RFMR_LOOP, 0)
779 | SSC_BF(RFMR_DATLEN, (bits - 1));
781 tcmr = SSC_BF(TCMR_PERIOD, 0)
782 | SSC_BF(TCMR_STTDLY, START_DELAY)
783 | SSC_BF(TCMR_START, SSC_START_RISING_RF)
784 | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
785 | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
786 | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
787 SSC_CKS_CLOCK : SSC_CKS_PIN);
789 tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
790 | SSC_BF(TFMR_FSDEN, 0)
791 | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
792 | SSC_BF(TFMR_FSLEN, 0)
793 | SSC_BF(TFMR_DATNB, (channels - 1))
795 | SSC_BF(TFMR_DATDEF, 0)
796 | SSC_BF(TFMR_DATLEN, (bits - 1));
800 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
804 pr_debug("atmel_ssc_hw_params: "
805 "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
806 rcmr, rfmr, tcmr, tfmr);
808 if (!ssc_p->initialized) {
809 if (!ssc_p->ssc->pdata->use_dma) {
810 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
811 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
812 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
813 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
815 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
816 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
817 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
818 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
821 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
825 "atmel_ssc_dai: request_irq failure\n");
826 pr_debug("Atmel_ssc_dai: Stopping clock\n");
827 clk_disable(ssc_p->ssc->clk);
831 ssc_p->initialized = 1;
834 /* set SSC clock mode register */
835 ssc_writel(ssc_p->ssc->regs, CMR, cmr_div);
837 /* set receive clock mode and format */
838 ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
839 ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
841 /* set transmit clock mode and format */
842 ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
843 ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
845 pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
850 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
851 struct snd_soc_dai *dai)
853 struct platform_device *pdev = to_platform_device(dai->dev);
854 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
855 struct atmel_pcm_dma_params *dma_params;
858 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
863 dma_params = ssc_p->dma_params[dir];
865 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
866 ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
868 pr_debug("%s enabled SSC_SR=0x%08x\n",
869 dir ? "receive" : "transmit",
870 ssc_readl(ssc_p->ssc->regs, SR));
874 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
875 int cmd, struct snd_soc_dai *dai)
877 struct platform_device *pdev = to_platform_device(dai->dev);
878 struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id];
879 struct atmel_pcm_dma_params *dma_params;
882 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
887 dma_params = ssc_p->dma_params[dir];
890 case SNDRV_PCM_TRIGGER_START:
891 case SNDRV_PCM_TRIGGER_RESUME:
892 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
893 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
896 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
904 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
906 struct atmel_ssc_info *ssc_p;
907 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
909 if (!cpu_dai->active)
912 ssc_p = &ssc_info[pdev->id];
914 /* Save the status register before disabling transmit and receive */
915 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
916 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
918 /* Save the current interrupt mask, then disable unmasked interrupts */
919 ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
920 ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
922 ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
923 ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
924 ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
925 ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
926 ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
933 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
935 struct atmel_ssc_info *ssc_p;
936 struct platform_device *pdev = to_platform_device(cpu_dai->dev);
939 if (!cpu_dai->active)
942 ssc_p = &ssc_info[pdev->id];
944 /* restore SSC register settings */
945 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
946 ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
947 ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
948 ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
949 ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
951 /* re-enable interrupts */
952 ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
954 /* Re-enable receive and transmit as appropriate */
957 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
959 (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
960 ssc_writel(ssc_p->ssc->regs, CR, cr);
964 #else /* CONFIG_PM */
965 # define atmel_ssc_suspend NULL
966 # define atmel_ssc_resume NULL
967 #endif /* CONFIG_PM */
969 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
970 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
972 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
973 .startup = atmel_ssc_startup,
974 .shutdown = atmel_ssc_shutdown,
975 .prepare = atmel_ssc_prepare,
976 .trigger = atmel_ssc_trigger,
977 .hw_params = atmel_ssc_hw_params,
978 .set_fmt = atmel_ssc_set_dai_fmt,
979 .set_clkdiv = atmel_ssc_set_dai_clkdiv,
982 static struct snd_soc_dai_driver atmel_ssc_dai = {
983 .suspend = atmel_ssc_suspend,
984 .resume = atmel_ssc_resume,
988 .rates = SNDRV_PCM_RATE_CONTINUOUS,
991 .formats = ATMEL_SSC_FORMATS,},
995 .rates = SNDRV_PCM_RATE_CONTINUOUS,
998 .formats = ATMEL_SSC_FORMATS,},
999 .ops = &atmel_ssc_dai_ops,
1002 static const struct snd_soc_component_driver atmel_ssc_component = {
1003 .name = "atmel-ssc",
1006 static int asoc_ssc_init(struct device *dev)
1008 struct ssc_device *ssc = dev_get_drvdata(dev);
1011 ret = snd_soc_register_component(dev, &atmel_ssc_component,
1014 dev_err(dev, "Could not register DAI: %d\n", ret);
1018 if (ssc->pdata->use_dma)
1019 ret = atmel_pcm_dma_platform_register(dev);
1021 ret = atmel_pcm_pdc_platform_register(dev);
1024 dev_err(dev, "Could not register PCM: %d\n", ret);
1025 goto err_unregister_dai;
1031 snd_soc_unregister_component(dev);
1036 static void asoc_ssc_exit(struct device *dev)
1038 struct ssc_device *ssc = dev_get_drvdata(dev);
1040 if (ssc->pdata->use_dma)
1041 atmel_pcm_dma_platform_unregister(dev);
1043 atmel_pcm_pdc_platform_unregister(dev);
1045 snd_soc_unregister_component(dev);
1049 * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
1051 int atmel_ssc_set_audio(int ssc_id)
1053 struct ssc_device *ssc;
1056 /* If we can grab the SSC briefly to parent the DAI device off it */
1057 ssc = ssc_request(ssc_id);
1059 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
1061 return PTR_ERR(ssc);
1063 ssc_info[ssc_id].ssc = ssc;
1066 ret = asoc_ssc_init(&ssc->pdev->dev);
1070 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
1072 void atmel_ssc_put_audio(int ssc_id)
1074 struct ssc_device *ssc = ssc_info[ssc_id].ssc;
1076 asoc_ssc_exit(&ssc->pdev->dev);
1079 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
1081 /* Module information */
1082 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
1083 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
1084 MODULE_LICENSE("GPL");